HP PAVILION DV4, COMPAQ CQ40 Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile AMD S1G3 CPU with ATI
RS880M(NB) & SB710(SB) core logic

3 3

2009-03-15

REV:0.3

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-4117P

1 56Monday, M arch 16, 2009

E

0.3

A

Compal Confidential

B

C

D

Consumer AMD 14" UMA - Ripley 2.0 (NBW20)

E

1 1

Accelerometer
ST LIS302DL TR

Page 30

Thermal Se nsor
AD M10 32A RMZ

Page 6

Fan c onn

Page 4

AMD S1G3 CPU

638-PIN uFCPGA 638

Page 4, 5, 6, 7

DDR2 800MHz 1.8V

Dual Channel

DDR2- SO-DIMM X2

BANK 0 , 1, 2, 3

Page 8, 9

72QFN

Clock Generator
SL G8SP6 26V TR

Page 15

Side-Port DDR2 SDRAM

Hyper Transport Link

16X16

LVDS Panel

Page 16

Page 18

Page 17

A- Li nk Expre ss II

Interface

2 2

CRT

HDMI

PCI-E B US*5

CardReader
JM icron
JMB38 5-LGEZ0A

3 3

CardReader Soc ket

Page 27

Page 27

Realtek
8102E(10 /100M)

Page 25

RJ 45/11 CONN

Page 25

Mini- Card*2

WLAN & WWAN

Page 26

Express Card

Page 26

ATI RS880M

4X P CI-E

ATI SB710

DDR2 4 00MHz

Page 10, 11, 12, 13, 14

USB2.0 X12

Azalia (HDA I/F)

SATA Master-1

SATA Master-2

SATA Slave

SATA Slave

Page 19, 20, 21, 22, 23

LPC BUS

1024Mbit s(64Mbx16)

USB conn x2

BT Conn

Mini-Card WWAN

USB conn x1

Page 12

Page 31

Page 31

Page 26

Page 31

USB WebCam

Page 17

FingerPrinter AES1610
USBx1

MD C V1.5

page 35

Page 34

Audio CKT

Codec_IDT9271B7

Page 28 Page 29

daughter board

Ne w Module

Mo dule

Mo dule

daughter board

AMP & Audio Jack

TPA6017A2

KBC

ENE KB926-C0

Page 33

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*S-VIDEO OUT
*SPDIF
*Headphone/Line Out L/R
*Stereo Mic L/R

4 4

*Volume Control

LED

P41

RTC CKT.

Page 19

Power OK CKT.

P35

Touch Pad CONN. Int.KBD

Consumer IR

Page 34

SPI

Page 34

Page 33

SP I ROM
MX 2 5 L 1605

AM2C- 12G

Page 32

SATA HDD Connector

SATA ODD Connector

Multi-Bay HDD/ODD Option Connector

Page 24

Page 24

Page 24

e-SATA Connector

Page 31

*Consumer IR
*USB x1
*DC JACK

Page 35

A

Power On/Off CKT.

P35

DC/DC Interface CKT.

Page 36

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-4117P

2 56Monday, M arch 16, 2009

E

0.3

A

B

C

D

E

Symbol Note :

1.0/1.0a

For Riply PA-> PA@, RP@

: means Digital Ground

Voltage Rails

1 1

State

2 2

S0

S1

S3

S5 S4/AC

S5 S 4/ Batter y only

S5 S 4/AC & Ba ttery
don't e xist

3 3

I2C / SMBUS ADDRESSING

DE VI CE

DD R S O- DI MM 0

DD R S O- DI MM 1

CL OCK GENE RATO R (E XT .)

EC SM Bus1 address

Device

Smart Battery

24C16

4 4

O MEANS ON X MEANS OFF

power
plane

+1.8V

HEX

A 0

D2

+B

O

O

O

O

O

X

+5VALW

+3VALW

O

O

O

O

X

X X X

AD DR ES S

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A 4

1 1 0 1 0 0 1 0

EC SM Bus2 address

HEX

Address Address

16H

101 0 000 X b

A0H

Device

CPU

ADI1032-2 CPU

HEX

98H

9AH

+5VS

+3VS

+1.5VS

+0.9V

+VCCP

+CPU_CO RE

+VGA_CO RE

+2.5VS

+1.8VS

+1.2VS

+0.9VGA

O

X X

X

100 1 100 X b000 1 011 X b

100 1 101 X b

: means Analog Ground

Lay out Note s

L

Please see VGA@ as no install. No support RX780M.

: Q ues ti on Are a Mark. (Wa it ch eck )

"*" as default BOM setting
*PA@ : means install when Ripley PA.
PR@ : means install when Ripley PR.
RM@ : means install when Rachman.
*RP@ : means install when Ripley.
SIDE@ : means install when SidePort support.
@ : means just reserve , no build
45@ : Install when 45 level Assy

R3 NB and SB: RS780R3@,SBR3@
R1 NB and SB: RS780R1@,SBR1@

OO

1.1

OO

X

For Riply PA-> PA@, RP@,RPZ@
For Riply PR-> PR@, RP@, PRM@,RPZ@
For Rachman UMA-> RM@, PRM@,RMZ@

PCB for 1.1

2.0

X

For Riply PA-> PA@/RP@/RPZ@

For Rachman UMA-> RM@/PRM@/RMZ@

SMBU S Control Table

SERIAL SENSOR

V V

XX XX
XX XX
XX XX

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

I2C_CLK

I2C_DATA

DDC_CLK0

DDC_DATA0

DDC_CLK1

DDC_DATA1

SCL0

SDA0

SCL1

SDA1

SCL2

SDA2

SCL3

SDA3

SOURCE

KB926

KB926

RS7 80M

RS780M

RS780M

SB700

SB700

SB700

SB700

INVERTER BATT EEPROM

X
X X X
X X X X X X X
X X X X X
X X X X X
X X X X X

PCB for 2.0

THERMAL

CPU &
ADM1032

ADM1032

V
V

CPU

SODIMM CLK CHIP

X
X X

X X X
X X X X

V V

X X

For Riply PR-> PR@, RP@, PRM@
For Rachman UMA-> RM@, PRM@

PCB for 1.0/1.0a

PCB-Ripley MB

DAZ=DAZ03Y00201 DAZ=DAZ03Y00101

RP11@,RM11@:For 1.A PCB
RP10@,RM10@:For 1.0 PCB.

U3

RS780

RS780 R1

RS780R1@

RP11@

ZZ Z

PCB-Ripley MB

DAZ=DAZ03Y00203 DAZ=DAZ03Y00102

RP@

ZZ Z

PCB-Ripley MB

MINI CARD

Slot 2I / II

X

X X
X

V

X
X

RP10@

ZZ Z

SB700

RM11@

ZZ Z

PCB-Rachman UMA MB

RM@

ZZ Z

PCB-Rachman UMA MB

DAZ=DAZ09100102DAZ=DAZ09000102

LCD

HDMI

X

X

X
X

V

V

XX
XXX X
XXX X
XX

RM10@

ZZ Z

PCB-Rachman UMA MB

U15

SB700 R1

SBR1@

X76

X76

G-Sensor

X
X
X
X
X
X
X

V

X

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-4117P

3 56Monday, M arch 16, 2009

E

0.3

A

1 1

H_C ADIP[0..15 ]<10>

H_ CADIP[0..1 5]

H_C ADIN[0 ..15]

B

H_CAD OP[0..15]

H_ CADON[0..1 5]

H_CAD OP[0..15] <10>

H_C ADON[0..15 ] <10>H_C ADIN[0..1 5]<10>

C

+1.2V_HT

250 mil

1

C1

4.7U_0805_10V4Z

2

1

C2

4.7U_0805_10V4Z

2

D

VLDT CAP.

1

C3

0.22U_0603_16V4 Z

2

1

C4

0.22U_0603_16V4 Z

2

1

C5
180P_0402_50V8J

2

E

1

C6
180P_0402_50V8J

2

Near CPU Socket

+1.2V_HT

VLDT= 500mA

H_CAD IP0
H_C ADIN0
H_CAD IP1
H_C ADIN1
H_CAD IP2

2 2

H_CLKIP0<10>
H_CLK IN0<10>
H_CLKIP1<10>

3 3

H_CLK IN1<10>

H_CTLIP0<10>

H_CTLIP1<10> H_CTLOP1 <10>
H_CTLIN1<10>

H_C ADIN2
H_CAD IP3
H_C ADIN3
H_CAD IP4
H_C ADIN4
H_CAD IP5
H_C ADIN5
H_CAD IP6
H_C ADIN6
H_CAD IP7
H_C ADIN7
H_CAD IP8
H_C ADIN8
H_CAD IP9
H_C ADIN9
H_CAD IP10
H_CAD IN10
H_CAD IP11
H_CAD IN11
H_CAD IP12
H_CAD IN12
H_CAD IP13
H_CAD IN13
H_CAD IP14
H_CAD IN14
H_CAD IP15
H_CAD IN15

JCPUA

D1
D2
D3
D4

E3
E2
E1

F1
G3
G2
G1

H1

J1

K1

L3
L2
L1

M1

N3

N2

E5

F5

F3

F4
G5

H5

H3

H4

K3

K4

L5
M5
M3
M4

N5
P5

J3

J2

J5

K5

N1
P1
P3
P4

9/2 0 SP0 70 00D M0 0/SP0 7000 EQ00

HT LINK

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

FOX_P Z6382A-284S-41F_GRIFFIN

CONN@

Athlon 64 S1
Processor Socket

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

AE2
AE3
AE4
AE5

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

Y1
W1
Y4
Y3

R2
R3
T5
R5

+VLDT_B

1 2

C7 4.7U_0805_10V4Z

If VL DT is conne cted only on on e sid e, one

4.7uF cap should be a dded to th e island

H_CAD OP0
H_CAD ON0
H_CAD OP1
H_CAD ON1
H_CAD OP2
H_CAD ON2
H_CAD OP3
H_CAD ON3
H_CAD OP4
H_CAD ON4
H_CAD OP5
H_CAD ON5
H_CAD OP6
H_CAD ON6
H_CAD OP7
H_CAD ON7
H_CAD OP8
H_CAD ON8
H_CAD OP9
H_CAD ON9
H_CAD OP10
H_CAD ON10
H_CAD OP11
H_CAD ON11
H_CAD OP12
H_CAD ON12
H_CAD OP13
H_CAD ON13
H_CAD OP14
H_CAD ON14
H_CAD OP15
H_CAD ON15

side.

H_CLKOP0 <10>
H_CLKON0 <10>
H_CLKOP1 <10>
H_CLKON1 <10>

H_CTLOP0 <10>
H_CTLON0 <10>H_CTLIN0<10>

H_CTLON1 <10>

PWM Fan Control circuit

CH751H -40PT_SOD323-2

FAN_PWM<33>

+5VS

JP2

1

D1

2 1

6

2

1

D

Q1

G

3

S

SI3456BDV-T1-E3_TSOP6

4 5

C8

4.7U_0805_10V4Z

2

+VCC_F AN

1

C9

0.1U_0402_16V4Z

2

12

D2

@

RLZ5.1 B_LL34

1

1

2

2

3

GND

4

GND

ACES_88231-02001

CONN@

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

LA-4117P

4 56Monday, M arch 16, 2009

E

0.3

A

B

C

D

E

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR

1 1

2 2

Pla ce th em cl os e t o CP U wit hin 1"

R4 39.2_0402_1%

1 2

DDR_A_BS #0<8>
DDR_A_BS #1<8>
DDR_A_BS #2<8>

DDR_A _RAS#<8>
DDR_A _CAS#<8>
DDR_A_W E#<8>

1 2

R3 39.2_0402_1%

T2 PAD

DDR_A _ODT0
DDR_A _ODT1

DDR_C S0_DIMMA#
DDR_C S1_DIMMA# DDR_C S0_DIMMB#

DDR_CKE 0_DIMMA
DDR_CKE 1_DIMMA

DDR_A _CLK0
DDR_A _CLK#0
DDR_A _CLK1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_BS #0
DDR_A_BS #1
DDR_A_BS #2

DDR_A _RAS#
DDR_A _CAS#
DDR_A_W E#

+1.8V

DDR_A _ODT0<8>
DDR_A _ODT1<8>

DDR_CS0_D IMMA#<8>
DDR_CS1_D IMMA#<8> DDR_CS0_D IMMB# <9>

DDR_CKE 0_DIMMA<8>
DDR_CKE 1_DIMMA<8>

DDR_A _CLK0<8>

DDR_A _CLK#0<8>

3 3

4 4

DDR_A _CLK1<8>

DDR_A _CLK#1<8>

DDR_A _MA[15..0]<8> DDR_B _MA[15..0] <9>

AD10

AF10

AE10

AA16

D10
C10
B10

H16

T19
V22
U21
V19

T20
U19
U20
V20

N19
N20
E16
F16
Y16

P19
P20

N21
M20
N22
M19
M22

M24

K22
R21

K20
V24
K24
K19

R20
R23

R19
T22
T24

J22
J20

L20

L21
L19

L22

J21

WITHIN 1.5 INCH

DDR_A _CLK0

DDR_A _CLK#0

DDR_A _CLK1

DDR_A _CLK#1

DDR_B _CLK0

DDR_B _CLK#0

DDR_B _CLK1

DDR_B _CLK#1

JCPUB

VTT1

MEM:CMD /CTRL/CLK

VTT2
VTT3
VTT4

MEMZP
MEMZN

RSVD_M1

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_CKE0
MA_CKE1

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_RAS_L
MA_CAS_L
MA_WE_L

FOX_P Z6382A-284S-41F_GRIFFIN

Athlo n 64 S1
Proce ssor
Socke t

CONN@

1

2

1

2

1

2

1

2

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CKE0
MB_CKE1

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8

MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

MB_WE_L

C10

1.5P_0402_50V9C

C11

1.5P_0402_50V9C

C14

1.5P_0402_50V9C

C15

1.5P_0402_50V9C

W10

VTT5

AC10

VTT6

AB10

VTT7

AA10

VTT8

A10

VTT9

Y10

W17

B18

W26
W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

+0.9V+0.9V

VTT_SENSE

+MCH_REF

DDR_B _ODT0
DDR_B _ODT1

DDR_C S1_DIMMB#

DDR_CKE 0_DIMMB
DDR_CKE 1_DIMMB

DDR_B _CLK0
DDR_B _CLK#0
DDR_B _CLK1
DDR_B _CLK#1DDR_A _CLK#1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_BS #0
DDR_B_BS #1
DDR_B_BS #2

DDR_B _RAS#
DDR_B _CAS#
DDR_B_W E#

R1

1K_0402_1%

R2

1K_0402_1%

T1PAD

T3PAD

DDR_B _ODT0 <9>
DDR_B _ODT1 <9>

DDR_CS1_D IMMB# <9>

DDR_CKE 0_DIMMB <9>
DDR_CKE 1_DIMMB <9>

DDR_B _CLK0 <9>
DDR_B _CLK#0 <9>
DDR_B _CLK1 <9>
DDR_B _CLK#1 <9>

DDR_B_BS #0 < 9>
DDR_B_BS #1 < 9>
DDR_B_BS #2 < 9>

DDR_B _RAS# <9>
DDR_B _CAS# <9>
DDR_B_W E# <9>

+1.8V

1 2

+MCH_REF

C12

1 2

0.1U_0402_16V4Z

1

C13

2

1000P_0402_25V8J

DDR _B_D[63.. 0]<9>

1

2

DDR_B _DM[7..0]<9> DDR_A _DM[7..0] <8>

DDR_B _DQS0<9>
DDR_B _DQS#0<9>
DDR_B _DQS1<9>
DDR_B _DQS#1<9>
DDR_B _DQS2<9>
DDR_B _DQS#2<9>
DDR_B _DQS3<9>
DDR_B _DQS#3<9>
DDR_B _DQS4<9>
DDR_B _DQS#4<9>
DDR_B _DQS5<9>
DDR_B _DQS#5<9>
DDR_B _DQS6<9>
DDR_B _DQS#6<9>
DDR_B _DQS7<9>
DDR_B _DQS#7<9>

DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_B _D10
DDR_B _D11
DDR_B _D12
DDR_B _D13
DDR_B _D14
DDR_B _D15
DDR_B _D16
DDR_B _D17
DDR_B _D18
DDR_B _D19
DDR_B _D20
DDR_B _D21
DDR_B _D22
DDR_B _D23
DDR_B _D24
DDR_B _D25
DDR_B _D26
DDR_B _D27
DDR_B _D28
DDR_B _D29
DDR_B _D30
DDR_B _D31
DDR_B _D32
DDR_B _D33
DDR_B _D34
DDR_B _D35
DDR_B _D36
DDR_B _D37
DDR_B _D38
DDR_B _D39
DDR_B _D40
DDR_B _D41
DDR_B _D42
DDR_B _D43
DDR_B _D44
DDR_B _D45
DDR_B _D46
DDR_B _D47
DDR_B _D48
DDR_B _D49
DDR_B _D50
DDR_B _D51
DDR_B _D52
DDR_B _D53
DDR_B _D54
DDR_B _D55
DDR_B _D56
DDR_B _D57
DDR_B _D58
DDR_B _D59
DDR_B _D60
DDR_B _D61
DDR_B _D62
DDR_B _D63

DDR_B_DM 0
DDR_B_DM 1
DDR_B_DM 2
DDR_B_DM 3
DDR_B_DM 4
DDR_B_DM 5
DDR_B_DM 6
DDR_B_DM 7

DDR_B _DQS0
DDR_B _DQS#0
DDR_B _DQS1
DDR_B _DQS#1
DDR_B _DQS2
DDR_B _DQS#2
DDR_B _DQS3
DDR_B _DQS#3
DDR_B _DQS4
DDR_B _DQS#4
DDR_B _DQS5
DDR_B _DQS#5
DDR_B _DQS6
DDR_B _DQS#6
DDR_B _DQS7
DDR_B _DQS#7

JCP UC

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23

G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11

Y11
AE14
AF14
AF11
AD11

A12

B16

A22

E25
AB26
AE22
AC16
AD12

C12

B12

D16

C16

A24

A23

F26

E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

FOX_P Z6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MEM:DATA

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0

MA_DQS_L0

MA_DQS_H1

MA_DQS_L1

MA_DQS_H2

MA_DQS_L2

MA_DQS_H3

MA_DQS_L3

MA_DQS_H4

MA_DQS_L4

MA_DQS_H5

MA_DQS_L5

MA_DQS_H6

MA_DQS_L6

MA_DQS_H7

MA_DQS_L7

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_A _D10
DDR_A _D11
DDR_A _D12
DDR_A _D13
DDR_A _D14
DDR_A _D15
DDR_A _D16
DDR_A _D17
DDR_A _D18
DDR_A _D19
DDR_A _D20
DDR_A _D21
DDR_A _D22
DDR_A _D23
DDR_A _D24
DDR_A _D25
DDR_A _D26
DDR_A _D27
DDR_A _D28
DDR_A _D29
DDR_A _D30
DDR_A _D31
DDR_A _D32
DDR_A _D33
DDR_A _D34
DDR_A _D35
DDR_A _D36
DDR_A _D37
DDR_A _D38
DDR_A _D39
DDR_A _D40
DDR_A _D41
DDR_A _D42
DDR_A _D43
DDR_A _D44
DDR_A _D45
DDR_A _D46
DDR_A _D47
DDR_A _D48
DDR_A _D49
DDR_A _D50
DDR_A _D51
DDR_A _D52
DDR_A _D53
DDR_A _D54
DDR_A _D55
DDR_A _D56
DDR_A _D57
DDR_A _D58
DDR_A _D59
DDR_A _D60
DDR_A _D61
DDR_A _D62
DDR_A _D63

DDR_A_DM 0
DDR_A_DM 1
DDR_A_DM 2
DDR_A_DM 3
DDR_A_DM 4
DDR_A_DM 5
DDR_A_DM 6
DDR_A_DM 7

DDR_A _DQS0
DDR_A _DQS#0
DDR_A _DQS1
DDR_A _DQS#1
DDR_A _DQS2
DDR_A _DQS#2
DDR_A _DQS3
DDR_A _DQS#3
DDR_A _DQS4
DDR_A _DQS#4
DDR_A _DQS5
DDR_A _DQS#5
DDR_A _DQS6
DDR_A _DQS#6
DDR_A _DQS7
DDR_A _DQS#7

DDR_ A_D[63..0 ] <8>

DDR_A _DQS0 <8>
DDR_A _DQS#0 <8>
DDR_A _DQS1 <8>
DDR_A _DQS#1 <8>
DDR_A _DQS2 <8>
DDR_A _DQS#2 <8>
DDR_A _DQS3 <8>
DDR_A _DQS#3 <8>
DDR_A _DQS4 <8>
DDR_A _DQS#4 <8>
DDR_A _DQS5 <8>
DDR_A _DQS#5 <8>
DDR_A _DQS6 <8>
DDR_A _DQS#6 <8>
DDR_A _DQS7 <8>
DDR_A _DQS#7 <8>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

LA-4117P

5 56Monday, M arch 16, 2009

E

0.3

A

+2.5VS

C16

@

100U_D2_10VM

1 1

CLK_CP U_BCLK<15>

Plac e cl ose to C PU wihtin 1.5"

C20

0718 Silego -- 216 ohm

CLK_CP U_BCLK#<15>

+1.8VS

2 2

LDT_RST#<19>

H_PW RGD_CPU<19>

3 3

LDT_STOP#<11,19>

R15
300_0402_5%

1 2

LDT_RST#

1

C22

0.01U_0402_25V4 Z

@

2

+1.8VS

R21
300_0402_5%

1 2

H_PW RGD_CPU

1

C23

0.1U_0402_16V7K

2

+1.8VS

R36
300_0402_5%

1 2

LDT_STOP#

1

C25

0.01U_0402_25V4 Z

@

2

071 8 AMD , ne ed chec k wi th A MD

+1.8VS

R30
300_0402_5%

1 2

4 4

CPU_LDT_R EQ#

1

C24

0.01U_0402_25V4 Z

@

2

CPU_LD T_REQ# <11,19>

A

+CPU_C ORE_0

R487 10_0402_5%

1 2
1 2

R486 10_0402_5%

+CPU_C ORE_0

R489 10_0402_5%@

1 2
1 2

R488 10_0402_5% @

Rese rve the R 488 and R4 89 for S1G 3 CPU

+3VS

20K_0402_5%

R18

+1.8V

2.2K_0402_5%
R19

+1.8V

2.2K_0402_5%

CPU_S IC

+3VS

1

C26

2

0.1U_0402_16V4Z

C27

220 0p ch ange to
100 p

100P_0402_25V8K

CPU_V DD0_FB_H
CPU_V DD0_FB_L

Close to CPU

CPU_V DD1_FB_H
CPU_V DD1_FB_L

@

R175

@

Q127

12

FDV301N_NL_ SOT23-3

12

@

THERMDA_CPU

THERMD C_CPU

12

S

FDV301N_NL_ SOT23-3

Q129

C21 3900P_0402_50V7K

G

B

L1

1 2

FBM_L11_201209_300L_0805

1

+

2

3900P_0402_50V7K

1 2

12

R8
169_0402_1%

1 2

1 2
@

C939 0 .1U_0402_16V4Z

R814

@

12

34.8K_0402_1%~N

2

SMB_EC_DA1CPU_S ID

13

D

G

2

SMB_EC_CK1

13

D

S

EC is PU to 5VALW

FDV301 N, the Vgs is:
min = 0. 65V
Typ = 0.85V
Max = 1.5V

U2

1

VDD

D+

SDATA

ALERT#

D-

THERM#4GND

B

SCLK

2

3

ADM1032ARMZ-2REEL_MSOP8

Addres s:100_1101

+2.5VDDA

VDDA= 300mA

3300P_0402_50V7K

1

1

C174.7U_0805_10V4Z

C18

2

2

Addres s:100_1100

R13 44.2_0402_1%

1 2

R14 44.2_0402_1%

T4 PAD

T9 PAD
T11 PAD

1 2

CPU_V DD0_FB_H<43>
CPU_V DD0_FB_L<43>

+1.2V_HT

2.09V for Gate

SMB_EC_DA1 <32,33,34,37>

SMB_EC_CK1 <32,33,34,37>

8

7

6

5

SMB_EC_CK2 <33>

SMB_EC_DA2 <33>

C

1

C19

0.22U_0603_16V4 Z

2

CPU_C LKIN_SC_P
CPU_C LKIN_SC_N

LDT_RST#
H_PW RGD_CPU
LDT_STOP#
CPU_LDT_R EQ#

CPU_S IC
CPU_S ID

CPU_HTREF0
CPU_HTREF1

CPU_V DD0_FB_H
CPU_V DD0_FB_L

CPU_V DD1_FB_H

CPU _DBRD Y
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_T DI

CPU_TEST23_TSTUPD

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_T EST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_T EST22_SCANSHIFTEN
CPU_T EST12_SCANSHIFTENB
CPU_T EST27_SINGLECHAIN

R25 0_0402_5%

1 2

JCP UD

F8

VDDA1

F9

VDDA2

A9

CLKIN_H

A8

CLKIN_L

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

C6

LDTREQ_L

AF4

SIC

AF5

SID

AE6

ALERT_L

R6

HT_REF0

P6

HT_REF1

F6

VDD0_FB_H

E6

VDD0_FB_L

Y6

VDD1_FB_H

AB6

VDD1_FB_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

AD7

TEST23

H10

TEST18

G9

TEST19

E9

TEST25_H

E8

TEST25_L

AB8

TEST21

AF7

TEST20

AE7

TEST24

AE8

TEST22

AC8

TEST12

AF8

TEST27

C2

TEST9

AA6

TEST6

A3

RSVD1

A5

RSVD2

B3

RSVD3

B5

RSVD4

C1

RSVD5

FOX_P Z6382A-284S-41F_GRIFFIN

CONN@

THERMTRIP_L

PROCHOT_L

VDDIO_FB_H

VDDIO_FB_L

VDDNB_FB_H

VDDNB_FB_L

KEY1
KEY2

SVC
SVD

MEMHOT_L

THERMDC
THERMDA

DBREQ_L

TDO

TEST28_H

TEST28_L

TEST17
TEST16
TEST15
TEST14

TEST7

TEST10

TEST8

TEST29_H

TEST29_L

RSVD10

RSVD9
RSVD8
RSVD7
RSVD6

M11
W18

CPU_SVC

A6

CPU_SVD

A4

AF6
AC7
AA8

THERMD C_CPU

W7

THERMDA_CPU

W8

W9
Y9

VDD_N B_FB_H

H6

VDD_N B_FB_LCPU_V DD1_FB_L

G6

CPU_D BREQ#

E10

CPU_TDO

AE9

CPU_T EST28_H_PLLCHRZ_P

J7

CPU_T EST28_L_PLLCHRZ_N

H8

CPU_TEST17_BP3

D7

CPU_TEST16_BP2

E7

CPU_TEST15_BP1

F7

CPU_TEST14_BP0

C7

C3
K8

C4

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

H18
H19
AA7
D5
C5

02/15 Follow Trinity design.
02/15 Change R18 and R19
from 390 to 2.2K ohm.

03/04 Reserve R175, R814, C 939 , Q 127 and Q129.

+1.8V

R3822 0_0402_5%@

R4022 0_0402_5%@

R3922 0_0402_5%@

R3722 0_0402_5%@

12

12

12

12

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

HDT Connector

R4130 0_0402_5%

12

CONN@

9/2 0 SP0 200 16900

Compal Secret Data

CPU_SVC <43>
CPU_SVD <43>

CPU_THER MTRIP#_R
CPU_P ROCHOT#_1.8
CPU_MEMHOT#_1.8V

T42PAD
T43PAD

VDD_N B_FB_H <43>
VDD_N B_FB_L <43>

JP3

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

Deciphered Date

D

+1.8V

1 2

R10 10K_0402_5%

1 2

R5 300_0402_5%

CPU_THER MTRIP#_R

Q3

PMBT3904_SOT23

+1.8V

R11 10K_0402_5%@

R9 300_0402_5%

CP U_P RO CHOT #_1.8

CBE

123

1 2

02/12 Remove R59.

R17

12

300_0402_5%@

+1.8V

+1.8V sense no support

route as differential

T5PAD

as shor t as possible

T6PAD

testpoint under package

T7PAD
T8PAD
T10PAD
T12PAD

T13PAD
T14PAD

CPU_T EST27_SINGLECHAIN

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_T EST22_SCANSHIFTEN
CPU_T EST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

+3VS

5

HDT_RST#

D

U1

4

Y

LDT_RST#

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5@

3

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

E

02/27 Change net name to EN0.

R6 0_0402_5%@

1 2

1 2

R16 0_0402_5%

1 2

R7 0_0402_5%

12

B

2

E

3 1

1 2

R59 0_0402_5 %@

CPU_SVC
CPU_SVD

Q2

EN0 <37,39>

H_THERMTRIP#_EC <33>

H_THERMTRIP# <20>

MMBT3904_NL_SOT23-3@

C

R22 1K_0402_5%

1 2
1 2

R23 1K_0402_5%

H_PROCH OT# <19>

+1.8V

0718 AMD --> 1K ohm

+CPU_ CORE_NB

VDD_N B_FB_H
VDD_N B_FB_L

R484 10_040 2_5%

1 2
1 2

R485 10_040 2_5%

Close to CPU

+1.8V

R24 300_0402_5%@

1 2

R26 300_0402_5%

1 2

R27 300_0402_5%@
R28 300_0402_5%
R29 300_0402_5%@
R31 300_0402_5%@
R32 300_0402_5%@
R33 300_0402_5%@
R34 300_0402_5%@
R35 300_0402_5%@

SB_PW RGD <20,33,43>

12
12
12
12
12
12
12
12

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

LA-4117P

6 56Monday, M arch 16, 2009

E

0.3

A

B

C

D

E

01/1 8 Ch ang e the net name from +CPU_ CORE_1 to +CPU_CORE _0

18A /72 0mil /36v ias

VDD(+CPU_CORE) decoupling.

+CPU_C ORE_0

1

+

1 1

C30
330U_X_2VM_R6M

2

01/1 8 Ch ang e the net name from +CPU_ CORE_1 to +CPU_CORE _0

+CPU_C ORE_0

1

+

C28
330U_X_2VM_R6M

2

1

+

C31
330U_X_2VM_R6M

2

1

+

2

C29
330U_X_2VM_R6M

Near CPU Socket

Tigr is p latform wi ll be 4A

+CPU_C ORE_0

1

C32
22U_0805_6.3V6M

2

+CPU_C ORE_0

1

C40

0.22U_0603_16V4 Z

2

2 2

1

C33
22U_0805_6.3V6M

2

1

C41

0.01U_0402_25V4 Z

2

1

C34
22U_0805_6.3V6M

2

1

2

1

C35
22U_0805_6.3V6M

2

C42
180P_0402_50V8J

Under CPU Socket

+CPU_C ORE_0

1

C36
22U_0805_6.3V6M

2

+CPU_C ORE_0

1

2

1

2

C43

0.22U_0603_16V4 Z

C37
22U_0805_6.3V6M

1

C44

0.01U_0402_25V4 Z

2

1

C38
22U_0805_6.3V6M

2

1

2

1

C39
22U_0805_6.3V6M

2

C45
180P_0402_50V8J

L

4A/ 16 0mil/8vias

L

L

+CPU_ CORE_NB

+1.8V

3A/ 12 0mil/6vias

JCPUE

G4

VDD0_1

H2

VDD0_2

J9

VDD0_3

J11

VDD0_4

J13

VDD0_5

J15

VDD0_6

K6

VDD0_7

K10

VDD0_8

K12

VDD0_9

K14

VDD0_10

L4

VDD0_11

L7

VDD0_12

L9

VDD0_13

L11

VDD0_14

L13

VDD0_15

L15

VDD0_16

M2

VDD0_17

M6

VDD0_18

M8

VDD0_19

M10

VDD0_20

N7

VDD0_21

N9

VDD0_22

N11

VDD0_23

K16

VDDNB_1

M16

VDDNB_2

P16

VDDNB_3

T16

VDDNB_4

V16

VDDNB_5

H25

VDDIO1

J17

VDDIO2

K18

VDDIO3

K21

VDDIO4

K23

VDDIO5

K25

VDDIO6

L17

VDDIO7

M18

VDDIO8

M21

VDDIO9

M23

VDDIO10

M25

VDDIO11

N17

VDDIO12

FOX_P Z6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+CPU_C ORE_0+CPU_C ORE_0

+1.8V

+CPU_CORE_NB decoupling.

VDDIO decoupling.

+1.8V

1

C46
22U_0805_6.3V6M

2

3 3

+1.8V

1

C55

0.22U_0603_16V4 Z

2

+1.8V +1.8V

1

C60

0.01U_0402_25V4 Z

2

4 4

+1.8V

1

C74

4.7U_0805_10V4Z

2

1

C47
22U_0805_6.3V6M

2

1

C48

0.22U_0603_16V4 Z

2

1

C49

0.22U_0603_16V4 Z

2

Under CPU Socket

Between CPU Socket and DIMM

1

C56

0.22U_0603_16V4 Z

2

1

C61

0.01U_0402_25V4 Z

2

1

2

A

C75

4.7U_0805_10V4Z

1

C57

0.22U_0603_16V4 Z

2

180 PF Qt 'y fo ll ow the dis tanc e bet ween
CPU s ock et an d DIMM 0. < 2.5i nch>

1

C62
180P_0402_50V8J

2

1

C76

4.7U_0805_10V4Z

2

1

C58

0.22U_0603_16V4 Z

2

1

C63
180P_0402_50V8J

2

A: Ad d C 16 5 an d C1 76
to fo llo w AMD Layo ut
rev ie w r ec omma nd f or
EMI

1

C77

4.7U_0805_10V4Z

2

1

C50

180P_0402_50V8J

2

1

2

1

C64
180P_0402_50V8J

2

1

C: Ch ang e to N BO C AP

+

C78
220U_Y_4VM

@

2

B

C51

180P_0402_50V8J

1

2

C65
180P_0402_50V8J

+CPU_ CORE_NB

@

1

C52
22U_0805_6.3V6M

2

1

C53
22U_0805_6.3V6M

2

VTT decoupling.

+0.9V

1

C66

4.7U_0805_10V4Z

2

+0.9V

1

C79

4.7U_0805_10V4Z

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C67

4.7U_0805_10V4Z

2

Near CPU Socket Right side.

1

C80

4.7U_0805_10V4Z

2

Near CPU Socket Left side.

2007/08/02 2008/08/02

C

1

2

1

C68

0.22U_0603_16V4 Z

2

1

C81

0.22U_0603_16V4 Z

2

C54
22U_0805_6.3V6M

+0.9V

Near Power Supply

1

C: Ch ang e to N BO C AP

+

C59
220U_Y_4VM

2

1

C69

0.22U_0603_16V4 Z

2

1

C82

0.22U_0603_16V4 Z

2

Compal Secret Data

Deciphered Date

1

C70
1000P_0402_25V8J

2

1

C83
1000P_0402_25V8J

2

D

1

C71
1000P_0402_25V8J

2

1

C84
1000P_0402_25V8J

2

1

C72
180P_0402_50V8J

2

1

C85
180P_0402_50V8J

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet

JCP UF

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

FOX_P Z6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

1

C73
180P_0402_50V8J

2

1

C86
180P_0402_50V8J

2

VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

VSS72

VSS73

VSS74

VSS75

VSS76

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS88

VSS89

VSS90

VSS91

VSS92

VSS93

VSS94

VSS95

VSS96

VSS97

VSS98

VSS99

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

LA-4117P

E

of

7 56Monday, M arch 16, 2009

0.3

A

DDR_A _D0
DDR_A _D1

1 1

2 2

DDR_CKE 0_DIMMA<5>

DDR_A_BS #2<5>

DDR_A_BS #0<5>
DDR_A_W E#<5>

DDR_A _CAS#<5>
DDR_C S1_DIMMA#<5>

DDR_A _ODT1<5>

3 3

SMB_CK_DAT0<9,15,20,30>
SMB_CK_CLK0<9,1 5,20,30>

4 4

A

+3VS

DDR_A _DQS#0
DDR_A _DQS0

DDR_A _D2
DDR_A _D3

DDR_A _D8
DDR_A _D9

DDR_A _DQS#1
DDR_A _DQS1

DDR_A _D10
DDR_A _D11

DDR_A _D16 DDR_A _D20
DDR_A _D17

DDR_A _DQS#2
DDR_A _DQS2

DDR_A _D18
DDR_A _D19

DDR_A _D24
DDR_A _D25

DDR_A_DM 3

DDR_A _D26
DDR_A _D27

DDR_CKE 0_DIMMA

DDR_A_BS #2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1 DDR_A_MA0

DDR_A_MA10
DDR_A_BS #0
DDR_A_W E#

DDR_A _CAS# DDR_A _ODT0
DDR_C S1_DIMMA#

DDR_A _ODT1

DDR_A _D32
DDR_A _D33

DDR_A _DQS#4
DDR_A _DQS4

DDR_A _D34
DDR_A _D35

DDR_A _D40
DDR_A _D41

DDR_A_DM 5

DDR_A _D42
DDR_A _D43

DDR_A _D48
DDR_A _D49

DDR_A _DQS#6
DDR_A _DQS6

DDR_A _D50
DDR_A _D51

DDR_A _D56
DDR_A _D57

DDR_A_DM 7

DDR_A _D58
DDR_A _D59

1

C103

0.1U_0402_16V4Z

2

B

+V_DD R_MCH_REF

JP4

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-N8RN -7F

CONN @

9/2 0 SP0 70 00B Z0 0/SP0 7000 EU00
DDR 2 SOC KE T H 9.2 ( REV)

B

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS

DM2
VSS

VSS

VSS

VSS

VSS

VDD

VDD

VDD

VDD
BA1

VDD

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SA0
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+1.8V+1.8V

C

DDR_A _D4
DDR_A _D5

DDR_A_DM 0

DDR_A _D6
DDR_A _D7

DDR_A _D12
DDR_A _D13

DDR_A_DM 1

DDR_A _D14
DDR_A _D15

DDR_A _D21

DDR_A_DM 2

DDR_A _D22
DDR_A _D23

DDR_A _D28
DDR_A _D29

DDR_A _DQS#3
DDR_A _DQS3

DDR_A _D30
DDR_A _D31

DDR_CKE 1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_BS #1
DDR_A _RAS#
DDR_C S0_DIMMA#

DDR_A_MA13

DDR_A _D36
DDR_A _D37

DDR_A_DM 4

DDR_A _D38
DDR_A _D39

DDR_A _D44
DDR_A _D45

DDR_A _DQS#5
DDR_A _DQS5

DDR_A _D46
DDR_A _D47

DDR_A _D52
DDR_A _D53

DDR_A_DM 6

DDR_A _D54
DDR_A _D55

DDR_A _D60
DDR_A _D61

DDR_A _DQS#7
DDR_A _DQS7

DDR_A _D62
DDR_A _D63

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR _A_D[0..6 3]

DDR_A _DM[0..7]

DDR _A_DQS[0. .7]

DDR_A _MA[0..15]

DDR_A _DQS#[0.. 7]

DDR_A _CLK0 <5>
DDR_A _CLK#0 <5>

+V_DD R_MCH_REF

1

C95

2

1000P_0402_25V8J

0.1U_0402_16V4Z

DDR_CKE 1_DIMMA <5>

DDR_A_BS #1 < 5>
DDR_A _RAS# <5>
DDR_CS0_D IMMA# <5>

DDR_A_ODT0 <5>

DDR_A _CLK1 <5>
DDR_A _CLK#1 <5>

C

DDR _A_D[0..6 3] <5>

DDR_A _DM[0..7] <5>

DDR_ A_DQS[0.. 7] <5>

DDR_A _MA[0..15] <5>

DDR_A _DQS#[0.. 7] <5>

+1.8V

R43
1K_0402_1%

1 2

1

C96

2

2007/08/02 2008/08/02

+V_DD R_MCH_REF <9>

R44
1K_0402_1%

1 2

Compal Secret Data

Deciphered Date

D

+0.9V

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_CKE 0_DIMMA
DDR_A_BS #2
DDR_CKE 1_DIMMA
DDR_A_MA15

DDR_A_MA4
DDR_A_MA2
DDR_A_BS #1
DDR_A_MA0

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

DDR_A_BS #0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

DDR_A _ODT1
DDR_C S1_DIMMA#
DDR_A_W E#
DDR_A _CAS#

DDR_C S0_DIMMA#
DDR_A _RAS#
DDR_A_MA13
DDR_A _ODT0

D

RP1

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

45

RP2

18
27
36
45

RP3

18
27
36
45

RP4

18
27
36
45

RP5

18
27
36
45

RP6

18
27
36
45

RP7

18
27
36
45

Compal Electronics, Inc.

DDRII SO-DIMM 0

LA-4117P

E

1 2

C87 0.1U_0402_16V4Z

1 2

C88 0.1U_0402_16V4Z

1 2

C90 0.1U_0402_16V4Z

1 2

C89 0.1U_0402_16V4Z

1 2

C91 0.1U_0402_16V4Z

1 2

C92 0.1U_0402_16V4Z

1 2

C93 0.1U_0402_16V4Z

1 2

C94 0.1U_0402_16V4Z

1 2

C98 0.1U_0402_16V4Z

1 2

C97 0.1U_0402_16V4Z

1 2

C100 0.1U_0402_16V 4Z

1 2

C99 0.1U_0402_16V4Z

1 2

C102 0.1U_0402_16V 4Z

1 2

C101 0.1U_0402_16V 4Z

E

+1.8V

0.3

8 56Monday, M arch 16, 2009

A

B

C

D

E

JP5

+V_DD R_MCH_REF<8>

1

C104

1 1

2 2

3 3

4 4

1000P_0402_25V8J

DDR_CKE 0_DIMMB<5>

DDR_B_BS #2<5>

DDR_B_BS #0<5>
DDR_B_W E#<5>

DDR_B _CAS#<5>
DDR_C S1_DIMMB#<5>

DDR_B _ODT1<5>

SMB_CK_DAT0<8,15,20,30>
SMB_CK_CLK0<8,1 5,20,30>

2

DDR_B _D0
DDR_B _D1

DDR_B _DQS#0
DDR_B _DQS0

DDR_B _D2
DDR_B _D3

DDR_B _D8
DDR_B _D13

DDR_B _DQS#1
DDR_B _DQS1

DDR_B _D10
DDR_B _D11

DDR_B _D21
DDR_B _D17

DDR_B _DQS#2
DDR_B _DQS2

DDR_B _D18 DDR_B _D22
DDR_B _D19

DDR_B _D24
DDR_B _D25

DDR_B_DM 3

DDR_B _D26
DDR_B _D27

DDR_CKE 0_DIMMB

DDR_B_BS #2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS #0
DDR_B_W E#

DDR_B _CAS# DDR_B _ODT0
DDR_C S1_DIMMB#

DDR_B _ODT1

DDR_B _D32
DDR_B _D33

DDR_B _DQS#4
DDR_B _DQS4

DDR_B _D34
DDR_B _D35

DDR_B _D40
DDR_B _D41

DDR_B_DM 5

DDR_B _D42
DDR_B _D43 DDR_B _D47

DDR_B _D48
DDR_B _D49 DDR_B _D53

DDR_B _DQS#6
DDR_B _DQS6

DDR_B _D50
DDR_B _D51 DDR_B _D55

DDR_B _D56
DDR_B _D57

DDR_B_DM 7

DDR_B _D58
DDR_B _D59

+3VS

0.1U_0402_16V4Z

C119

1

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_292527-4

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1
RAS#

S0#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

GND

NC

A7
A6

A4
A2
A0

NC

9/2 0 SP0 70 00E T0 0/SP0 7000 GN00

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_B _D4
DDR_B _D5

DDR_B_DM 0

DDR_B _D6
DDR_B _D7

DDR_B _D12
DDR_B _D9

DDR_B_DM 1

DDR_B _D14
DDR_B _D15

DDR_B _D20
DDR_B _D16

DDR_B_DM 2

DDR_B _D23

DDR_B _D28
DDR_B _D29

DDR_B _DQS#3
DDR_B _DQS3

DDR_B _D30
DDR_B _D31

DDR_CKE 1_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS #1
DDR_B _RAS#
DDR_C S0_DIMMB#

DDR_B_MA13

DDR_B _D36
DDR_B _D37

DDR_B_DM 4

DDR_B _D38
DDR_B _D39

DDR_B _D44
DDR_B _D45

DDR_B _DQS#5
DDR_B _DQS5

DDR_B _D46

DDR_B _D52

DDR_B_DM 6

DDR_B _D54

DDR_B _D60
DDR_B _D61

DDR_B _DQS#7
DDR_B _DQS7

DDR_B _D62
DDR_B _D63

+3VS

DDR _B_D[0..6 3]

DDR_B _DM[0..7]

DDR _B_DQS[0. .7]

DDR_B _MA[0..15]

DDR_B _DQS#[0.. 7]

DDR_B _CLK0 <5>
DDR_B _CLK#0 <5>

DDR_CKE 1_DIMMB <5>

DDR_B_BS #1 <5>
DDR_B _RAS# <5>
DDR_C S0_DIMMB# <5>

DDR_B _ODT0 <5>

DDR_B _CLK1 <5>
DDR_B _CLK#1 <5>

DDR_ B_D[0..63 ] <5>

DDR_B _DM[0..7] <5>

DDR_B _DQS[0..7 ] <5>

DDR_B _MA[0..15] <5>

DDR_B _DQS#[0.. 7] <5>

DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_C S0_DIMMB#

DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4

DDR_CKE 1_DIMMB
DDR_B_MA15
DDR_CKE 0_DIMMB
DDR_B_BS #2

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_MA10
DDR_B_BS #0
DDR_B_MA1
DDR_B_MA3

DDR_B _ODT1
DDR_C S1_DIMMB#
DDR_B _CAS#
DDR_B_W E#

DDR_B _RAS#
DDR_B_BS #1
DDR_B _ODT0
DDR_B_MA13

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

RP8

RP9

RP10

RP11

RP12

RP13

RP14

+0.9V

18

C105 0.1U_0402_16V 4Z

27
36

1 2

C106 0.1U_0402_16V 4Z

45

18

C108 0.1U_0402_16V 4Z

27

1 2

36

C107 0.1U_0402_16V 4Z

45

18

C109 0.1U_0402_16V 4Z

27
36

1 2

C110 0.1U_0402_16V 4Z

45

18

C111 0.1U_0402_16V 4Z

27
36

1 2

C112 0.1U_0402_16V 4Z

45

18

C114 0.1U_0402_16V 4Z

27

1 2

36

C113 0.1U_0402_16V 4Z

45

18

C116 0.1U_0402_16V 4Z

27

1 2

36

C115 0.1U_0402_16V 4Z

45

18

C118 0.1U_0402_16V 4Z

27
36

1 2

C117 0.1U_0402_16V 4Z

45

12

12

12

12

12

12

12

+1.8V

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

DDRII SO-DIMM 1

LA-4117P

9 56Monday, M arch 16, 2009

E

0.3

A

U3B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

AE3
AD4
AE2
AD3
AD1
AD2

AA8

AA7

AA5
AA6

H5
H6

J6
J5
J7
J8
L5
L6

M8

L8
P7

M7

P5
M5
R8

P8
R6
R5

P4

P3

T4

T3

V5
W6
U5
U6
U8
U7

Y8

Y7

W5

Y5

GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

1 1

PCIE_PTX_C_IRX_P0<26>
PCIE_PTX_C_IRX_N0<26>
PCIE_PTX_C_IRX_P1<27>
PCIE_PTX_C_IRX_N1<27>
PCIE_PTX_C_IRX_P2<26>
PCIE_PTX_C_IRX_N2<26>
PCIE_PTX_C_IRX_P3<25>

2 2

PCIE_PTX_C_IRX_N3<25>

PCIE_PTX_C_IRX_P5<26>
PCIE_PTX_C_IRX_N5<26>

SB_RX0P<19>
SB_RX0N<19>
SB_RX1P<19>
SB_RX1N<19>
SB_RX2P<19>
SB_RX2N<19>
SB_RX3P<19>
SB_RX3N<19>

PAR T 2 O F 6

PCIE I/F GFX

PC IE I/ F GP P

PCI E I/F SB

PCE_CALRP(PCE_BCALR P)
PCE_CALRN(PCE_BCALR N)

RS880M_FCBGA528

RS780 M Displa y Port Suppor t (muxed on GFX)

DP0

DP1

3 3

9/2 0 SA0 00 01Z G0 0( A11 ) S I C 216 -067 4001 -00/ RS780 M FC BGA5 28P 0FH

GFX_TX0,TX1,TX2 and TX3

AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7

AUX1 and HPD1

B

GFX_TX0P

GFX_TX0N

GFX_TX1P

GFX_TX1N

GFX_TX2P

GFX_TX2N

GFX_TX3P

GFX_TX3N

GFX_TX4P

GFX_TX4N

GFX_TX5P

GFX_TX5N

GFX_TX6P

GFX_TX6N

GFX_TX7P

GFX_TX7N

GFX_TX8P

GFX_TX8N

GFX_TX9P

GFX_TX9N

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

GFX_TX15P

GFX_TX15N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_ITX_PRX_P0

AC1

PCIE_ITX_PRX_N0

AC2

PCIE_ITX_PRX_P1

AB4

PCIE_ITX_PRX_N1

AB3

PCIE_ITX_PRX_P2

AA2

PCIE_ITX_PRX_N2

AA1

PCIE_ITX_PRX_P3

Y1

PCIE_ITX_PRX_N3

Y2
Y4
Y3

PCIE_ITX_PRX_P5

V1

PCIE_ITX_PRX_N5

V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5

AC8
AB8

TMDS_B_DATA2 <18>
TMDS_B_DATA2# <18>
TMDS_B_DATA1 <18>
TMDS_B_DATA1# <18>
TMDS_B_DATA0 <18>
TMDS_B_DATA0# <18>
TMDS_B_CLK <18>
TMDS_B_CLK# <18>

C152 0.1U_0402_16V7K
C153 0.1U_0402_16V7K
C154 0.1U_0402_16V7K
C155 0.1U_0402_16V7K
C156 0.1U_0402_16V7K
C157 0.1U_0402_16V7K
C158 0.1U_0402_16V7K
C159 0.1U_0402_16V7K

C160 0.1U_0402_16V7K
C161 0.1U_0402_16V7K

C162 0.1U_0402_16V7K
C163 0.1U_0402_16V7K
C164 0.1U_0402_16V7K
C165 0.1U_0402_16V7K
C166 0.1U_0402_16V7K
C168 0.1U_0402_16V7K
C169 0.1U_0402_16V7K
C167 0.1U_0402_16V7K

R55 1.27K_0402_1%

1 2

R56 2K_0402_1%

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

+1.1VS

C

PCIE_ITX_C_PRX_P0 <26>
PCIE_ITX_C_PRX_N0 <26>
PCIE_ITX_C_PRX_P1 <27>
PCIE_ITX_C_PRX_N1 <27>
PCIE_ITX_C_PRX_P2 <26>
PCIE_ITX_C_PRX_N2 <26>
PCIE_ITX_C_PRX_P3 <25>
PCIE_ITX_C_PRX_N3 <25>

PCIE_ITX_C_PRX_P5 <26>
PCIE_ITX_C_PRX_N5 <26>

SB_TX0P <19>
SB_TX0N <19>
SB_TX1P <19>
SB_TX1N <19>
SB_TX2P <19>
SB_TX2N <19>
SB_TX3P <19>
SB_TX3N <19>

New Card

CardReader

WLAN

LAN10/100

TV Tuner

H_CLKOP0<4>
H_CLKON0<4>
H_CLKOP1<4>
H_CLKON1<4>

H_CTLOP0<4>
H_CTLON0<4>

H_CTLON1<4>

0718 Place within 1"
layout 1:2

H_CAD OP[0..15]<4>

H_C ADON[0..15 ]<4> H_C ADIN[0. .15] <4>

H_CAD OP10
H_CAD ON10
H_CAD OP11
H_CAD ON11
H_CAD OP12
H_CAD ON12
H_CAD OP13
H_CAD ON13
H_CAD OP14
H_CAD ON14
H_CAD OP15
H_CAD ON15

H_CTLOP0
H_CTLON0
H_CTLOP1

R57 301_0402_1%

1 2

H_CAD OP0
H_CAD ON0
H_CAD OP1
H_CAD ON1
H_CAD OP2
H_CAD ON2
H_CAD OP3
H_CAD ON3
H_CAD OP4
H_CAD ON4
H_CAD OP5
H_CAD ON5
H_CAD OP6
H_CAD ON6
H_CAD OP7
H_CAD ON7

H_CAD OP8
H_CAD ON8
H_CAD OP9
H_CAD ON9

D

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

H_ CADON[0..1 5]

U3A

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS880M_FCBGA528

PAR T 1 O F 6

HYPER TRANSPORT CPU I/F

H_ CADIP[0..1 5]H_ CADOP[0..1 5]

H_C ADIN[0 ..15]

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

HT_TXCALP
HT_TXCALN

E

H_C ADIP[0..15 ] <4>

H_CAD IP0

D24

H_C ADIN0

D25

H_CAD IP1

E24

H_C ADIN1

E25

H_CAD IP2

F24

H_C ADIN2

F25

H_CAD IP3

F23

H_C ADIN3

F22

H_CAD IP4

H23

H_C ADIN4

H22

H_CAD IP5

J25

H_C ADIN5

J24

H_CAD IP6

K24

H_C ADIN6

K25

H_CAD IP7

K23

H_C ADIN7

K22

H_CAD IP8

F21

H_C ADIN8

G21

H_CAD IP9

G20

H_C ADIN9

H21

H_CAD IP10

J20

H_CAD IN10

J21

H_CAD IP11

J18

H_CAD IN11

K17

H_CAD IP12

L19

H_CAD IN12

J19

H_CAD IP13

M19

H_CAD IN13

L18

H_CAD IP14

M21

H_CAD IN14

P21

H_CAD IP15

P18

H_CAD IN15

M18

H24
H25
L21
L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1H_CTLON1

R18

B24
B25

0718 Place within 1"
layout 1:2

H_CLK IP0 <4>
H_CLK IN0 <4>
H_CLK IP1 <4>
H_CLK IN1 <4>

H_CTLIP0 <4>

H_CTL IN0 <4>

H_CTLIP1 <4>H_CTLOP1<4>

H_CTL IN1 <4>

R58 301_0402_1%

1 2

NEED CHECK R68 & R69 WITH AMD

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RS880-HT/PCIE

LA-4117P

10 56Monday, Marc h 16, 2009

E

0.3

A

1 1

R67

LDT_STOP#<6,19>

CPU_LDT_R EQ#<6,19>

2 2

3 3

1 2

0_0402_5%

R68

1 2

0_0402_5%

+1.8VS

BLM18PG121SN1D_0603

NB_LDTSTOP#

NB_ALLOW_LDTSTOP

+1.8VS

+1.8VS

1 2

BLM18PG121SN1D_0603

L11

1 2

C180

2.2U_0 603_6.3V4Z

1 2

+1.1VS

4.7K_0402_5%

1 2

1 2

1 2

+1.1VS

1 2

BLM18PG121SN1D_0603

L7

1 2

BLM18PG121SN1D_0603

L10

1

C179

2.2U_0 603_6.3V4Z

1

2

2

R71

1 2

R62 150_0402_1%@

R63 150_0402_1%@

R64 150_0402_1%@

C176

2.2U_0 603_6.3V4Z

R72

4.7K_0402_5%

+1.8VS

L9

1

2

B

+1.8VS

L6

1 2

BLM18PG121SN1D_0603

2.2U_0 603_6.3V4Z

RED

GREEN

BLUE

1

C178

2.2U_0 603_6.3V4Z

2

+NB_PLLVDD
+NB_HTPVDD

+VDDA18HTPLL

+VDDA 18PCIEPLL

PLT_RST#<14,1 9,25,26,27,32,33>

NB_PW RGD<20>

+1.8VS

R371 300_0402_5%

CLK_NBHT<15>
CLK_NBHT#<15>

NB_OSC_14.318M<15>

NBGFX_CLK<15>
NBGFX_CLK#<15>

CLK_S BLINK_BCLK<15>
CLK_SB LINK_BCLK#<15>

LCD_D DC_CLK<17>

LCD_D DC_DAT<17>
HDMIDAT_UMA<18>
HDMICLK_UMA<18>

+3VS

1 2

BLM18PG121SN1D_0603

L4

0_0603_5%

+AVDDQ

1

C175

2

T46 PAD
T47 PAD
T48 PAD

RED<16>

GREEN<16>

BLUE<16>

CRT _HSYNC<14,16>

CRT_ VSYNC<14,16>
UMA_CRT_CLK<16>
UMA_CRT_DAT<16>

R65 715_0402_1%

R66 0_0402_5%

1 2

1 2

RS780_D FT_GPIO_0<14>

+3VS

L2

+AVDD1

+AVDD2

1

C172

2.2U_0 603_6.3V4Z

2

RED

GREEN

BLUE

1 2

NB_RESET#
NB_PW RGD
NB_LDTSTOP#

NB_ALLOW_LDTSTOP

Strap pin

R88 10K_0402_5%

AUX_CAL<14>

Strap pin

AVDD= 100mA

1

2

TV_CRMA
TV_LUMA
TV_COMPS

CR T_HSYNC
CRT_V SYNC

12

C170

2.2U_0 603_6.3V4Z

U3C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLK P)

V3

GPPSB_REFCLKN(SB_REFCLK N)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS880M_FCBGA528

C

PAR T 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

TXOUT_L0P(NC)

TXOUT_L0N(NC)

TXOUT_L1P(NC)

TXOUT_L1N(NC)

TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM _GPIO2)

CLOCKs PLL PWR

MIS.

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

HPD(NC)

THERMALDIODE_P
THERMALDIODE_N

TESTMODE

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9

NB_PWM

F7
G12

D9
D10

D12

NB_THERMAL_DA

AE8

NB_THERMAL_DC

AD8

D13

1 2

R80

1.8K_0402_5%

D

LVDS_A0+ <17>
LVDS_A0- <17>
LVDS_A1+ <17>
LVDS_A1- <17>
LVDS_A2+ <17>
LVDS_A2- <17>

LVDS_ACLK+ <17>
LVDS_ACLK- <17>

+VDDLTP18

+VDDLT18

C173

0.1U_0402_16V4Z

R69 0_0402_5%

1 2

1 2

R73

1 2

R1072 100K_0402_5%

1 2

R77 0_0402_5 %

PA_RS780A4
placement close to NB ball

L3

1 2

BLM18PG121SN1D_0603

1

C171

2.2U_0 603_6.3V4Z

2

1

1

2

2

L

1 2

BLM18PG121SN1D_0603

C174

4.7U_0805_10V4Z

0.0 8A /10mil/1 vias

1

C1120

0.1U_0402_16V4Z

2

L5

+1.8VS

Ripe ly 2 .0 su pport Veri -Bright fu nction

0_0402_5%

HPD <18>

SUS_STAT_R# <14>
SUS_STAT# <20>

T49PAD
T50PAD

UMA_ENVDD <17>

ENBKL <33>

Strap pin

NB t emp to SB

R

Veri-Bright Non Veri-Bright

R1085 0_0402_5%@

R1086 100K_0402_5%@

NB_PWM <17>

1 2

1 2

R73
R1072
R1085
R1086

@
@

E

+1.8VS

ENBKL

@
@

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RS880 VEDIO/CLK GEN

LA-4117P

11 56Monday, Marc h 16, 2009

E

0.3

A

B

C

D

E

MEM_BA0
MEM_BA1

MEM_A12

1 1

12

R91

100_0402_1%

2 2

MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1
MEM_A0

MEM_CLKN
MEM_CLKP

MEM_CKE

MEM_CS#

MEM_WE#

MEM_RAS#

MEM_CAS#

MEM_DM0
MEM_DM1

MEM_ODT

MEM_DQS_P0
MEM_DQS_N0

MEM_DQS_P1
MEM_DQS_N1

+MEM_VREF

MEM_BA2

Supp ort 8M x 16 bit x 8 ba nk side po rt

U61

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC

E2

NC

L1

NC

R3

NC

R7

NC

R8

NC

HY5PS5 61621AFP-25_FBGA84

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD

VDDL

VSSDL

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS

MEM_DQ12

B9

MEM_DQ13

B1

MEM_DQ9

D9

MEM_DQ14

D1

MEM_DQ15

D3

MEM_DQ8

D7

MEM_DQ10

C2

MEM_DQ11

C8

MEM_DQ5

F9

MEM_DQ2

F1

MEM_DQ6

H9

MEM_DQ1

H1

MEM_DQ0

H3

MEM_DQ4

H7

MEM_DQ3

G2

MEM_DQ7

G8

+VDDL

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

1

C184

2

Layout Note: 50 mil for VSSDL

02/15 Remove L96.

1U_0603_10V6K

R92 40.2_0402_1%

R93 40.2_0402_1%

+1.8V_MEM_VDDQ

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

12

12

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

MEM_COMP_P

MEM_COMP_N

U3D

AB12

MEM_A0(NC)

AE16

MEM_A1(NC)

V11

MEM_A2(NC)

AE15

MEM_A3(NC)

AA12

MEM_A4(NC)

AB16

MEM_A5(NC)

AB14

MEM_A6(NC)

AD14

MEM_A7(NC)

AD13

MEM_A8(NC)

AD15

MEM_A9(NC)

AC16

MEM_A10(NC)

AE13

MEM_A11(NC)

AC14

MEM_A12(NC)

Y14

MEM_A13(NC)

AD16

MEM_BA0(NC)

AE17

MEM_BA1(NC)

AD17

MEM_BA2(NC)

W12

MEM_RASb(NC)

Y12

MEM_CASb(NC)

AD18

MEM_WEb(NC)

AB13

MEM_CSb(NC)

AB18

MEM_CKE(NC)

V14

MEM_ODT(NC)

V15

MEM_CKP(NC)

W14

MEM_CKN(NC)

AE12

MEM_COMPP(NC)

AD12

MEM_COMPN(NC)

RS880M_FCBGA528

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)

MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)

MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)

MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)

MEM_DQS1N(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

MEM_VREF(NC)

MEM_DQ4(NC)

MEM_DM0(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

MEM_DQ0

AA18

MEM_DQ1

AA20

MEM_DQ2

AA19

MEM_DQ3

Y19

MEM_DQ4

V17

MEM_DQ5

AA17

MEM_DQ6

AA15

MEM_DQ7

Y15

MEM_DQ8

AC20

MEM_DQ9

AD19

MEM_DQ10

AE22

MEM_DQ11

AC18

MEM_DQ12

AB20

MEM_DQ13

AD22

MEM_DQ14

AC22

MEM_DQ15

AD21

MEM_DQS_P0

Y17

MEM_DQS_N0

W18
AD20
AE21

W17
AE19

AE23
AE24

AD23

AE18

MEM_DQS_P1
MEM_DQS_N1

MEM_DM0
MEM_DM1

+NB_I OPLLVDD

+MEM_VREF1

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

1 2

0_0603_5%

1

C181

2.2U_0 603_6.3V4Z

2

L13

+1.8V_ IOPLLVDD

1

C182

0.1U_0402_16V4Z

2

+1.1VS

L12

1 2

0_0603_5%

1

C183

2.2U_0 603_6.3V4Z

2

02/15 Change L12 and L13 fr om bea d t o 0 oh m resistor.

+1.8VS

9/2 0 SA0 00 012 G2 0 S I C D2 32 M16 HY5P S1216 21CF P-25 FBG A 84 P

3 3

1

C195

2

R96

1 2

1K_0402_1%

0.1U_0402_16V4Z

+MEM_VREF

1

C199

2

R98

0.1U_0402_16V4Z

1 2

1K_0402_1%

4 4

A

Side Port d isable,VREF need
connect to +1.8VS for DDR2

+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ

1

C196

2

R97

1 2

1K_0402_1%

0.1U_0402_16V4Z

+MEM_VREF1

1

C200

2

R99

0.1U_0402_16V4Z

1 2

1K_0402_1%

B

+1.8V_MEM_VDDQ

2

C608

1

2

C607

1

1U_0402_6.3V4Z

1

C201

2

1U_0402_6.3V4Z

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

1

C203

C202

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2007/08/02 2008/08/02

L15

1 2

0_0805_5%

220 ohm @ 100MHz,2A

22U_0805_6.3V6M

Compal Secret Data

Deciphered Date

+1.8VS

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RS880 Side-Port DDR2 SDRAM

LA-4117P

12 56Monday, Marc h 16, 2009

E

0.3

A

B

C

D

E

1 1

0.6 A/ 50mi l/4v ias

12

12

2A

C215

4.7U_0805_10V4Z

2A

12

1

C235

2

4.7U_0805_10V4Z

L

2A

0.1U_0402_16V4Z
C206

1

C209

2

0.4 5A /40mil/3 vias

L

0.1U_0402_16V4Z

1

1

C214

2

2

0.1U_0402_16V4Z

0.5 A/ 50mi l/4v ias

L

2A

1

C225

C226

2

0.1U_0402_16V4Z

0.2 5A /30mil/2 vias

L

1

C236

C246

2

0.1U_0402_16V4Z

+1.8VS

C251

1U_04 02_6.3V4Z

1

C207

2

0.1U_0402_16V4Z

1

C216

2

1

C227

2

0.1U_0402_16V4Z

1

C237

2

0.1U_0402_16V4Z

+1.8VS

1

2

0.1U_0402_16V4Z
C208

1

1

2

2

0.1U_0402_16V4Z
C217

1

2

1

1

C228

C229

2

2

0.1U_0402_16V4Z

1

1

C239

C238

2

2

0.1U_0402_16V4Z

1 2

R1051 0_0603_5%

+VDDHT

1

C210

0.1U_0402_16V4Z

2

+VDDHTRX

1

C218

0.1U_0402_16V4Z

2

+VDDHTTX

1

2

0.1U_0402_16V4Z

+VDDA 18PCIE

1

2

0.1U_0402_16V4Z

+1.8V_VDD_SP

J17
K16
L16

M16

P16

R16

T16

H18
G19

F20
E21

D22

B23
A23

AE25
AD24
AC23
AB22
AA21

Y20

W19

V18

U17

T17

R17

P17

M17

J10
P10
K10

M10

L10
W9

T10

R10

AA9
AB9
AD9
AE9
U10

AE11
AD11

1

C252
1U_0402_6.3V4Z

2

U3E

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6

H9

VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9

Y9

VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

F9

VDD18_1

G9

VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS880M_FCBGA528

PAR T 5 /6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

0.7 A/ 60mi l/4v ias

L

VDDA_ 12=2.5A

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

L17

1 2

FBMA-L11-201209-221LMA30T_0805

+VDDA 11PCIE

L

C211

C212

C220 1U_04 02_6.3V4Z
C219 1U_04 02_6.3V4Z
C222 1U_04 02_6.3V4Z
C221 1U_04 02_6.3V4Z
C224 0.1U_04 02_16V4Z
C223 0.1U_04 02_16V4Z

+1.1VS +NB_VD DC

7A/ 28 0mil/16vias

L

1

1

1

1

C2470.1U_0402_16V4 Z

2

1

C2420.1U_0402_16V4 Z

C2410.1U_0402_16V4 Z

C2400.1U_0402_16V4 Z

C2430.1U_0402_16V4 Z

2

2

2

2

+1.8VS

0.1 5A /30mil/2 vias

+3VS

10U_0805_10V4Z

10U_0805_10V4Z

1 2
1 2
1 2
1 2

12
12

PJP604

1 2

PAD-OP EN 4x4m

VDD_C ORE=5A

330U_D2E_2.5VM_R15

1

1

1

C2310.1U_0402_16V4 Z

C2300.1U_0402_16V4 Z

2

2

C249 4.7U_0805_10V4Z
C248 0.1U_0402_16V4Z
C597 0.1U_0402_16V4Z
C598 0.1U_0402_16V4Z
C599 0.1U_0402_16V4Z

1 2

1 2

1

1

C2440.1U_0402_16V4 Z

C23310U_0805_10V4Z

C2320.1U_0402_16V4 Z

2

2

2

C2500.1U_0402_16V4Z

C2530.1U_0402_16V4Z

12
12
12
12
12

+1.1VS

1

C234

1

C24510U_0805_10V4Z

+

2

2

L18

0_0805_5%

4.7U_0805_10V4Z

L19

12

L22

0_0805_5%

4.7U_0805_10V4Z

L16

0_0805_5%

4.7U_0805_10V4Z

+1.1VS

2 2

3 3

+1.2V_HT

+1.8VS

0_0805_5%

U3F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS880M_FCBGA528

PAR T 6 /6

GROUND

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

+1.8VS

1

C1064

10U_0805_10V4Z@

4 4

VLDT_EN#<36>

1 2

R1017 0_0402_5%@

A

2

2N7002_SOT23-3@

2

1

Jus t for RS780M A11 version boot issue

L

12

R1015
1K_0402_1%

+VREF1.35V

@

Q163

C1068

0.1U_0402_16V7K@

2

G

12

R1016

13

D

S

3K_0402_5%@

C1066

0.1U_0402_16V7K@

U64

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8@

1

2

C1067

10U_0805_10V4Z@

2

1

B

+1.35VS

6

5

NC

7

NC

8

NC

9

TP

+3VS

1

C1065

1U_0603_10V6K@

2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RS880 PWR/GND

LA-4117P

13 56Monday, Marc h 16, 2009

E

0.3

A

B

C

D

E

1 1

2 2

RS78 0 DF T_G PIO5 mux at CRT_VS YNC pull l ow to 3K

CRT_V SYNC<11,16>

12

R101 1K_0402_5%

12

R102 1K_0402_5%@

+3VS

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.
1 : Disable (RS780) Enable (RX780)
0 : Enable (RS780) Disable (RX780)
PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#

DFT_GPIO1: LOAD_EEPROM_STRAPS

1 2

R104 150_0402_1%@

D4 CH751H-40PT_S OD323-2@

2 1

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RS78 0 DFT_GPI O1

AUX_CAL<11>

SUS_STAT_R#<11> PLT_RST# <11 ,19,25,26,27,32,33>

RX78 0 DF T_G PIO1 mux at GREEN( Ball E18) and change pull low form 150 t o 3K.

3 3

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RS780 _DFT_GPIO_0<11>

RS78 0 us e H SYNC to enable SIDE PORT (internal pull high)

CRT _HSYNC<11,16>

4 4

A

B

12

R105 1K_0402_5%@

12

R107 3K_0402_5%

12

R1064 3K_0402_5%

RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)

+3VS

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

RS880 STRAPS

LA-4117P

14 56Monday, Marc h 16, 2009

E

0.3

A

B

C

D

E

R167

1 2

0_0805_5%

+3VS_CLK

1

C444
10U_0805_10V4Z

2

1

C445

0.1U_0402_16V4Z

2

1

C458

0.1U_0402_16V4Z

2

1

C446

0.1U_0402_16V4Z

2

1

C459

0.1U_0402_16V4Z

2

1

C447

0.1U_0402_16V4Z

2

1

C460

0.1U_0402_16V4Z

2

1

C448

0.1U_0402_16V4Z

2

1

C461

0.1U_0402_16V4Z

2

1

C449

0.1U_0402_16V4Z

2

1

C450

0.1U_0402_16V4Z

2

1

C451

@

1U_0402_6.3V4Z

2

+3VS

R168

1 2

0_0805_5%

+VDDC LK_IO

1

2

0.1U_0402_16V4Z

1

C452

2

1

C453

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C454

1

C455

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C456

2

1

C457

2

+1.2V_HT

10U_0805_10V4Z

1 1

EMI Ca ps fo r sin gle e nd cl ock.

CLK_48M_USB

R170 33_0402_5%

1 2

1 2

CLK_XTAL_OUT

CLK_XTAL_IN

Y2

12

14.31818MHZ_20P_6X1430004201

+3VS_CLK

+VDDC LK_IO

1

C465

22P_0402_50V8J

2

+3VS_CLK

+VDDC LK_IO

U10

1

SCL

2

SDA

3

VDD_DOT

4

SRC_7#/27M

5

SRC_7/27M_SS

6

VSS_DOT

7

SRC_5#

8

SRC_5

9

SRC_4#

10

SRC_4

11

VSS_SRC

12

VDD_SRC_IO

13

SRC_3#

14

SRC_3

15

SRC_2#

16

SRC_2

17

VDD_SRC

18

VDD_SRC_IO

72

73

GND

2 2

22P_0402_50V8J

C464

1

2

Rou tin g t he tr ace at l eas t 10mil

SMB_CK_CLK0<8,9,20,30>
SMB_CK_DAT0<8,9,20,30>

PA_RS7X0A1

SB LIN K SB SRC

MiniCard_1

MiniCard_2

3 3

CLK_SB LINK_BCLK#<11>

CLK_SB LINK_BCLK<11> CLK_SBSRC _BCLK# <19>

CLK_P CIE_MCARD1#<26>

CLK_P CIE_MCARD1<26>

CLK_P CIE_MCARD2#<26>

CLK_P CIE_MCARD2<26>

R379 158_0402_1%

@

R1105 75_0402_1%

+3VS_CLK

SEL_SATA

CLK_XTAL_OUT

CLK_XTAL_IN

CLK_48M_USB_R

NB_OSC_14 .318M_R

64

65

66

67

68

69

71

VSS_48

VDD_48

XTAL_IN

48MHz_17048MHz_0

VSS_REF

XTAL_OUT

REF_1/SEL_SATA

REF_0/SEL_HTT66

R1106

+3VS_CLK

+3VS_CLK

27M_SEL

63

62

61

60

59

58

57

56

PD#

VSS_HTT

VDD_HTT

VDD_REF

HTT_0/66M_0

HTT_0#/66M_1

REF_2/SEL_27

R380

1 2

1 2

110_0402_5%

1 2

R174 8.2K_0402_5%

CLK_C PU_BCLK_R

CLK_C PU_BCLK#_R

55

CPU_K8_0

CPU_K8_0#

VDD_CPU

VDD_CPU_I/O

VSS_CPU
CLKREQ_1#
CLKREQ_2#

VDD_A
VSS_A

VSS_SATA

SRC_6/SATA

SRC_6#/SATA#

VDD_SATA
CLKREQ_3#
CLKREQ_4#

SB_SRC_SLOW#

SB_SRC_0

SB_SRC_0#

VDD_SB_SRC

VDD_SB_SRC_IO

CLK_48M_USB <20>

NB_OSC_14.318M <11>

90.9_0402_1%

CLK_14M_SB <19>

CLK_NBHT <11>
CLK_NBHT# <11>

+3VS_CLK

1 2

R946 0_0402_1%

1 2

R945 0_0402_1%

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

+3VS_CLK
+VDDC LK_IO

CLKRE Q_NCARD#
CLKRE Q_MCARD2#

+3VS_CLK

CLKRE Q_MCARD1#
CLKREQ4

1 2

R372 10K_0402_5%

+3VS_CLK
+VDDC LK_IO

RS780

01/2 3 14 .318MHz For SB710 reference

NB

R186
261_0402_1%@

1 2

CLK_SBSRC _BCLK <19>

+3VS_CLK

CLKRE Q_MCARD1# <26>

+3VS_CLK

OSC_14M_NB

1.8V 75R/100RRX780

1.1V 200R/100R

CLK_CP U_BCLK <6>

CP U

CLK_CP U_BCLK# <6>

CLKRE Q_NCARD# <26>
CLKRE Q_MCARD2# <26>

For I CS ne ed to p ull high .
For S LG i s NC

C1123

1 2

1U_04 02_6.3V4Z

+3VS_CLK

1

2

C1106

0.1U_0603_25V7K

PA_RS7X0A1

NB_OSC_14.318M

CLK_14M_SIO

C1076

12P_0402_50V8J

1

2

1

C1074

1

12P_0402_50V8J

2

2

C1075
12P_0402_50V8J

VSS_SRC19SRC_1#20SRC_121SRC_0#22SRC_023CLKREQ_0#24ATIGCLK_2#25ATIGCLK_226VSS_ATIG27VDD_ATIG_IO28VDD_ATIG29ATIGCLK_1#30ATIGCLK_131ATIGCLK_0#32VSS_SB_SRC36SB_SRC_135SB_SRC_1#34ATIGCLK_0

+3VS_CLK

R179

@

8.2K_0402_5%

1 2

SEL_SATA

R181

8.2K_0402_5%

4 4

SEL_SATA

* def ault

1 2

1

configur e as SATA ou tput

*

conf igure as normal S RC(SRC_ 6) output

0

+3VS_CLK

1 2

27M_SEL

R180

8.2K_0402_5%

27M_SEL

configur e as 27M and 2 7M_SS output

1 *

0 conf igure as SRC _7 output

* def ault

+3VS_CLK

+VDDC LK_IO

CLKREQ_LAN#

SLG8SP626VT R_QFN72_10x10

33

NBGFX_CLK <11>
NBGFX_CLK# <11>

CLK_P CIE_MCARD0 <27>
CLK_P CIE_MCARD0# <27>
CLKRE Q_LAN# <25>
CLK_P CIE_LAN <25>
CLK_P CIE_LAN# <25>

CLK_P CIE_NCARD <26>
CLK_P CIE_NCARD# <26>

NB GF X

Card Reader

GLAN

New Card

CLKRE Q_NCARD#

CLKRE Q_MCARD2#

CLKRE Q_MCARD1#

CLKREQ_LAN#

CLKREQ4

NB CLOCK INPUT TABLE

NB CL OCKS

HT_REFCLKP

HT_REF CLKN

REFCLK_P

REFCL K_N

GFX_REFCLK 100M DIFF

1 2

R324 8.2K_0402_5%

1 2

R325 8.2K_0402_5%

1 2

R326 8.2K_0402_5%

1 2

R1039 8.2K_0402_5%

1 2

R1045 8.2K_0402_5%@

RX780 RS780

100M D IFF
100M D IFF

14M SE (1.8V) 14M SE (1.1V)
NC vr ef

+3VS_CLK

100M D IFF
100M D IFF

100M D IFF(IN/OU T)*

Use v olt age d ivide r res is tor R3 79 & R38 0 to pull low

NB_OSC_14.318M

configur e as single-ended 6 6MHz output1

*0 conf igure as dif ferential 100 MHz output

* def ault

A

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Clock generator

LA-4117P

15 56Monday, Marc h 16, 2009

E

0.3

A

B

C

D

E

1 1

1

D35

@

DAN217_SC5 9

2

3

L47

1 2

BLM15AG121SN1D_0402

L48

1 2

BLM15AG121SN1D_0402

L49

1 2

BLM15AG121SN1D_0402

1

2

6P_0402_50V8K

C858

1

2

CRT _HSYNC<11,14>

CRT_V SYNC<11,14>

R217

75_0402_1%

+CRT_VCC

1

2

RED

GREEN

BLUE

12

C471

75_0402_1%

R218

6.8K_0402_5%

D_DDC DATA

D_DDC CLK

C856

@

470P_0402_50V8J

1

2

6P_0402_50V8K

C859

1

C469

2

6P_0402_50V8K

D_DDC DATA <35>

D_DDC CLK <35>

RED<11>

GREEN<11>

BLUE<11>

12

12

R211

+3VS

R1023 0_0402_5%@

3

2

1 2

Q10B

R214

R100

6.8K_0402_5%

61

Q10A

v0.2 ADD

C857

@

470P_0402_50V8J

75_0402_1%

1

2

2 2

12

R237

4.7K_0402_5%

UMA_CRT_DAT<11>

UMA_CRT_CLK<11>

3 3

R238

4.7K_0402_5%

1 2

2N7002DW -7-F_SOT363-6

5

4

2N7002DW-7-F_SOT363-6

1 2

R1022 0_0402_5%@

v0.2 ADD

C476

6P_0402_50V8K

1

D37

@

DAN217_SC5 9

2

RED_L

GREEN_L

BLUE_L

1

2

6P_0402_50V8K

3

C472

@

1

2

CRT CONNECTOR

+R_CR T_VCC

D36

1

D34

DAN217_SC5 9

2

3

6P_0402_50V8K

@

2 1

+CRT_VCC

1 2

C473

0.1U_0402_16V4Z

1 2

C477

0.1U_0402_16V4Z

RB491D_SOT23

+3VS

D_DDC DATA

HS YNC

VSYN C

D_DDC CLK

+CRT_VCC

1

5

P

OE#

A2Y

G

U14
SN74AHCT1G125GW_SOT353-5

3

1

5

P

OE#

A2Y

G

U13

SN74AHCT1G125GW_SOT353-5

3

F2

21

1A_6V DC_MINISMDC110

0.1U_0402_16V4Z

JCRT

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

16
17

SUYIN_0 70546FR0 15S263ZRCONN@

D_H SYNC

4

D_V SYNC

4

+CRT_VCC+5VS

1

C475

2

RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND

GND
GND

R240 0_0603_5%

1 2

R241 0_0603_5%

1 2

+CRT_VCC

1

C1107

0.1U_0603_25V7K

2

RED_L <35>

GREEN_L <35>

BLUE_L <35>

D_V SYNC <35>

D_H SYNC <35>

HS YNC

VSYN C

1

1

C470

@

C474

@

2

2

10P_0402_50V8J

10P_0402_50V8J

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

CRT Connector

LA-4117P

16 56Monday, Marc h 16, 2009

E

0.3

A

B

C

D

E

USB_VCC A is +3.9 V, R89 2:100K;
R891: 215K Kohm
G916 Vref=1.25V when U54 install
G916 -390T1UF

C71 8 ins ta ll when U54 is

L

RT919 3-39GB

Clo se to JLV DS

L

+USB_CAM

R222

USB20_N5

4

3

PRTR5V0U2X_SOT143-4@

2

C863

1000P_0402_50V7K

1

4.7U_0805_10V4Z

D22

VIN

IO2

C487

2

IO1

1

GND

+3VS

80mil

S

G

2

D

1 3

USB20_P5

SI2301BDS-T1-E3_SOT23-3
Q43

80mil

+LCDV DD

1

C491

0.1U_0402_16V4Z

2

Ripe ly 2 .0 Su pport Veri -Bright fu nction

R1084 0_0402_5%

R1078 0_0402_5%@

1 2

1 2

1 2

1 2

1 2

+3VS

R4834.7K_0402_5%@

R2744.7K_0402_5%

R2754.7K_0402_5%

680P_0402_50V7K

NB_PWM<11>

EC_PWM<33>

BKOFF# <33>
DAC_B RIG <33>

BKOFF#

LCD_D DC_CLK

LCD_D DC_DAT

INV_PWM

1

2

+LCDVD D

+USB_CAM

12

R891

215K_0402_1%@

12

R892

100K_0402_1%@

12

61

2

5

R276

1 2

100_0805_5%

C482

@

680P_0402_50V7K

2

C719

10U_0805_10V4Z

1

+5VALW

R224
1M_0402_5%

1 2

1 2

100K_0402_5%

3

Q45B
2N7002DW-7-F_SOT363-6

4

+5VS

1

1

C483

2

2

@

+5VALW

+5VS

1 1

2 2

INVPW R_B++LCD VDD

680P_0402_50V7K

C479

1

12

C480

680P_0402_50V7K

2

LVDS_A2-

C1056 10P_0402_50V8J@

1 2

C1057 10P_0402_50V8J@

3 3

LVDS_ACLK- LVDS_ACLK+

1 2

C1058 10P_0402_50V8J@

1 2

C1059 10P_0402_50V8J@

1 2

LVDS_A2+

LVDS_A1+LVDS_A1-

LVDS_A0+LVDS_A0-

C481

680P_0402_50V7K

+3VS

USB20_P5<20>
USB20_N5<20>

12

PJP4

PAD-OP EN 2x2m

2 1

2

C720

10U_0805_10V4Z

FBMA-L11-201209-221LMA30T_0805

1 2

USB20_P5
USB20_N5

1

L44

LVDS CONN

JLVDS

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

ACES_88242-4001

CONN@

B+

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND41GND

PJP6

PAD-OP EN 2x2m

2 1

12

R1013

0_0402_5%

1

2

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

C1108
680P_0402_50V7K

LVDS_A2­LVDS_A2+
LVDS_A1­LVDS_A1+
LVDS_A0­LVDS_A0+
LVDS_ACLK­LVDS_ACLK+

DMIC_DAT
DMIC_C LK

INV_PWM
BKOFF#
DAC_B RIG

LCD_D DC_CLK
LCD_D DC_DAT

9/2 0 SP0 20 00E A00 /SP0 2000B W00

U54

1

VIN

2

GND

3

EN

RT9193-39GB_SOT23-5

@

1 2

0_0402_5%

UMA_ENVDD<11>

+USB_CAM

12

C867

C866

@

680P_0402_50V7K

680P_0402_50V7K

5

VOUT

4

BP

0.1U_0402_16V4Z

R1014

220_0402_5%

2N7002DW -7-F_SOT363-6

LVDS_A2- <11>
LVDS_A2+ <11>
LVDS_A1- <11>
LVDS_A1+ <11>
LVDS_A0- <11>
LVDS_A0+ <11>
LVDS_ACLK- <11>
LVDS_ACLK+ <11>

DMIC_DAT <28>
DMIC_CLK <28>

LCD_D DC_CLK <11>
LCD_D DC_DAT <11>

12

@

C718

CAM_SHDN# <21>

R225

Q45A

2.2K_0402_5%

R491

1 2

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet

Compal Electronics, Inc.

LCD CONN. / WebCam

LA-4117P

17 56Monday, Marc h 16, 2009

E

0.3

of

A

1 1

0.1U_0402_16V4Z

2 2

C851

+HDMI_5V_OUT

2

5

1

P

A2Y

G

3

1

OE#

2.2K_0402_5%

4

U39
SN74AHCT1G125GW_SOT353-5

B

1 2

HDMI_ HPD

2

C850

0.1U_0402_16V4Z

1

12

+3VS

R615

HPD <11>

R628

100K_0402_5%

C

12

R176

4.7K_0402_5%

HDMIDAT_UMA<11>

HDMICLK_UMA<11>

R209

4.7K_0402_5%

1 2

2N7002DW-7-F_SOT363-6

2N7002DW -7-F_SOT363-6

5

4

R1018

@

1 2

0_0402_5%

D

3

Q134B

2

R1019

@

1 2

0_0402_5%

v0.2 ADD

61

Q134A

R210

6.8K_0402_5%

v0.2 ADD

E

+HDMI_5V_OUT+3VS

R236

6.8K_0402_5%

HDMI_SDATA

HDMI_SCLK

HDMI_CLK+

R172

715_0402_1%

R304

1 2

1 2

HDMI_C LK­HDMI_CLK+

HDMI_TX0­HDMI_TX0+

HDMI_TX1­HDMI_TX1+

HDMI_TX2­HDMI_TX2+

HDMI_TX2­HDMI_TX2+

715_0402_1%

R139

715_0402_1%

R141

1 2

1 2

HDMI_C LK-

HDMI_TX0+

HDMI_TX0-

HDMI_TX1+

HDMI_TX1-

HDMI_TX2-

Cha nge P CB Foo tpr in t f rom SW_W CM2 012F2 S_ 4P to KI NG_ WCM-2012-900T_4P

L

C507 0.1U_0402_16V7K

TMDS_B_CLK#<10>
TMDS_B_CLK<10>

TMDS_B_DATA0#<10>

TMDS_B_DATA0<10>

TMDS_B_DATA1#<10>

TMDS_B_DATA1<10>

TMDS_B_DATA2#<10>
TMDS_B_DATA2<10>

3 3

100K_0402_5%

4 4

R1104

+5VS

715_0402_1%

1 2

HDMI_C LK-

R315

2

G

12

R307

715_0402_1%

1 2

13

D

2N7002_SOT23-3

S

1 2

C508 0.1U_0402_16V7K

1 2

C655 0.1U_0402_16V7K

1 2

C675 0.1U_0402_16V7K

1 2

C804 0.1U_0402_16V7K

1 2

C827 0.1U_0402_16V7K

1 2

C852 0.1U_0402_16V7K

1 2

C853 0.1U_0402_16V7K

1 2

HDMI_TX0­HDMI_TX0+

R173

715_0402_1%

Q173

715_0402_1%

R297

1 2

1 2

1/1 9 Us e o ne mos to instead of two du le MOS des ign

HDMI_TX1­HDMI_TX1+

715_0402_1%

03/0 7 Ch agn ge R 315, R307 , R173, R2 97, R172, R304, R139 , R141 fro m 750 ohm to 715 ohm .

1 2

R112 0_0402_5%@

L85

1

1

4

4

WCM-2012-900T_4P

1 2

R113 0_0402_5%@

1 2

R115 0_0402_5%@

L86

1

1

4

4

WCM-2012-900T_4P

1 2

R116 0_0402_5%@

1 2

R117 0_0402_5%@

L87

1

1

4

4

WCM-2012-900T_4P

1 2

R118 0_0402_5%@

1 2

R119 0_0402_5%@

L88

1

1

4

4

WCM-2012-900T_4P

1 2

R120 0_0402_5%@

2

2

3

3

2

2

3

3

2

2

3

3

2

2

3

3

HDMI_R _CK+

HDMI_ R_CK-

HDMI_R _D0+

HDMI_ R_D0-

HDMI_R _D1+

HDMI_ R_D1-

HDMI_R _D2+HDMI_TX2+

HDMI_ R_D2-

+5VS +HDMI_5V_OUT

RB491D_SOT23

1

C468

0.1U_0402_16V4Z

2

D10

2 1

HDMI Connector

+HDMI_5V_OUT

JHDM I

18

HDMI_SDATA
HDMI_SCLK
HDMI_ HPDHDMI_CLK+

HDMI_ R_CK­HDMI_R _CK+
HDMI_ R_D0­HDMI_R _D0+
HDMI_ R_D1­HDMI_R _D1+
HDMI_ R_D2­HDMI_R _D2+

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

DDC/CEC_GND

SUYIN_1 00042MR019S153ZLCONN@

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

13
14

2
5
8
11
20
21
22
23
17

MP: Up dat e D10 to mee t HDM I.

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HDMI

LA-4117P

18 56Monday, Marc h 16, 2009

E

0.3

A

+3VALW

C506

12

5

0.1U_0402_16V4Z@

NB_RST#_R

1 1

2 2

3 3

4 4

R312 33_0402_5%

18P_0402_50V8J

20M_0402_5%

18P_0402_50V8J

+1.8VS

+3VS

H_PW RGD_CPU<6>

U16

2

P

B

Y

1

A

G

3

12

R314 20M_0402_5%@

1 2

C643

1 2

12

R389

C652

1 2

Close to SB

R318 10K_0402_5%@

R319 10K_0402_5%

H_PW RGD<43>

PLT_RST#

4

NC7SZ08P5X_NL_SC70-5@

12

12

PLT_RST# <11 ,14,25,26,27,32,33>

Y3

4

OSC

NC

1

OSC

R311

1 2

0_0402_5%

R1079

1 2

0_0402_5%

NC

32.768KHZ_12.5PF_Q13MC 14610050_10PPM

CPU_LDT_R EQ#

H_PROCH OT#

3

2

Check AMD need pull low or not

SB_RX0N<10>

SB_RX1P<10>

SB_RX1N<10>

SB_RX2P<10>

SB_RX2N<10>

SB_RX3P<10>

SB_RX3N<10>

SB_TX0P<10>
SB_TX0N<10>
SB_TX1P<10>
SB_TX1N<10>
SB_TX2P<10>
SB_TX2N<10>
SB_TX3P<10>
SB_TX3N<10>

+PCIE _VDDR

+1.2V_HT

SB_32KHI

SB_32KHO

H_PW RGD_SB

1 2

BLM18PG121SN1D_0603

01/2 3 14 .318MHz for SB710 reference

1 2

R300 8.2K_0402_5%@

C492 0.1U_0402_16V7K

1 2

C493 0.1U_0402_16V7K

1 2

C494 0.1U_0402_16V7K

1 2

C495 0.1U_0402_16V7K

1 2

C496 0.1U_0402_16V7K

1 2

C497 0.1U_0402_16V7K

1 2

C498 0.1U_0402_16V7K

1 2

C499 0.1U_0402_16V7K

1 2

L53

C504

10U_0805_10V4Z

Close to SB

CLK_SB SRC_BCLK<15>
CLK_SBSRC _BCLK#<15>

CLK_14M_SB<15>

CPU_LDT_R EQ#<6,11>

H_PROCH OT#<6>

LDT_STOP#<6,11>

B

NB_RST#_R

R305 562_0402_1%
R306 2.05K_0402_1%

1

1

2

2

R1107 0_0402_5%

R1108 0_0402_5%@

R1109 1K_0402_5%@

H_PW RGD<43>

LDT_RST#<6>

C

12
12

+SB_PC IEVDD

C505

1U_0402_6.3V4Z

1 2

12

CPU_LDT_R EQ#
H_PROCH OT#
H_PW RGD

NB_RST#_R

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

12

SB_32KHI

SB_32KHO

U15A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

14M_X1

J20

14M_X2

A3

X1

B3

X2

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

SB700

Part 1 of 5

PC I CL KS

PC I EX PR ES S INTE RFA CE

PC I IN TE RF ACE

CL OCK GEN ERAT OR

LDRQ1#/GNT5#/GPIO68

L PC

BMREQ#/REQ5#/GPIO65

RT C X TAL

C PU

218-0660011 A14 SB7_FCBGA528

9/2 0 SA0 00 01S 51 0 S I C 218 S7 EALA 11FG SB70 0 BG A 52 8P S B 0F H

RTC

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4

PCICLK5/GPIO41

PCIRST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#
CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP#
PERR#
SERR#
REQ0#
REQ1#

REQ2#
REQ3#/GPIO70
REQ4#/GPIO71

GNT0#

GNT1#

GNT2#
GNT3#/GPIO72
GNT4#/GPIO73

CLKRUN#

LOCK#

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

LPCCLK0
LPCCLK1

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

INTRUDER_ALERT#

VBAT

D

P4
P3
P1

CLK_P CI_SIO_R PCI_CLK3

P2
T4
T3

N1

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3

PCI_AD23

Y2

PCI_AD24

AA2

PCI_AD25

AB4

PCI_AD26

AA1

PCI_AD27

AB3

PCI_AD28

AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

AD3
AC4
AE2

PCI_P IRQH#

AE3

CLK_P CI_EC_R

G22

LPCCLK1

E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

C3
C2
B2

+SB_VBAT

R301 0_0402_5%

1 2

PCI_AD23 <23>
PCI_AD24 <23>
PCI_AD25 <23>
PCI_AD26 <23>
PCI_AD27 <23>
PCI_AD28 <23>

PCI_S ERR# <33>

T15PAD

T16PAD
T17PAD

R967 0_0402_5%

R302 33_0402_5%

1 2

LPCCLK1 <23>
LPC_AD0 <32,33>
LPC_AD1 <32,33>
LPC_AD2 <32,33>
LPC_AD3 <32,33>

1

2

LPC_FRAME# <32,33>

LPC_DR Q# <32>

SIRQ <32,33>

RTC_CLK <23>

+SB_VBAT

C510

1U_0402_6.3V4Z

T18PAD

C509

0.1U_0402_16V4Z

LPCCLK1 C LK_PCI_SIO

12

CLK_P CI_EC

STRAP PIN

R316
120_0402_5%

1 2

1

W=2 0mi ls

2

CLK_P CI_SIO2

CLK_P CI_SIO

CLK_P CI_EC

R308 33_0402_5%

1 2

ACCEL_INT <30>

CLK_P CI_EC <23,33>

STRAP PIN
EC & Debug

+RTCV CC_R

2

J1

2

1

1

+RTCVCC

R317
120_0402_5%

1 2

JUMP_43X39@

PCICLK2 <23>SB_RX0P<10>
PCI_CLK3 <23>
PCI_CLK4 <23>
PCI_CLK5 <23>

D42

1

DAN202 U_SC70

C1085 12P_0402_50V8J@

1 2

C1086 12P_0402_50V8J

1 2

C1087 12P_0402_50V8J

1 2

CLK_P CI_SIO <32>

+3VL

+RTCBATT

2

R876

1 2

3

W=20m ils

1K_0402_5%

+RTCBATT_R

E

W=20m ils

9/2 0 SP0 200 08T00

1
2
3
4

JBATT1

1
2
GND
GND

ACES_85205-02001CONN@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

SB710-PCIE/PCI/ACPI/LPC/RTC

LA-4117P

19 56Monday, March 16, 2009

E

0.3

A

B

C

D

E

NB_PW RGD<11>

R1053

For SB700 A11 divider to

100_0402_5%@

R1052

12

1.8V for RS & RX780

1 1

2 2

3 3

4 4

+3VS

1 2

R388 4.7K_0402_5%

+3VALW

1 2

R320 2.2K_0402_5%@

1 2

R321 2.2K_0402_5%@

1 2

R322 2.2K_0402_5%@

+3VS

R328 1.2K_0402_5%

1 2

R329 1.2K_0402_5%

1 2

+3VALW

R331 2.2K_0402_5%

1 2

R332 2.2K_0402_5%

1 2

LAN_PCIE_W AKE#<25>

MINI_P CIE_WAKE#<26>

C1122

@

0.1U_0402_16V4Z

A

SUS_STAT#

SMB_CK_CLK0

SMB_CK_DAT0

SMB_CK_CLK1

SMB_CK_DAT1

R993 47_0402_5%

R994 0_0402_5%@

HDA_B ITCLK_CODEC<28>
HDA_B ITCLK_MDC<34>

C1088 82P_0402_50V8J

1 2

C1089 82P_0402_50V8J

1 2

C1090 82P_0402_50V8J

1 2

C1091 82P_0402_50V8J

1 2

+3VS

HDAB ITCLK

R1081

@

10K_0402_5%

1

ASM3P623S00BF-08TR_TSSOP8

2

SB_TEST2

SB_TEST1

SB_TEST0

12

12

HDA_SDOUT_ MDC<34>

HDA_S DOUT_CODEC<28>
HDA_S DIN0<28>
HDA_S DIN1<34>

HDA_S YNC_MDC<34>

HDA _SYNC_COD EC<28>

HDA_R ST#_CODEC<28>
HDA_RST#_MDC<34>

HDA_B ITCLK_CODEC

HDA_B ITCLK_MDC

HDA_S DOUT_MDC

HDA_S DOUT_CODEC

U66

@

7

VDD

6

CLKOUT

12

5

SSON

4

GND

3/5V_OK<39,41>

+3VALW

HDARST#<23,33>

CLKIN

R540
10K_0402_5%

1 2

PCIE_WAKE#

NC

NC

SS

NBPW RGD

12

0_0402_5%

CH751H-40PT_S OD323-2

R333 33_0402_5%
R334 33_0402_5%

R335 33_0402_5%
R336 33_0402_5%

R337 33_0402_5%
R338 33_0402_5%

R339 33_0402_5%
R340 33_0402_5%

STRAP PIN

HDA_BITCLK

1

2

8

@

3

10K_0402_5%

R1083

@

10K_0402_5%

1 2

D58

R1082

dem o cir cu it LID use RI#

SLP_S3#<33>
SLP_S5#<33>

PWRBTN_OUT#<33>

SB_PW RGD<6,33,43>
SUS_STAT#<11>

GATEA20<33>
KB_RST#<33>
EC_SC I#<33>
EC_SMI#<33>

H_THERMTRIP#<6>

EC_RSMRST#<33>

SB7 00 ha s inte rnal PD

EC_RSMRST#

21

EC_LID_OUT#<33>

EXP_CPPE#<26>

CR_CP PE#<27>

1 2
1 2

12

1 2
1 2

1 2
1 2

1 2
1 2

03/05 Add SSC circuit for H DA_ BITCLK.

+3VS

+3VS

HDAB ITCLK

SMB_CK_CLK0<8,9 ,15,30>
SMB_CK_DAT0<8,9,15,30>

SMB_CK_CLK1<26>

SMB_CK_DAT1<26>

SB_SPKR<28>

R83

1 2

10K_0402_5%

EXP_CPPE#
CR_CPPE#

2.2K_0402_5%

1 2

R1080 0_0402_5%

HDA_SDOUT
HDA_S DIN0
HDA_S DIN1

SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0

T19P AD

PCIE_WAKE#

H_THERMTRIP#
NBPW RGD

EC_RSMRST#

R327

1 2

SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

SB_GPIO5

R82 0_0402_5%

1 2
1 2

R81 0_0402_5%

HDA_BITCLK

HDA _SYNC

HDARST#

T41P AD

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U15D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVEN T2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT1/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SMARTVOLT2/SHUTDOWN #/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

PS2_DAT

H20

PS2_CLK

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

PS2KB_DAT

E24

PS2KB_CLK

E25

PS2M_DAT

D23

PS2M_CLK

218-06 60011 A14 SB7_FCBGA528

C

SB700

AC PI / W AKE UP EV ENT S

US B O C

HD AUD IO

Part 4 of 5

USBCLK/14M_25M_48M_OSC

USB_RCOMP

USB_FSD13P

USB_FSD13N

US B MI SC

USB_FSD12P

USB_FSD12N

USB_HSD11P

US B 1. 1

USB_HSD11N

USB_HSD10P
USB_HSD10N

USB_HSD9P
USB_HSD9N

USB_HSD8P
USB_HSD8N

USB_HSD7P
USB_HSD7N

USB_HSD6P
USB_HSD6N

USB_HSD5P
USB_HSD5N

USB_HSD4P

US B 2. 0

USB_HSD4N

USB_HSD3P
USB_HSD3N

GP IO

USB_HSD2P
USB_HSD2N

USB_HSD1P
USB_HSD1N

USB_HSD0P
USB_HSD0N

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11

SDA2/IMC_GPIO12

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

IN TE GR ATED u C

KSO_16
KSO_17

KSI_0
KSI_1
KSI_2
KSI_3
KSI_4
KSI_5
KSI_6
KSI_7

KSO_0
KSO_1
KSO_2
KSO_3
KSO_4
KSO_5
KSO_6
KSO_7
KSO_8

KSO_9
KSO_10
KSO_11
KSO_12
KSO_13
KSO_14
KSO_15

C8

USB_RCOMP

G8

E6
E7

F7
E8

USB20_P11

H11

USB20_N11

J10

USB20_P10

E11

USB20_N10

F11

A11
B11

USB20_P8

C10

USB20_N8

D10

USB20_P7

G11

USB20_N7

H12

USB20_P6

E12

USB20_N6

E14

USB20_P5

C12

USB20_N5

D12

B12
A12

USB20_P3

G12

USB20_N3

G14

USB20_P2

H14

USB20_N2

H15

USB20_P1

A13

USB20_N1

B13

USB20_P0

B14

USB20_N0

A14

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

G20
G21
D25
D24
C25
C24
B25
C23

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

IN TE GR ATED u C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

1 2

GPIO16 < 23>
GPIO17 < 23>

CLK_48M_USB <15>

R32311.8K_0402_1%

Touch Screen (dele te)

USB20_P11 <26>
USB20_N11 <26>

USB20_P10 <26>
USB20_N10 <26>

USB-11 New Card

USB-10 MiniCard(TV or WWAN)

USB-9 Card Rea der (d elete)

USB20_P8 <26>
USB20_N8 <26>

USB20_P7 <31>
USB20_N7 <31>

USB20_P6 <31>
USB20_N6 <31>

USB20_P5 <17>
USB20_N5 <17>

USB-8 MiniCard(WLAN)

USB-7 Fingerprint

USB-6 Bluetooth

USB-5 USB Camera

USB-4 Left side

USB20_P3 <35>
USB20_N3 <35>

USB20_P2 <31>
USB20_N2 <31>

USB20_P1 <31>
USB20_N1 <31>

USB20_P0 <31>
USB20_N0 <31>

USB-3 Dock

USB-2 L eft Side

USB-1 Right side

USB-0 Right side (S/W Debug Port)

STRAP PIN
STRAP PIN

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

SB710 USB/AC97

LA-4117P

E

20 56Monday, March 16, 2009

0.3

A

B

C

D

E

C51610P_0402_50V8J

12

12

Y4

25MHz_20pF_6X25000017

1 1

SATA_TXP0<24>
SATA_TXN0<24>

SATA_TXP1<24>
SATA_TXN1<24>

SATA_TXP2<31>
SATA_TXN2<31>

SATA_TXP3<24>
SATA_TXN3<24>

2 2

+1.2V_HT

BLM18PG121SN1D_0603

+3VS

3 3

C51710P_0402_50V8J

12

C512 0.01U_0402_25V7K

1 2

C513 0.01U_0402_25V7K

1 2

C514 0.01U_0402_25V7K

1 2

C515 0.01U_0402_25V7K

1 2

C520 1000P_0402_50V7K

1 2

C521 1000P_0402_50V7K

1 2

C518 0.01U_0402_25V7K

1 2

C519 0.01U_0402_25V7K

1 2

+3VS

L54

12

C522

1U_0402_6.3V4Z

L55

12

BLM18PG121SN1D_0603

1U_0402_6.3V4Z

12

R341

10M_0402_5%

R343 10K_ 0402_5%

1 2

SATA_LED#<34>

2

2

1

1

2

C524

1

SATA_X1

SATA_X2

SATA_RXN0_C<24>

SATA_RXP0_C<24>

SATA_RXN1_C<24>

SATA_RXP1_C<24>

SATA_RXN2_C<31>

SATA_RXP2_C<31>

SATA_RXN3_C<24>

SATA_RXP3_C<24>

R342 1K_0402_1%

+PLLVDD_SATA

C523
1U_04 02_6.3V4Z

+XTLVDD_SATA

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SATA_STX_DRX_P1
SATA_STX_DRX_N1

SATA_STX_DRX_P2
SATA_STX_DRX_N2

SATA_STX_DRX_P3
SATA_STX_DRX_N3

SATA_CAL

12

SATA_X1

SATA_X2

U15B

AD9

SATA_TX0P

AE9

SATA_TX0N

AB10

SATA_RX0N

AC10

SATA_RX0P

AE10

SATA_TX1P

AD10

SATA_TX1N

AD11

SATA_RX1N

AE11

SATA_RX1P

AB12

SATA_TX2P

AC12

SATA_TX2N

AE12

SATA_RX2N

AD12

SATA_RX2P

AD13

SATA_TX3P

AE13

SATA_TX3N

AB14

SATA_RX3N

AC14

SATA_RX3P

AE14

SATA_TX4P

AD14

SATA_TX4N

AD15

SATA_RX4N

AE15

SATA_RX4P

AB16

SATA_TX5P

AC16

SATA_TX5N

AE16

SATA_RX5N

AD16

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA

W12

XTLVDD_SATA

218-0660011 A14 SB7_FCBGA528

SB700

Part 2 of 5

SAT A P WR SER IAL ATA

HW M ONITO R

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24

AT A 66 /10 0/133

IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS1#/GPIO32

LAN_RST#/GPIO13

ROM_RST#/GPIO14

SP I ROM

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD

AVSS

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

G6
D2
D1
F4
F3

U15
J1

M8
M5
M7

P5
P8
R8

THERMAL_DC

C6
B6
A6
A5
B5

A4
B4
C4
D4

LFB_ID 0

D5

LFB_ID 1

D6

LFB_ID 2

A7
B7

F6

G7

C525

0.1U_0402_16V4Z

R1062 0_0402_5%

1 2

+SB_AVDD

1

2

BLM18PG121SN1D_0603

1

C526

2.2U_0 603_6.3V4Z

2

+3VALW

+3VALW

CR_WAKE# <27>

HDD_H ALTLED# <34>
SB_INT_FLASH _SEL

WLOF F# <26>
BT_COMBO_EN# <26>
WW OFF# <26>

EC_THERM# <33>

BT_OFF <31>
CAM_SHD N# <17>

AC_IN_SB

02/18 Add R1071 and D56 to con nec t t o AC_IN.

L56

+3VALW

12

Local Frame Buffer Strapping List
Copy from Becks.

LFB_ID0LFB_I D1LFB _ID 2

Hynix

Qimonda

Samsung

0 0 0

0 0 1

0 01

LFB_ID0 to LFB_ID2 got internal PU 10K to S5.

LFB_ID 2

R344 1K_0402_5%

R1032

1 2

1K_0402_5%@

1 2

1K_0402_5%@
R1033

+3VALW

12

LFB_ID 1

LFB_ID 0

R1071

150K_0402_5%

2 1

D56
CH751H-40PT_S OD323-2

1 2

R367 10K_0402_5%

1 2

R345 10K_0402_5%

1 2

AC_IN <33,38>

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

SB710 SATA/IDE/SPI

LA-4117P

21 56Monday, March 16, 2009

E

0.3

A

B

C

D

E

0.6 A/ 50mi l/4v ias

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

V5_VREF

AVDDC

L

L15
M12
M14
N13
P12
P14
R11
R15
T16

0.3 A/ 30mi l/2v ias

L

L21
L22
L24
L25

0.1 A/ 30m il/ 2via s ?

L

A17
A24
B17
J4
J5
L1
L2

G2
G4

A10
B10

+V5_VREF

AE7

+AVDD CK_3.3V

J16

+AVDD CK_1.2V

K17

+AVDDC

E9

+1.2V_SB_CORE

+1.2V_CKVD D

+S5_3V

R564 0_0805_5%

+S5_1.2V

+1.2_USB

1 2

R592 0_0805_5%@

1 2

R593 0_0805_5%

C546 1U_0402_6.3V4Z

C545 1U_0402_6.3V4Z
C548 0.1U_0402_16V4Z
C551 0.1U_0402_16V4Z

C550 10U_0805_10V4Z

1 2

1 2

L65 0_0603_5%

1 2

2

C578

0.1U_0402_16V4Z

0_0805_5%

1

L67

1 2

12
12
12
12
12
12

L60

0_0805_5%

1 2
1 2

12
12

1 2

C55622U _0805_6.3V6M

C5591U_0402_6.3V4Z

12

C5611U_0402_6.3V4Z

12

C5621U_0402_6.3V4Z

12

C5630.1U_0402_16V4Z

12

C5640.1U_0402_16V4Z

12

C5650.1U_0402_16V4Z

12

+1.2VALW

C57310U_0805_10V4Z

C5741U_0402_6.3V4Z

12

C5751U_0402_6.3V4Z

12

2

C579

1U_0603_10V4Z

1

12

C52910U_0805_6.3V6M
C5321U_0402_6.3V4Z
C5341U_0402_6.3V4Z
C5381U_0402_6.3V4Z
C5371U_0402_6.3V4Z
C5270.1 U_0402_16V4Z
C5400.1 U_0402_16V4Z

12

+3VALW

12

12

+1.2VALW

+1.2V_HT

+3VALW

C5852.2U_0603_6.3V4Z

C5860.1 U_0402_16V4Z

+1.2V_HT

L64 0_0603_5%

R3461K_0402_5%

12

D14

21

CH751H-40PT_S OD323-2

+5VS

+3VS

+1.2VALW

C5691U_0 402_6.3V4Z

12

C5700.1U _0402_16V4Z

12

0.4 5A /40 mil /3vias ?

+3VS

1 1

L

2 2

L

L

<1. 25 A/5 0mil/4v ias?

3 3

C528 22U_0805_6.3V6M
C531 1U_0402_6.3V4Z

1 2

C530 1U_0402_6.3V4Z

1 2

C533 1U_0402_6.3V4Z

1 2

C549 1U_0402_6.3V4Z

1 2

C535 1U_0402_6.3V4Z

1 2

C539 1U_0402_6.3V4Z

1 2

C541 0.1U_0402_16V4Z

1 2

C542 0.1U_0402_16V4Z

1 2

0_0603_5%@

R12

+3VS

+1.2V_HT

0.8 A/ 50mi l/4v ias

+1.2V_HT

1 2

C543 22U_0805_6.3V6M@
C544 1U_0 402_6.3V4Z@

1 2

C547 1U_0 402_6.3V4Z@

1 2

C536 1U_0 402_6.3V4Z@

1 2

C552 4.7U_0805_10V4Z
C553 1U_0402_6.3V4Z
C555 1U_0402_6.3V4Z
C554 1U_0402_6.3V4Z
C558 1U_0402_6.3V4Z
C557 0.1U_0402_16V4Z
C560 0.1U_0402_16V4Z

<1. 25 A/5 0mil/4vias

C56 7, C56 8 cha nge to 1 U_0 402 when SI-2

L

+3VALW

C566 22U_0805_6.3V6M
C567 1U_0805_16V7K
C568 1U_0805_16V7K
C571 0.1U_0402_16V4Z
C572 0.1U_0402_16V4Z

C576 10U_0805_10V4Z
C577 10U_0805_10V4Z
C580 1U_0402_6.3V4Z
C581 1U_0402_6.3V4Z
C583 0.1U_0402_16V4Z
C582 0.1U_0402_16V4Z
C584 0.1U_0402_16V4Z

12

12

0_0805_5%

1 2
1 2
1 2
1 2
1 2
1 2

0_0805_5%

1 2
1 2
1 2
1 2

0_0805_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2

L

L

L61

12

L63

12

L66

0.4 5A /30mil/3 vias

+3.3V_SB_IDE

+PCIE _VDDR

12

+1.2V_SATA

12

+AVDD_USB

12

U15C

L9

VDDQ_1

M9

VDDQ_2

T15

VDDQ_3

U9

VDDQ_4

U16

VDDQ_5

U17

VDDQ_6

V8

VDDQ_7

W7

VDDQ_8

Y6

VDDQ_9

AA4

VDDQ_10

AB5

VDDQ_11

AB21

VDDQ_12

Y20

VDD33_18_1

AA21

VDD33_18_2

AA22

VDD33_18_3

AE25

VDD33_18_4

P18

PCIE_VDDR_1

P19

PCIE_VDDR_2

P20

PCIE_VDDR_3

P21

PCIE_VDDR_4

R22

PCIE_VDDR_5

R24

PCIE_VDDR_6

R25

PCIE_VDDR_7

AA14

AVDD_SATA_1

AB18

AVDD_SATA_4

AA15

AVDD_SATA_2

AA17

AVDD_SATA_3

AC18

AVDD_SATA_5

AD17

AVDD_SATA_6

AE17

AVDD_SATA_7

A16

AVDDTX_0

B16

AVDDTX_1

C16

AVDDTX_2

D16

AVDDTX_3

D17

AVDDTX_4

E17

AVDDTX_5

F15

AVDDRX_0

F17

AVDDRX_1

F18

AVDDRX_2

G15

AVDDRX_3

G17

AVDDRX_4

G18

AVDDRX_5

218-066001 1 A14 SB7_FCBGA528

SB700

Part 3 of 5

PCI/ GPIO I/ O

ID E/ FLS H I/O

POWER

A-L INK I/O

3.3 V_S5 I /OCO RE S5

SATA I/O

USB_PHY_1.2V_1
USB_PHY_1.2V_2

PL L CL KG EN I /O

US B I/O

CO RE S0

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

S5_1.2V_1
S5_1.2V_2

AVDDCK_3.3V

AVDDCK_1.2V

U15E

SB700

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

Part 5 of 5

218-066001 1 A14 SB7_FCBGA528

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43

GROUND

VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

L17

+AVDD CK_1.2V

+AVDD CK_3.3V

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

L68

12

0_0805_5%

L69

0_0805_5%

2007/08/02 2008/08/02

+1.2V_HT

C5872.2U_0 603_6.3V4Z

12

C5880.1 U_0402_16V4Z

12

12

+3VS

C5892.2U_06 03_6.3V4Z

12

C5900.1U_0402_16V4Z

12

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

SB710 PWR/GND

LA-4117P

22 56Monday, March 16, 2009

E

0.3

A

B

C

D

E

REQUIRED STRAPS

PCI_CLK3

PULL

1 1

2 2

HIGH

PULL
LOW

PCICLK2<19>

PCI_C LK3<19>

PCI_CLK4<19>
PCI_CLK5<19>

CLK_P CI_EC<19,33>

LPCCLK1<19>
RTC_CLK<19>
HDARST#<20,33>

GPIO17<20>
GPIO16<20>

BOOTFAIL
TIMER
ENABLED

BOOTFAIL
TIMER
DISABLED

DEF AULT

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VA LW +3VALW +3VALW +3VALW

R347

10K_0402_5%

@

R357

10K_0402_5%

USE
DEBUG
STR APS

IGNORE
DEBUG
STR APS

DEF AULT

12

R348

@

12

R358

12

10K_0402_5%

12

10K_0402_5%

PCI_CLK4 PCI_CLK5

RESERVED

R349

@

R359

@

RESERVED

12

10K_0402_5%

12

10K_0402_5%

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

AZ_RST_CD#

ENABLE PCI
MEM BOOT

DISABLE PCI
MEM BOOT

DEF AULT

12

R350

10K_0402_5%

@

R360

10K_0402_5%

@

R351

@

12

R361

CLKGEN
ENABLED

CLKGEN
DISABLED

DEF AULT

12

10K_0402_5%

10K_0402_5%

R352

10K_0402_5%

@

12

R362

10K_0402_5%

RTC_CLKLPC_CLK1

INTERNA L
RT C

DEF AULT

EXT . RTC

(PD on X1,
apply
32KHz to
RTC_CLK)

12

R353

@

12

R363

@

LPC_CLK0

EC
ENABLED

GP17

GP16PCI_CLK2

In tern al pull up

H,H = Reserved

H,L = SPI ROM

EC
DISABLED

DEF AULT

12

10K_0402_5%

2.2K_0402_5%

R354

10K_0402_5%

@

12

R364

10K_0402_5%

12

12

L,H = LPC ROM (Default)

L,L = FWH ROM

12

12

R356

2.2K_0402_5%

R355

10K_0402_5%

@

12

R365

2.2K_0402_5%

12

R366

2.2K_0402_5%

@

DEBUG STRAPS

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

12

2.2K_0402_5%

PCI_AD27 PCI_AD26

USE PCI
PL L

DEF AULT

BYP ASS
PC I PLL

R374

@

USE ACPI
BCLK

DEF AULT

BYP ASS
AC PI
BCLK

12

R375

2.2K_0402_5%

@

PCI_AD28

3 3

PCI_AD28<19>
PCI_AD27<19>
PCI_AD26<19>
PCI_AD25<19>
PCI_AD24<19>
PCI_AD23<19>

4 4

PULL
HIGH

PULL
LOW

USE
LONG
RESET

DEF AULT

USE
SHORT
RESET

R373

@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

2.2K_0402_5%

C

PCI_AD25 PCI_AD24

USE IDE
PL L

DEF AULT

BYPASS IDE
PL L

R376

@

USE DEFAULT
PCI E ST RAPS

DEF AULT

USE EEPROM
PCI E ST RAPS

12

R377

2.2K_0402_5%

@

2007/08/02 2008/08/02

PCI_AD23

RESERVED

12

R378

2.2K_0402_5%

2.2K_0402_5%

@

Compal Secret Data

Deciphered Date

12

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

SB700 STRAPS

LA-4117P

23 56Monday, March 16, 2009

E

0.3

A

B

C

D

E

HDD Connector

+5VS

1

1 1

C593

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

C594

2

1

C591

2

0.1U_0402_16V4Z

1

C595

2

Pleace near HD CONN (JP23)

+3VS +3VS_HDD1

R1009

@

1 2

0_0805_5%

C1032

@

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

C1034

@

2

0.1U_0402_16V4Z

1

C1035

2

@

1

C1033

@

2

Pleace near HD CONN (JP23)

JP9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

CONN@

1

GND

2

A+

3

A-

GND

B-

B+

GND

V33
V33

V33
GND
GND
GND

V5
V5
V5

GND

Reserved

GND

V12

V12

V12

SUYIN_1 27072FR022G523_R V

4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

0.01U_0402_16V7K

0.01U_0402_16V7K

SATA_TXP0

SATA_RXN0 SATA_RXN0_C

Near CONN side.

+3VS_HDD1

+5VS

SATA_TXN0

C592

12

SATA_RXP0_CSATA_RXP0

C596

12

SATA_TXP0 <21>
SATA_TXN0 <21>

SATA_RXN0_C <21>
SATA_RXP0_C <21>

2 2

+5VS

Max 3A

10U_0805_10V4Z

1

1

+

C600

150U_ Y_6.3VM@

3 3

C601

PA@

2

Place close to Multi-Bay
Connec tor-option JP10

PA@

2

0.1U_0402_16V4Z

1

C602

2

PA@

PA@

1

C603

2

0.1U_0402_16V4Z

1

C604

0.1U_0402_16V4Z

2

+5VS

CONN@

2

GND

VCC5

4

VCC5

6

VCC5

8

GND

VCC3

10

VCC3

12

VCC3

14

GND

GND

16

GND

GND

18

GND

GND

TYCO_2023087-3

RX+

JP10

TX+

TX-

RX-

1
3
5

0.01U_0402_16V7K

7

SATA_RXN1 SATA_RXN1_C

9

SATA_RXP1 SATA_RXP1_C

11

0.01U_0402_16V7K

13
15

17

Near CONN side.

SATA_TXP1
SATA_TXN1

C605

12

C606

12

SATA_TXP1 <21>
SATA_TXN1 <21>

SATA_RXN1_C <21>
SATA_RXP1_C <21>

CD-ROM Connector

Multi-Bay Connector-option

+5VS

Pl acea cap s. near O DD C ONN .

1U_0603_10V4Z

0.1U_0402_16V4Z

C613

1

C614

2

4 4

10U_0805_10V4Z

1

1

C615

2

1

C616
10U_0805_10V4Z

2

2

JP11

1

GND

2

A+

3

A-

GND

B-

B+

GND

DP

V5
V5

MD
GND
GND

SUYIN_1 27382FR0 13G509ZRCONN@

0.01U_0402_16V7K

4

SATA_RXN3 SATA_RXN3_C

5

SATA_RXP3

6

0.01U_0402_16V7K

7

R970 0_0402 _5%

1 2

8
9
10
11
12
13

+5VS

SATA_TXP3
SATA_TXN3

C612

12

SATA_RXP3_C

C611

12

Near CONN side.

SATA_TXP3 <21>
SATA_TXN3 <21>

SATA_RXN3_C <21>
SATA_RXP3_C <21>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HDD/CDROM

LA-4117P

24 56Monday, March 16, 2009

E

0.3

A

LAN_D I

LAN_CS

1 1

Place Close to Chip

1 2

PCIE_PTX_IRX_P3

PCIE_PTX_IRX_N3

ISOLATEB

LAN_X1
LAN_X2

U19

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+
TD-8TX-

NS681680

RX+

RX-

CT
NC
NC
CT

TX+

C485 0.1U_0402_16V7K

PCIE_PTX_C_IRX_P3<10>

PCIE_PTX_C_IRX_N3<10>

+3VS

12

R1060
1K_0402_1%

2 2

1

2

3 3

4 4

ISOLATEB

R1061
15K_0402_5%

Y5

LAN_X1 LAN_X2

12

25MHz_20pF_6X25000017

C653

27P_0402_50V8J

27P_0402_50V8J

C648 0.01U_0402_16V7K

1 2

C647 0.01U_0402_16V7K

1 2

12

C488 0.1U_0402_16V7K

12

PCIE_ITX_C_PRX_P3<10>

PCIE_ITX_C_PRX_N3<10>

CLK_P CIE_LAN<15>

CLK_P CIE_LAN#<15>

CLKREQ_LAN#<15>

PLT_RST#<11 ,14,19,26,27,32,33>

R1059 2.49K_0402_1%

LAN_PCIE_W AKE#<20>

1

C654

2

LAN_MDI0+
LAN_MDI0­LAN_CT0

LAN_CT1
LAN_MDI1+
LAN_MDI1-

B

1 2

R1055 3.6K_0402_5%

R1058 10K_0402_5%

U44

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_M

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKXTAL1

42

CKXTAL2

23

NC

24

NC

7

GND

14

GND

31

GND

47

GND

22

GNDTX

RTL8103EL-GR_LQFP48_7X7

RJ45_ MIDI0+

16

RJ45_ MIDI0-

15

RJ45_CT0

14
13
12

RJ45_CT1

11

RJ45_ MIDI1+

10

RJ45_ MIDI1-

9

+3V_LAN

12

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

EECS

RTL8102 EL

C1083 0.01U_0603_100V7-M

1 2

C1084 0.01U_0603_100V7-M

1 2

LED0

MDIP0
MDIN0
MDIP1
MDIN1

NC
NC
NC
NC

NC

VCTRL12A

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

NC

NC

VCTRL12D

VDD33
VDD33

AVDD33

NC
NC

RJ45_ MIDI0+ <35>
RJ45_ MIDI0- <35>

RJ45_ MIDI1+ <35>
RJ45_ MIDI1- <35>

33

LAN_D I

34

LAN_SK _LAN_LINK#

35

LAN_CS

32

LAN_A CTIVITY#

38

LAN_MDI0+

2

LAN_MDI0-

3

LAN_MDI1+

5

LAN_MDI1-

6
8
9
11
12

4

VCTRL12

48

19
30
36
13
10

39

44
45

29
37

1
40
43

RJ45_CT0 _C
RJ45_CT1 _C

+EVDD12
+LAN_VDD12

+LAN_VDD12

+3V_LAN

75_0402_1%
R394

1 2
1 2

R396
75_0402_1%

C

RJ45_ GND

C658

1000P_1206_2KV7K

LAN_P OWER_OFF<33>

1

2

LAN_A CTIVITY#
LAN_SK _LAN_LINK#

PACD N042Y3R_SOT23-3

@

100K_0402_5%

1 2

R1057 0_0402_5%

Clos e to P in10,13,30 ,36

D55

2

C628

0.1U_0402_16V4Z

1

2

3

1

2

C629

0.1U_0402_16V4Z

1

D

+3VALW

R1056

@

1 2

2

1

Clos e to Pin1 9

2

C1081
1U_0402_6.3V4Z

1

LAN_A CTIVITY#

LAN_SK _LAN_LINK#

R1067 0_0805_5%@

2

C1077

@

1

0.1U_0402_16V4Z

+LAN_VDD12

C630

0.1U_0402_16V4Z

Clos e to Pin4 8

VCTRL12

0.1U_0402_16V4Z

1

C1079

2

10U_0805_10V4Z@

+EVDD12

2

C1082

0.1U_0402_16V4Z

1

R391 300_0402_5%

1

C656
68P_0402_50V8K

@

2

2

C657

@

68P_0402_50V8K

1

R395 300_0402_5%

1 2

S

D

13

G

2

Q144

SI2301BDS-T1-E3_SOT23-3

2

C631

0.1U_0402_16V4Z

1

2

C1080

1

RJ45_ MIDI1-

RJ45_ MIDI1+

RJ45_ MIDI0-

RJ45_ MIDI0+

12

12

40 mils

+3V_LAN

Clos e to Pi n1,37,29

2

C620

0.1U_0402_16V4Z

1

+3V_LAN

+3V_LAN

13

14

11

12

1

C661

0.1U_0402_16V4Z

2

2

C621

0.1U_0402_16V4Z

1

Clos e to Pin4 5

2

C632

0.1U_0402_16V4Z

1

LAN Conn.

JRJ4 5

Yellow LED+

Yellow LED-

8

PR4-

7

6

5

4

3

2

1

DETECT PIN1

PR4+

PR2-

PR3-

PR3+

PR2+

PR1-

DETCET PIN2

PR1+

Green LED+

Green LED-

FOX_JM36113-P1122-7F

CONN@

1

2

E

+3V_LAN

+LAN_VDD12

1

C633

2

SHLD1

SHLD1

C662

4.7U_0805_10V4Z

2

C622

0.1U_0402_16V4Z

1

10U_0805_10V4Z@

16

9

10

15

LANGND

9/2 0 DC2 340 01G00

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

RTL8111C/8102E 10/100/1000 LAN

LA-4117P

25 56Monday, March 16, 2009

E

0.3

A

Mini Card Slot 2---WLAN

+3VS +1.5VS+3VS_WLAN +1.5VS_WLAN +3VALW_WLAN

Max 1A Max 0.5A

R407

12

0_0805_5%

0.1U_0402_16V4Z

1 1

CLKRE Q_MCARD2#<15>

CLK_P CIE_MCARD2#<15>

CLK_P CIE_MCARD2<15 >

PCIE_PTX_C_IRX_N2<10>
PCIE_PTX_C_IRX_P2<10>

PCIE_ITX_C_PRX_N2<10>
PCIE_ITX_C_PRX_P2<10>

BT_COMBO_EN#<21>

2 2

New Card

RP@

Max 0.275A

+3VALW

3 3

EXP_CPPE#<20>

C665

CH_DATA<31>

CH_CL K<31>

+3VS_WLAN

C681

RP@

C679

PLT_RST#<11 ,14,19,25,27,32,33>

SYSO N<33,36,40>

SUSP#<28,3 3,36,38,41>

0.1U_0402_16V4Z

12

RP@

C680

1

1

C666

2

MINI_P CIE_WAKE#
CH_DATA
CH_CL K

1 2

R49

1 2

0_0402_5%

4.7K_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

PLT_RST#

1 2

EXP_CPPE#

4.7U_0805_10V4Z

CH_CL K

12

R48

+1.5VS

+3VS

RP@

R54

0_0402_5%

2

R47 0_0603_5%

12

Express Card Power Switch

Near to Express Card slot.

USB20_N11<20>

USB20_P11<20>

SMB_CK_CLK1<20>
SMB_CK_DAT1<20>

+1.5VS_PEC

CLKRE Q_NCARD#<15>

CLK_P CIE_NCARD#<15>

4 4

CLK_P CIE_NCARD<15>

PCIE_PTX_C_IRX_N0<10>
PCIE_PTX_C_IRX_P0<10>

PCIE_ITX_C_PRX_N0<10>
PCIE_ITX_C_PRX_P0<10>

A

+3V_PEC

+3VS_PEC

EXP_CPPE#

SMB_CK_CLK1
SMB_CK_DAT1

MINI_P CIE_WAKE#

PERST#

CLKRE Q_NCARD#
EXP_CPPE#

R406

1 2

0_0805_5%

0.01U_0402_16V7K

JP14

1
3
5
7
9

C668

1
3
5
7
9
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

G153G254G355G3

1

2

0.1U_0402_16V4Z

2

2

4

4

6

6

8

8

10

10

12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

CONN@

56

FOX_AS0B226-S99N-7F

9/2 0 SP0 10 00H S0 0/SP0 1000 LX00

9/2 0 STA ND OFF ( H= 7.5 m m) E S000 000D 00

U21

RP@

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin

AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538D00 1-TR-F_QFN20_4X4~D

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

GND

THERMAL_PAD

OC#

NC

USE TI TPS2231MRGPR

9/2 0 SP0 200 0B000

JEXP

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SANTA_130801-5_LTCO NN@

1

C669

2

WL_O FF#
PLT_RST#

SMB_CK_CLK1
SMB_CK_DAT1

WL_LED#

11
13

3
5

15

19

PERST#

8

16

7

21

RP@

C677

+1.5VS_PEC

RP@

C683

RP@

C684

B

+3VALW

R1043 0_0603_5%@

1 2

R1042 0_0603_5%

1

C670

4.7U_0805_10V4Z

2

+3VS_WLAN

+1.5VS_WLAN

+3VALW_WLAN

Max 0.3A Max 0.3A

USB20_N8 <20>
USB20_P8 <20>

WL_LED# <34>

WL_O FF#

+3V_PEC

+3VS_PEC

1

2

1

2

+3V_PEC

1

2

B

2 1

+1.5VS_PEC

Max 0.65A

+3VS_PEC

Max 1.3A

4.7U_0805_10V4Z

1

RP@

C678

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

RP@

C682

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

RP@

C685

2

0.1U_0402_16V4Z

D59
CH751H-40PT_S OD323-2

1

C667

0.1U_0402_16V4Z

2

1 2

+3VS_WLAN

WLOFF# <21>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Mini Card Slot 1---TV tuner / WWAN / Robson

+3VALW +3VS +1.5VS

+3VS_MINI

2007/08/02 2008/08/02

C

PA@

R971 0_0603 _5%

R972 0_0603 _5%@

0.1U_0402_16V4Z

MINI_P CIE_WAKE#<20>

CLKREQ_MCA RD1#<15>

CLK_P CIE_MCARD1#<15>

CLK_P CIE_MCARD1<15>

PCIE_PTX_C_IRX_N5<10>

PCIE_PTX_C_IRX_P5<10>

PCIE_ITX_C_PRX_N5<10>

PCIE_ITX_C_PRX_P5<10>

PA@

R401 0_0603_5%

1 2

39P_0402_50V8J

WW _OFF#

2 1

D60
CH751H-40PT_S OD323-2

Compal Secret Data

12

12

1

C671

PA@

2

C738

PA@

WW AN_POWER_OFF<33>

UIM_CLK UIMCLK

1 2

33_0402_5%

Deciphered Date

Max 2.7A

PA@

L78

1 2

0_1206_5%

1

C784

@

0.1U_0402_16V7K

2

1

2

WW OFF# <21>

+3VS_MINI

UIM_PWR
UIM_DATA

R421

UIM_RST
UIM_VPP

R1037

1 2

10K_0402_5%@

0.01U_0402_16V7K

PA@

1

C785

2

JP13

1

1

3

3

5

5

7

7

9

9

10
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

G153G254G355G3

56

SI2301BDS-T1-E3_SOT23-3

JP6

1

1

2

2

3

3

4

4

5

5

6

6

7

7

ACES_88266-07001

CONN@

UIM_PWRUIM_DATA

D

PA@

C786

0.1U_0402_16V4Z

2

2

4

4

6

6

8

8

10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

CONN@

FOX_AS0B226-S99N-7F

9/2 0 SP0 10 00H S0 0/SP0 1000 LX00

9/2 0 STA ND OFF ( H= 7.5 m m) E S000 000D 00

R1087 0_0603_5%@

1 2

1 3

D

G1
G2

+3VS_MINI + 1.5VS_MINI+3VALW_W WAN+3VS_MINI

4.7U_0805_10V4Z

PA@

1

C787

2

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

WW _OFF#
PLT_RST#

SMB_CK_CLK1
SMB_CK_DAT1

WW_LED#

Q167

@

S

G

2

9/2 0 SP0 200 0IQ00

8
9

0.1U_0402_16V4Z

PA@

1

C1070

2

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Max 0.5A

PA@

1

2

39P_0402_50V8J

39P_0402_50V8J

PA@

1

C1071

4.7U_0805_10V4Z

2

L79

0_0805_5%

0.01U_0402_16V7K

PA@

C1092

PA@

39P_0402_50V8J

USB20_N10 <20>
USB20_P10 <20>

WW_LED# <34>

PA@

+3VS_MINI+3VALW

12

PA@

C781

C1095

1

2

C1094

4.7U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

PA@

C1093
39P_0402_50V8J

2

1

2

Compal Electronics, Inc.

WLAN/TV tuner/Express Card

LA-4117P

E

E

PA@

C782

1

2

1

2

PA@

1

C783

2

+3VS_MINI

+1.5VS_MINI

+3VALW_WW AN

PA@

C1096
39P_0402_50V8J

26 56Monday, March 16, 2009

1

2

0.3

A

B

C

D

E

+VCC_OUT +VCC_ 4IN1

+3VS

C895

1 1

0.1U_0402_16V4Z@

U22

3

IN

4

EN

1

2

GND

G5250C2T1U_SOT23-5@

2

40mil

1

OUT

5

OUT

C896

@

1U_0603_10V4Z

12

1

2

R123

@

150K_0402_5%

+VCC_ 4IN1 +VCC_ 4IN1

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7

SDCMD_MSBS_XDWE#
XDWP#_SDW P#
XD_ALE
XD_CD#
XD_RB#
XD_RE#
XDCE#
XD_CLE

Use 0805 type and over 20 mils
trace width on both side

+VCC_ 4IN1+VCC_OUT

R383

1 2

0_0805_5%

C689

10U_0805_10V4Z

2 2

CR_CPPE#<20>

CR_WAKE#<21>

3 3

1

2

+3VS

12

R124

10K_0402_5%

2

G

Q54

1 3

D

S

2N7002_SOT23-3

0_0402_5%

1 2

R369

1

C694

0.1U_0402_16V4Z

2

CPPE#

XDCD 0#_SDCD#

470_0402_5%

PCIE_PTX_C_IRX_N1<10>
PCIE_PTX_C_IRX_P1<10>

R370

+5VS_LED

12

21

D5
HT-F196BP5_WHITE

13

D

@

S

R1070

1 2

0_0402_5%

Q53

2

G

2N7002_SOT23-3

@

4.7K_0402_5%

100_0402_5%

100P_0402_25V8K

Pla ce R4 13 ,C902 clo se to JRE AD.20 ; R41 2,C901

L

clo se to JREA D.26; R411,C90 0 cl ose to JREAD.37

CLK_P CIE_MCARD0#<15>

CLK_P CIE_MCARD0<15>

PCIE_ITX_C_PRX_N1<10>
PCIE_ITX_C_PRX_P1<10>

C693 0.1U_0402_16V7K

1 2

C697 0.1U_0402_16V7K

1 2

+3VS_CR

PLT_RST#<11 ,14,19,25,26,32,33>

+VCC_OUT

CR_LED #

12

R454

White LED: VF=3V, IF = 1 0mA , R es = 200 ohm

SDCLK

R413

@

1 2
2

C902

@

1

PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1

R114

8.2K_0402_5%

10K_0402_5%

CPPE#

XDCD1#_MSCD#
XDCD 0#_SDCD#

At least 20 mils

L

use for PWR_EN#

8mA sink current

Card Reader Connector

JREAD

3

XD-VCC

32

XD-D0

10

9
8
7
6
5
4

34
33
35
40
39
38
37
36

11
31

41
42

MSCLK XDCE#

R412

@

100_0402_5%

C901

@

100P_0402_25V8K

APREXT

12

12mil

R409

12

T45P AD

7 IN 1 CONN

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

7IN1 GND
7IN1 GND

7IN1 GND
7IN1 GND

TAITW_R015-B10-LM

CONN@

@

100_0402_5%

1 2
2

@

100P_0402_25V8K

1

Power Circuit

D3 Normal 30mA Deepest 3mA

U23

3

APCLKN

4

APCLKP

9

APRXN

8

APRXP

11

APTXN

12

APTXP

7

APREXT

38

PCIES_EN

39

PCIES

1

XRSTN

2

XTEST

13

SEEDAT

14

SEECLK

15

CR1_CD1N

16

CR1_CD0N

17

CR1_PCTLN

21

CR1_LEDN

JM B385- LGEZ0 A_LQF P48_7 X7

R411

1 2
2

C900

1

JMB385

SD-WP-SW

58mA

1mA

SD-VCC

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CMD

SD-CD-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS

APVDD

APV18
TAV33

DV33

45mA

DV33
DV33
DV18

25mA

DV18

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

APGND

GND
GND
GND
GND

21
28

20
14
12
30
29
27
23
18
16
25
1

2

26
17
15
19
24
22
13

5
10
30

19
20
44
18
37

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

34

NC

35

NC

36

NC

6

24
31
32
33

SDCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
SDCMD_MSBS_XDWE#
XDCD 0#_SDCD#

XDWP#_SDW P#

MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#

+1.8VS_OUT

20mil

@

C892

Ripple 100mV

Ripple 100mV

Ripple 250mV

Ripple 250mV

XD_SD_MS_D0

XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
XDWP#_SDW P#
XD_CLE
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
XD_RE#
XD_RB#
XD_ALE

pla ce ne ar pin 5 a nd
pin 10 .

0.1U_0402_16V4Z

1

C688

2

10U_0805_10V4Z

C6950 .1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

XDWP#_SDW P#

XD_RB#

1U_04 02_6.3V4Z

1

C687

2

12

1

C691

2

1

C686

2

R457 22_0402_5%
R456 22_0402_5%
R455 22_0402_5%

L

1

1

C893

2

2

0.1U_0402_16V4Z

R1021

0_0603_5%

1

C692

2

0.1U_0402_16V4Z

+1.8VS_OUT

1

C690

0.1U_0402_16V4Z

2

12
12
12

Pla ce R4 55 ~R457 clos e to U23.42

+VCC_ 4IN1

R45 10K_0402_5%

12

12

R106 10K_ 0402_5%

R1020

12

0_0603_5%

@

+3VS+3VS_CR

12

SDCLK
MSCLK
XDCE#

+1.8VS

D40

R121 4.7K_0402 _5%

R111 4.7K_0402 _5%

1

12

R40510K_0402_5%

12

R12210K_0402_5% @

12

R106910K _0402_5%

12

R86200K_ 0402_5%

1

2

XDCD 0#_SDCD#

XDCD1#_MSCD#

2

3

DAN202 U_SC70

Strap pin for JMicro

+3VS_CR

+3VS_CR

12

12

XD_CD#

C696

270P_0402_50V7K

XD_CLE

XD_ALE

XD_RE#

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

PCI-E I/F Card Reader-JM385

LA-4117P

27 56Monday, March 16, 2009

E

0.3

A

B

C

D

E

CODEC POWER

R885

1 2

+3VS

BLM18BD601SN1D_0603

1 1

+3VDD _CODEC +VDDA _CODEC

0.1U_0402_16V4Z

1

C733

C734

2

1U_0603_10V4Z

+3VS_HDA

R978

1 2

1

2

BLM18BD601SN1D_0603

1

C1046

0.1U_0402_16V4Z

2

+VDDA _CODEC_R+3VS

1

C730

2

0.1U_0402_16V4Z

R979

1 2

0_0603_5%

1

C731

1U_0603_10V4Z

2

W=40Mil

1 2

C728 0.1U_0402_16V 4Z

SUSP#<26,3 3,36,38,41>

+5VALW +VDDA _CODEC

U32

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

5

4

1

2

1

C732

0.1U_0402_16V4Z

2

(4.75V(4.56~4.94V))

300mA

C729

2.2U_0805_16V4Z

U27

12

SENSEB#

9

DVDD_CORE*

1

DVDD_CORE

25

AVDD1*

38

AVDD2**

3

DVDD_IO

32

MONO_OUT

6

BITCLK

5

SDO

8

SDI_CODEC

10

SYNC

11

RESET#

46

DMIC_CLK

33

CAP2

12

PCBEEP

40

NC / OTP

34

SENSE_B / NC

37

NC

18

NC

19

NC

20

NC

27

VREFFILT

26

AVSS1*

42

AVSS2**

7

DVSS**

92HD71B7X5NLGXA1X8_QFN48_7X7

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

VOL_UP/DMIC_0/GPIO 1

VOL_DN/DMIC_1/GPIO 2

GPIO 3

VREFOUT-E / GPIO 4

GPIO 5

GPIO 6

SPDIF OUT1 / GPIO 7

SPDIF OUT0

VREFOUT-B

VREFOUT-C

SENSE_A

PORTA_R

PORTA_L

PORTB_R

PORTB_L

PORTC_R

PORTC_L

PORTD_R

PORTD_L

PORTE_R

PORTE_L

PORTF_R

PORTF_L

+3VDD _CODEC

+VDDA _CODEC_R

HDA_B ITCLK_CODEC

12

R525

47_0402_5%@

1

C745

33P_0402_50V8K@

2 2

3 3

2

EC_BEEP<33>

SB_SPKR<20>

HDA_B ITCLK_CODEC<20>

HDA_S DOUT_CODEC<20>

HDA _SYNC_COD EC<20>

HDA_R ST#_CODEC<20>

R563 47K_0402_5%@

1 2

R524 47K_0402_5%

1 2

R523 10K_0402_5%

1 2

C956 0.1U_0402_16V4Z

1 2

+VDDA _CODEC_R

SENSE_B#<35>

HDA_S DIN0<20>

DMIC_CLK<17>

R982 5.1K_0402_1%

1 2

R910 39.2K_0402_1%RP@

1 2

+3VS_HDA

HDA_B ITCLK_CODEC

HDA_S DOUT_CODEC

R522 33_0402_5%

1 2

HD A_SYNC_CO DEC

HDA_R ST#_CODEC

R230

1 2

C979

RP@

0.1U_0402_16V4Z

10U_0805_10V4Z
C744

1 2

22_0402_5%RP@

1 2

C913 1U_0603_10V4Z

MONO_INR

0.1U_0402_16V4Z
C955

1

2

VC_RE FA

EAPD_ CODEC

47

2

4

30

31

43

44

SPDIF _OUT

45

48

VREFOUT_B

28

29

SENSE

13

HP_OUTR

41

HP_OUTL

39

MIC_EXTR

22

MIC_EXTL

21

MIC_IN R

24

MIC_IN L

23

LINE_OUT_R

36

LINE_OUT_L

35

DOCK_ MICR

15

DOCK_M ICL

14

17

16

EAPD_ CODEC <33>

DMIC_DAT <17>

SPDIF_OUT <35>

T21PAD

VREFOUT_B <29>

R548 5.1K_0402_1%

1 2

R569 20K_0402_1%

1 2

R571 39.2K_0402_1%

1 2

R570 10K_0402_1%

1 2

C951 0.1U_0402_16V4Z

1 2

HP_OUTR <29>

HP_OUTL <29>

1 2

C981 1U_0603_10V6K

1 2

C982 1U_0603_10V6K

LINE_OUT_R <29>

LINE_OUT_L <29>

1 2

C985 1U_0603_10V6KRP@

1 2

C986 1U_0603_10V6KRP@

+VDDA _CODEC_R

HP Jack & Dock

Internal SPKR.

EXTMIC_DET# <29>
JACK_DET# <29,35>
INTMIC_DET# <29>

C983 0.022U_0603_25V7KPRM @

1 2

C984 0.022U_0603_25V7KPRM @

1 2

12

RM@

R911

0_0603_5%

1 2

R422 0_0603 _5%PR@

MIC_EXT_R <29>

MIC_EXT_L <29>
MIC_IN _R <29>

MIC_IN _L <29>

DOCK_ MIC_R <35>

DOCK_M IC_L < 35>

Jack MIC

Internal MIC

DOCK MIC

C746

@

1 2

0.1U_0402_16V4Z

C747

@

1 2

0.1U_0402_16V4Z

C748

SENSE A

Port

4 4

A

B

C

D

39.2K E

20K

10K

5.11K

A

PortResistor

F

G

H

SENSE B

Resistor

39.2K

20K

10K

5.11K

@

1 2

C749

@

1 2

1 2

1 2

1 2

B

@

0_0402_5%

R195

@

0_0805_5%

0_1206_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R1006

R198

Use an 80mil to
connect ion o r place
a 1206 resistor under
CODEC with double
vias.

Secur ity Classification

GNDA <29>

GNDAGND

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet

Compal Electronics, Inc.

Audio Codec-IDT9271B7

LA-4117P

28 56Monday, March 16, 2009

E

0.3

of

A

B

C

D

E

0.1U_0402_16V4Z

1

C767

2

2

3

18

14

4

8

12

NC

10

B+

12

RP@

R975
330K_0402_5%

Q147A

6 1

Q147B

3

1

2

0.1U_0402_16V4Z

SPKR+

SPKR-

SPKL+

SPKL-

1

2

2

5

4

C773 1 50U_Y_6.3VM

+

1 2

C774 1 50U_Y_6.3VM

+

1 2

C766

10U_0805_10V4Z

1 1

U28

C1049 0.022U_0603_25V7K

1 2
1 2

LINE_ OUT_R<28>

LINE_OUT_L<28>

2 2

3 3

4 4

R1002

0_0402_5%

R1005

0_0402_5%

EC_MUTE#<33>

JACK_DET#<28,35>

0_0402_5%

HP_OUTR<28>

HP_OUTL<28>

A

C1052 47P_0402_50V8J

C1050 0.022U_0603_25V7K

12

C1053 47P_0402_50V8J

C1040 0.022U_0603_25V7K

C1054 47P_0402_50V8J

C1041 0.022U_0603_25V7K

12

C1055 47P_0402_50V8J

EC_MUTE#

RP@

10K_0402_5%

1 2

HP_DET#

R973

RM@

R414

1 2
1 2

1 2
1 2

1 2
1 2

VREFOUT_B<28>

MIC_EXT_R<28>

MIC_EXT_L<28>

+3VALW

10K_0402_5%

1 2

2

RP@

R974

+3VALW

1 2
61

7

17

9

5

19

R909

12

0_0402_5%

R907

4.7K_0402_5%

MIC_EXT_R

MIC_EXT_L

Clo se to CO DEC U27

2

G

RP@

2N7002DW -7-F_SOT363-6
Q145A

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

C742

12

12

R908

4.7K_0402_5%

EXTMIC IN

13

D

RP@

Q161

S

2N7002_SOT23-3

B

16

15

6

VDD

PVDD1

PVDD2

GND41GND311GND213GND1

20

1 2

1U_0603_10V4Z

3

RP@

2N7002DW -7-F_SOT363-6

5

Q145B

4

2N7002DW -7-F_SOT363-6RP@

GAIN0

GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

THERMAL PAD

21

TPA6017A2_TSSOP20

2N7002DW -7-F_SOT363-6RP@

R594

1 2

0_1206_5%

1

C1051

2

R1000

100K_0402_5%

@

R1003

100K_0402_5%

Ke ep 1 0 mi l wid th

C1044
1U_0805_50V4Z

2

5

4

HP_OUT_R

HP_OUT_L

+5VS+5VAMP

GAIN0 GAI N1 Av(i nv)

D61

@

R125

12

R126

12

+

+

0 6dB

0

1

MIC_IN _L

MIC_IN _R

2

3

1

GNDA_ DOCK_2

GNDA_ DOCK_1GNDA_ DOCK

DOCK_ LOUT_CR_R

DOCK_ LOUT_CR_LDOCK_LOUT_L

15.6dB

21.6dB

ANA_MIC_DET<33>

INTMIC_DET#<28>

GNDA_ DOCK_2 <35>

GNDA_ DOCK_1 <35>

R968

RP@

DOCK_ LOUT_C_R

1 2

60.4_0603_1%

R969

RP@

DOCK_LOUT_C _L

1 2

60.4_0603_1%

+VDDA _CODEC

2N7002_SOT23-3

15.6dB

12

12

Q148A

2N7002DW-7-F_SOT363-6RP@

Q148B

+5VS

12

R1001
100K_0402_5%

12

R1004

100K_0402_5%@

R977 0_0603_5%RP@

1 2

61

3

2N7002DW -7-F_SOT363-6RP@

DOCK_LOUT_R

0

0 1 10dB

1

1

PRM@

PSOT24C_SOT23-3

0_0402_5%

0_0402_5%

RP@

C775 1 50U_Y_6.3VM

1 2

RP@

C776 1 50U_Y_6.3VM

1 2

HP OUT For M/B

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

SPKR­SPKR+
SPKL­SPKL+

1

PR@

MIC_IN _R<28>

Q160

C760

100P_0402_50V8J

MIC_IN _L<28>

D

S

13

2

4.7K_0402_5%

+3VS

2

G

C761

100P_0402_50V8J

R906

1K_0402_5% PRM@

R904

PRM@

MIC_IN _L
MIC_IN _R

R955 10K_ 0402_5%PRM@

2N7002_SOT23-3

12

R103
10K_0402_5%

PA@

Clo se to CO DEC U27

EXTMIC_DET#<28>

CIR _IN<33,35>

DOCK_ LOUT_C_R <35>

HP OUT For Docking

DOCK_LOUT_C _L <35>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

1

1

C762

2

100P_0402_50V8J

C743

PRM@

1U_0603_10V4Z

1 2

12

R905

PR@

4.7K_0402_5%

12

13

D

Q151

S

C763

100P_0402_50V8J

2

12

12

PR@

9/2 0 SP0 20 00H 70 0/SP0 2000 H900

MIC_EXT_R
MIC_EXT_L

HP_OUT_R
HP_OUT_L

EXTMIC_DET#
HP_DET#

CIR _IN

+5VL

Compal Electronics, Inc.

AMP & Audio Jack

LA-4117P

1

2

+VDDA _CODEC

12

R951

PR@

100K_0402_5%

2

G

10
11
12
13
14

9/2 0 SP0 200 0H800

E

SPEAKER

JP20

1

1

2

2

3

3

4

4

5

GND1

6

GND2

E&T_3806-F04N-02RCON N@

INTMIC IN

JP42

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACES_88231-04001

CONN@

Audio/B & CIR

JP43

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9
10
11
12
13
14

ACES_87213-1400GCON N@

29 56Monday, March 16, 2009

0.3

A

1 1

B

C

D

E

ACCELEROMETER

RP@

D44

2 1

CH751H-40PT_S OD323-2

2 2

VDDIO absolute man
rating is VDD+0.1

+3VS_ACL_IO

3 3

+3VS_ACL

RP@

R997
0_0402_5%

1 2

R999 10K_0402_5%

L

+3VS_ACL+3VS +3VS_ACL_IO

RP@

R959 0_0603_5%

1 2

RP@

1

RP@

U63

Vdd_IO

GND

Reserved

GND

GND

Vdd

2

12

1

C1031

10U_0805_6.3V6M

2

SMB_CK_CLK0

14

SCL / SPC

SDA / SDI / SDO

CS

LIS302D LTR_LGA14_3x5

7

SDO

Reserved

GND

INT 2

INT 1

13

12

11

10

9

8

SMB_CK_DAT0

RP@

0_0402_5%

1 2

C1030

RP@

0.1U_0402_16V4Z

1

2

3

4

5

6

RP@

Mus t b e pla ce d i n the cent er of th e s yste m.

0011101b

R998

SMB_CK_CLK0 <8,9,15,20>

SMB_CK_DAT0 <8 ,9,15,20>

HDD_H ALTLED <34>

ACCE L_INT <19>

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Accelerometer

LA-4117P

30 56Monday, March 16, 2009

E

0.3

A

B

C

D

E

Left side USB CONNECTOR Right side USB 0&1 Board Conn

Max 2.5A

1 1

1

C788

4.7U_0805_10V4Z

2

USB_EN#

U40

1

GND

2
3
4

OUT

IN

OUT
OUT

IN

OC#

EN#

TPS2061IDGN_MSOP8~N

8
7
6

1

5

+

C789

2

150U_D_6.3VM

W=100mils

1

C790

2

0.1U_0402_16V4Z

+USB_VCCA+5VALW

C791

1000P_0402_50V7K

+USB_VCCA

USB20_N2_R

1

1

+USB_VCCA

C1121

2

SATA_TXN2

2

0.1U_0402_16V4Z

D11

4

IO1

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

D12

4

IO1

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4

@

2

1

2

1

USB20_P2_R

SATA_TXP2

USB20_N2<20>

USB20_P2<20>

SATA_TXP2<21>
SATA_TXN2<21>

SATA_RXN2_C<21>

SATA_RXP2_C<21>

L51

4

4

1

1

WCM-2012-900T_4P

C792 1000P_0402_50V7K

1 2

C793 1000P_0402_50V7K

1 2

3

3

2

2

Max 0.5A

+USB_VCCA

USB20_N2_R
USB20_P2_R

SATA_TXP2
SATA_TXN2

SATA_RXN2
SATA_RXP2

1
2
3
4

5
6
7
8

9
10
11

12
13
14
15

CONN@

JESAT

VBUS
D­D+
GND

GND
A+
A­GND
B­B+
GND

GND
GND
GND
GND

USB

ESATA

TYCO_1759576-1

USB_EN#<33>

+5VALW

1

2

USB20_N0<20>
USB20_P0<20>

USB20_N1<20>
USB20_P1<20>

+5VALW

C1109
820P_0402_25V7K

USB_EN#

JP47

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

9/2 0 SP0 200 0DX00

CONN@

JST_SM06B-XSRK-ETB(HF)

2 2

Finger printer

Q31 SI2301BDS-T1-E3_SOT23-3@

S

D

13

G

2

USB_EN#

USB20_N7<20>
USB20_P7<20>

D21

+3VS_FB

USB20_N7

3 3

@

4

3

PRTR5V0U2X_SOT143-4

2

IO1

VIN

1

GND

IO2

USB20_P7

+3VS_FB

1

C832

0.1U_0402_16V4Z

2

USB20_N7
USB20_P7

R581

1 2

0_0603_5%

JP39

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

CONN@

9/2 0 SP0 100 0B000

+3VS+3VALW

BT Connector

JP32

CONN@

ACES 87213-0800G

9/2 0 SP0 20 00H C00 /SP0 2000H B00

BT_OFF<21>

Check BT power consumption < 1A

GND2
GND1

8
7
6
5
4
3
2
1

1

C798

1U_0603_10V4Z

2

10
9
8
7
6
5
4
3
2
1

USB20_P6
USB20_N6

BT_LED

R517 1K_0402_5%@
R518 1K_0402_5%@

+3VAUX_BT

R520

1 2

10K_0402_5%

1 2
1 2

USB20_N6

12

R519

100K_0402_5%

CONN@

D16

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

Q24 SI2301BDS-T1-E3_SOT23-3

S

G

2

0.01U_0402_16V7K

1 2

C802 0.1U_0402_16V 4Z

D

13

GND

GND
GND

IO1

1

2

8
7
6

6

5

5

4

4

3

3

2

2

1

1

JP55

+3VAUX_BT

USB20_P6

2

1

0.1U_0402_16V4Z

1

C799

2

USB20_P6
USB20_N6
BT_LED

+3VAUX_BT+3VS

1

C800

2

4.7U_0805_10V4Z

USB20_P6 <20>
USB20_N6 <20>
BT_LED <34>
CH_DATA <26>

CH_CL K <26>

C801

+3VAUX_BT

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

USB, BT, eSATA,FPR

LA-4117P

31 56Monday, March 16, 2009

E

0.3

A

B

C

D

E

Ripe ly 2 .0 will support 1 6Mb SPI RO M

SPI Flash (16Mb*1)

SA000 01IT00

SPI_CS#<33>

SPI_CLK<33>

EC_SO_SP I_SI<33>

Nee d add ba ck R2 21 if no e xt BIO S desig n U 30 in stall.

L

0.1U_0402_16V4Z

SPI_CS# INT_SPI_CS#

C803

0.1U_0402_16V4Z

+3VAL

1

2

U31

8
7
6
5

AT24C16A N-10SI-2.7_SO8

@

VCC
WP
SCL
SDA

GND

A0
A1
A2

12

R521
100K_0402_5%

1
2
3
4

12

R526
100K_0402_5%

+3VL

1 2

R995 0_0402_5%@

+3VALW

1 2

1 1

2 2

R996 0_0402_5%

SMB_EC_CK1<6,3 3,34,37>
SMB_EC_DA1<6,3 3,34,37>

+3VL

1

C484

2

1 2

R221 0_0402_5%

1 2

R227 0_0402_5%

R229 0_0402_5%

EC_SO _SPI_SI_R EC_SI _SPI_SO_R

12

20mil s

SPI_CLK_R

CONN@

U29

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

D

WIES ON G6179 8P SPI

&U29

4

45@

SA00001IT00

2

Q

12

R223 0_0402_5%

EC_SI _SPI_SO <33>

3 3

SIRQ<19,33>

LPC_AD3<19,33>

LPC_AD1<19,33>

LPC_FRAME#<19,33>

4 4

A

LPC Debug Port

+3VALW

SIRQ

LPC_AD3

LPC_AD1

LPC_FRAME#

7

8

9

10

9/2 0 ???? ??

H31

LPC_DR Q#

56

PLT_RST#

4

LPC_AD2

3

LPC_AD0

2

CLK_P CI_SIO

1

DEBU G_PAD@

B

@

1 2
2

1

LPC_DR Q# <19>

PLT_RST# <11 ,14,19,25,26,27,33>

LPC_AD2 <19,33>

LPC_AD0 <19,33>

CLK_P CI_SIO <19>

R232

22_0402_5%

C486

@

22P_0402_50V8J

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet

Compal Electronics, Inc.

BIOS ROM/Debug Tool

LA-4117P

32 56Monday, March 16, 2009

E

of

0.3

A

+3VL_EC

0.1U_0402_16V4Z

1

1

2

0.1U_0402_16V4Z

1 1

C805

C806

2

0.1U_0402_16V4Z

1

C807

2

1000P_0402_50V7K

CLK_P CI_EC<19,23>

1

2

+3VL_EC

1000P_0402_50V7K

1

C809

C808

2

1/19 Change EC P/N to D3 version

C811

R533

R530

1 2

1 2

12

0.1U_0402_16V4Z

33_0402_5%@

47K_0402_5%

C810

1 2

15P_0402_50V8J@

02/22 Add R1076, C1104 and R10 77 for EM I request.

+3VL_EC

2 2

3 3

4 4

12

R538
10K_0402_5%

LID_SW#

+3VL

R528

+3VS

R529

R531

R532

R513

+3VL

R514 4.7K_0402_5%

R515 4.7K_0402_5%

EC DEBUG port

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

10K_0402_5%

1 2

1 2

SMB_EC_DA1

12

SMB_EC_CK1

12

SMB_EC_DA2

12

SMB_EC_CK2

12

WL_BLUE_BTN

EC_CLK

EC_DAT

12

ESB_CLK<34>
ESB_DAT<34>

33P_0402_50V8K

Ple as e clo se to EC.

L

ON/OF F#<34>

DOCK_SLP_BTN#<35>

R542 0_0402_5%

LAN_P OWER_OFF<25>

R1076 0_0402_5%

ESB_CLK

1 2

ESB_DAT

C1104

@

4.7K_0402_5%

1 2

RP@

1 2

R1077 0_0402_5%

1

2

+3VL_EC

R543

32.768 KHZ_12.5PF_Q13MC30610003

VLDT_EN<36>

1 2

R1063 10K_0402_5%

C813
15P_0402_50V8J

1 2

3

NC

2

NC

1 2

C815
15P_0402_50V8J

LAN_P OWER_OFF E51_RXD

02/15 Remove JP34 and

EC_CLK
EC_DAT

H_THERMTRIP#_EC<6>

OUT

IN

Y7

GATEA20<20>
KB_RST#<20>

SIRQ<19,32>

LPC_FRAME#<19,32>

LPC_AD3<19,32>
LPC_AD2<19,32>
LPC_AD1<19,32>
LPC_AD0<19,32>

PLT_RST#<11 ,14,19,25,26,27,32>

EC_SC I#<20>

HDARST#<20,23>

SMB_EC_CK1<6,3 2,34,37>
SMB_EC_DA1<6,3 2,34,37>
SMB_EC_CK2<6>
SMB_EC_DA2<6>

SLP_S3#<20>
SLP_S5#<20>
EC_SMI#<20>

LID_SW#<34>

WL_BLUE_BTN<34>

12

NUM_LED#<34>

4

1

R544

1 2

0_0402_5%

B

CONA#<35>

GATEA20
KB_RST#
SIRQ
LPC_LFRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_P CI_EC

PLT_RST#
ECRST#
EC_SC I#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
EC_CLK
EC_DAT
WL_BLUE_BTN

H_THERMTRIP#_EC

E51_TXD
E51_RXD
ON/ OFF#

CR Y2

12

@

R545
20M_0402_5%

CR Y1

R527

1 2

0_0805_5%

U33

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

+3VL_EC

+EC_AVCC

+3VL_EC+3VL

9

22

33

96

VCC

VCC

VCC

VCC

PW M Outp ut

DA Ou tput

PS 2 Inter face

Int . K/B
Matr ix

SP I Device Inter face

SP I Fl ash R OM

SM Bu s

GP IO

GND

GND

GND

11

24

35

12

L80
0_0603_5%

1 2

C816 0.1U_0402_16V 4Z

C

+EC_AVCC

67

111

125

VCC

VCC

AVCC

INVT_PWM/PWM 1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD In pu t

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

GP IO

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

ICH_PWROK/GPXO06

G PO

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

GP I

AGND

GND

GND

KB926QFC0_LQFP128_14X14

69

94

113

ECAGND

AD3/GPIO3B
AD4/GPIO42

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

EC_SWI#/GPXO06

BKOFF#/GPXO08

GPXO10
GPXO11

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

L81

1 2

0_0603_5%

D

+3VL

1

+

C1105
22U_A_4VM

@

2

EC_PWM

21

FAN_PWM

23

EC_BEEP

26

ACOF F

27

BATT_TEMP

63

BATT_OVP

64
65
66

TP_BTN#

75
76

68
70

IRE F

71
72

83
84
85
86

TP_CLK

87

TP_DATA

88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

1 2

R1044 100K_0402_5%

CIR _IN
NB_OTP
FSTCHG

BAT_LED#
ON/OFF BTN_LED#
SYS ONSMB_EC_CK2
VR_ON
AC_IN _EC

EC_RSMRST#

SB_PWRGD
BKOFF#

TP_LED#

SUSP#
PWRBTN_OUT#
NMI_DBG#

C814 4.7U_0805_10V 4Z

Need 4.7uf for 926 C version

EC_PWM <17>
FAN_PWM <4>
EC_BEEP <28>
ACOF F <38>

C812

BATT_TEMP <37>
BATT_OVP <37>
ADP_I <38>
ADP_I D <37>
TP_BTN# <34>
ANA_MIC_DET <29>

DAC_B RIG <17>
VCTRL <38>
IREF <38>
AC_SET <38>

EC_MUTE# <29>
USB_EN# <31>
I2C_INT <34>
MUTE_LED <35>
TP_CLK <34>
TP_DATA <34>

AC_LED# <37>
DOCK_VOL_UP # <35>
DOCK_ VOL_DWN# <35>
VGATE <43>

EC_SI _SPI_SO <32>
EC_SO _SPI_SI <32>
SPI_CLK <32>
SPI_CS# <32>

R46 10K_0402_5%

CIR _IN <29,35>
NB_OTP <37>
FSTCHG <38>
STD_ADP <38>
CAPS_LED# <34>
BAT_LED# <34>
ON/OFF BTN_LED# <34>

SYSO N <26,36,40>

EC_RSMRST# <20>

EC_LID_OUT# <20>
EC_ON <36,39>

WL_BLUE_LED# <34>
SB_PWRGD <6,20,43>
BKOFF# <17>
WW AN_POWER_OFF <26>

TP_LED# <34>

ENBKL <11>
EAPD_ CODEC <28>DIM_LED<36>
EC_THERM# <21>
SUSP# <26,28,36,38,41>
PWRBTN_OUT# <20>

12

1 2

1 2

0.01U_0402_16V7K

ECAGND

L

Keyboard Connector

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2

KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

JP33

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

GND1

26

GND2

ACES_85201-24051

CONN@

9/2 0 SP0 10 00F F0 0/SP0 1000 G300

+5VL

12

R541 10K_ 0402_5%

2 1

D54
CH751H-40PT_S OD323-2

R1040
150K_0402_5%

1 2

C1073
100P_0402_50V8J

TP_ LED#= L, T/ P d is abl e
TP _L ED# =f loa t ( GP O), T/P enabl e

VFIX_EN <43>

R547

1 2

0_0402_5%

12

VR_ON <43>
AC_IN <21,38>

+3VL_EC

PCI_S ERR# <19>

E

For EMI

KSO15

C213 100P_0402_25V8K@

KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0

KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

1 2

C609 100P_0402_25V8K@

1 2

C754 100P_0402_25V8K@

1 2

C756 100P_0402_25V8K@

1 2

C757 100P_0402_25V8K@

1 2

C758 100P_0402_25V8K@

1 2

C759 100P_0402_25V8K@

1 2

C764 100P_0402_25V8K@

1 2

C768 100P_0402_25V8K@

1 2

C769 100P_0402_25V8K@

1 2

C822 100P_0402_25V8K@

1 2

C823 100P_0402_25V8K@

1 2

C824 100P_0402_25V8K@

1 2

C825 100P_0402_25V8K@

1 2

C826 100P_0402_25V8K@

1 2

C875 100P_0402_25V8K@

1 2

C876 100P_0402_25V8K@

1 2

C877 100P_0402_25V8K@

1 2

C878 100P_0402_25V8K@

1 2

C884 100P_0402_25V8K@

1 2

C885 100P_0402_25V8K@

1 2

C886 100P_0402_25V8K@

1 2

C887 100P_0402_25V8K@

1 2

C888 100P_0402_25V8K@

1 2

KB Back Light Conn

R516

150_0603_1%

JP48

1

1

2

2

3

5

3

G1

4

6

4

G2

ACES_85201-04051

CONN@

9/2 0 SP0 10 00K C00 /SP0 10009 O10

DOCK_VOL_UP #

DOCK_ VOL_DWN#

TP_CLK

TP_DATA

10K_0402_5%

10K_0402_5%

R534

10K_0402_5%

1 2

R535

10K_0402_5%

1 2

SUSP# SYSON

12

R536
100K_0402_5%

R1050

TP_BTN#

1 2

10K_0402_5%

+5VS_LED

12

R589

12

12

R590

12

R539
100K_0402_5%

+3VS

+5V_TP

+3VS

reserve R1068 for EC debug.

R1068

@

1 2

0_0603_5%

A

E51_TXD

B

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet

Compal Electronics, Inc.

EC KB926/KB conn

LA-4117P

33 56Monday, March 16, 2009

E

of

0.3

A

B

C

D

E

ON/OFF Button Connector

+5VALW_LED

JP25

1
3
5
7
9
11

GND13GND14GND15GND16GND17GND

ON/ OFF#
ON/OFF BTN_LED#

2

2

4

4

6

6

8

8

10

10

12

12

18

ON/OF F#<33>

ON/OFF BTN_LED#<33>

1 1

MDC 1.5 Conn.

HDA_S DOUT_MDC<20>

HDA_S YNC_MDC<20>

HDA_S DIN1<20>

HDA_RST#_MDC<20>

2 2

+3VS

1

1

C779

C778

2

2

1000P_0402_50V7K

0.1U_0402_16V4Z

R495

1 2

33_0402_5%

1

C780

4.7U_0805_10V4Z

@

2

HDA_S DIN1_MDC

9/2 0 SP0 100 0J100
9/2 0 STA ND OFF ( H= 5.0 mm) ES0 00000 800

1
3
5
7
9

11

ACES_88020-12101

CONN@

JP1

1

1

2

2

3

3

G1

4

4

G2

ACES_85201-04051

CONN@

+3VS

+3VS

R496

10_0402_5%@

1 2
1

C777

10P_0402_50V8J@

2

5
6

HDA_B ITCLK_MDC <20>

TouchPAD ON/OFF LED

HDD/G-Sensor LED

+5VS

12

R20

10K_0402_5%

61

Q7A

2N7002DW-7-F_SOT363-6

SATA_LED#<21>

3 3

2N7002DW -7-F_SOT363-6

2

Q7B

5

+5VS_LED

R987

200_0402_5%

3

WHITE

4

2N7002_SOT23-3@

Q156

+3VS

12

12

R988

RP@

200_0402_5%

21

43

D18

HT-29 7UY5/BP5_YELLOW -WHITE

YELLO W

D

S

13

1 2

R42

RP@

0_0402_5%

2

G

HDD_H ALTLED# <21>

HDD_H ALTLED <30>

HT-29 7UY5/BP5_YELLOW -WHITE

+5VS

R985

@

10K_0402_5%

200_0402_5%

PA@

12

D17

2N7002_SOT23-3

TP ON/OFF

SW1
SMT1-05-A_4P

3

4

5

+5VALW +5V_TP

SYSON #<35,36,42>

+5VS_LED

12

12

R984

2

G

Q153

R983

200_0402_5%

21

43

YELLO W

WHITE

13

D

TP_LED#

S

T/P Enab le (TP_ LED#=L)-> White
T/P Disa ble (TP _LED#=X)-> Amber

1

2

6

R235 0_0603_5%

43

YELLO W

TP_BTN#

1 2

S

+3VALW

12

R1038

10K_0402_5%@

TP_BTN# <33>

Max 0.5A

D

13

Q85

@

G

SI2301BDS-T1-E3_SOT23-3

2

21

PRM@

D19

WHITE

HT-29 7UY5/BP5_YELLOW -WHITE

TP_LED# <33>

M/B TO TP/B

C819

0.1U_0402_16V4Z

JP37

1
2

5

3

G1

6

4

G2

ACES_85201-04051

CONN@

9/2 0
SP0 10 00K C0 0/S P01E 0009 00

SWITCH BOARD.

ON/OFF BTN_LED#
ON/ OFF#

ENE
CY S

+3VL

R1065 0_0402_5%RM @
R1066 0_0402_5%RM @

WL_BLUE_BTN<33>

SMB_EC_CK1<6,3 2,33,37>

ESB_CLK<33>
ESB_DAT<33>

SMB_EC_DA1<6,3 2,33,37>

：：：：

ESB

：：：：

MB_EC

R558 10K_0402_5%RM@

11/11 Del reserved LDO for ENE ca p board

Max 0.5A

+5V_TP

1

2

1

TP_CLK

2

TP_DATA

3
4

100P_0402_50V8J

1 2
1 2

WL_BLUE_LED#

I2C_INT

12

TP_DATA
TP_CLK

D31

PSOT24C_SOT23-3

1

1

@

C820

@

2

2

100P_0402_50V8J

R1034 0_0402_5%RM @
R1035 0_0402_5%RM @

R1046 0_0402_5%RP @
R1048 47_0402_5%RP@
R1049 47_0402_5%RP@

I2C_INT<33>

NUM_LED#<33>

1 2

R1047 0_0402_5%

RP@

3

1

TP_CLK <33>
TP_DATA <33>

C821

EC_CK1
EC_DA1

1 2
1 2

1 2
1 2
1 2

PJP605

@

PAD-OP EN 2x2m

2

02/22 Reserve for EMI request.

R1074

ESB_CLK1

ESB_DAT1

L

C1119

C255

C254

RP@

0.047U_0402_16V7K

RP@

RP@

0.047U_0402_16V7K

0.1U_0402_16V4Z

21

+3VL_CAP+3VL

RP@

0_0402_5%

@

47_0402_5%

Ple as e clo se to JP36

+3VL_CAP

R554

0_0603_5%RP@

+5VS_LED

C256

0.1U_0402_16V4Z

1 2

EC_CK1
ESB_CLK1
ESB_DAT1

I2C_INT

EC_DA1

1

2

RP@

12

33P_0402_50V8J

@

R1075

12

33P_0402_50V8K

+5VALW_LED

12

12

+3VL_R

JP36

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

CONN@

9/2 0 SP0 100 0H400

C1103

R555

C1102

12

12

0_0603_5%RM@

1

1

C257

2

2

C1098

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

Battery Charge LED

R550

1 2

200_0402_5%

R552

1 2

470_0402_5%

R549

200_0402_5%

+5VALW_LED

+5VS_LED

+5VALW_LED

B

WHITE

D6

BAT_LED#<33>

CAPS LOCK LED

21

HT-F196BP5_WHITE

WHITE

D7

CAPS_LED#<33>

POWER LED

4 4

ON/OFF BTN_LED#

White LED: VF=3V, IF = 10mA, Res = 200 ohm
Amber LED: VF=1.8V, IF = 8mA, Res = 390 ohm

A

21

HT-F196BP5_WHITE

WHITE

D8

21

HT-F196BP5_WHITE

1 2

WLAN and BT LED inform pin to KBC

+3VS

R989

1 2

47K_0402_5%

WL_BLUE_LED#<33>

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

WL_BLUE_LED#

2N7002_SOT23-3

C

Q55

100K_0402_5%

2007/08/02 2008/08/02

13

D

S

R1025

2 1

D57
CH751H-40PT_S OD323-2

2

G

12

WL/W W_LED#

Compal Secret Data

Deciphered Date

R1007 0_0402_5%

R1008 0_0402_5%PA @

BT_LED <31>

D

1 2

1 2

R1041

12

10K_0402_5%@

+3VS

WL_LED# <26>

WW_LED# <26>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Reed switch BOARD.

+3VL

LID_SW #<33>

1

1

C1100

0.1U_0402_16V4Z

C1101
10P_0402_50V8J

2

2

Compal Electronics, Inc.

TP,MDC,ON/OFF,S/W,LED,Reed

LA-4117P

E

JP40

1

1

2

2

3

3

G1

4

4

G2

ACES_85201-04051

CONN@

34 56Monday, March 16, 2009

5
6

0.3

A

B

C

D

E

+DOCK VIN

D_DDC DATA<16>
D_DDC CLK<16>
D_H SYNC<16>
D_V SYNC<16>

USB20_N3<20>
USB20_P3<20>

RJ45_ MIDI1-<25>
RJ45_ MIDI1+<25>
RJ45_ MIDI0-<25>
RJ45_ MIDI0+<25>

B+

B

RED_L<16>
GREEN_L<16>
BLUE_L<16>

PJP5

PAD-OP EN 2x2m

GNDA_ DOCK_1

GNDA_ DOCK_2

21

D_DDC DATA
D_DDC CLK
D_H SYNC
D_V SYNC
USB20_N3
USB20_P3

RJ45_ MIDI1­RJ45_ MIDI1+
RJ45_ MIDI0­RJ45_ MIDI0+
+V_BATTERY

GNDA_ DOCKA

12

R127
0_0402_5%

12

1

RP@

C831

1000P_0402_50V7K

1 1

2

DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off

2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on

RP@

1 2

+5VS

R586 1K_0402_5%

+3VALW

2 2

1 2

R585 1K_0402_5%

RP@

SYSON #<34,36,42>

Q36
2N7002_SOT23-3

RP@

13

D

2

G

S

01/2 3 Ch ang e NMOS type to so lve Saturn docking i ssue

DOCK_PRESE NT

3 3

H_2P8@

H_2P8@

H_2P8@

H_3P3@

H_1P5N@

4 4

H32

1

H37

1

H42

1

H47

1

H52

1

1 2

R572 22_0402_5%

RP@

H33

H34

H_2P8@

H_2P8@

1

1

H39

H_2P8@

1

H43

H44

H_4P2@

H_4P2@

1

1

H48

H_3P3@

1

H51

H_6P0X5P0N@

1

12

R566
2K_0402_5%

RP@

H35

H_2P8@

1

H40

H_2P8@

1

H56
H_2P5N@

1

A

1 2

H36

H_2P8@

H41

H_2P8@

H46

H_4P2@

RP@

2

3

DAN20 2U_SC70

R588
10K_0402_5%

RP@

+3VL_EC

2

G

1

1

1

H53

H_3P3X0P6N@

D43

R565
10K_0402_5%

RP@

1 2

13

D

Q33
2N7002_SOT23-3

S

RP@

1

H57
H_2P8@

1

DOCK_ PWR_ON

1

H54

H_3P3X0P6N@

1

CONA# <33>

H55

H_5P6N@

GNDA_ DOCK_1<29>

GNDA_ DOCK_2<29>

1

Atlas/ Saturn Dock

JDOCK

38

CRT_Red

40

CRT_Green

34

CRT_Blue

36

DDC_DATA

30

DDC_Clock

32

Hsync

26

Vsync

28

USB-

22

USB+

24

Digital gnd

18

MDI3-

20

MDI3+

14

MD2I-

16

MDI2+

10

MDI1-

12

MDI1+

6

MDI0-

8

MDI0+

2

Battery out

4

Battery out

45

GND

46

GND

FOX_QL1122L-H212AR-9F

CONN@

03/03 Change JDOCK Footprint

R_VOL_UP# R_VOL_DWN#

1

RP@

C843
1000P_0402_50V7K

2

1

RP@

C942

2

220P_0402_50V7K

1 2

R418 0_0603_5%RP@

R417 0_0603 _5%RP@

1 2

R128
0_0402_5%

AUDIO_ OGND

AU DIO_IGND

@

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Audio Output gnd
Right headphone

RP@

C943

220P_0402_50V7K

C

Digital gnd

TV Luma

TV chroma

TV composite

TV ground

CIR input

PWR_ON

Mute_LED

Sleep Botton

Jack Detect

VOL_up

VOL_down

SPDIF

Left headphone

Mic_Right

Mic_Left

Mic gnd

Dock_present

GND
GND
GND
GND

1

RP@

C844
1000P_0402_50V7K

2

DOCK_LOUT_C _LDOCK_ LOUT_C_R

1

2

2007/08/02 2008/08/02

39

TV_LUMA_L

37

TV_CRMA_L

35

TV_COMPS_L

33
31

CIR _IN

29

DOCK_ PWR_ON

27

MUTELED

25

DOCK_SLP_BTN#

23

JACK_DET#

21

R_VOL_UP# DOCK_VOL_UP #

19

R_VOL_DW N# DOCK_VOL_DW N#

17

SPDIF O_L

15

AUDIO_ OGND

13

DOCK_ LOUT_C_R

11

DOCK_LOUT_C _L

9

DOCK_ MIC_R_C

7

DOCK_ MIC_L_C

5

AU DIO_IGND

3

DOCK_PRESE NT

1

41
42
43
44

@

T51PAD
T52PAD
T53PAD

CIR _IN <29,33>

1 2

R591 1K_0402_5%RP@

R567 200_0402_5%RP@

1 2

R568 200_0402_5%RP@

1 2

DOCK_ LOUT_C_R <29>
DOCK_LOUT_C _L <29>

+DOCK VIN

R97 6/ Q14 9/ R646 be option with R99 2/C9 45

L

MMBT3904_NL_SOT23-3

SPDIF O_L

Q149

+1.5VS

C

1 2

E

3 1

R976

33_0402_5%@

2

B

1 2

R992

0_0603_5%RP@

220P_0402_50V7K

MIC_Dock

DOCK_ MIC_R<28>

DOCK_ MIC_L_C

Compal Secret Data

Deciphered Date

DOCK_M IC_L<28>

RP@

1.21K_0402_1%

R944

RP@

R912

1 2

10K_0402_5%

D

12

RP@

47K_0402_5%

AU DIO_IGND

SPDIF

RP@

1

C944

2

R942 10K_ 0402_5%RP@

12

R943 10K_ 0402_5%RP@

12

12

R980

RP@

1.21K_0402_1%

10K_0402_5%

Q16

RP@

PMBT3904_SOT23

R913

1 2

MUTE_LED <33>
DOCK_SLP_BTN# <33>
JACK_DET# <28,29>
DOCK_VOL_UP # <33>
DOCK_ VOL_DWN# <33>

R646

1 2

0_0402_5%@

RP@

C945

1 2

12

0.1U_0402_16V7K

R573

110_0402_5%RP@

RP@

R647

1 2

220_0402_5%

SPDIF _OUT <28>

Need 600 Oh m 500 mA

L94

RP@

FCM1608KF-601T02_2P

DOCK_ MIC_L_R

R914

RP@

2

B

2

C978

RP@

1

1U_0603_10V6K

Cus tom

Date: Sheet of

1 2

1 2

FCM1608KF-601T02_2P

RP@

RP@

220P_0402_50V7K

+3VS

C

E

Title

Size Doc ument Number Re v

AU DIO_IGND

RP@

R915

10K_0402_5%

1 2

13

R415

RP@

0_0402_5%

2

G

D

S

RP@

Q18
2N7002_SOT23-3

1 2

1

3

1 2

Compal Electronics, Inc.

LA-4117P

DOCK_ MIC_R_CDOCK_ MIC_R_R

DOCK_ MIC_L_C

L93

1

C921

2

13

D

Q100

2

G

S

RP@

GNDA_ DOCKA

Clo se to CO DEC U27

DOCK CONN

E

1

C922

RP@

2

220P_0402_50V7K

SENSE_B# <28>

2N7002_SOT23-3

35 56Monday, March 16, 2009

0.3

A

B

C

D

E

DIM LED

21

@

R587

2

G

DIM_LED#

EC_ON#

R419 0_0603 _5%

1 2

Q32 SI2301BDS-T1-E3_SOT23-3@

S

12

DIM_LED#

13

D

Q51

@

2N7002_SOT23-3

S

R420 0_0603 _5%

2

G

+5VALW TO +5VS

+5VALW

1 1

1

C1113

0.1U_0603_25V7K

2

Q35

8

D

7

D

6

D

5

D

SI4800 BDY_SO8

1

C864

4.7U_0805_10V4Z

2

G

S
S
S

C833

1
2
3
4

+5VS

4.7U_0805_10V4Z

1

2

1U_0402_6.3V4Z

RU NON

C835

1

2

1

C1111

0.1U_0603_25V7K

2

0.1U_0603_25V7K

+1.8V TO +1.8VS

+1.8V

2 2

C1116

0.1U_0603_25V7K

8
7

5

1

1

C842

2

2

4.7U_0805_10V4Z

0.01U_0402_25V7K

Q4

IRF811 3PBF_SO8

C849

4

1.8VS_ENABLE

12

1

2

+1.8VS

1
2
36

1U_0402_6.3V4Z

R137

750K_0402_5%

1

C848

2

10U_0805_10V4Z

2

C841

1

1 2

330K_0402_5%

13

D

2

G

Q13

S

2N7002_SOT23-3

R138

SUSP

1

C1114

0.1U_0603_25V7K

2

B+

0.1U_0603_25V7K

C1117

+3VALW TO +3VS

+3VALW +3VS

Q14

8

S

D

7

S

D

6

S

D

5

G

D

SI4800 BDY_SO8

1

2

4.7U_0805_10V4Z

1

2

C840

C1112

+1.2VALW TO +1.2V_HT

+1.2VALW +1.2V_HT

Q11

IRF811 3PBF_SO8

8
7

5

1

1

C847

4.7U_0805_10V4Z

2

2

0.01U_0402_25V7K

4

C837

1
2
3
4

0.01U_0402_25V7K

C839

1U_04 02_6.3V4Z

RU NON

1

C834

2

1
2
36

1

2

1

2

13

D

S

1

C846

2

1U_0402_6.3V4Z

12

R234

750K_0402_5%

4.7U_0805_10V4Z

1

C838

2

R152

330K_0402_5%

SUSP

Q17

2

G

2N7002_SOT23-3

4.7U_0805_10V4Z

C862

12

B+

1

2

330K_0402_5%

13

D

Q12

G

2N7002_SOT23-3

S

1

C1110

0.1U_0603_25V7K

2

1

2

R233

VLDT_EN#

2

C1115

0.1U_0603_25V7K

12

B+

+5VALW

+5VS

PJP7

21

PAD-OP EN 2x2m

10K_0402_5%

DIM_LED<33>

DIM_LED

PJP8

PAD-OP EN 2x2m

EC_ON<33,39>

Discharge circuit

2

G

+1.8VS

R279
470_0805_5%

1 2

13

D

2N7002_SOT23-3

S

Q48

+5VS

3 3

SUSP SUSP

2

G

R239
470_0805_5%

1 2

13

D

Q46

2N7002_SOT23-3

S

+1.2V_HT +1.8V +1.2VALW

R280
470_0805_5%

1 2

13

2

G

D

Q37

2N7002_SOT23-3

S

VLDT_EN# SYSO N#

2

G

R284
470_0805_5%

1 2

13

D

Q41

2N7002_SOT23-3

S

EC_ON#

R368

470_0805_5%@

1 2

13

D

Q42

2

G

2N7002_SOT23-3@

S

G

2

Q166 SI2301BDS-T1-E3_SOT23-3@

S

G

2

1 2

+5VL

12

R598

100K_0402_5%

13

D

S

+5VALW_LED

D

13

+5VS_LED

D

13

Q44
2N7002_SOT23-3

1

C836

@

0.1U_0402_16V4Z

2

1

C1069

@

0.1U_0402_16V4Z

2

+5VL+5VL

12

+3VS

R288
470_0805_5%

1 2

13

FM2

1

2

G

FM3

D

S

1

Q47

2N7002_SOT23-3

CF1

CF2

1

A

CF3

1

4 4

SUSP

FM1

1

1

2

G

+0.9V

R292
470_0805_5%

1 2

13

D

Q49

2N7002_SOT23-3

S

+1.5VS +1.1VS

R293
470_0805_5%

1 2

13

2

G

D

Q50

2N7002_SOT23-3

S

B

SUSPS YSON#

SUSP

2

G

R294
470_0805_5%

1 2

13

D

Q52

2N7002_SOT23-3

S

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SYSON #<34,35,42> SUSP <42>

2007/08/02 2008/08/02

100K_0402_5%

SYSO N#

SYS ON

2N7002_SOT23-3

Compal Secret Data

12

R595

13

D

Q38

2

G

S

Deciphered Date

R596

100K_0402_5%

13

D

Q39

2N7002_SOT23-3

S

Change to +3VL(same as EC)
to avoid leakage

SUSP

2

G

D

SUSP# <2 6,28,33,38,41>SYSO N<26,33,40> VLDT_EN<33>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

+5VL

12

VLDT_EN#<13>

VLDT_EN#

VLDT_EN

13

D

2

G

S

Compal Electronics, Inc.

DC/DC Circuits

LA-4117P

E

R597

100K_0402_5%

Q40
2N7002_SOT23-3

36 56Monday, March 16, 2009

0.3

A

BATT1

45@

CR2032 RTC BATTERY

B

C

D

E

5

5

4

4

3

3

2

2

1

1

PC14

+3VALW

1 3

PR8

2K_0402_5%

PC15 0.1U_0402_16V7K

1 2

1 2

ADP_S IGNAL

ADP INADP IN

12

820P_0402_50V7K

PQ3
TP0610K-T1-E3_SOT23-3

PR9

1 2

100K_0402_5%

2

1 2

PR3
10K_0402_5%

2

3

PD1

@PJSOT24C_SOT23-3

1

+3VL

12

100P_0402_50V8J

PC2

AC_LED# <33>

12

PR2
10K_0402_5%

12

PC3
1000P_0402_50V7K

12

PD4

RLZ3.6B_LL34

PL1

SMB3025500YA_2P

1 2

PC12

12

@1000P_0402_50V7K

12

PC4

100P_0402_50V8J

ADP_ID <3 3>

VIN +DOCKVIN

PL2

SMB3025500YA_2P

12

PC5

1000P_0402_50V7K

12

12

PC13

PC7

390P_0402_50V7K

2200P_0402_50V7K

12

BATT

12

+5VALW

PR1

340K_0402_1%

12

PR4

499K_0402_1%

12

PC6

0.01U_0402_25V7K

12

PR6

105K_0402_1%

12

PC1

0.01U_0402_25V7K

3

2

PU1A

LM358ADT_SO8

8

P

+

1

0

-

G

4

PR5

10K_0402_5%

12

BATT_OVP < 33>

1 1

ACES_88334-057N

PJP1

2 2

PH1 under CPU botten side :

PL3

VMB

HCB2012KF-121T50_0805

1 2

PJP2

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

9

GND

10

GND

3 3

4 4

SUYIN_2 00275MR008GXOLZR

12

PR17
1K_0402_5%

A

6.49K_0402_1%

1 2

PR16

EC_SMD
EC_SMC

12

PR13

100_0402_5%

BAT_ID <38>

+3VL

PD2
@SM05_SOT23

3

2

12

PR14
100_0402_5%

BATT_TEMP <33>

PC16

@0.22U_0603_10V7K

1

2

3

1

PD3
@SM24.TC_SOT23-3

SMB_EC_DA1

SMB_EC_CK1

+5VS

12

PH2

@10KB_0603_1%_TH11-3H103FT

+5VALW

12

12

PR21
@2.21K_0402_1%

B

PL4
HCB2012KF-121T50_0805

12

PC8
1000P_0402_50V7K

PR19

@15K_0402_1%

1 2

1 2

PR20

@150K_0402_1%

PR22

@150K_0402_1%

1 2

12

SMB_EC_DA1 <6,32,33,34>

SMB_EC_CK1 <6,32,33,34>

PR18

@47K_0402_1%

1 2

+5VALW

12

PC18

1

@0.01U_0402_25V7K

IN+

3

IN-

12

PC17
@1000P_0402_50V7K

BATT

+5VS

12

PC9

0.01U_0402_50V4 Z

0.22U_0603_10V7K

5

PU2

P

4

O

G

2

@LMV 331IDCKRG4_SC70-5

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

CPU

12

PC10

+5VS

12

PR23
@10K_0402_5%

2007/08/02 2008/08/02

CPU thermal protection at 95 +-3 degree C

PR7

604K_0402_1%

1 2

12

PH1

10KB_0603_1%_TH11-3H103FT

12

PR12

2.21K_0402_1%

2

G

PR10

200K_0402_1%

1 2

1 2

PR11

+5VALW

150K_0402_1%

150K_0402_1%

+3VL

PR24

1 2

@100K_0402_5%

13

D

PQ4
@SSM3K7002FU_SC70-3

S

Compal Secret Data

Deciphered Date

12

PR15

NB_OTP < 33>

8

5

P

+

6

-

G

4

12

PC11
1000P_0402_50V7K

D

7

0

PU1B
LM358ADT_SO8

13

D

PQ1

2

G

@SSM3K7002FU_SC70-3

S

EN0 <6, 39>

13

D

PQ2

2

G

SSM3K7002FU_SC70-3

S

ENTRIP1 <39>

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

DC Connector/CPU_OTP

LA-4111P

37 56Monday, March 16, 2009

E

0.1

A

B

C

D

P4

VI N

1 1

PR1 01

47K _0402_5 %

1 2

12

PR1 07
47K _0402_1 %

1 2

2

G

PC1 01

47P _0402_ 50V8J

2

13

D

S

PQ1 07
SSM 3K70 02FU_S C70-3

2

13

PQ1 05
DTC 115 EUA_S C70-3

PQ10 1
SI4 835B DY-T1- E3_SO8

8
7

5

DTA 144E UA_SC 70-3

PQ1 04

1 3

PACIN_1 < 39>

PR1 11

3K_ 0402_1%

PA CIN

1 2

2 2

AC OFF #

PD1 01

1 2

1SS 355_S OD323-2

2

G

13

D

PQ1 09
SSM 3K70 02FU_S C70-3

S

VCT RL<33>

Cha rg e D etec tor

VI N

PD1 04
1SS 355_S OD323-2

1 2

PR1 23

3

2

VIN _1

12

8

+

-

4

1M_0 402_5%

1 2

PR1 25
47_ 1206_5%

12

P

1

O

G

PU1 02A
LM3 93DG_S O8

PC1 25

0.1 U_06 03_25V7 K

3 3

VI N

12

PR1 31
133 K_0402 _1%

12

PR1 35
10K _0603_ 0.1%

1.2 4VRE F

4 4

4

1 2

1U_ 0603_ 10V6K

+3VL

12

PR1 29

10K _0402_ 1%

STD_ADP <3 3>

1
2
36

12

PC1 06

0.4 7U_0 603_16V7K

PR1 14
@0_ 0402_5%

PC1 17

PR1 28

2

G

P2

SI4 835B DY-T1 -E3_SO8

12

PR1 06

12

PR1 09
150 K_0402_ 5%

143 K_0402_ 1%

12

+3VL

12

10K _0402_5 %

CH GEN #

13

D

PQ1 12
SSM 3K70 02FU_S C70-3

S

FST CHG<33>

PQ1 03

1
2
3 6

4

AC_S ET<33>

200 K_0402 _5%

12

PR1 13

12

PR1 15

100 K_0402 _1%

FST CHG #

1 2

PR1 37

20K _0402_1 %

8
7

5

SUS P#<26 ,28,3 3,36,41 >

ADP_I<3 3>

PR1 04
0_0 402_5%

1 2

@0. 01U _0402_16 V7K

PR1 10
0_0 402_5%

1 2

PC1 12

1 2

1U_ 0603_6. 3V6M

15K _0402_1 %

12

PC1 20

0.2 2U_0 603_10V7K

+3VL

12

PR1 32

100 K_0402_ 5%

13

D

PQ1 13

2

G

SSM 3K70 02FU_S C70-3

S

ACD ET

12

PR1 38

100 K_0402_ 1%

PC1 07

BQ2 4740 VREF

+3VL

PR1 16

10K _0402_5 %

1 2

12

10

11

12

13

14

12

PR1 18

0.1 U_04 02_10V7 K

AC SET

AC SET

12

8

9

PR1 40

100 K_0402_ 5%

IADSLP

AGND

VREF

VDAC

VADJ

EXTPWR

ISYNSET

PC1 21

100 P_0402 _50V8J

PC1 23

ACD ET

7

LPREF

IADAPT

15

IAD APT

12

12

0.1 U_06 03_25V7 K

4

5

6

LPMD

ACSET

ACDET

PU1 01

BQ2 4740 RHDR _QFN 28_5X5

BAT

SRSET

SRN

17

16

18

BATT

12

PR1 02

0.0 12_251 2_1%

1 2

PC1 02

1U_ 0603_6. 3V6M

1 2

PC1 08

3

2

ACP

SRP

19

20

PR1 20

133 K_0402_ 1%

12

PR1 21

200 K_0402 _1%

B+

PL10 1
HCB 2012 KF-121 T50_0805

1 2

12

PC1 09
@0. 1U_ 0603_25V 7K

CH GEN #

1

ACN

TP

CHGEN

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

DPMDET

CELLS

21

SSM 3K70 02FU_S C70-3

12

29

28

BST _CHG

27

DH _C HG

26

LX_ CHG

25

RE GNVA DJ

24

DL _CH G

23

22

PQ1 11

IR EF <33>

12

PC1 03

4.7 U_08 05_25V6- K

PR1 08
10_ 1206_5%

1 2

PC1 10
1U_ 0805_ 25V6K

1 2

PD1 02

1SS 355_S OD323-2

12

PC1 19

1U_ 0603_ 10V6K

PR1 17

100 K_0402 _5%

1 2

13

D

2

G

S

12

PC1 04

PC1 11

0.1 U_04 02_10V7 K

12

4.7 U_08 05_25V6- K

1 2

12

12

PC1 05

4.7 U_08 05_25V6- K

BQ2 4740 VREF

12

47K _0402_5 %
PR1 19

12

PC1 24

0.1 U_06 03_25V7 K

PC1 28

CHG _B+

220 P_0402 _50V7K

578

3 6

578

3 6

12

241

241

12

PC1 29

PC1 30

680 P_0402 _50V7K

120 0P_040 2_50V7K

PQ1 08
AO4 466_SO8

PL1 02
10U _LF9 19AS- 100M-P3_ 4.5A_20%

1 2

PR1 39

4.7 _1206_5 %

1 2
12

PC1 31

PQ1 10

FDS 6690 AS_SO8

BAT_ ID < 37>

12

PC1 22

@0. 1U_ 0603_25V7 K

0.0 47U_ 0402_16 V7K

680 P_0603 _50V7K

100 K_0402_ 1%

PC1 26

CHG _B+

PR1 26

12

12

PC1 13

4.7 U_08 05_25V6 -K

VI N

12

1 2

12

PR1 33
10K _0603_ 0.1%

22P _0402 _50V8J

12

PC1 14

4.7 U_08 05_25V6 -K

0.1 U_04 02_10V7K

PR1 30

2.1 5K_040 2_1%

PC1 27

PQ1 02
FDS 6675 BZ_SO 8

1
2
3 6

PR1 12

0.0 15_120 6_1%

1 2

1 2

PC1 18

12

4

AC OFF #

BATT

12

PC1 15

PR1 22
681 K_0402_ 1%

1 2

8

PU1 02B

5

P

+

O

6

-

G

LM3 93DG_ SO8

4

60. 4K_040 2_1%

1 2

4

REF

5

ANODE

APL 1431LB BC-TR_S OT23-5

8
7

5

12

4.7 U_08 05_25V6 -K

7

RLZ 4.3 B_LL34

PR1 36

CATHODE

BATT

PR1 03

47K _0402_5 %

1 2

2

1.2 4VRE F

VI N

AC OFF <33>

AC_IN <21,3 3>

PACIN

12

PR1 05

10K _0402_ 5%

13

PQ1 06
DTC 115 EUA_S C70-3

12

PC1 16

PC1 32

4.7 U_08 05_25V6 -K

4.7 U_08 05_25V6 -K

PR1 27
10K _0402_1 %

PR1 24
1K_ 0402_5%

1 2

12

PR1 34
10K _0402_ 5%

PD1 03

PU1 03

VIN _1

NC

NC

VI N

12

12

3

2

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/29 2008/05/29

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ume nt N umber R ev

Dat e: Shee t o f

Charger

LA -394 1P

D

38 56Mon day, Ma rch 16 , 2009

0.1

A

B

C

D

E

2VREF_51125

1 1

0.22U_0603_10V7K

PR301

13.7K_0402_1%

1 2

20K_0402_1%

140K_0402_1%

BST_3V

UG_3V

PR311

+5VALWP

+3VALWP

PR303

1 2

PR305

1 2

25

7

8

9

10

11

12

12

2VREF_51125

12

PC316

@0.1U_0402_25V4K

+3VALWP

@22U_0805_6.3V6M

B++

12

PC301

2200P_0402_50V7K

PC320

12

PC303

4.7U_0805_25V6-K

12

150U_D_6.3VM

ENTRIP1<37>

PQ305

SSM3K7002FU_SC70-3

@SSM3K7002FU_SC70-3

1 2

PR318
@604K_0402_1%

PC318

@0.047U_0603_16V7K

PL302

4.7UH _SIQB74B-4R7PF_4A_20%

1

PC309

+

2

12

PR315

@4.7_1206_5%

PC314

@680P_0603_50V8J

13

D

2

G

S

PQ308

2

G

12

13

D

S

1
2
3
4

12

12

D

S

PQ301

D1
D1
G2
S2

AO4932_SO8

13

8

1G

7

1S/2D

6

1S/2D

5

1S/2D

ENTRIP2

13

D

PQ306

2

G

SSM3K7002FU_SC70-3

S

PR313
100K_0402_5%

1 2

PQ307
SSM3K7002FU_SC70-3

2

G

10U_0805_6.3V6M

UG1_3V

0_0402_5%

1 2

12

PR314
100K_0402_5%

PR309

PC306

VL

+3VLP

12

1 2

PC307

0.1U_0402_10V7K

LX_3V

LG_3V

EC_ON <33, 36>

PR307

1 2

0_0402_5%

B++

PR312

1 2

1M_0402_1%

EN0<6,37>

191K_0402_1%

B+

12

PC321

2200P_0402_50V7K

2 2

3 3

PL301
HCB2012KF-121T50_0805

<BOM S tructure>

1 2

12

PC322

390P_0402_50V7K

PACIN_1<38>

4 4

PC302

ENTRIP2

6

P PAD

ENTRIP2

VO2

VREG3

VBST2

DRVH2

LL2

DRVL2

EN0

13

PJP302

1 2

PAD-OP EN 4x4m
PJP303

1 2

PAD-OP EN 4x4m

12

PR302

30.9K_0402_1%

1 2

PR304
20K_0402_1%

1 2

PR306
113K_0402_1%

ENTRIP1

1 2

3

4

1

2

5

VFB1

VFB2

VREF

TONSEL

ENTRIP1

24

VO1

23

PGOOD

VBST1

DRVH1

DRVL1

VREG5

GND

VIN

SKIPSEL

15

14

VCLK

PU301

17

16

18

TPS51125RGER_QFN24_4X4

BST_5V

22

UG_5V

21

LX_5V

20

LL1

LG_5V

19

VL

12

PC311
10U_0805_10V6K

12

B++

PC312

0.1U_0603_25V7K

(4.5A, 180mils ,Via NO.= 9)

+5VALW

(3A,120mils ,Via NO.= 6)

+3VALW

PR308

2.2_0402_5%

1 2

+3VL

12

B++

12

PC317

@0.1U_0402_25V4K

PC308

0.1U_0402_10V7K

1 2

PR317
100K_0402_5%

12

12

PC304

2200P_0402_50V7K

PR310
0_0402_5%

1 2

3/5V_OK <20,41>

12

PC313

PC305

4.7U_0805_25V6-K

4.7U_0805_25V6-K

578

3 6

241

578

3 6

241

PQ304

SI4894 BDY-T1-E3_SO8

+3VLP

VL

PQ302

AO4466_SO8

PL303

4.7UH_PC MC063T-4R7MN_5.5A_20%

1 2

12

PR316

4.7_1206_5%

12

PC315
680P_0603_50V8J

PJP301

2 1

PAD-OP EN 2x2m

PJP304

2 1

PAD-OP EN 2x2m

+3VL

+5VL

1

+

PC310
150U_D_6.3VM

2

+5VALWP

12

PC319
@22U_0805_6.3V6M

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

3.3VALWP/5VALWP

LA-4111P

39 56Monday, March 16, 2009

E

0.1

A

1 1

PR4 01

0_0402_ 5%

SYSON<26,33,36>

1 2

PC4 01

@1000P_ 0402_50V7K

12

+5VALW

2 2

+1.8VP

3 3

PR4 05

0_0402_ 5%

PR4 03

316_040 2_1%

12

+5V ALW

12

12

PC4 09
1U_ 0603_10V6K

+1.8VP

PR4 04
255K_04 02_1%

PR4 08

1 2

14.3 K_0603_0.1 %

1 2

PC4 13
@10P_04 02_50V8J

PR4 09

10K _0603_0.1%

1 2

12

PU4 01

2

3

4

5

6

TON

VOUT

V5FILT

VFB

PGOOD

1

EN_PSV

GND7PGND

B

1 2

PR4 02

0_0402_ 5%

14TP15

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

TPS 51117R GYR_QFN 14_3.5 x3.5

8

DH _1.8V

LX_1.8V

+5VALW+5VALW

DL_ 1.8V

BST1_1.8 VB ST_1.8V

0.1U _0402_10V7 K

PR4 10

1 2

0_0402_ 5%

12

PC4 15

4.7U _0805_10V6 K

1 2

PC4 02

1 2

PR4 06

10.7 K_0402_1%

DH_ 1.8V_1

578

PQ401

3 6

241

AO4466_ SO8

578

PQ402

3 6

241

SI489 4BDY-T1 -E3_SO8

C

D

PL401

12

12

PC4 04

4.7 U_0805_25V 6-K

PL402

1 2

HCB 1608KF-121 T30_0603

1 2

PC4 05

2200P _0402_50V7K

1

+

PC4 08

2

220 U_D2_4 VY_R25M

12

PC4 06
470P_04 02_50V7K

+1.8VP

B+

1.8V_B+

12

12

PC4 14

PC4 03

4.7 U_0805_25V 6-K

@0. 1U_0402_2 5V4K

2.2U H_PCM C063T-2R2 MN_8A_20%

12

PR4 07

@4.7 _1206_5%

PC4 12
@680P_0 603_50V7K

1 2

PJP401

+1.8VP

4 4

1 2

PA D-OPE N 4x4m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

(7A,28 0mils ,Via NO.= 14)

+1.8V

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

Title

Size D ocum ent Nu mber R ev

Da te: Sh eet o f

Compal Electronics, Inc.

1.8VP

LA-3941P

D

40 56Mo nday, Marc h 16, 2009

0.1

A

1 1

B+++

241

241

+1.1VS

+1.1VSP

3 6

3 6

SUSP#<26,28 ,33,36,38>

B+++

12

12

PC501

PC517

4.7U_0805_25V6-K

2 2

PC502

4.7U_0805_25V6-K

12

12

PC518

2200P_0402_50V7K

@0.1U_0402_25V4K

PQ501

AO4466_SO8

+1.1VSP

PL501

+1.1VSP

1

+

2

PC508

220U_ D2_4VY_R25M

3 3

2.2UH_PCMC 063T-2R2MN_8A_20%

12

PC509

4.7U_08 05_6.3V6K

12

PR515

4.7_1206_5%

PC519

470P_0603_50V8J

12

12

PR518
0_0402_5%

1 2

1 2

PR517
10_0402_5%

578

0.1U_0402_10V7K

UG1_1.1V

578

PQ503
FDS6690AS_N L_SO8

B

+1.1VSP

VCCP_POK

@0.022U_0603_25V7K

PC506

PR513

0_0402_5%

0.1U_0402_10V7K

12

PC513

11.5K_0402_1%

PC503

PR506

2.2_0402_5%

12

12

PR5080_0402_5%

12

PR501

1 2

12

12

BST_1.1V

UG_1.1V

LX_1.1V

LG_1.1V

1U_0603_10V6K

24.9K_0402_1%

1 2

PU501

25

P PAD

7

PGOOD2

8

EN2

9

VBST2

10

DR VH2

11

LL2

12

DR VL2

PR511

15.4K_0402_1%

1 2

12

PC514

PR502

PR505

0_0402_5%

1 2

3.3_0402_5%

6

VO2

PGND2

13

PR514

5

VFB2

TRIP2

14

1 2

3

4

GND

TONSEL

V5FILT

V5IN

15

16

12

C

2

VFB1

TRIP1

17

12

PC515

4.7U_0805_10V6K

PR503

18.7K_0402_1%

12

1

VO1

24

PGOOD1

23

EN1

BST_1.2V

22

VBST1

DR VH1

DR VL1

PGND1

TPS51 124RGER_QFN24_4x4

18

PR510

10.5K_0402_1%

+5VALW

UG_1.2V

21

LX_1.2V

20

LL1

LG_1.2V

19

PR504

11.5K_0402_1%

12

1 2

12

PC512

0.1U_0402_16V7K

PR507

2.2_0402_5%

PR509

0_0402_5%

PR512

33K_0402_5%

+1.2VALWP

12

12

PC507

0.1U_0402_10V7K

1 2

UG1_1.2V

3/5V_OK <20 ,39>

D

PQ502

AO4466_SO8

PQ504

AO4468_SO8

B+++

578

3 6

578

3 6

241

241

PL502

HCB2012KF-121T50_0805

12

PC516

470P_0402_50V7K

3.3UH 30% MSCD RI-7030AB-3R3N 4.1A

12

PR516

4.7_1206_5%

12

PC520

470P_0603_50V8J

12

12

PC504

4.7U_0805_25V6-K

PL503

1 2

PR519

1K_0402_5%

E

B+

12

12

PC505

PC521

2200P_0402_50V7K

@0.1U_0402_25V4K

+1.2VALWP

+1.2VALWP

12

PC510

4.7U_08 05_6.3V6K

1

+

1 2

2

PC511

220U_B2_2.5VM

(6A,240mils ,Via NO.=12)

PJP501

+1.1VSP

4 4

A

+1.1VSP

1 2

PAD-OP EN 4x4m

PJP503

1 2

PAD-OP EN 4x4m

+1.1VS

+1.1VS

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

(4A,160mils ,Via NO.=8)

+1.2VALWP

1 2

D

PJP502

PAD-OP EN 4x4m

+1.2VALW

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

1.1VSP/1.2VALWP

LA-4111P

41 56Monday, March 16, 2009

E

0.1

A

1 1

B

C

D

E

+1.8V

PU601

VIN1VCNTL

12

PQ601

2

12

PC606
@0.1U_0402_16V7K

+0.9VP

+1.5VSP

12

G

PC601

10U_0805_10V4Z

SYSON#<34,3 5,36>

2 2

SUSP<36>

3 3

1 2

PR602

0_0402_5%

SSM3K7002FU_SC70-3

1 2

PR604

@0_0402_5%

PC602

@10U_0805_10V4Z

13

D

S

PJP601

1 2

PAD-OP EN 3x3m

PJP603

1 2

PAD-OP EN 3x3m

12

PR601

1K_0402_1%

12

PR603
1K_0402_1%

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

12

12

PC605
10U_0805_6.3V6M

0.1U_0402_16V7K

PC604

(2A,80mils ,Via NO.= 4)

+0.9V

(1A,40mils ,Via NO.= 2)

+1.5VS

NC

NC

NC

+0.9VP

6

5

7

8

9

TP

+5VALW

12

PC603
1U_0603_16V6K

10U_0805_10V4Z

SUSP<36>

+3VS

+1.8V

PC613

SSM3K7002FU_SC70-3

1 2

PR608

0_0402_5%

12

PC607

1U_0603_6.3V6M

12

12

PC609

@10U_0805_10V4Z

PQ602

13

D

2

G

S

12

PC610
@0.1U_0402_16V7K

(500mA ,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3

2

IN

OUT

GND

1

12

PR606
1K_0402_1%

VREF1.5V

12

PR607

5.1K_0402_1%

3

PU603

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

6

5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC612
1U_0603_16V6K

+1.5VSP

12

12

PC614
10U_0805_6.3V6M

0.1U_0402_16V7K

PC611

+2.5VSP

12

12

PR605
@150_1206_5%

PC608

4.7U_0805_6.3V6K

PJP602

+2.5VSP

4 4

A

1 2

PAD-OP EN 3x3m

(500mA ,40mils ,Via NO.= 1)

+2.5VS

B

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

0.9VSP/2.5VSP/1.5VSP

LA-4111P

42 56Monday, March 16, 2009

E

0.1

A

+CPU_CORE_NB

VDD_N B_FB_H<6>

VDD_N B_FB_L<6>

1 1

PR204

ISL6265_P WROK

13

D

VFIX_EN<33>

2

G

S

Connect to EC pin 110.

2 2

VGATE<33>
H_PW RGD<19>
SB_PW RGD<6,20,33>

CPU_S VD<6>

CPU_SVC<6>

VR_ON<33>

PR225

1 2

3 3

4 4

255_0402_1%

PR230

1 2

54.9K_0402_1%

CPU_V DD0_FB_H<6>

CPU_V DD0_FB_L<6>

PC223

1 2

4700P_0402_25V7K

PR227

1 2

1K_0402_1%

PC225

1 2

1200P_0402_50V7K

1 2

PC227
180P_0402_50V8J

+1.8V

A

22K_0402_1%

1 2

1 2

1000P_0402_50V7K

PQ209
@SSM3K7002FU_SC70-3

CPU_B+

+5VS

+3VS

12

PR216

10K_0402_1%

PR246 100K_0402_5%

1 2
1 2

PR234 @100K_0402_5%

PR218

1 2

0_0402_5%

PR222

1 2

PR223

1 2

107K_0402_1%

PC205

0_0402_5%

PR232

1 2

6.81K_0402_1%

1 2

PC228
1000P_0402_50V7K

PR239
0_0402_5%

PR241
@0_0402_5%

+5VS

PR208

2_0402_5%

1 2

0.1U_0603_25V7K

1 2

PR212

0_0402_5%

1 2

PR213

@0_0402_5%

1 2

PR215

@10K_0402_5%

ISL6265_PW ROK

ISL6265_PW ROK

SVD

SVC

PR224

1 2

10K_0402_1%

1 2

PR235
0_0402_5%

1 2

PR237
0_0402_5%

1 2

1 2

PR205

2_0402_5%

1 2

0.1U_0402_16V7K

12

PC216

1

2

3

4

5

6

7

8

9

10

11

12

PC241
1000P_0402_50V7K

PC242
@1000P_0402_50V7K

PC207

PU201

OFS/VFIXEN

PGOOD

PWROK

SVD

SVC

ENABLE

RBIAS

OCSET

VDIFF0

FB0

COMP0

VW0

12

12

12

47

48

VIN

VCC

ISN0

ISP0

14

13

ISP 0

+CPU_C ORE_0

B

12

PR206

0_0402_5%

12

12

PC209

PC208

33P_0402_50V8K

1200P_0402_50V7K

12

PR210

1 2

44.2K_0402_1%

VSEN_NB

43

44

45

46

FB_NB

FSET_NB

COMP_NB

ISL6265IRZ -T_QFN48_6X6

RTN117VSEN0

RTN0

15

16

18

RTN1

RTN0

VSEN0

VSEN1

12

PC244

@1000P_0402_50V7K

12

PC245

@1000P_0402_50V7K

12

PC246

@1000P_0402_50V7K

12

B

PR245

4.7_1206_5%

BOOT0

PC230

PR236

12

12

2.2_0603_5%

C

1
2

PC251

3 6

680P_0603_50V7K

2.2_0603_5%
PR214

1 2

PR226

1 2

0_0603_5%

1 2

PR228

0.22U_0603_10V7K

12

12

C

PQ201

AO4468_SO8

8
7

5

4

0_0402_5%

12

PC210

2.2U_0603_6.3V6K

PC231

12

PR238

@54.9K_0402_1%

12

PR240

@1K_0402_1%

PR243

@255_0402_1%

12

PHASE NB

UGATE0_1

UGATE1_1

12

LGATE NB

+5VS

0.22U_0603_10V7K
PC217

1 2

1 2

0_0603_5%

PR219

1 2

PC224

@180P_0402_50V8J

PC232

@1200P_0402_50V7K

@4700P_0402_25V7K

PC233

2007/08/02 2008/08/02

PQ202

AO4466_SO8

1
2
3 6

4

PR203

1 2

UGATE NB

5

4

3 5

5

4

12

12

Compal Secret Data

Deciphered Date

8
7

5

786

123

IRF871 4TRPBF_SO8

<BOM S tructure>

241

IRFH7 932TRPBF_PQFN

786

123

3 5

241

PQ208

IRFH7 932TRPBF_PQFN

PL201

1

12

+

2

PC201

10U_0805_6.3V6M

12

PR209

0_0402_5%

12

PR207

17.4K_0402_1%

PC243

1000P_0402_50V7K

RTN_NB

42

RTN_NB

VSEN_NB

VDIFF1

VSEN1

19

41

20

OCSET_NB

FB1

LGATE NB

39

40

PGND_NB

COMP121ISP1

22

PHASE NB

38

LGATE_NB

PHASE_NB

VW1

23

12

4.7UH _PCMC063T-4R7MN_5.5A_20%

PC202
220U_B2_2.5VM

12

PC206

0.1U_0402_16V7K

BOOT_NB1

12

PR211

1_0603_5%

UGATE NB

37

UGATE_NB

ISN1

24

BOOT_NB

UGATE0

PHASE0

LGATE0

LGATE1

PHASE1

UGATE1

36

35

BOOT0

34

33

32

PGND0

31

30

PVCC

29

28

PGND1

27

26

25

BOOT1

TP

49

+CPU_C ORE_0

ISP 1

BOOT_NB

UGATE0

PHASE0

LGATE0

LGATE1

PHASE1

UGATE1

BOOT1

@1000P_0402_50V7K

@6.81K_0402_1%

Secur ity Classification

PC247

@1000P_0402_50V7K

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

12

12

PC238

470P_0402_50V7K

12

12

PC239

PC234

330P_0402_50V7K

4.7U_0805_25V6-K

PQ203

PR220

4.7_1206_5%

PQ205

PQ206

IRF871 4TRPBF_SO8

PR229

4.7_1206_5%

D

PC204

12

PC203

2200P_0402_50V7K

12

PC235

4.7U_0805_25V6-K

12

12

PR242

4.7_1206_5%

12

PC218

2200P_0603_50V7K

12

PC240

2200P_0402_50V7K

12

12

PR244

4.7_1206_5%

12

PC226
2200P_0603_50V7K

12

PC258

4.7U_0805_25V6-K

12

PC212

4.7U_0805_25V6-K

0.1U_0603_25V7K

12

PC237

4.7U_0805_25V6-K

0.1U_0603_25V7K

2200P_0402_50V7K

CPU_B+

12

12

PC213

4.7U_0805_25V6-K

0.36UH_PCMC 104T-R36MN1R17_30A_20%

PR221

PC219

12

PC236

4.7U_0805_25V6-K

PC229

12

PC214

PC248

2200P_0402_50V7K

3300P_0402_50V7K

12

PL203

PR217

@4.02k_0603_1%

3.65K_0402_1%

1 2

1 2

ISP 0

12

PC220

PC221

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PL204

0.36UH_PC MC104T-R36MN1R17_30A_20%

12

PR231

PR233

3.65K_0402_1%

@4.02k_0603_1%

1 2

1 2

ISP 1

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

E

CPU_B+

PL202

SMB3025500YA_2P

12

12

PC254

PC255

390P_0402_50V7K

1800P_0402_50V7K

12

12

12

PC222

2200P_0402_50V7K

12

12

12

12

PC261

47P_0402_50V8J

12

PC252

47P_0402_50V8J

12

PC249

PC250

3300P_0402_50V7K

1800P_0402_50V7K

12

PC259

47P_0402_50V8J

12

12

PC257

PC256

390P_0402_50V7K

1800P_0402_50V7K

12

PC260

47P_0402_50V8J

Compal Electronics, Inc.

CPU_CORE

LA-4111P

E

1

+

PC211

2

68U_25V_M

+CPU_C ORE_0

CPU_B+

+CPU_C ORE_0

43 56Monday, March 16, 2009

B+

1

12

12

+

2

PC253

PC215

47P_0402_50V8J

1000P_0402_50V7K

PC262 68U_25V_M

0.1

A

V e rsion C h a n g e L ist (

V e rsion C h a n g e L ist ( P . I. R . L ist ) for P ow e r Circu it

V e rsion C h a n g e L ist ( V e rsion C h a n g e L ist (

P a

P a ge #

I t em

I t emI te m

1 1

g e #

P aP a

g e #g e#

1

37

TTTT it le

it le

it leit le

DC Connector
/CPU_OTP

D a t e

D a t e

D a t eD a te

P . I . R . L ist ) for P o w er C irc u it

P . I . R . L ist ) for P o w er C irc u itP . I . R . L ist ) for P o w er C irc u it

R eq

R eq u e st

u e st

R eqR eq

u e stu e st

O w n

O w n e r

e r

O w nO w n

e re r

9/29

Compal

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

for Layout

e s cri p ti o nI t em

e s cri p ti o ne sc ri pt io n

C

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

PL3 change the value from SMB3025500YA_2P to HCB2012KF-121T50_0805
and add PL4 the same of the value.

D

E

R ev .

R ev .I s su e D

R ev .R e v.

2

41

3

41

4

43

5

43

2 2

3 3

43 Add PJP201 PJ、P202

6

7

38 Charger 9/29 Compal the footprint is wrong Change the footprint of PR102

8

37

9

38 Charger 10/08 Compal the footprint is wrong Change the footp rint o f PR102

10

40 1.8VP 10/08 Compal Delete PC410 and PC411

11

41 1.1VSP/1.2VALWP 10/08 Compal Add PR517 P、R518PWR request

12

37

13

37 11/01 Compal for Layout change PQ301, Cencel PQ303

1.1VSP/1.2VALWP Compal HW request

CPU_CORE Compal HW request

CPU_CORE Compal

CPU_CORE

DC Connector
/CPU_OTP

DC Connector
/CPU_OTP

3.3VALWP/5VALWP

9/29

Compal1.1VSP/1.2VALWP

9/29

9/29

9/29

9/29

Compal

10/08 Compal for Layout These two choke are parallel ,it's not series.

11/01 Compal PWR request Add PD4 P、C12

HW request

TI FAE suggested that after he review
the layout.

TI FAE suggested that after he review
the layout.

PWR request

PC508 and PC511 change the value from 220U_6.3VM_R15 to
220U_D24VY_R25M

Add PJP503

PC202 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M

Add PC241 PC242 PC243, and the value are 1000P
Reserve PC244 PC245 PC246 PC247, and the
1000P_0402_50V7K.

、 、

、 、 、

_0402_50V7K.

value are

14

43 CPU_CORE EMI requestCompal11/02 Add PC248, PC249, PC250

15

37 3.3VALWP/5VALWP 11/12 Compal for Layout Change PC31 0, add PC319

16

17

4 4

A

12/31 PWR requestCompal3.3VALWP/5VALWP37

12/31CPU_CORE Compal Vendor request43

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Add PU302, control signal changed to ACOFF

Change PR221 and PR231 to 16.6K_ohm
Change PR217 and PR233 to 4.02K_ohm
Change PR223 to 17.8K_ohm
Change PR224 to 100K_ohm

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

Power Changed-List History-1

LA-4117P

44 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist (

V e rsion C h a n g e L ist ( P . I. R . L ist ) for P ow e r Circu it

V e rsion C h a n g e L ist ( V e rsion C h a n g e L ist (

P a

P a ge #

I t em

I t emI te m

1 1

g e #

P aP a

g e #g e#

18

38 Charger 01/08 Compal EMI request Add PC128 220pF

TTTT it le

it le

it leit le

D a t e

D a t e

D a t eD a te

P . I . R . L ist ) for P o w er C irc u it

P . I . R . L ist ) for P o w er C irc u itP . I . R . L ist ) for P o w er C irc u it

R eq

R eq u e st

u e st

R eqR eq

u e stu e st

O w n

O w n e r

e r

O w nO w n

e re r

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e s cri p ti o nI t em

e s cri p ti o ne sc ri pt io n

C

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

D

E

R ev .

R ev .I s su e D

R ev .R e v.

37 01/09 Compal AC LED change to KBC control AC_LED# connect to KBC pin 97

19

20

21

22

23

2 2

24

25

37 3.3VALWP/5VALWP 02/27 Change OT C shun down pin.Compal Change OTC shun down pin to PU301 pin13.

26

27

28

29

30

37

3 3

37

31

DC Connector
/CPU_OTP

Change PC309 to D size and add PC32001/14 Compal for layout3.3VALWP/5VALWP37

Charger 02/2738 Compal EMI request CHG_B+ Add 1200pF and 330pF

02/27 Compal EMI request CPU_B+ Add 1800pF*2 2200pF*1 and 390pF*243 CPU_CORE

02/27 Compal3.3VALWP/5VALWP37 EMI request B+ Add 2200pF and 390pF

DC Connector
/CPU_OTP

CPU_CORE Compal03/04 Change high-side MOS for WWAN issue Change PQ203 and PQ206 to powerpak43

CPU_CORE Compal03/04 HW request add H_PWRGD control net43

/CPU_OTP

DC Connector
/CPU_OTP

1.1VSP/1.2VALWP

02/2737 Compal EMI request VIN Add 2200pF and 390pF, ADPIN add 820pF

Compal04/02 AC LED issue37 Chaange AC_LED# pull high to +3VLDC Connector

04/24 Compal acoustic noise43 Add PC262CPU_CORE

04/24 Compal HW CPU thermal protection

05/23 Compal +1.2VALW leakage Add PR519

change to 95 +-3 degree C

Chaange PR12 to 2.21K_ohm

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

Power Changed-List History-1

LA-4117P

45 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a ge #

I t emI te m

1111 2 5

1 1

2222 2 5

4444 2 9

6666 2 9

7777 3 4

8888 1 1 ,

2 2

9999 1 1 ,

1 0 2 1 ,

1 01 0

1 1

1 1 0 .2

1 11 1

g e #

P aP a

g e #g e#

2 5

2 52 5

2 5

2 52 5

1 6

1 61 6

2 9

2 92 9

44445555 0 .2

2 9

2 92 9

3 4

3 43 4

1 1 , 3 5

3 5

1 1 ,1 1 ,

3 53 5

1 1 , 2 1

2 1

1 1 ,1 1 ,

2 12 1

2 1 , 3 1

3 1

2 1 ,2 1 ,

3 13 1

2 1

2 12 1

TTTT it le

it le

it leit le

LLLL A N

A N 1 0

A NA N

LLLL A N

A N 1 0

A NA N

CCCC R T

R T 1 0

R TR T

A ud io

A ud io

A ud ioA u d io
FFFF A N

A N

A NA N

S p

S p ea ker

ea ke r

S pS p

ea ke rea ke r

M D C

M D C 1 1

M D CM D C

TTTT V _ O U T

V _ O U T 1 1

V _ O U TV _ OU T

N B / SB T h e

N B / SB T h e rm al

N B / SB T h eN B /S B T h e

S B

S B S A TA

S AT A 1 1

S BS B

S AT A S A T A

S B

S B S A TA

S AT A 1 1

S BS B

S AT A S A T A

rm al 1 1

rm alr m al

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

1 0 /2 9

/ 2 9

1 01 0

/ 2 9/ 2 9

1 0 /2 9

/ 2 9

1 01 0

/ 2 9/ 2 9

1 0 /2 9

/ 2 9

1 01 0

/ 2 9/ 2 9

1 0

1 0 /3 0

/ 3 0

1 01 0

/ 3 0/ 3 0

1 1

1 1 /0 1

/ 0 1

1 11 1

/ 0 1/ 0 1

1 1

1 1 /0 1

/ 0 1

1 11 1

/ 0 1/ 0 1

1 1 /0 1

/ 0 1

1 11 1

/ 0 1/ 0 1

1 1 /0 5

/ 0 5

1 11 1

/ 0 5/ 0 5

1 1 /0 5

/ 0 5

1 11 1

/ 0 5/ 0 5

1 1 /0 5

/ 0 5

1 11 1

/ 0 5/ 0 5

1 1 /0 5

/ 0 5

1 11 1

/ 0 5/ 0 5

u e stu e st

O w n

O w n e r

O w nO w n

H W

H W C h an ge L A N C h

H WH W

H P Q

H P Q A dd

H P QH P Q

H W

H W C R T

H WH W

H W

H W S p e a k e

H WH W

H W

H WH W

H W

H W S pe ak e r C on n. n ot c or re c t pa

H WH W

H W

H W M D C C o n n. no t c or r ec t

H WH W

H W

H W T V -O U T F u n

H WH W

H W

H W N B T h e rm

H WH W

H W

H W S B S

H WH W

H W

H W S B SA TA _ AC T # P u l l H i gh b ec om

H WH W

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

C ha n g e LA N C h ip U 2 0 f r om M a rv ell 88 E8 04 2 t o

C ha n g e LA N C hC ha ng e L A N C h

R ea lt e k

R ea lt e k R T L8 10 2E L

R ea lt e kR e a lt ek

A d d PO E (P ow e r O v e r E th er n et ) d es i gn

A d d A d d

C R T ca n n ot d is pl a y

C R TC R T

S pe ak e r n o s ou n d

S pe ak eS pe ak e

FFFF A N C on n. n ot c or re c t pa rt

A N C on n. n ot c or re c t pa rtH W

A N C on n. n ot c or re c t pa rtA N C on n. n ot c or re c t pa rt

S p ea ke r Co n n . no t c or r ec t p a rt

S p ea ke r Co n n . no t c or r ec t p aS p ea ke r C o n n . no t c or r ec t p a

M D C Co nn . n ot co rr e ct pa rt

M D C Co nn . n ot co rr e ct M D C Co nn . n ot co rr e ct

T V -O U T F u n ct io n no s u pp or t

T V -O U T F u nT V -O U T F u n

N B T h er m a l F un ct i on n o s u pp or t ( lo ca te t oo fa r)

N B T h er mN B Th er m

S B S A T A P o rt 5 c h a ng e to P ort 2 f or AT I C om m on

S B SS B S

DDDD e si gn

e s ig n

e s ig ne s i gn

S B S A T A _A C T# P u ll H i g h b ec om e + 3V S

S B S A T A _A C T# P u ll H i g h b ec omS B S A T A _A C T# P ul l H ig h b ec o m

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

ip U 2 0 f ro m M a rv el l 88 E8 04 2 t o

ip U 2 0 f ro m M a rv el l 88 E8 04 2 t oip U 2 0 fr om M a rv el l 88 E 8 04 2 t o

R T L 8 1 0 2 E L

R T L 8 1 0 2 E L RT L 8 1 0 2 E L

P O E (P ow e r O v e r E th ern et ) de s ig n

P O E (P ow e r O v e r E th ern et ) de s ig nP O E (P ow e r O v e r E th ern et ) de s ig n

c an n ot d is p la y

c an n ot d is p la y ca n no t d is p la y

r n o s ou nd

r n o s ou ndr n o s ou n d

rt

rtrt

p a rt 0 .2

p a rtp art

c t io n n o s up po r t

c t io n n o s up po r tct io n n o s up p or t

a l F u n ct io n n o s up p o rt (l o ca te t oo f ar)

a l F u n ct io n n o s up p o rt (l o ca te t oo f ar)a l F u n ct io n n o s up p o rt (l o ca te t oo f ar)

A TA P or t 5 c h a n ge to P ort 2 f or AT I C om m on

A TA P or t 5 c h a n ge to P ort 2 f or AT I C om m onA T A Po rt 5 c h an ge to P o rt 2 f or A T I C o m m on

C

e + 3V S

e + 3V Se + 3V S

D

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

U p

U p da te t h e L A N D e s ig n p ag e an d s up po r t c ir c uit

d a t e th e L A N D es ig n p ag e a nd s u p p or t c ir cu it

U pU p

d a t e th e L A N D es ig n p ag e a nd s u p p or t c ir cu itd a t e th e L A N D es ig n p ag e a nd s u p p or t c ir cu it

U p

U p da te t h e L A N D e s ig n p ag e an d s up po r t c ir c uit

d a t e th e L A N D es ig n p ag e a nd s u p p or t c ir cu it

U pU p

d a t e th e L A N D es ig n p ag e a nd s u p p or t c ir cu itd a t e th e L A N D es ig n p ag e a nd s u p p or t c ir cu it

C ha ng e th e CR T C on n.

C ha ng e th e CR T C on n. s ig na ls c o nn e c ti o n f ir st .

C ha ng e th e CR T C on n.C h a n g e t he C R T C o n n .

W a it c o r re ct s y m b ol f

W a it c o r re ct s y m b ol f or f i x

W a it c o r re ct s y m b ol fW a it c o rr ec t sy m b ol f

A d d R 9 73 (1 0 K _ 0 40 2 ) to + 3 V A L W o n H P _ D ET #

A d d R 9 73 (1 0 K _ 0 40 2 ) to + 3 V A L W o n H P _ D ET #

A d d R 9 73 (1 0 K _ 0 40 2 ) to + 3 V A L W o n H P _ D ET #A d d R 9 73 (1 0K _ 04 02 ) t o +3 V A L W o n H P _ D E T #

C ha ng e JP 2 P C B F o ot p r in t f ro m A C E S_ 8 5 20 4- 02

C ha ng e JP 2 P C B F o ot p r in t f ro m A C E S_ 8 5 20 4- 02 0 01 _2 P t o

C ha ng e JP 2 P C B F o ot p r in t f ro m A C E S_ 8 5 20 4- 02C ha ng e JP 2 P C B F o ot p r in t f ro m A C E S_ 8 5 20 4- 02

A C E S _ 8

A C E S _ 8 8 23 1 -0 2 00 1 _ 2 P

A C E S _ 8A C E S _8

C ha ng e JP 2 0 PC B F oo tp ri nt f ro m A C E S_ 8 52 04 -0 4 0

C ha ng e JP 2 0 PC B F oo tp ri nt f ro m A C E S_ 8 52 04 -0 4 0 0 1_ 4 P to

C ha ng e JP 2 0 PC B F oo tp ri nt f ro m A C E S_ 8 52 04 -0 4 0C ha ng e JP 2 0 P C B Fo o tp ri n t f ro m A C E S_ 85 20 4- 0 40

A C E S _ 8

A C E S _ 8 8 23 1 -0 4 00 1 _ 4 P

A C E S _ 8A C E S _8

C ha ng e JP 2 0 PC B F oo tp ri nt f ro m A C E S_ 8 80 18 -1

C ha ng e JP 2 0 PC B F oo tp ri nt f ro m A C E S_ 8 80 18 -1 2 4G _ 1 2P t o

C ha ng e JP 2 0 PC B F oo tp ri nt f ro m A C E S_ 8 80 18 -1C ha ng e JP 2 0 PC B F oo tp ri nt f ro m A C E S_ 8 80 18 -1

A C E S _ 8 8

A C E S _ 8 8 02 0- 1 21 0 1_ 1 2 P

A C E S _ 8 8A C E S _ 8 8

DDDD e l R 59 ,R 6 0, R 61 , R 1 15 , R1 16 , R1 17 a n d T V -O U T r el at ed d es ig n .

C an ce l N B _ TH E R M A L _ D A / D C c o n n ec ti on b e

C an ce l N B _ TH E R M A L _ D A / D C c o n n ec ti on b e tw e en N B a nd

C an ce l N B _ TH E R M A L _ D A / D C c o n n ec ti on b eC an ce l N B _ TH E R M A L _ D A / D C c o n n ec ti on b e

S B

S B ,d el C 5 00

S BS B

C ha ng e SB S A T A

C ha ng e SB S A T A p or t 5 to p or t 2

C ha ng e SB S A T A C ha ng e SB S A T A

C ha ng e R 3 43 .1 p ow e r ra i l f ro m + 5 V S t o +3 V

C ha ng e R 3 43 .1 p ow e r ra i l f ro m + 5 V S t o +3 V S . In st all R 34 3.

C ha ng e R 3 43 .1 p ow e r ra i l f ro m + 5 V S t o +3 VC ha ng e R 3 4 3 .1 p ow e r ra i l f ro m + 5 V S t o +3 V

8 23 1 -0 2 00 1 _ 2 P

8 23 1 -0 2 00 1 _ 2 P8 23 1- 0 20 01 _2 P

8 23 1 -0 4 00 1 _ 4 P

8 23 1 -0 4 00 1 _ 4 P8 23 1- 0 40 01 _4 P

0 20 - 12 1 01 _ 1 2 P

0 20 - 12 1 01 _ 1 2 P0 20 -1 2 10 1 _1 2P

e l R 5 9, R 60 , R 6 1, R 11 5, R 11 6,R 1 17 a nd T V -O U T r el a te d d e s ig n .

e l R 5 9, R 60 , R 6 1, R 11 5, R 11 6,R 1 17 a nd T V -O U T r el a te d d e s ig n .e l R 5 9, R 60 , R 6 1, R 11 5, R 11 6,R 1 17 a nd T V -O U T r el a te d d e s ig n .

,d el C 5 00

,d el C 5 00,d el C 5 00

s ig n a ls c on n e ct io n fi rs t .

s ig n a ls c on n e ct io n fi rs t . si gn a ls c o nn ec ti o n f ir st .

o r fix

o r fixo r fi x

p or t 5 t o p or t 2

p or t 5 t o p or t 2p o r t 5 t o p or t 2

0 01 _ 2 P t o

0 01 _ 2 P t o0 01 _2 P t o

0 1_ 4 P t o

0 1_ 4 P t o0 1 _4 P t o

2 4G _ 12 P t o

2 4G _ 12 P t o24 G_ 12 P t o

tw een N B a nd

tw een N B a ndtw ee n N B a nd

S . I ns ta ll R 3 4 3.

S . I ns ta ll R 3 4 3.S . In st all R 34 3 .

E

R ev .

R ev .P a

R ev .R e v.

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .23333 1 6

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .21 0

0 .20 .2

0 .22 1

0 .20 .2

1 . Co nn ec t U 1 5. C 6 to G

1 . Co nn ec t U 1 5. C 6 to G N D b y 0 _0 4 02 .

1 2

1 2 2 1

2 1 0 .2

1 21 2

2 12 1

1 3

1 3 3 1

3 1 0 .2

1 31 3

3 13 1

1 4

1 4 2 9

2 9

1 41 4

2 92 9

3 3

1 5

1 5 2 5

2 5

1 51 5

2 52 5

1 6

1 6 0 .2

2 1 , 2 4

1 61 6

2 1 ,2 1 ,

1 7

1 7 3 6

3 6

1 71 7

3 63 6

1 8

1 8 2 7

2 7

1 81 8

2 72 7

4 4

SSSS B G PI O

B G P I O 1 1

B G P I OB G P I O

S B

S B S A TA

S AT A 1 1

S BS B

S AT A S A T A

A ud io H

A ud io H P O U T

A ud io HA u d io H
L A N

L A N T ra ns f er m o r

L A NL A N

2 4

2 42 4

S B

S B S A TA

S BS B
D IM L E D

D IM L E D 1 1

D IM L E DD I M L E D

C a r

C a r dR ea de r

C a rC a r

P O U T 11

P O U TP O U T

T ra ns fe rm o r 1 1

T ra ns fe rm o r T ra ns fe rm o r

S AT A 1 1

S AT A S A T A

d R ea d e r 1 1

d R ea d e rdR ea de r

A

1 1 /0 5

1 11 1

1 1 /0 5

1 11 1
1 1 /0 5

1 11 1
1 1 /0 5

1 11 1
1 1 /0 6

1 11 1
1 1 /0 6

1 11 1

1 1 /0 6

1 11 1

H W

H W CCCC h a n g e S B G P IO r ef e r t o J B K 00 f or co m mo n

H WH W

/ 0 5

/ 0 5/ 0 5

H W

H W V e rt ic a

H WH W

/ 0 5

/ 0 5/ 0 5

H W

H W 0 .2

H WH W

/ 0 5

/ 0 5/ 0 5

H W

H W C o r re ct

H WH W

/ 0 5

/ 0 5/ 0 5

H W

H W SSSS B S A T A P o r t 4 c ha n g e t o P or t 3 f o r A T I O p en I s su e

H WH W

/ 0 6

/ 0 6/ 0 6

H W

H W 0 .2

H WH W

/ 0 6

/ 0 6/ 0 6

H W

H W 0 .2

H WH W

/ 0 6

/ 0 6/ 0 6

h an g e S B G P I O r e fe r t o J BK 0 0 f o r c o m m o n

h an g e S B G P I O r e fe r t o J BK 0 0 f o r c o m m o nh an g e S B G P I O r e fe r t o J BK 0 0 f o r c o m m o n

V e r ti c a l L5 1 1 < - -> 4 , 2 < - -> 3 fo r l a yo ut ro ut i ng

V e r ti c aV e rt i ca

A d d 15 0 U F Ca ps fo r e ac h D O C K _ L O U T_ R/ L

A d d A d d

C or re ct U 1 9 L A N Tr a ns f er m o r p in d ef i nit io n

C or re ct C o rr ec t

R e du c e D I M L E D un n ec es sa r y d es i gn

R eR e

C ha ng e C a r dR ea de r S oc ke t f or M / E n ew p a r t a nd

C ha ng e C a r dR ea de r S oc ke t f or M / E n ew p a r tC ha ng e C a r dR ea de r S oc ke t f or M / E n ew p a r t

C hi p f o

C hi p f o r JM i cro n n ew v e r si on

C hi p f oC hi p f o

l L 5 1 1 <- - >4 , 2 <- - >3 f or la yo ut r ou ti ng

l L 5 1 1 <- - >4 , 2 <- - >3 f or la yo ut r ou ti ngl L 5 1 1 <- - >4 , 2 <- - >3 f or la yo ut r ou ti ng

1 50 U F C ap s f o r e ac h D O CK _ L O U T_ R/ L

1 50 U F C ap s f o r e ac h D O CK _ L O U T_ R/ L1 5 0 U F Ca ps fo r e ac h D O C K_ L O U T _R /L

U 1 9 L A N T ra ns f er m o r p in d ef in it i on

U 1 9 L A N T ra ns f er m o r p in d ef in it i onU 1 9 LA N T ra ns f er m o r p in d ef in it i on

B S A TA P o rt 4 c h a ng e to P ort 3 f or AT I O p e n I ss u e

B S A TA P o rt 4 c h a ng e to P ort 3 f or AT I O p e n I ss u eB S A TA P o rt 4 c h a ng e to P ort 3 f or AT I O p e n I ss u e

d uc e D I M L E D u n n ec es sa r y d es i gn

d uc e D I M L E D u n n ec es sa r y d es i gnd u ce D I M LE D u n n ec e ss a ry de s ig n

a n d

a n d a nd

r J M ic r on ne w v er s io n

r J M ic r on ne w v er s io nr J M ic ro n n ew v er s io n

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

1 . Co nn ec t U 1 5. C 6 to G1 . Co nn ec t U 1 5. C 6 t o G

2 . Ch an ge W L O F F# f ro m G P IO 5 0 t o G P IO 6

2 . Ch an ge W L O F F# f ro m G P IO 5 0 t o G P IO 6 1.

2 . Ch an ge W L O F F# f ro m G P IO 5 0 t o G P IO 62 . Ch an ge W L O F F# f ro m G P IO 5 0 t o G P IO 6

3 . Ch an ge B T _ C O M B O _E N # f r om G P I O 5

3 . Ch an ge B T _ C O M B O _E N # f r om G P I O 5 1 t o G P IO 6 2 .

3 . Ch an ge B T _ C O M B O _E N # f r om G P I O 53 . Ch an ge B T _ C O M B O _E N # f r om G P I O 5

4 . Ch an ge W W O F F # fr om G P IO 5 2 t o G PI O 6 3.

4 . Ch an ge W W O F F # fr om G P IO 5 2 t o G PI O 6 3.

4 . Ch an ge W W O F F # fr om G P IO 5 2 t o G PI O 6 3.4 . Ch an ge W W O F F # fr om G P IO 5 2 t o G PI O 6 3.

V er t ic al L 5 1 1 < -- > 4 , 2 < -- >3 f or l ay o ut

V er t ic al L 5 1 1 < -- > 4 , 2 < -- >3 f or l ay o ut r ou ti ng

V er t ic al L 5 1 1 < -- > 4 , 2 < -- >3 f or l ay o utV e rt ic a l L 5 1 1< -- > 4 , 2< -- > 3 fo r la yo ut

A d d 1 5 0U F C a p s f or e ac h D O CK _ L O U T_ R /L

A d d 1 5 0U F C a p s f or e ac h D O CK _ L O U T_ R /L

A d d 1 5 0U F C a p s f or e ac h D O CK _ L O U T_ R /LA d d 1 5 0U F C a p s f or e ac h D O CK _ L O U T_ R /L

C orr ec t U 19 L A N T r an s fe rm o r pi n de

C orr ec t U 19 L A N T r an s fe rm o r pi n de fi nit i o n

C orr ec t U 19 L A N T r an s fe rm o r pi n deC orr ec t U 19 L A N T r an s fe rm o r pi n de

C ha ng e SB S A T A

C ha ng e SB S A T A p or t 4 to p or t 3

C ha ng e SB S A T A C ha ng e SB S A T A

D el R 1 0 2 6 a n d Q 1 6 7, a dd N e t "D I M _ LE D # " f o

D el R 1 0 2 6 a n d Q 1 6 7, a dd N e t "D I M _ LE D # " f o r co nn ec t .

D el R 1 0 2 6 a n d Q 1 6 7, a dd N e t "D I M _ LE D # " f oD el R 1 0 2 6 a n d Q 1 6 7, a dd N e t "D I M _ LE D # " f o

C ha ng e lo ca ti on f ro m P J P 60

C ha ng e lo ca ti on f ro m P J P 60 4 t o PJ P8 .

C ha ng e lo ca ti on f ro m P J P 60C ha n g e lo c a ti o n f ro m PJ P6 0

C ha ng e JR E A D t o T A I T W _ R 01 5 -B 1 0- L

C ha ng e JR E A D t o T A I T W _ R 01 5 -B 1 0- L M .

C ha ng e JR E A D t o T A I T W _ R 01 5 -B 1 0- LC ha ng e JR E A D t o T A IT W _ R 0 1 5- B1 0- L

R es e r ve R 4 1 3 ,C 9 02 c lo s e t o JR E A D .2

R es e r ve R 4 1 3 ,C 9 02 c lo s e t o JR E A D .2 0 ;

R es e r ve R 4 1 3 ,C 9 02 c lo s e t o JR E A D .2R es e r ve R 4 1 3 ,C 9 02 c lo s e t o JR E A D .2

R 41 2, C 9 01 c l os e t o JR E A D . 26 ; R4 11 , C9 0 0 c lo se

R 41 2, C 9 01 c l os e t o JR E A D . 26 ; R4 11 , C9 0 0 c lo se t o J RE A D .3 7.

R 41 2, C 9 01 c l os e t o JR E A D . 26 ; R4 11 , C9 0 0 c lo seR 41 2, C 9 01 c l os e t o JR E A D . 26 ; R4 11 , C9 0 0 c lo se

CCCC h an ge R4 57 c lo se t o U 23 .4 2

h an g e R 45 7 c lo se t o U 23 . 42

h an g e R 45 7 c lo se t o U 23 . 42h an ge R 45 7 c lo se t o U 2 3. 4 2

A d d

A d d R 45 5 ,R 4 56 c lo se t o U 23 . 42

R 45 5, R 4 56 c lo se t o U 23 .4 2

A d d A d d

R 45 5, R 4 56 c lo se t o U 23 .4 2R4 55 , R4 56 c lo se to U 2 3 .4 2

D e l Q

D e l Q 1 69 ,R 1 05 1 .

1 69 , R1 05 1 .

D e l QD e l Q

1 69 , R1 05 1 .1 69 ,R 1 05 1 .

C ha ng e ne t CR _ LE D # b e co m e C R _ L ED c on n ec t U

C ha ng e ne t CR _ LE D # b e co m e C R _ L ED c on n ec t U 2 3.2 1 an d Q 53 .2

C ha ng e ne t CR _ LE D # b e co m e C R _ L ED c on n ec t UC ha n g e n e t CR _ LE D # b ec om e C R _L E D c on n e ct U

A d d R 4 54 p u ll d ow n t o

A d d R 4 54 p u ll d ow n t o GN D

A d d R 4 54 p u ll d ow n t o A d d R 4 54 p ul l d ow n t o

C ha ng e R 4 05 ,R 1 2 2 f ro m 2 0 0K t o 1 0K p ull -h

C ha ng e R 4 05 ,R 1 2 2 f ro m 2 0 0K t o 1 0K p ull -h ig h

C ha ng e R 4 05 ,R 1 2 2 f ro m 2 0 0K t o 1 0K p ull -hCh an ge R 4 05 , R1 22 f ro m 2 0 0K to 1 0 K p u l l- h

R e m o v

R e m o v e C 8 95 ,U 2 2

e C 8 95 , U 2 2

R e m o vR e m ov

e C 8 95 , U 2 2e C 8 95 ,U 2 2

Compal Secret Data

Deciphered Date

N D b y 0_ 0 40 2 .

N D b y 0_ 0 40 2 .N D b y 0_ 0 40 2.

p or t 4 t o p or t 3

p or t 4 t o p or t 3p o r t 4 t o p or t 3

4 to P JP 8 .

4 to P JP 8 .4 t o PJ P 8.

G N D

G N DG N D

D

0 .2

1 .

1 .1 .

1 to G P IO 62 .

1 to G P IO 62 .1 t o G P IO 62 .

r ou ti ng

r ou ti ng r ou ti ng

fin it io n

fin it io nf in it io n

r co nn ec t .

r co nn ec t .r co nn ec t .

M .

M .M .

0 ;

0 ; 0;

t o J R E A D .3 7.

t o J R E A D .3 7. t o J R E A D .3 7.

2 3. 21 a n d Q5 3 .2

2 3. 21 a n d Q5 3 .223 .2 1 an d Q 53 .2

ig h

ig hi gh

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-1

LA-4117P

0 .20 .2

0 .2

0 .20 .2

0 .2A d d

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .22 1 ,

0 .20 .2

0 .2R e

0 .20 .2

0 .2C ha ng e C a r dR ea de r S oc ke t f or M / E n ew p a r t

0 .20 .2

46 56Monday, March 16, 2009

E

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1 9 1 6

1 91 9

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2 2 3 3

2 22 2

2 3

2 32 3

2 4 H W

2 42 4

2 5

2 5 1 9 ,

2 52 5

2 6

2 6 2 5

2 62 6

2 2

2 7

2 7 1 8

2 72 7

2 8

2 8 6666

2 82 8

2 9

2 9 3 3

2 92 9

3 0

3 0 3 5

3 03 0

3 1 0 .2

3 13 1

3 2

3 2 3 3

3 23 2

3 3

3 3 2 7

3 33 3

3 4

3 4 3 4

3 43 4

3 3

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3 5 2 1

3 53 5

3 6

3 6 3 3

3 63 6

3 7

3 7 6 ,

3 73 7

3 8

3 8 1 1

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1 61 6

1 7

1 72 0

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1 82 4

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1 9 , 3 2

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3 33 3

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3 53 5

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2 63 1

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2 72 7

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L C D

L C D 1 1

L C DL C D
L C D

L C D 1 1

L C DL C D
K B C

K B C 1 1

K B CK B C
W e b C

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W e b CW eb C

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D M I

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S B -C L K - D e b u g

S B -C L K - D e b u g 1 1

S B -C L K - D e b u gS B -C L K - D e b u g

LLLL A N

A N 1 1

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HHHH D M I

D M I 1 1

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C P U

C P U 1 1

C P UC P U
K B C

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H ole s

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H ole sH o le s
M in i- C a r d

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SSSS B - G P IO

B -G P IO 1 1

B -G P IOB - G P I O

K B C -

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G PI O 11

K B C -K B C-

G PI OG P I O

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P U ,F P R

P U ,F P RP U ,F P R

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N B

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W e b C

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K B CK BC

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D M I 1 1

D M ID M I

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

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1 1 /0 7

/ 0 7

1 11 1

/ 0 7/ 0 7

1 1 /0 7

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1 1 /0 7

/ 0 7

1 11 1

/ 0 7/ 0 7

1 1 /0 7

/ 0 7

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/ 0 7/ 0 7

1 1 /0 9

/ 0 9

1 11 1

/ 0 9/ 0 9

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1 1 /0 9

/ 0 9HHHH D M I

1 11 1

/ 0 9/ 0 9

1 1 /0 9

/ 0 9

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/ 0 9/ 0 9

1 1 /0 9

/ 0 9

1 11 1

/ 0 9/ 0 9

1 1 /0 9

/ 0 9

1 11 1

/ 0 9/ 0 9

1 1 /0 9

/ 0 9

1 11 1

/ 0 9/ 0 9

1 1 /0 9

/ 0 9

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/ 0 9/ 0 9

1 1 /0 9

/ 0 9

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/ 0 9/ 0 9

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1 1 /0 9

/ 0 9M in i

1 11 1

/ 0 9/ 0 9

1 1 /0 9

/ 0 9

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1 1 /1 0

/ 1 0

1 11 1

/ 1 0/ 1 0

1 1 /1 0

/ 1 0

1 11 1

/ 1 0/ 1 0

1 1 /1 0

/ 1 0

1 11 1

/ 1 0/ 1 0

1 1 /1 1

/ 1 1

1 11 1

/ 1 1/ 1 1

1 1

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

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/ 1 3/ 1 3

1 1 /1 3

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1 1 /1 3

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H W N o rm a l i

H WH W

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H WH W

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IC CI C f ee db ac k R M A c on c er n f or

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H W N o rm a l iz e K

H WH W

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H WH W

H W

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H W D e bu g

H WH W

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H W R J 4

H WH W

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H W R e d u c e H D M I D e s ig n

H WH W

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H W AAAA d d H _ TH E RM T R I P # on e m o r e w a y

H WH W

H W

H W U p d a t e K B

H WH W

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M E U p d at e f

M EM E

H W

H W

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H W

H W R e se rv

H WH W

H W

H W C or re ct C a r dR ea de r L

H WH W

H W

H W C o r re c

H WH W

H W

H W A d d on e m

H WH W

H W

H W A d d C IR _I N PH t o + 5

H WH W

H W

H W R e du ce S3

H WH W

H W

H W R e du ce

H WH W

H W

H W U p da te t he W e bC am + D i g it a l M i c r es e rv e r

H WH W

H W

H W UUUU p da te TH E RM T R I P # d e s ig n t o E C

H WH W

H W

H W R e

H WH W

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

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N o r m al i z e C R T d es ig n f or c om m on

N o r m al iN o rm a li

N o r m al i ze L C D d es i gn fo r c om m o n

N o r m al i zeN o rm a li ze

C IC f ee db ac k R M A c on ce rn f o r c om m on

C IC f ee db ac k R M A c on ce rn f o rC I C f e ed ba c k R M A c o nc er n f or

N o r m al i ze K B 9 26 C ry s ta l p a r t fo r c om m on

N o r m al i ze KN o r m al i z e K

C ha n ge U 5 4 W eb C a m p ow e r d es i gn a nd re la te d

C ha nC h an

R ed uc e H D M I D e si gn

R ed uc e H D M I D e si gn

R ed uc e H D M I D e si gnR e d u c e H D M I D e s ig n

D e b u g C a r d n o f un ct io n i ss ue

D e b u gD e bu g

R J4 5 L E D Po w e r co r re ct ba c k

R J4R J4

R ed uc e H D M I D e si gn

R ed uc e H D M I D e si gnR e d u c e H D M I D e s ig n

d d H _ T HE R M TR IP # on e m o re w a y

d d H _ T HE R M TR IP # on e m o re w a yd d H _ T HE R M TR IP # on e m o re w a y

U p da te K B C P in D e fi nit io n f or c om m on

U p da te K BU p d a t e K B

U p da te f o r M / E D r aw in g

U p da te fU p d a t e f

R ed uc e M i ni- C a r d d es i gn , c ha ng e S IM C a r d d e

R ed uc e M i ni- C a r d d es i gn , c ha ng e S IM C a r d d e s ig n

R ed uc e M i ni- C a r d d es i gn , c ha ng e S IM C a r d d eR ed uc e M i ni- C a r d d es i gn , c ha ng e S IM C a r d d e

R es er v e 0 _ 0 60 3 f or K B B ac k L ig h t

R es er vR e se rv

C or re c t C ar d R ea d e r L ED p a rt

C or re c t C ar d R ea d e r LC o r re ct Ca rd R ea d e r L

C or re c t LE D f un ct io n fo r co m m on

C or re cC o r re c

A d d o ne m o re wa y f or G S E N S OR L E D # i nf or m p in

A d d o ne mA dd o ne m

A dd C I R _ IN P H t o + 5 V L

A dd C I R _ IN P H t o + 5A dd CI R_ IN P H to + 5

AAAA d d E S B _ CL K /D A T PH t o + 3V L

d d E S B _C LK / D A T PH t o + 3 VL

d d E S B _C LK / D A T PH t o + 3 VLdd E S B _ C L K /D A T P H t o + 3 V L

R ed u c e S 3 p ow e r co ns um pt io n

R ed u c e S 3 R ed u ce S3

R ed u c e th e l ev e l s h if t d e s ig n f or C h i p A 1 2.

R ed u c eR e du ce

U p d a t e th e W eb C a m +D ig it al M i c r e se r ve r c o nn .

U p d a t e th e W eb C a m +D ig it al M i c r e se r ve r U p d a t e th e W eb C a m +D ig it al M i c r e se r ve r

p da te T H E R M T RI P# d es i gn to E C

p da te T H E R M T RI P# d es i gn to E Cp da te T H E R M T RI P# d es i gn to E C

R e mo ve E M I s olu tio n b ec om e r es e rv e f or ve r if y

m ov e E M I s ol u tio n b ec o m e re se rv e fo r v er i fy

R eR e

m ov e E M I s ol u tio n b ec o m e re se rv e fo r v er i fym o ve EM I s olu tio n b ec om e r es e rv e f or ve r if y

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

z e CR T d e s ig n f or c om m on

z e CR T d e s ig n f or c om m onz e C R T d es i gn f or c om m on

L C D d es i gn fo r c om m o n

L C D d es i gn fo r c om m o n L C D de si g n f or c om m on

c o mm on

c o mm on co m m on

B 92 6 C ry st al p a r t fo r c om m o n

B 92 6 C ry st al p a r t fo r c om m o nB 9 2 6 Cr y st a l pa rt f or c om m on

g e U 5 4 W e b C a m p ow er de s ig n a n d r ela te d

g e U 5 4 W e b C a m p ow er de s ig n a n d r ela te dg e U 5 4 W e b C a m p ow er de s ig n a n d r ela te d

C ar d n o fu n c ti on i s su e

C ar d n o fu n c ti on i s su e C ar d n o fu n c ti on i s su e

5 L E D Po we r co rr e ct ba ck

5 L E D Po we r co rr e ct ba ck5 L E D P o w e r c or r ec t b ac k

C P in D e f in it i on fo r c om m o n

C P in D e f in it i on fo r c om m o nC P i n D e fi ni t io n f or c om m on

o r M / E D r aw in g

o r M / E D r aw in go r M / E D r a w in g

e 0_ 06 03 f o r K B B a c k L ig ht

e 0_ 06 03 f o r K B B a c k L ig hte 0 _0 60 3 f or K B B ac k L ig h t

E D p ar t

E D p ar tE D p ar t

t L E D f un c ti o n f or c om m on

t L E D f un c ti o n f or c om m ont L E D f un c ti o n f or c om m on

o r e w a y f or GS E N S O R L E D # i nf o rm p in

o r e w a y f or GS E N S O R L E D # i nf o rm p ino r e w a y f or GS E N S O R L E D # i nf o rm p in

V L

V LV L

p ow e r co ns um p tio n

p ow e r co ns um p tio np ow e r co ns um p tio n

t h e l ev e l s h if t d es ig n f or C h i p A 1 2.

t h e l ev e l s h if t d es ig n f or C h i p A 1 2. t h e l ev el sh if t d es ig n f or C h ip A 1 2.

C

co nn .

co nn .c o nn .

si g n

si g ns i g n

D

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S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

C h an

C h an g e L 8 3 , L8 4 ( 1 0_ 0 4 02 ) be co m e R 2 4 1 ,R 2 4 0 ( 0_ 06 03 )

g e L8 3, L 8 4 (1 0 _0 40 2) b ec o me R 2 41 , R 2 40 ( 0 _ 0 6 0 3)

C h anC h a n

g e L8 3, L 8 4 (1 0 _0 40 2) b ec o me R 2 41 , R 2 40 ( 0 _ 0 6 0 3)g e L 83 , L 8 4 (1 0 _0 40 2) b e co m e R 24 1 ,R 2 40 ( 0_ 0 60 3)

C ha ng e R

C ha ng e R 4 91 f r om 2 00 _0 40 2 to 2 00 _0 80 5

C ha ng e RC h a n g e R

C h an ge Q 43 f ro m A O S3 41 3 to S I2 3

C h an ge Q 43 f ro m A O S3 41 3 to S I2 3 01

C h an ge Q 43 f ro m A O S3 41 3 to S I2 3C h an ge Q 43 f ro m A O S3 41 3 to S I2 3

C ha ng e Y7 f ro m 9 H 0 32 0 04 13 s m a ll t o 1 T JS 1 25 D J4 A 4

C ha ng e Y7 f ro m 9 H 0 32 0 04 13 s m a ll t o 1 T JS 1 25 D J4 A 4 20 P no rm al.

C ha ng e Y7 f ro m 9 H 0 32 0 04 13 s m a ll t o 1 T JS 1 25 D J4 A 4C ha ng e Y 7 f ro m 9 H 0 32 0 04 13 s m al l to 1 TJ S1 25 D J4 A 4

C h an

C h an g e U 54 f ro m G 9 16 -3 9 0T 1 U F t o R T9 19 3 -3 9 G B .

C h anC h a n

R e m o

R e m o v e R 8 91 ,R 8 9 2 i f n o u s e G 9 16 -3 9 0T 1 U F.

R e m oR em o

A d d C 7 18 c lo se t o U 54 . 4 fo r R T 91 93 - 39 G B .

A d d C 7 18 c lo se t o U 54 . 4 fo r R T 91 93 - 39 G B .

A d d C 7 18 c lo se t o U 54 . 4 fo r R T 91 93 - 39 G B .A d d C 71 8 c lo se to U 5 4 .4 f or R T 91 9 3- 3 9 G B .

R em o v e R1 02 7~ R 1 03 0 f or J P 7 no i ns

R em o v e R1 02 7~ R 1 03 0 f or J P 7 no i ns ta ll.

R em o v e R1 02 7~ R 1 03 0 f or J P 7 no i nsR em o v e R 10 2 7~ R 10 3 0 fo r JP 7 n o i ns

C ha ng e JP 7 f ro m 8p in

C ha ng e JP 7 f ro m 8p in to 6 pi n

C ha ng e JP 7 f ro m 8p inC h a n g e J P 7 fr om 8 pi n

R em o v

R em o v e R 49 0 ( 10 0 K _ 04 0 2 )

R em o vR em o v

D e l R

D e l R 1 0 31 ,a dd R 3 0 3 cl os e t o R 3 0 1 a n d U 1 5 .P 2

D e l RD e l R

C on n e ct f o

C on n e ct f o r CL K _P C I _S IO 2 to J P 4 1 . 15

C on n e ct f oC o nn ec t f o

C ha ng e JR J 4 5 .1 3 , JR J 4 5 .1 1 f ro m + 3 V _L A N

C ha ng e JR J 4 5 .1 3 , JR J 4 5 .1 1 f ro m + 3 V _L A N _ LE D t o + 3V _L A N

C ha ng e JR J 4 5 .1 3 , JR J 4 5 .1 1 f ro m + 3 V _L A NC h an ge J R J4 5 .1 3 , J R J4 5 .1 1 fr om +3 V _L A N

R em o v

R em o v e R 49 0 ( 10 0 K _ 04 0 2 )

R em o vR em o v

A dd R 1 6

A dd R 1 6 c l os e to Q 3 . 1 fo r H _T H E R M TR IP #

A dd R 1 6A dd R 16

A dd H _ T H E R

A dd H _ T H E R M T R I P # t o U 3 3 .2 5

A dd H _ T H E RA dd H _ T H E R

D el H 4 9 H 50 H 3 8 H 4 5 fo r M /E d ra w i n

D el H 4 9 H 50 H 3 8 H 4 5 fo r M /E d ra w i n g c h an ge

D el H 4 9 H 50 H 3 8 H 4 5 fo r M /E d ra w i nD el H 4 9 H 50 H 3 8 H 4 5 fo r M /E d ra w i n

R ep la ce D 1 7 an

R ep la ce D 1 7 an d D 4 7 b ec om e R 5 2 a n d R 5 3

R ep la ce D 1 7 anR e p l ac e D 17 a n

D e l R 4 0 0 a n d R 4 6

D e l R 4 0 0 a n d R 4 6 , C h a ng e JP 6 p in d ef in it io n fo r c o m mo n

D e l R 4 0 0 a n d R 4 6D e l R 4 0 0 a n d R 4 6

A d d R 5 16 ( 0 _ 0

A d d R 5 16 ( 0 _ 0 6 0 3) be tw ee n J P 4 8. 1/ 4 a n d +5 V S _ L E D

A d d R 5 16 ( 0 _ 0A d d R 5 1 6 ( 0 _ 0

C ha ng e D 5 fro m S C 50 0 00 4 E 00 (A Q U A _

C ha ng e D 5 fro m S C 50 0 00 4 E 00 (A Q U A _ W HI T E ) t o

C ha ng e D 5 fro m S C 50 0 00 4 E 00 (A Q U A _Ch an ge D 5 f ro m S C 50 00 04 E 0 0( A Q U A _

S C 50 00 0 4W

S C 50 00 0 4W 00 (W H I T E)

S C 50 00 0 4WS C 5 0 0 00 4 W

C ha ng e L E D f ro m D 5 0, D 3 0, D 2 7 S C 5

C ha ng e L E D f ro m D 5 0, D 3 0, D 2 7 S C 5 0 00 0 4E 0 0

C ha ng e L E D f ro m D 5 0, D 3 0, D 2 7 S C 5C ha ng e L E D f ro m D 5 0, D 3 0, D 2 7 S C 5

(A Q U A _W H I TE ) t o D 6, D 7 , D 8 SC 5 0 00 04 W 00 (W H I T E)

(A Q U A _W H I TE ) t o D 6, D 7 , D 8 SC 5 0 00 04 W 00 (W H I T E)

(A Q U A _W H I TE ) t o D 6, D 7 , D 8 SC 5 0 00 04 W 00 (W H I T E)(A Q U A _W H I TE ) t o D 6, D 7 , D 8 SC 5 0 00 04 W 00 (W H I T E)

C ha ng e L E D f ro m D 4 5, D 4 6 S C 50 0 0

C ha ng e L E D f ro m D 4 5, D 4 6 S C 50 0 0 04 B 00

C ha ng e L E D f ro m D 4 5, D 4 6 S C 50 0 0C ha n g e L E D f ro m D 4 5 , D 46 S C 5 00 0

(A Q U A _W H I TE /A M B E R ) t o D 17 ,D 1 8 SC 5 00 00 5M 0 0

(A Q U A _W H I TE /A M B E R ) t o D 17 ,D 1 8 SC 5 00 00 5M 0 0

(A Q U A _W H I TE /A M B E R ) t o D 17 ,D 1 8 SC 5 00 00 5M 0 0(A Q U A _W H I TE /A M B E R ) t o D 17 ,D 1 8 SC 5 00 00 5M 0 0

(Y E L LO W /W H I TE ); A d d Q 7 , R2 0 a nd R 4 2 c lo se t o D 1 8

(Y E L LO W /W H I TE ); A d d Q 7 , R2 0 a nd R 4 2 c lo se t o D 1 8

(Y E L LO W /W H I TE ); A d d Q 7 , R2 0 a nd R 4 2 c lo se t o D 1 8(Y E L LO W /W H I TE ); A d d Q 7 , R2 0 a nd R 4 2 c lo se t o D 1 8

A d d H D D _ H A L T

A d d H D D _ H A L T L ED # c on ne c t f ro m U 1 5 . P8

A d d H D D _ H A L TA d d H D D _ H A L T

A dd R 4 6 1 0K _ 0 4 0 2 P H t o + 5 V L c lo se t o U 33

A dd R 4 6 1 0K _ 0 4 0 2 P H t o + 5 V L c lo se t o U 33

A dd R 4 6 1 0K _ 0 4 0 2 P H t o + 5 V L c lo se t o U 33A d d R 4 6 10 K _ 0 4 0 2 P H t o + 5 V L c lo s e to U 3 3

A dd R 5 14 ,R 5 1 5 10 K _ 0 40 2 P H t o + 3V L c lo se to U

A dd R 5 14 ,R 5 1 5 10 K _ 0 40 2 P H t o + 3V L c lo se to U 3 3

A dd R 5 14 ,R 5 1 5 10 K _ 0 40 2 P H t o + 3V L c lo se to UA dd R 5 14 ,R 5 1 5 10 K _ 0 40 2 P H t o + 3V L c lo se to U

C ha ng e R 1 5. 2, R 21 . 2 ,R 3 6 .2 ,R 3 0 . 2 co n

C ha ng e R 1 5. 2, R 21 . 2 ,R 3 6 .2 ,R 3 0 . 2 co n n ec ti o n f ro m

C ha ng e R 1 5. 2, R 21 . 2 ,R 3 6 .2 ,R 3 0 . 2 co nC ha n ge R 1 5. 2 , R2 1. 2 ,R 3 6 .2 ,R 3 0 . 2 co n

+ 1. 8 V t o + 1. 8V S ; Re m o ve R6 22 , in s

+ 1. 8 V t o + 1. 8V S ; Re m o ve R6 22 , in s ta ll R 58 1

+ 1. 8 V t o + 1. 8V S ; Re m o ve R6 22 , in s+ 1. 8 V t o + 1. 8V S ; Re m o ve R6 22 , in s

D e l Q 6 ,R 8 7 ; Q

D e l Q 6 ,R 8 7 ; Q 5, R 8 4 an d r ep la c e by 0 oh m ( a d d R 6 7, R 6 8)

D e l Q 6 ,R 8 7 ; QD e l Q 6 ,R 8 7 ; Q

c o n ne ct

c o n ne ct d ir e ct ly . I ns ta ll R 3 71 ( 1 0 K o hm )

c o n ne ct c o n n e c t

C h an g e

C h an g e J P 7 f ro m S P 02 00 0 H C0 0(8 pin )- -> S P 0 20 0 0I L 00 (6 p in )

C h an g e C ha n ge

C h a n g e R 1 6 . 2 co n ne c

C h a n g e R 1 6 . 2 co n ne ct io n f ro m T H ER M T RI P# to

C h a n g e R 1 6 . 2 co n ne cC h a ng e R 16 .2 c on n ec

T H E R M T R IP # _ E C fo r

T H E R M T R IP # _ E C fo r s ep a r at e

T H E R M T R IP # _ E C fo rTH E R M T R I P # _ E C fo r

A d d R

A d d R 1 1 2, R 11 3, R 11 5~ R 1 20 c lo se t o e a c h L 85 ~ L 88 f or c o- la y

A d d RA d d R

4 9 1 f ro m 2 0 0 _ 0 40 2 t o 2 0 0_ 08 05

4 9 1 f ro m 2 0 0 _ 0 40 2 t o 2 0 0_ 08 0549 1 fr om 2 00 _ 0 4 02 t o 2 00 _ 0 8 05

0 1

0 10 1

2 0P n o rm al .

2 0P n o rm al .2 0 P n orm a l .

g e U 54 f r om G 9 1 6 -3 9 0T 1U F t o R T 91 9 3- 3 9G B .

g e U 54 f r om G 9 1 6 -3 9 0T 1U F t o R T 91 9 3- 3 9G B .g e U 5 4 fr o m G 9 16 - 3 90 T 1 U F t o R T9 19 3 -3 9 G B .

v e R 8 91 ,R 8 92 i f no u s e G 9 16 - 39 0 T1 U F.

v e R 8 91 ,R 8 92 i f no u s e G 9 16 - 39 0 T1 U F.v e R 8 91 ,R 8 92 i f no u s e G 9 16 - 39 0 T1 U F.

ta ll .

ta ll .ta ll .

t o 6 pi n

t o 6 pi n t o 6p in

e R 4 9 0 ( 1 0 0K _ 0 4 02 )

e R 4 9 0 ( 1 0 0K _ 0 4 02 )e R 4 9 0 ( 1 0 0K _ 0 4 02 )

1 03 1 ,a dd R 3 0 3 cl os e t o R 3 0 1 a n d U 15 .P 2

1 03 1 ,a dd R 3 0 3 cl os e t o R 3 0 1 a n d U 15 .P 21 0 3 1 , a d d R 3 03 c lo se to R 3 01 a n d U 1 5 . P2

r C L K _P CI _S IO 2 t o J P4 1. 15

r C L K _P CI _S IO 2 t o J P4 1. 15r C L K _ P C I _ S I O 2 t o JP 4 1. 15

_ LE D t o +3 V _L A N

_ LE D t o +3 V _L A N_ L E D t o + 3V _L A N

e R 4 9 0 ( 1 0 0K _ 0 4 02 )

e R 4 9 0 ( 1 0 0K _ 0 4 02 )e R 4 9 0 ( 1 0 0K _ 0 4 02 )

c lo se t o Q 3 .1 f o r H _ T H ER M T R I P #

c lo se t o Q 3 .1 f o r H _ T H ER M T R I P # c lo se t o Q 3 .1 f o r H _ T H ER M T R I P #

M T R IP # t o U 3 3 .2 5

M T R IP # t o U 3 3 .2 5M T R I P # t o U 33 .2 5

g c ha n ge

g c ha n geg c ha ng e

d D 4 7 be c om e R 5 2 an d R 5 3

d D 4 7 be c om e R 5 2 an d R 5 3d D 4 7 b ec o m e R 5 2 a nd R 5 3

, C h a n g e JP 6 p in d ef in it io n f or c om m o n

, C h a n g e JP 6 p in d ef in it io n f or c om m o n, C h a n g e JP 6 p in d ef in it io n f or c om m o n

6 03 ) b et w ee n J P 4 8 . 1 /4 a n d + 5 V S _ L E D

6 03 ) b et w ee n J P 4 8 . 1 /4 a n d + 5 V S _ L E D6 03 ) b et w e e n J P4 8. 1 /4 a nd + 5 VS _L E D

W H IT E ) to

W H IT E ) toW H I TE ) to

0 0( W H IT E )

0 0( W H IT E )0 0( W H IT E )

0 00 04 E0 0

0 00 04 E0 00 00 04 E 00

0 4B 0 0

0 4B 0 00 4B 0 0

L E D # co n n ec t fr om U 1 5 . P8

L E D # co n n ec t fr om U 1 5 . P8L E D # co n n ec t fr om U 1 5 . P8

n ec ti on f ro m

n ec ti on f ro mn e c ti o n fr om

ta ll R 58 1

ta ll R 58 1t all R 58 1

5 ,R 8 4 a n d re pl a ce b y 0 oh m ( ad d R 6 7 , R6 8)

5 ,R 8 4 a n d re pl a ce b y 0 oh m ( ad d R 6 7 , R6 8)5, R 8 4 an d r ep la ce b y 0 oh m ( ad d R 6 7, R 6 8)

d ir ec tly . I n s ta l l R3 71 ( 10 K o hm )

d ir ec tly . I n s ta l l R3 71 ( 10 K o hm )di re ct ly . I ns ta ll R 3 71 ( 10 K o h m )

J P7 f ro m S P 0 2 00 0H C 00 (8 p i n) -- > S P0 20 00 I L0 0( 6 pi n )

J P7 f ro m S P 0 2 00 0H C 00 (8 p i n) -- > S P0 20 00 I L0 0( 6 pi n )J P7 f ro m S P 0 2 00 0H C 00 (8 p i n) -- > S P0 20 00 I L0 0( 6 pi n )

t i on f ro m TH E R M T R I P # t o

t i on f ro m TH E R M T R I P # t ot io n f ro m T H ER M T RI P# to

s ep ar at e

1 12 , R1 13 , R1 15 ~ R 12 0 c lo se t o ea c h L 85 ~ L 88 f or c o- la y

1 12 , R1 13 , R1 15 ~ R 12 0 c lo se t o ea c h L 85 ~ L 88 f or c o- la y1 12 , R1 13 , R1 15 ~ R 12 0 c lo se t o ea c h L 85 ~ L 88 f or c o- la y

s ep ar at e s ep ar at e

3 3

3 33 3

E

R ev .

R ev .P a

R ev .R e v.

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

47 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a ge #

I t emI te m

4 2

4 2 1 9 .

4 24 2

1 1

4 3

4 3 2 1 ,

4 34 3

4 4

4 4 2 5

4 44 4

4 5

4 5 1 3

4 54 5

4 6

4 6 1 8

4 64 6

4 7

4 7 2 0

4 74 7

4 8

4 8 2 0 , 2 1 ,

4 84 8

2 2

4 9

4 9 2 1 ,

4 94 9

5 0

5 0 2 8 ,

5 05 0

5 1

5 1 3 3

5 15 1

5 2

5 2 3 3

5 25 2

5 3

5 3 3 4

5 35 3

5 4

5 4 3 4

5 45 4

3 3

5 5

5 55 5

5 6 2 9

5 65 6

5 7

5 7 M E

5 75 7

5 8

5 8 M E

5 85 8

5 9

5 9 AAAA T I

5 95 9

6 0

6 0

6 06 0

6 1

6 1 3 5

6 16 1

6 2

6 2 3 3

6 26 2

6 3

6 3 2 8 ,

6 36 3

4 4

6 4

6 4 2 9

6 46 4

g e #

P aP a

g e #g e#

1 9 . 3 2

3 2

1 9 .1 9 .

3 23 2

2 1 , 3 2

3 2

2 1 ,2 1 ,

3 23 2

2 5

2 52 5

1 3

1 31 3

1 8

1 81 8

2 0

2 02 0

2 0, 2 1 ,

2 0, 2 1 ,20 ,2 1,

2 7

2 7

2 72 7
2 1 , 3 3

3 3

2 1 ,2 1 ,

3 33 3

2 8 , 3 3

3 3

2 8 ,2 8 ,

3 33 3

3 3

3 33 3

3 3

3 33 3

3 4

3 43 4

3 4

3 43 4

2 9

2 9

2 92 9

2 9

2 92 9

4 , 2 4

2 4

4 ,4 ,

2 42 4

3 3

3 33 3

2 0

2 02 0

3 3 C h

3 33 3

3 5

3 53 5

3 3

3 33 3

2 8 , 2 9

2 9

2 8 ,2 8 ,

2 92 9

2 9

2 92 9

TTTT it le

it le

it leit le

S B

S B ,B IO S

,B IO S 1 1

S BS B

,B IO S,B IO S

S B

S B ,B IO S

,B IO S 1 1

S BS B

,B IO S,B IO S

LLLL A N

A N 1 1

A NA N

N B

N B 1 1

N BN B
HHHH D M I

D M I 1 1

D M ID M I

S B

S B 1 1

S BS B

S B ,C

S B ,C ar dr ea d e r

a r d r ea der 1 1

S B ,CS B ,C

a r d r ea derar dr ea d e r

S B ,K B C

S B ,K B C 1 1

S B ,K B CS B ,K B C
CCCC od ec , K BC

o d ec ,K B C 1 1

o d ec ,K B Co de c, K B C

K B C

K B C 1 1

K B CK B C

K B C

K B C 1 1

K B CK B C

S w i

S w it c h D e si g n

tc h D es ig n 1 1

S w iSw i

tc h D es ig nt ch D e si g n

LLLL E D

E D 1 1

E DE D

A ud io

A ud io -D oc k

-D o c k 1 1

A ud ioA u d io

-D o c k-D o ck

H ole s

H ole s 1 1

H ole sH o le s
M u

M u lti - B a y

lt i-B a y 1 1

M uM u

lt i-B a yl ti - Ba y

H ole s

H ole s 1 1

H ole sH o le s
S B

S B 1 1

S BS B
K B C

K B C 1 1

K B CK B C
D O C K

D O C K 1 1

D O C KD O C K
KKKK / B

/ B 1 1

/ B/ B

A U

A U D IO

D IO 1 1

A UA U

D IOD IO

A U

A U D IO

D IO 1 1

A UA U

D IOD IO

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 3

/ 1 3

1 11 1

/ 1 3/ 1 3

1 1 /1 4

/ 1 4

1 11 1

/ 1 4/ 1 4

1 1 /1 4

/ 1 4

1 11 1

/ 1 4/ 1 4

1 1 /1 4

/ 1 4

1 11 1

/ 1 4/ 1 4

1 1 /1 4

/ 1 4

1 11 1

/ 1 4/ 1 4

1 1 /1 4

/ 1 4

1 11 1

/ 1 4/ 1 4

1 1 /1 6

/ 1 6

1 11 1

/ 1 6/ 1 6

1 1 /1 6

/ 1 6

1 11 1

/ 1 6/ 1 6

1 1 /1 6

/ 1 6

1 11 1

/ 1 6/ 1 6

1 1 /1 6

/ 1 6

1 11 1

/ 1 6/ 1 6

1 1 /1 8

/ 1 8

1 11 1

/ 1 8/ 1 8

1 1 /1 9

/ 1 9

1 11 1

/ 1 9/ 1 9

u e stu e st

O w n

O w n e r

O w nO w n

H W

H W R e d

H WH W

H W

H W B I O S D e bu g T oo l r es er

H WH W

H W

H W U p d a t e

H WH W

H W

H W A d d 0o hm _ 06 0 3 t o

H WH W

H W

H W R e

H WH W

H W

H W R e du

H WH W

H W

H W R e s er ve C a r dre ad er D 3 E fu nc ti on (C R _W A

H WH W

H W

H W RRRR e d u c e S B r ela te d d e s ig n f or c om m on

H WH W

H P Q

H P Q E C

H P QH P Q

H W

H W R e du ce

H WH W

H W

H W R e d uc e K B C D e s ig n f or co m mo n a nd V e r :C 0

H WH W

H W

H W U p d a t e C SD f

H WH W

H W

H W C or re ct T / P O n/ Of f LE D d es ig n d ef

H WH W

H P Q

H P Q FFFF o r G S m a r k r eq ui r em en t

H P QH P Q

M E

M E U p d at e

M EM E

M E U p d at e Sy

M EM E

M E U p d at e

M EM E

T I R e

T IT I

E C

E C3 3

E CE C

EEEE M C

M C Co nn e

M CM C

H W

H W F ix K B m a tr i

H WH W

H P Q

H P Q M a ke s

H P QH P Q

H P Q

H P Q M a ke s

H P QH P Q

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

R ed u ce S B r el at e d d es i gn fo r C h i p A 1 2 a n d ot he rs

R edR e d

B IO S D e b u g T o o l re se r v e

B IO S D e b u g T o o l re se rB IO S D e bu g T oo l r e se r

U p da te L A N C h i p S ym bo l li nk t o C I S s e rv er

U p da teU p d a t e

A d d 0 o h m _ 0 6 0 3 t o s ep a r at e V D D 18 _ M E M

A d d 0 o h m _ 0 6 0 3 t oA d d 0 o h m _ 0 6 0 3 t o

R e du c e H D M I r ela te d d e s ig n f or c om m on

d uc e H D M I r ela te d de si g n f or c om m on

R eR e

d uc e H D M I r ela te d de si g n f or c om m ond u ce H D M I r el at e d d es ig n f or c om m on

R ed u ce S B r el at e d d es i gn fo r c om m o n a nd A 1 2 c hi p

R ed uR e du

R es e rv e C a r dr e ad er D 3 E fu n c ti on ( C R _W A K E # &

R es e rv e C a r dr e ad er D 3 E fu n c ti on ( C R _W AR es er v e C a r dr e ad er D 3 E fu n c ti on ( C R _W A

C R_ C

C R_ C PP E # )

C R_ CC R_ C

e d uc e SB r ela te d d e s ig n f or c om m on

e d uc e SB r ela te d d e s ig n f or c om m one du ce S B r el at e d d es i gn f or c om m on

E C _ B E E P f u n c tio n f o r K B C a d d

E CE C

R ed u c e S5 P o w e r C o n su mp tio n

R ed u c e R ed u c e

R ed uc e K B C D e si gn fo r c om m o n a n d V e r: C0 C h i p

R ed uc e K B C D e si gn fo r c om m o n a n d V e r: C0R e d u c e K B C D e s ig n f or co m mo n a nd V e r :C 0

C ha n g e fr om S A 00 0 0 1 J5 30 t o S A

C ha n g e fr om S A 00 0 0 1 J5 30 t o S A 00 00 1J 54 0

C ha n g e fr om S A 00 0 0 1 J5 30 t o S AC h a n g e f r om S A 00 0 0 1 J5 30 t o SA

U p da te C S D f u nc ti on bo a rd d es i gn fo r c om m o n

U p da te C S D fU p da te C S D f

C or re c t T /P O n / O f f L E D de s ig n d ef in e

C or re c t T /P O n / O f f L E D de s ig n d efC or r ec t T /P O n/ O f f L E D d es i gn d ef

C or re

C or re c t G - S en so r L E D de s ig n d ef in e

C or reC o rr e

o r G S m a r k r eq ui r em en t

o r G S m a r k r eq ui r em en tor G S m a rk r eq u ir e m e nt

U p da te H ol e s t o m e et M / E D r a w in g

U p da te U p d at e

U p da te S y m b ol to m e et M / E D ra w i ng

U p da te S yU p da te Sy

U p da te H ol e s t o m e et M / E D r a w in g

U p da te U p d at e

R e se rv e t o f ix t he O T S3 2 5 0 5 5 Is su e

s e rv e t o f ix t he O T S 3 2 5 0 5 5 I ss u e

R eR e

s e rv e t o f ix t he O T S 3 2 5 0 5 5 I ss u e se r ve to f i x th e O T S3 25 05 5 I ss ue

C h an g e d es ig n f or E C t ea m d eb ug

a n ge d es i gn fo r E C t ea m d eb ug

C hC h

a n ge d es i gn fo r E C t ea m d eb uga n ge d es i gn fo r E C t ea m d eb ug

C on ne c t D O C K g uid e p in t o G N D

C on neC o nn e

F ix K B m at ri x i s su e

F ix K B m at riF ix K B m a tr i

M a ke s o me A u d io r el at e d d es i gn ch a n ge

M a ke sM a k e s

M a ke s o me A u d io r el at e d d es i gn ch a n ge

M a ke sM a k e s

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

u c e S B re la te d d es ig n f o r Ch ip A 1 2 a n d o t he rs

u c e S B re la te d d es ig n f o r Ch ip A 1 2 a n d o t he rsuc e S B r e la t ed d es i gn fo r C hi p A 1 2 a n d o t he rs

v e

v ev e

L A N C h ip S y m b o l l i nk t o CI S se rv er

L A N C h ip S y m b o l l i nk t o CI S se rv er L A N C h ip S y m b ol l in k t o C IS s er ve r

s e p a ra te V D D 18 _M E M

s e p a ra te V D D 18 _M E M s e p a ra te V D D 18 _M E M

c e S B r e la t ed d es i gn f o r c om m o n a n d A 1 2 c hi p

c e S B r e la t ed d es i gn f o r c om m o n a n d A 1 2 c hi pce S B r el at e d d es ig n f or c om m on a nd A 1 2 c h i p

P PE # )

P PE # )P PE # )

_ BE E P f un ct io n f or K B C a dd

_ BE E P f un ct io n f or K B C a dd_ BE E P f un ct io n f or K B C a dd

S 5 P ow er Co ns u m p ti o n

S 5 P ow er Co ns u m p ti o nS 5 Po w e r Co ns u m p ti o n

u n ct io n b oa rd d e s ig n f or c om m on

u n ct io n b oa rd d e s ig n f or c om m onu nc ti on b oa rd d es i gn f or c om m on

c t G -S en so r L E D d e s ig n d ef in e

c t G -S en so r L E D d e s ig n d ef in ec t G- S en so r L E D de s ig n d e f in e

H ol e s t o m ee t M / E D ra w i ng

H ol e s t o m ee t M / E D ra w i ngH ol e s t o m e et M / E D r a w in g

m bo l t o m e e t M / E D r a w in g

m bo l t o m e e t M / E D r a w in gm bo l t o m e e t M /E D r aw i ng

H ol e s t o m ee t M / E D ra w i ng

H ol e s t o m ee t M / E D ra w i ngH ol e s t o m e et M / E D r a w in g

c t D O C K g ui d e p in t o G N D

c t D O C K g ui d e p in t o G N Dct D O C K gu id e pi n t o G N D

x i ss u e

x i ss u ex i s su e

o m e A u di o re la te d d es ig n c h a ng e

o m e A u di o re la te d d es ig n c h a ng eo me A u d io r e la t ed d es i gn c h a n ge

o m e A u di o re la te d d es ig n c h a ng e

o m e A u di o re la te d d es ig n c h a ng eo me A u d io r e la t ed d es i gn c h a n ge

C

0 00 0 1J 5 4 0

0 00 0 1J 5 4 00 00 01 J5 40

in e

in ein e

K E# &

K E# &K E # &

C hi p

C hi p C h i p

D

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

D e

D e l Q1 55 ,R 9 86 , a n d a d d R 3 11 c lo se to U 1 5 .

l Q 1 55 ,R 9 8 6 , a nd a dd R 3 11 c lo se t o U 1 5.

D eD e

l Q 1 55 ,R 9 8 6 , a nd a dd R 3 11 c lo se t o U 1 5.l Q 1 55 ,R 9 86 , a n d a d d R 31 1 c lo se t o U 1 5.

D e l R 1 0 1 1 b ec om e T

D e l R 1 0 1 1 b ec om e T 1 8 , C an ce l R 1 0 1 2 a n d co n n ec t to H 3 1

D e l R 1 0 1 1 b ec om e TD e l R 1 0 1 1 b ec om e T

a nd J P 41

a nd J P 41 d ir ec t ly

a nd J P 41 a n d J P 4 1

A d d S B _I N T _ F L A S H _ S E

A d d S B _I N T _ F L A S H _ S E L a n d r el a te d

A d d S B _I N T _ F L A S H _ S EA d d SB _ IN T _F L A SH _ SE

(J P1 2,U 3 0,R 2 2 8, R 2 26 ,C 4 8 9 c lo se to U

(J P1 2,U 3 0,R 2 2 8, R 2 26 ,C 4 8 9 c lo se to U 2 9)

(J P1 2,U 3 0,R 2 2 8, R 2 26 ,C 4 8 9 c lo se to U( J P1 2,U 3 0,R 2 2 8 , R2 26 ,C 4 8 9 cl os e t o U

U p da te L A N

U p da te L A N C h i p U 2 0 S ym bo l l in k to C I S s er ve r

U p da te L A N U p d a t e L A N

A d d R 1 05 1( 0_ 0 6 0 3 ) b

A d d R 1 05 1( 0_ 0 6 0 3 ) b e tw e en + 1.8 V S & + 1. 8 V _V D D _ S P

A d d R 1 05 1( 0_ 0 6 0 3 ) bA d d R 1 0 51 (0 _ 0 6 0 3 ) b

D e l

D e l R 49 0 ( 1 0 0 K _0 40 2)

D e lD e l

R em o v e

R em o v e R 99 4 ( 0 _ 0 4 0 2)

R em o v e R e m o v e

C h a n g e U 1

C h a n g e U 1 5 .F 1 c on ne c tio n b ec om e t es t p oin t

C h a n g e U 1C h an ge U 1

R em o v e R 10 53 ,

R em o v e R 10 53 , c ha ng e R 1 05 2 b ec om e 0 _0 40 2

R em o v e R 10 53 ,R e m ov e R 1 0 5 3 ,

A d d R

A d d R 8 1 c lo se to U 1 5 ;Q 5 4, R 12 4 c lo s e t o U 23 f or c o n n ec t U 15 .F 8

A d d RA d d R

t o U 23 . 1 3 ; Ad d R 3 69 c l os e t o U 23 f or c o n n ec t U 15 . M 5 to U 2 3.

t o U 23 . 1 3 ; Ad d R 3 69 c l os e t o U 23 f or c o n n ec t U 15 . M 5 to U 2 3. 1 6

t o U 23 . 1 3 ; Ad d R 3 69 c l os e t o U 23 f or c o n n ec t U 15 . M 5 to U 2 3. t o U 2 3 . 13 ; Ad d R 3 6 9 c lo se t o U 23 f or c on n e ct U 1 5 .M 5 t o U 2 3.

D el D 5 1 a nd R 1 03 4, C h an ge t he n e t A C_ I N

D el D 5 1 a nd R 1 03 4, C h an ge t he n e t A C_ I N b eco me A C _ IN _ D

D el D 5 1 a nd R 1 03 4, C h an ge t he n e t A C_ I ND el D 5 1 a n d R 1 0 3 4, C ha n g e th e n et A C _I N

A d

A d d R 5 63 c l os e t o C 9 55 ; A dd R 5 4 4 c lo se t o U 33 .3 1

d R 5 63 c lo se t o C 9 55 ; A d d R 54 4 c lo se to U 3 3 .3 1

A dA d

d R 5 63 c lo se t o C 9 55 ; A d d R 54 4 c lo se to U 3 3 .3 1d R 5 6 3 c lo s e to C 9 55 ; A d d R 5 44 c lo se t o U 3 3 . 31

C ha ng e R 1 04 0. 1 c on n e ct io n f ro m + 3 V L_

C ha ng e R 1 04 0. 1 c on n e ct io n f ro m + 3 V L_ E C to + 3V A L W

C ha ng e R 1 04 0. 1 c on n e ct io n f ro m + 3 V L_C h an ge R 1 0 4 0 .1 c on n ec ti o n f ro m + 3 V L _

D el R 5 4 6 P H t o +3 V L _ E C , D el D 2 6 r e pla ce b y a d d R 5 47 c lo s

D el R 5 4 6 P H t o +3 V L _ E C , D el D 2 6 r e pla ce b y a d d R 5 47 c lo s e to

D el R 5 4 6 P H t o +3 V L _ E C , D el D 2 6 r e pla ce b y a d d R 5 47 c lo sD e l R5 46 P H t o + 3V L _ E C , D el D 2 6 r ep la c e by a dd R 5 47 c lo s

UUUU 3 3 f or s h o rt

3 3 fo r sh o r t

3 3 fo r sh o r t3 3 f or s h o rt

D el R 5 3 7 b ec o m e Te st P o in t , c ha n ge R 5 1 6 b ec o m e 15 0 _ 0 6

D el R 5 3 7 b ec o m e Te st P o in t , c ha n ge R 5 1 6 b ec o m e 15 0 _ 0 6 03

D el R 5 3 7 b ec o m e Te st P o in t , c ha n ge R 5 1 6 b ec o m e 15 0 _ 0 6D el R 5 3 7 b ec o m e Te st P o in t , c ha n ge R 5 1 6 b ec o m e 15 0 _ 0 6

R em o v e R1 04 4, c h an g e R 10 4 0 fr o m 1 0K t o 1

R em o v e R1 04 4, c h an g e R 10 4 0 fr o m 1 0K t o 1 0 0K

R em o v e R1 04 4, c h an g e R 10 4 0 fr o m 1 0K t o 1R e m ov e R 1 04 4 , ch a ng e R 1 04 0 f ro m 1 0 K t o 1

C ha ng e R 5 28 .2 , R5 29 . 2 co n ne ct io n f ro m + 5

C ha ng e R 5 28 .2 , R5 29 . 2 co n ne ct io n f ro m + 5 V AL W t o +5 VL

C ha ng e R 5 28 .2 , R5 29 . 2 co n ne ct io n f ro m + 5C h an ge R 52 8. 2 , R 5 29 .2 c o n n ec t io n f ro m + 5

I ns ta ll C 8 14 ( 4. 7U _ 08 05 )

I ns ta ll C 8 14 ( 4. 7U _ 08 05 )

I ns ta ll C 8 14 ( 4. 7U _ 08 05 )I n s ta l l C 81 4 ( 4 .7 U _ 08 05 )

C ha ng e JP 3 6 . 1 co n n e ct io n b ec om e + 3 VL ;C ha ng e R 1

C ha ng e JP 3 6 . 1 co n n e ct io n b ec om e + 3 VL ;C ha ng e R 1 0 46 .1

C ha ng e JP 3 6 . 1 co n n e ct io n b ec om e + 3 VL ;C ha ng e R 1Ch an ge J P3 6. 1 c on n e ct io n b ec om e + 3 V L ;C ha n g e R 1

a nd R 1 04 7 .1 c o n n ec t io n b ec o m e S M B _

a nd R 1 04 7 .1 c o n n ec t io n b ec o m e S M B _ EC _C K 1/ D A1

a nd R 1 04 7 .1 c o n n ec t io n b ec o m e S M B _an d R 1 0 4 7 .1 c on n ec ti o n b ec o m e SM B _

C ha ng e JP 3 6 . 7 co n n e ct io n f ro m G N

C ha ng e JP 3 6 . 7 co n n e ct io n f ro m G N D to + 5V A LW _ L E D b y

C ha ng e JP 3 6 . 7 co n n e ct io n f ro m G NC h an g e JP 36 .7 c o n n ec t io n f ro m G N

CCCC h an ge Q1 53 f ro m 2 N 7 0 02 D W t o 2 N 70 02

h an g e Q 15 3 f ro m 2 N 7 00 2 D W t o 2 N 70 0 2

h an g e Q 15 3 f ro m 2 N 7 00 2 D W t o 2 N 70 0 2h an g e Q 15 3 f ro m 2 N 7 00 2 D W t o 2 N 70 0 2

C ha ng e R 9 88 .1 c on n ec ti o n f ro m +

C ha ng e R 9 88 .1 c on n ec ti o n f ro m + 5 V S_ L E D t o + 3V S

C ha ng e R 9 88 .1 c on n ec ti o n f ro m +C h a n ge R 9 88 . 1 c on n e ct io n f ro m +

A d

A d d R 9 68 ,R 9 69 c lo se t o C 77 5/ C7 7 6.

d R 9 68 , R 9 69 c lo se t o C 7 75 /C 7 76 .

A dA d

d R 9 68 , R 9 69 c lo se t o C 7 75 /C 7 76 .d R 9 68 , R 9 69 c lo se t o C 7 7 5/ C7 7 6.

A d d

A d d ba ck H 5 2 b e co m e H _1 P 5 N ; D el C F 4

A d d A d d

U p da t e JP 2 ,J P 9, J P 10 ,J P 1 1 , JP 2 0, J P 40 , J H D M I, J

U p da t e JP 2 ,J P 9, J P 10 ,J P 1 1 , JP 2 0, J P 40 , J H D M I, J ES A T ,J C RT ,

U p da t e JP 2 ,J P 9, J P 10 ,J P 1 1 , JP 2 0, J P 40 , J H D M I, JU pd at e JP 2 ,J P 9, JP 1 0, J P 11 ,J P 2 0, JP 4 0, J H D M I, J

J D OC K

J D OC K S y m b ol

J D OC KJD O C K

A d d

A d d ba ck H 5 2 b e co m e H _1 P 5 N ; D el C F 4

A d d A d d

R e s

R e s e r ve R 8 3 PH t o + 3V S

R e sR es

C ha ng e JP 3 4 . 1 fro m + 5 V A L W

C ha ng e JP 3 4 . 1 fro m + 5 V A L W t o + 5V L

C ha ng e JP 3 4 . 1 fro m + 5 V A L W C ha n ge J P 3 4. 1 fr om + 5V A L W

A d d J D O CK . 4 5/ 46

A d d J D O CK . 4 5/ 46 to G N D

A d d J D O CK . 4 5/ 46 A d d JD O C K . 4 5 / 46

D el K S I6 a nd K S O 9 o ut of p

D el K S I6 a nd K S O 9 o ut of p a ge n et c o nn ec t

D el K S I6 a nd K S O 9 o ut of pD e l K SI 6 a n d K S O 9 o ut o f p

C ha ng e C 9 8 3, C 98 4 f r om 1 U F to 0 . 02 2 U F . Ch a n ge C1 0 49 ,C

C ha ng e C 9 8 3, C 98 4 f r om 1 U F to 0 . 02 2 U F . Ch a n ge C1 0 49 ,C 1 0 50 ,C 1 04 0 ,C 10 4 1

C ha ng e C 9 8 3, C 98 4 f r om 1 U F to 0 . 02 2 U F . Ch a n ge C1 0 49 ,CC ha n g e C 98 3 ,C 9 8 4 fr o m 1 U F t o 0 .0 2 2 U F. C h an g e C 10 49 , C

f ro m 0 . 47 U F t o 0 .0 2 2U F . C h an g e R 1 00 2 ,R 1 0 05 fr o m 2 0 K t o 0 o h m. C h an g

f ro m 0 . 47 U F t o 0 .0 2 2U F . C h an g e R 1 00 2 ,R 1 0 05 fr o m 2 0 K t o 0 o h m. C h an g e

f ro m 0 . 47 U F t o 0 .0 2 2U F . C h an g e R 1 00 2 ,R 1 0 05 fr o m 2 0 K t o 0 o h m. C h an gf ro m 0 . 47 U F t o 0 .0 2 2U F . C h an g e R 1 00 2 ,R 1 0 05 fr o m 2 0 K t o 0 o h m. C h an g

C 10 44 fr o m 1 0 U F t o 4 .7 U F . R em o v e R 10 0 0 ,R

C 10 44 fr o m 1 0 U F t o 4 .7 U F . R em o v e R 10 0 0 ,R 1 00 4; I ns ta ll R 10 0 1, R1 0 03 .

C 10 44 fr o m 1 0 U F t o 4 .7 U F . R em o v e R 10 0 0 ,RC 1 04 4 f ro m 1 0 U F to 4 . 7U F . R e m ov e R 10 00 ,R

C ha ng e R 9 68 ,R 9 6 9 f ro m 4 0 .2 _ 04 02 t o 47 _ 0 60 3

C ha ng e R 9 68 ,R 9 6 9 f ro m 4 0 .2 _ 04 02 t o 47 _ 0 60 3

C ha ng e R 9 68 ,R 9 6 9 f ro m 4 0 .2 _ 04 02 t o 47 _ 0 60 3C h an ge R 96 8, R 9 69 f ro m 4 0 . 2_ 0 4 0 2 t o 47 _0 60 3

d ir ec tly

d ir ec tlydi r ec tl y

R 4 9 0 ( 10 0K _ 0 4 0 2 )

R 4 9 0 ( 10 0K _ 0 4 0 2 ) R 4 90 ( 10 0K _ 0 40 2)

R 99 4 ( 0 _ 0 4 0 2 )

R 99 4 ( 0 _ 0 4 0 2 )R 99 4 (0 _ 0 4 0 2 )

5 .F 1 co nn ec t io n b ec o m e t es t p oi n t

5 .F 1 co nn ec t io n b ec o m e t es t p oi n t5 .F 1 co nn ec t io n b ec o m e t es t p oi n t

8 1 cl o s e to U 1 5; Q 54 , R 1 24 c lo se t o U 2 3 f or c o nn e ct U 1 5 . F8

8 1 cl o s e to U 1 5; Q 54 , R 1 24 c lo se t o U 2 3 f or c o nn e ct U 1 5 . F881 c lo s e t o U 15 ;Q 5 4, R 1 24 c lo se t o U 2 3 fo r co n ne ct U 1 5.F 8

b ac k H 5 2 be co m e H _ 1P 5 N ; D e l CF 4

b ac k H 5 2 be co m e H _ 1P 5 N ; D e l CF 4b a c k H 52 b ec o m e H _1 P 5 N ; D e l C F 4

S y mb ol

S y mb ol S ym b ol

b ac k H 5 2 be co m e H _ 1P 5 N ; D e l CF 4

b ac k H 5 2 be co m e H _ 1P 5 N ; D e l CF 4b a c k H 52 b ec o m e H _1 P 5 N ; D e l C F 4

e r ve R 8 3 PH t o + 3V S

e r ve R 8 3 PH t o + 3V Se rv e R 8 3 P H t o +3 V S

1 8, C a n ce l R 1 01 2 a nd c on n ec t t o H 3 1

1 8, C a n ce l R 1 01 2 a nd c on n ec t t o H 3 11 8 , C an ce l R 1 0 1 2 a n d c o nn ec t t o H 3 1

L a n d r el a te d

L a n d r el a te dL a nd r el at ed

2 9 )

C hi p U 2 0 Sy m bo l l in k t o C IS s er v er

C hi p U 2 0 Sy m bo l l in k t o C IS s er v erC h ip U 2 0 S ym b ol l in k to C I S s er ve r

e t w e en + 1. 8 V S & + 1 . 8V _ V D D _ SP

e t w e en + 1. 8 V S & + 1 . 8V _ V D D _ SPe tw e en + 1. 8 V S & + 1 . 8 V _V D D _S P

c h a n ge R 1 0 5 2 b ec om e 0_ 0 40 2

c h a n ge R 1 0 5 2 b ec om e 0_ 0 40 2 ch an ge R1 05 2 b ec om e 0 _0 40 2

D t o +5 VA L W _L E D b y

D t o +5 VA L W _L E D b y D to + 5V A L W _L E D b y

5 VS _L E D t o +3 VS

5 VS _L E D t o +3 VS5V S _ L E D to + 3V S

to + 5V L

to + 5V Lt o +5 V L

to G N D

to G N Dt o G N D

a ge n et c on n e ct

a ge n et c on n e cta g e n et c o nn e c t

2 9 )2 9)

b ec o m e A C_ IN _ D

b ec o m e A C_ IN _ D b ec om e A C _I N _D

E C t o + 3V A L W

E C t o + 3V A L WE C to + 3V A L W

0 0K

0 0K0 0 K

V A LW t o + 5V L

V A LW t o + 5V LV AL W t o +5 V L

0 46 .1

0 46 .1 0 46 .1

E C_ CK 1/ DA 1

E C_ CK 1/ DA 1E C _C K 1 / DA 1

E SA T , JC R T,

E SA T , JC R T,E S A T, JC RT ,

1 05 0 ,C 10 4 0, C1 0 41

1 05 0 ,C 10 4 0, C1 0 41 1 05 0 ,C 1 04 0, C 10 4 1

1 00 4 ; I n st al l R1 0 01 ,R 1 00 3.

1 00 4 ; I n st al l R1 0 01 ,R 1 00 3.1 0 04 ; In s ta ll R 10 0 1, R 10 03 .

E

1 6

1 61 6

e t o

e t oe t o

0 3

0 30 3

R ev .

R ev .P a

R ev .R e v.

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .25 5

0 .20 .2

0 .2

0 .25 6

0 .20 .2

0 .2

0 .24 ,

0 .20 .2

0 .2

0 .23 3

0 .20 .2

0 .2

0 .22 0

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

e

e e

0 .2

0 .2

0 .20 .2

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

48 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a ge #

I t emI te m

6 5

6 5 1 3

6 56 5

1 1

6 6

6 6 2 2

6 66 6

6 7

6 7 2 2

6 76 7

6 8

6 8 3 3 ,

6 86 8

6 9

6 9 2 3

6 96 9

7 0

7 0 3 1

7 07 0

7 1

7 1 3 4

7 17 1

7 2

7 2 3 3

7 27 2

7 3

7 3 6666

7 37 3

7 4

7 4 1 9

7 47 4

2 2

7 5

7 5 2 6

7 57 5

7 6

7 6 2 8

7 67 6

7 7

7 7 1 0

7 77 7

7 8

7 8 1 9

7 87 8

7 9

7 9 2 2

7 97 9

8 0

8 0 2 8

8 08 0

8 1

8 1 3 4

8 18 1

8 2

8 2 1 4

8 28 2

8 3

8 3 1 5

8 38 3

8 4

8 4 2 8

8 48 4

8 5

8 58 5

3 3

8 6

8 68 6

8 7

8 7 3 4

8 78 7

8 8

8 8 1 9

8 88 8

8 9

8 9

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9 0 3 3

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9 2

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g e #

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3 3 , 3 4

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3 3 ,3 3 ,

3 43 4

2 3

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3 1

3 13 1

3 4

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3 3

3 33 3

1 9

1 91 9

2 6

2 62 6

2 8

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1 0 ~ 1 3

~ 13

1 01 0

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1 9

1 91 9

2 2

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1 5

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it leit le

N B

N B 1 1

N BN B

S B

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S BS B
S B

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F un c t io n B o

F un c t io n B o ar d

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lu eT oo th 1 1

lu eT oo thlu eT o o th

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K B C

K B C 1 1

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C P U

C P U 1 1

C P UC P U
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a r d R ea d e rar d R ea d e r

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a r d 1 1

a r da rd

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( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

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R eq u e st

u e st

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O w n e r

O w nO w n

AAAA T I

T I D e si g

T IT I

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T I D e si g

T IT I

H W

H W R e du ce SB

H WH W

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H W R e s er ve f or R a ch m an U M A s e le c

H WH W

H W

H W M a k

H WH W

H W

H W U p d a t e B

H WH W

H W

H W C a nc e

H WH W

H W

H W M o d if y

H WH W

H W

H W L in k P R OC H OT # b et w e en C P

H WH W

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H W RRRR e s er v e L P CC L K 1 f or d eb ug ca rd f un ct io n

H WH W

H W

H W T o av oi d N

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H W R e se rv

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H W B O M c or r ec t f or S I- 1 S M T b u

H WH W

H W

H W CCCC h a n g e C ry s ta l R e s . si ze fo r l a yo ut sp ac e

H WH W

H W

H W R e d u c e S B S A TA P ow er Ca ps ( Co nf i rm w it h A T I F A E )

H WH W

H W

H W S P D I F 0 - -> 1

H WH W

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H W C h an ge T /

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T I F i

T IT I

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H W C h an

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H W C h a ng e E C _ BE E P f un ct io n b ec om e r e

H WH W

H W

H W D i sc o n n e c t D 3 E s u p

H WH W

H W

H W U s e Ex t. B I O S as d

H WH W

H W

H W C a n ce l W L A N /W W A N e x t p ul l h ig h

H WH W

H W

H W F ix P A M / E In te rf er e i s su e fo

H WH W

AAAA T I

T I A T I

T IT I

H W

H W CCCC h a n g e 3 2. 7 6 8 K Hz M a in S ou rc e V en do r be co m e E P SO N

H WH W

H W

H W C a n ce l E x t. B IO S r ef l as h d e s ig n b ec a u

H WH W

H W

H W C a nc e l

H WH W

1 1 /2 0

1 11 1

1 1 /2 0

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1 1 /2 0

1 11 1
1 1 /2 0

1 11 1

1 1 /2 0

1 11 1
1 1 /2 0

1 11 1

tc h 1 1

1 1 /2 2

tc ht ch

1 11 1
1 1 /2 2

1 11 1
1 1 /2 2

1 11 1
1 1 /2 2

1 11 1
1 1 /2 2

1 11 1
1 1 /2 2

1 11 1
1 1 /2 3

1 11 1

1 1 /2 3

1 11 1
1 1 /2 6

1 11 1
1 1 /2 6

1 11 1
1 1 /2 8

1 11 1
1 1 /2 8

1 11 1
1 1 /2 8

1 11 1
1 1 /2 8

1 11 1
1 1 /2 8

1 11 1
1 1 /2 8

1 11 1
1 1 /2 8

1 11 1
1 1 /3 0

1 11 1
1 1 /3 0

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1 1 /3 0

1 11 1
1 2

1 2 /0 3

1 21 2
1 2

1 2 /0 3

1 21 2

D a t e

D a t eD a te

/ 2 0

/ 2 0/ 2 0

/ 2 0

/ 2 0/ 2 0
/ 2 0

/ 2 0/ 2 0
/ 2 0

/ 2 0/ 2 0

/ 2 0

/ 2 0/ 2 0
/ 2 0

/ 2 0/ 2 0
/ 2 2

/ 2 2/ 2 2
/ 2 2

/ 2 2/ 2 2
/ 2 2

/ 2 2/ 2 2
/ 2 2

/ 2 2/ 2 2
/ 2 2

/ 2 2/ 2 2
/ 2 2

/ 2 2/ 2 2
/ 2 3

/ 2 3/ 2 3

/ 2 3

/ 2 3/ 2 3
/ 2 6

/ 2 6/ 2 6
/ 2 6

/ 2 6/ 2 6
/ 2 8

/ 2 8/ 2 8
/ 2 8

/ 2 8/ 2 8
/ 2 8

/ 2 8/ 2 8
/ 2 8

/ 2 8/ 2 8
/ 2 8

/ 2 8/ 2 8
/ 2 8

/ 2 8/ 2 8
/ 2 8

/ 2 8/ 2 8
/ 3 0

/ 3 0/ 3 0
/ 3 0

/ 3 0/ 3 0

/ 3 0

/ 3 0/ 3 0
/ 0 3

/ 0 3/ 0 3
/ 0 3

/ 0 3/ 0 3

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

D e s ig n C h a n g e f or N B A 12 V e rs io n c hi p

D e s igD e si g

D e s ig n C h a n g e f or S B A 1 2 V er s io n c hi p

D e s igD e si g

R ed u c e S B P ow e r D e si gn -N o I D E su pp or t

R ed u c e S B R e d u ce SB

R es e rv e f or Ra ch m an U M A s e le c ti v e

R es e rv e f or Ra ch m an U M A s e le cR es er v e f or R a ch m an U M A s e le c

M a k e th e S B S tr ap S ee ti ng f o r c om m on

M a kM a k

U p da te B T d es ig n f or co m mo n

U p da te BU p d a t e B

C an ce l o ne re se r ve d p ow e r on s w i t ch

C an ceC a nc e

M o di fy S M B _E C _ D A 1/ C K 1 P H f or co m mo n

M o di fy M o d i fy

L in k P R O C H O T # be t w e en C P U a nd N B

L in k P R O C H O T # be t w e en C PL in k P R O C H O T # b et w e e n C P

e s erv e L P C C LK 1 fo r d eb ug c a rd f un c tio n

e s erv e L P C C LK 1 fo r d eb ug c a rd f un c tio nes er ve LP C C L K 1 f o r de b u g c ar d f u nc ti on

T o a v o id N e w Ca rd S w it ch l ea k a ge i s su e

T o a v o id NT o a v o i d N

R es er v e S P D I F O U T 1 t e st p o i nt f or ve r if y

R es er vR e se rv

B O M co rr e ct f or SI - 1 S M T b u ild

B O M co rr e ct f or SI - 1 S M T b uB O M c or r ec t f or S I- 1 S M T b u

h an g e C ry st al Re s. s iz e f or l ay o u t s pa ce

h an g e C ry st al Re s. s iz e f or l ay o u t s pa ceh an ge C ry st a l R e s. s iz e f or l ay o ut s pa ce

R ed uc e S B SA TA P ow er C ap s ( C o n fir m w i t h A T I FA E )

R ed uc e S B SA TA P ow er C ap s ( C o n fir m w i t h A T I FA E )R e du ce SB S A T A P o w e r Ca ps ( Co nf i rm w it h A T I F A E )

S PD I F 0 - - > 1 d es i gn c h a n ge t o fo llo w V a de r

S PD I F 0 - - > 1S PD I F 0 - - > 1

C ha n g e T/ P Po w e r fo r r ed u c e S 4/ S5 p ow er co ns um p tio n

C ha n g e T/C h a n g e T/

F i x H D M I no fu nc ti on is su e

x H D M I n o f un c tio n i s su e

F iF i

x H D M I n o f un c tio n i s su ex H D M I n o f un ct io n is su e

C ha n ge de si g n f or n ew v er sio n C L K G e n .

C ha nC h an

C ha ng e E C _B E E P f u nc ti on be c om e r es e rv e

C ha ng e E C _B E E P f u nc ti on be c om e r eC ha ng e E C _ B E E P f u n c ti on b ec o m e re

D is co nn ec t D 3 E su p p o r t fo r A v er si on t o av oi d r is k

D is co nn ec t D 3 E su pD is co nn ec t D 3 E su p

U se E x t . BI OS a s d e f au lt

U se E x t . BI OS a s dU se E x t . B I O S a s d

C an c el W LA N /W W A N e xt pu ll hi g h

C an c el W LA N /W W A N e xt pu ll hi g hC an ce l W L A N / W W A N ex t p u l l h ig h

F ix P A M / E I nt e rf er e i ss ue f or S I-1

F ix P A M / E I nt e rf er e i ss ue f oF i x P A M / E In te rf er e i s su e f o

A T I r ec o m m e nd f o r u pd at e

A T I A T I

h an g e 3 2 . 7 6 8 K H z M a in S ou rc e V e n d o r b ec om e E P SO N

h an g e 3 2 . 7 6 8 K H z M a in S ou rc e V e n d o r b ec om e E P SO Nh an g e 3 2 . 7 6 8 K H z M a in S ou rc e V e n d o r b ec om e E P SO N

C an c el Ex t. B I O S re fla sh d es i gn b ec au se o f +3 V L e r ro e

C an c el Ex t. B I O S re fla sh d es i gn b ec auC a nc el Ex t. B I O S r e fl a sh d es i gn b ec au

C an ce l G -S en s or IN T 2 L E D f un c ti o n

C an ce lC an ce l

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

n Ch an ge f or N B A 1 2 V er s io n c h i p

n Ch an ge f or N B A 1 2 V er s io n c h i pn C h a n g e f or N B A 12 V e rs io n c hi p

n Ch an ge f or SB A 1 2 V e r si on c hip

n Ch an ge f or SB A 1 2 V e r si on c hipn C h a n g e f or S B A 1 2 V er s io n c hi p

P ow er D e sig n-N o ID E s u p p or t

P ow er D e sig n-N o ID E s u p p or tP o w e r D e si gn - N o I D E s u pp or t

e th e S B St r ap S ee ti n g f or c om m on

e th e S B St r ap S ee ti n g f or c om m one th e S B S tra p S ee t in g f or co m mo n

T d es i gn f o r c om m o n

T d es i gn f o r c om m o nT d es i gn f o r c om m on

l o ne r es erv ed p ow er o n s wi t ch

l o ne r es erv ed p ow er o n s wi t chl on e r es er v ed p o w e r o n s w i tc h

S M B _ E C _ D A 1 /C K 1 P H f or co m mo n

S M B _ E C _ D A 1 /C K 1 P H f or co m mo nS M B _ E C _ D A 1 /C K 1 P H f or co m mo n

U a nd N B

U a nd N BU a n d N B

e w C a r d S w i tc h l ea k a ge i ss ue

e w C a r d S w i tc h l ea k a ge i ss ueew C ard S w it ch l e ak ag e is su e

e SP D IF O U T1 t es t p oi n t f or v er if y

e SP D IF O U T1 t es t p oi n t f or v er if ye S P D IF O U T1 t es t p oi n t f o r v er i fy

ild

ildi l d

d es i gn c h an ge to f o ll ow V a de r

d es i gn c h an ge to f o ll ow V a de r de s ig n c ha ng e to f ol l ow V a de r

P P o w e r f or re du ce S 4 / S5 p ow e r c on su m pt io n

P P o w e r f or re du ce S 4 / S5 p ow e r c on su m pt io nP P o w e r f or r ed uc e S 4 / S5 p ow er co n s um p t io n

g e d es ig n f or n ew v er sio n C L K G e n .

g e d es ig n f or n ew v er sio n C L K G e n .ge de s ig n f or ne w v er s io n C L K Ge n.

p or t fo r A v ers io n t o av oid r is k

p or t fo r A v ers io n t o av oid r is kpo rt f or A v er s io n t o a vo id r is k

ef a ult

ef a ulte f au l t

r S I- 1

r S I- 1r S I- 1

re co m m e nd f or u p d a t e

re co m m e nd f or u p d a t er e co m m e nd f or u p d at e

G -S en so r IN T 2 L E D f un ct io n

G -S en so r IN T 2 L E D f un ct io n G - S en so r I N T 2 L E D f un ct io n

C

ti v e

ti v eti v e

se r ve

se r ves er ve

se of + 3V L e rr o e

se of + 3V L e rr o ese o f +3 V L e r ro e

D

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

R e m

R e m ov e U 6 4, C 10 6 4 , C1 0 6 5 ,C 1 0 6 6 , C1 0 6 7 ,R 1 0 15 , R1 01 6, Q 1 63 , R1 01 7.

o ve U 6 4, C 1 06 4 ,C 1 06 5, C 1 06 6 ,C 1 06 7,R 1 01 5 ,R 1 0 16 , Q 16 3 ,R 1 0 17 .

R e mR e m

o ve U 6 4, C 1 06 4 ,C 1 06 5, C 1 06 6 ,C 1 06 7,R 1 01 5 ,R 1 0 16 , Q 16 3 ,R 1 0 17 .o ve U 6 4, C 1 06 4 ,C 1 06 5, C 1 06 6 ,C 1 06 7,R 1 01 5 ,R 1 0 16 , Q 16 3 ,R 1 0 17 .

I n

I n st a ll L 1 9 , re m ov e L 9 5

s ta ll L 1 9, r e mo ve L 9 5

I nI n

s ta ll L 1 9, r e mo ve L 9 5s t al l L 19 , re m ov e L 95

I ns ta l l

I ns ta l l R 5 9 3 , r em o v e R 5 9 2

I ns ta l l I n st al l

R e

R e mo ve R 1 2,C 5 4 3, C 5 4 4 , C5 47 ,C 53 6

R eR e

R e se r

R e se r v e R 55 5 f o r + 5V A L W _ L ED , a d d R 5 5 4 f o r + 3V L cl os e t o J P 36 . 1

R e se rR e se r

R e se r ve R 1 0 3 4 c lo se

R e se r ve R 1 0 3 4 c lo se t o J P 36 .4 ,R 1 03 5 c lo se J P3 6. 5, R em o v e R 10 3 6

R e se r ve R 1 0 3 4 c lo seR e se rv e R 1 0 34 cl os e

A d d R 51 3 P H t o +3 V S c lo s e to U 3 3 .1 9

A d d R 51 3 P H t o +3 V S c lo s e to U 3 3 .1 9

A d d R 51 3 P H t o +3 V S c lo s e to U 3 3 .1 9A dd R 5 1 3 P H t o + 3V S cl os e t o U 3 3. 1 9

I ns t

I ns t a ll R 3 56 ( 1 0 K _ 04 02 )

I ns tI ns t

C ha ng e R 5 20 f ro m 47 K _ 0 4 02 t o 1 0K _ 0

C ha ng e R 5 20 f ro m 47 K _ 0 4 02 t o 1 0K _ 04 02

C ha ng e R 5 20 f ro m 47 K _ 0 4 02 t o 1 0K _ 0C h a n g e R 5 2 0 f ro m 4 7K _ 04 02 t o 10 K _ 0

D e l S

D e l S W 3

D e l SD e l S

C h a n g e

C h a n g e R 52 8 ,R 5 2 9 pi n 2 c o nn ec ti o n f ro m + 5 V L t o + 3 V L

C h a n g e C h a n ge

A dd R 5 9 c l os e t o Q 2

A dd R 5 9 c l os e t o Q 2

A dd R 5 9 c l os e t o Q 2A d d R 5 9 c lo se to Q 2

A d d

A d d R 3 08 2 2_ 04 02 f or U 1 5. E 2 2 c l os e t o R 3 6 2 .1 , r em o ve R 3 01

A d dA d d

A dd R 5 4(0 _0 40 2) c lo se to U 2

A dd R 5 4(0 _0 40 2) c lo se to U 2 1 .6

A dd R 5 4(0 _0 40 2) c lo se to U 2A d d R 5 4( 0_ 04 02 ) c lo se to U 2

A dd T 2 1 c lo s e to U 2 7 .

A dd T 2 1 c lo s e to U 2 7 . 45

A dd T 2 1 c lo s e to U 2 7 .A d d T 2 1 c lo s e t o U 27 .

U p da t e U 3 (S A 00 00 1Z G 00 -- > SA 0 0 00 1 Z G 20 ) ;U 1 0 ( SA 0 0 00

U p da t e U 3 (S A 00 00 1Z G 00 -- > SA 0 0 00 1 Z G 20 ) ;U 1 0 ( SA 0 0 00 1 Z 30 0- ->

U p da t e U 3 (S A 00 00 1Z G 00 -- > SA 0 0 00 1 Z G 20 ) ;U 1 0 ( SA 0 0 00U pd a te U 3( S A0 00 0 1 ZG 0 0- -> SA 0 00 0 1 Z G 2 0 ); U 1 0 (S A 0 00 0

S A 00 0 01 Z 31 0 ); U 1 5 (S A 0 00 0 1 S5 1 0- -> S A 0

S A 00 0 01 Z 31 0 ); U 1 5 (S A 0 00 0 1 S5 1 0- -> S A 0 0 00 1 S5 6 0 )

S A 00 0 01 Z 31 0 ); U 1 5 (S A 0 00 0 1 S5 1 0- -> S A 0S A 0 0 00 1Z 3 10 ) ;U 1 5 ( SA 0 0 00 1 S 51 0 -- > SA 0

C ha ng e R 3 89 f ro m 06 03 t o

C ha ng e R 3 89 f ro m 06 03 t o 0 40 2

C ha ng e R 3 89 f ro m 06 03 t oC ha ng e R 3 89 f ro m 06 03 t o

C ha ng e C 5 6 7 , C5 68 f ro m 10 U _ 0 8 0 5 t o 1 U _ 0

C ha ng e C 5 6 7 , C5 68 f ro m 10 U _ 0 8 0 5 t o 1 U _ 0 8 0 5

C ha ng e C 5 6 7 , C5 68 f ro m 10 U _ 0 8 0 5 t o 1 U _ 0C ha ng e C 5 6 7 , C5 68 f ro m 10 U _ 0 8 0 5 t o 1 U _ 0

C h a n g e U 27 .4

C h a n g e U 27 .4 8 /4 5 p in c o nn ec t io n

C h a n g e U 27 .4C h an ge U 2 7 .4

R em o v

R em o v e R 2 35 ; A d d Q 8 5 , R 6 4 5 , Q 3 4

R em o vR em o v

R em o v e

R em o v e R 1 02 ; Ad d R 1 0 1

R em o v eR e m o v e

R em o v e

R em o v e R 10 45

R em o v e R e m o v e

R em o v e

R em o v e R 56 3

R em o v e R e m o v e

R em o v e

R em o v e R 81 ,R 3 69

R em o v e R e m o v e

R em o v e

R em o v e R 22 1

R em o v e R e m o v e

R em o v e

R em o v e R 10 41

R em o v e R e m o v e

c ha n g e Y

c ha n g e Y 3 f ro m S J 10 0 00 1 U 00 t o S J 10 00 06 6 00 w i th 1 0 PP M

c ha n g e Yc h an g e Y

C ha ng e R 3 1 2 f ro m 0 _ 0 40 2 t o 3 3 _0 4 0 2; C h a n

C ha ng e R 3 1 2 f ro m 0 _ 0 40 2 t o 3 3 _0 4 0 2; C h a n ge R 3 56 fro m 1 0 K _0 4 02

C ha ng e R 3 1 2 f ro m 0 _ 0 40 2 t o 3 3 _0 4 0 2; C h a nC ha ng e R 3 1 2 f ro m 0 _ 0 40 2 t o 3 3 _0 4 0 2; C h a n

to 2 . 2K _ 0 4 02 ; I ns t al l

to 2 . 2K _ 0 4 02 ; I ns t al l C 2 3 as 0 .1 U F _0 4 02

to 2 . 2K _ 0 4 02 ; I ns t al l to 2. 2 K_ 04 02 ; I n st a ll

CCCC h an g e Y 7 fr om S J 1 0 0 00 1V 0 0 t o S J1 32 P7 K 22 0

A d d

A d d R 2 21 ; R e m o v e U 3 0, R 2 26 ,R 2 2 8 , C 4 89

A d dA d d

R em o v e

R em o v e Q 15 6

R em o v e R e m o v e

R 59 3, r em o ve R5 92

R 59 3, r em o ve R5 92R 59 3, r em o ve R 5 92

m ov e R1 2, C 5 4 3 , C 5 44 ,C 54 7, C 5 3 6

m ov e R1 2, C 5 4 3 , C 5 44 ,C 54 7, C 5 3 6m o ve R 1 2, C 5 4 3 , C5 44 ,C 54 7, C 5 3 6

v e R 55 5 f or + 5 V A L W _L E D , ad d R 5 54 f or + 3V L c lo s e to J P 36 .1

v e R 55 5 f or + 5 V A L W _L E D , ad d R 5 54 f or + 3V L c lo s e to J P 36 .1v e R 55 5 f or + 5 V A L W _L E D , ad d R 5 54 f or + 3V L c lo s e to J P 36 .1

a l l R3 56 ( 10 K_ 04 02 )

a l l R3 56 ( 10 K_ 04 02 )al l R 3 56 ( 1 0 K _ 04 02 )

W 3

W 3W 3

R 52 8, R 5 29 p in 2 c on n ec ti on f ro m + 5 V L t o + 3 V L

R 52 8, R 5 29 p in 2 c on n ec ti on f ro m + 5 V L t o + 3 V LR 52 8, R 5 29 p in 2 c on n ec ti on f ro m + 5 V L t o + 3 V L

R 3 0 8 2 2_ 0 4 02 f or U 1 5. E 2 2 c lo se t o R3 62 .1 , r e m o ve R 3 01

R 3 0 8 2 2_ 0 4 02 f or U 1 5. E 2 2 c lo se t o R3 62 .1 , r e m o ve R 3 01 R 3 0 8 2 2_ 0 4 02 f or U 1 5. E 2 2 c lo se t o R3 62 .1 , r e m o ve R 3 01

e R 2 35 ; Ad d Q 8 5 , R 6 4 5 , Q 3 4

e R 2 35 ; Ad d Q 8 5 , R 6 4 5 , Q 3 4e R 2 35 ; Ad d Q 8 5 , R 6 4 5 , Q 3 4

R 1 0 2 ; A d d R 1 01

R 1 0 2 ; A d d R 1 01 R 1 02 ; Ad d R 1 01

R 10 45

R 10 45R 10 45

R 56 3

R 56 3R 56 3

R 81 ,R 3 69

R 81 ,R 3 69R 8 1, R 3 6 9

R 22 1

R 22 1R 22 1

R 10 41

R 10 41R 10 41

3 f ro m S J 10 0 00 1U 0 0 t o S J 10 00 06 60 0 w i th 1 0 P P M

3 f ro m S J 10 0 00 1U 0 0 t o S J 10 00 06 60 0 w i th 1 0 P P M3 f ro m S J 10 0 00 1 U 00 t o S J 10 00 06 6 00 w i th 1 0 PP M

h an g e Y 7 fr om S J 1 0 0 00 1V 0 0 t o S J1 32 P7 K 22 0

h an g e Y 7 fr om S J 1 0 0 00 1V 0 0 t o S J1 32 P7 K 22 0h a n g e Y 7 fr om S J 1 00 00 1V 0 0 t o S J1 32 P7 K 2 2 0

R 2 2 1 ; R em ov e U 30 ,R 2 26 ,R 2 2 8, C 4 8 9

R 2 2 1 ; R em ov e U 30 ,R 2 26 ,R 2 2 8, C 4 8 9 R 2 21 ; Re mo ve U 3 0 , R 2 26 ,R 2 28 ,C 48 9

Q 15 6

Q 15 6Q 15 6

t o J P 3 6. 4 ,R 1 03 5 c lo se J P 36 . 5, R em o v e R 10 3 6

t o J P 3 6. 4 ,R 1 03 5 c lo se J P 36 . 5, R em o v e R 10 3 6 t o J P 36 .4 ,R 1 03 5 c lo se J P3 6.5 ,R e m ov e R 1 0 36

4 0 2

4 0 24 0 2

1 . 6

1 . 61. 6

4 5

4 54 5

0 00 1 S5 60 )

0 00 1 S5 60 )00 01 S 56 0 )

0 4 02

0 4 02 0 4 02

8 0 5

8 0 58 0 5

8 /4 5 p in c on n ec ti o n

8 /4 5 p in c on n ec ti o n8/ 45 p in c o nn ec t io n

g e R3 5 6 fr om 1 0 K_ 0 40 2

C 23 a s 0 .1 U F_ 0 40 2

C 23 a s 0 .1 U F_ 0 40 2C 2 3 as 0 .1 U F _0 4 02

g e R3 5 6 fr om 1 0 K_ 0 40 2g e R3 5 6 fr om 10 K _0 40 2

1 Z3 0 0- ->

1 Z3 0 0- ->1Z 30 0- ->

E

R ev .

R ev .P a

R ev .R e v.

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

0 .2

0 .2

0 .20 .2

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

49 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a ge #

I t emI te m

1 1

2 2

g e #

P aP a

g e #g e#

TTTT it le

it le

it leit le

01 19 SB HW
02

19

03

23

04

29 Amplifier

05

23

06

31 Finger Printer

07

32 BIOS ROM

08

32

09

33

11

34

12

35 Docking

13

35 MDC

15

34

161734

34

18

SB
SB

Speaker

BIOS ROM
EC
T/P ON/OFF LED

Switch board
Switch board
Switch board
EC

14 HW 0.319 SB

20

Webcam and Digital MIC

22 HW21 SB
25 Realtek22 LAN
31 Layout23 USB port
19 EMI

24 SB

3 3

25 19 EMI

SB
26 20 SB EMI
27 21 SB DFB
28 25 LAN DFB
29 26 WWAN EMI
30 33 EC HW
31 35 M/B ME
32 36 DC-DC HW

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

12/2 6

12/2 6

12/2 6

12/2 6

12/2 6

12/2 6

12/2 6

12/2 6

12/2 6

12/2 6

12/2 6

12/2 6

01/0 3

01/0 3

01/0 3 Opti on Cy press and EN E Cap. board.

01/0 7

01/0 8 Add pul l hig h res istor R1064.

u e stu e st

O w n

O w n e r

O w nO w n

HW
HW
HW
HW
HW
HW
HW
HW
EC
HW
ME
HW
HW
HW
Power 0.333

HW17 0.3

01/0 8

01/0 8 Cha ge part numbe r fro m SA0 00026 Q00 to SA 00002 6Q10

01/0 8 Swap D 11, D1 2, L5 1 pin defin e per layo ut re quest.

01/0 9 Add re serve cap. C1085 ~C1087.

01/0 9

01/0 9

01/0 9

01/0 9

01/0 9

01/0 9

01/0 9

01/0 9

33 34 Switch board HW
34 33 Keyboard connector
35 34 Lid switch connector

4 4

36 34 Switch board
36 06 HDT debug port

A

01/1 0

01/1 0

01/1 0

01/1 4

DFB
DFB
EMI
AMD

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

Speake r ri ght and left channel reverse. Rever se JP 20 pin define.

Common design.

ME change stan d off.

Useless

Useless

B

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

S o

S o lu tio n D es cr ip tio n

S oS o

Remov e R30 3 fro m PCIC LK3 a nd add R301 as 0 ohm.

Add R3 03 an d conn ect t o CLK_ PCI_ ISO2.

Chage net n ame to PCI_CLK3.

Change valu e fro m 4.7uF to 1uF.

Delet e R622

Reser ve R221

Stu ff U30 , R 228, R226 , C48 9. Ch ange po wer f rom + 3VALW to +3 VL

Add pul l dow n resi stor R106 3.

Rever se TP on/off LED

Cha nge R5 72 to 22 ohm an d R56 6 to 2K ohm

Chan ge PC B Foot print from 3P3 to 4P 0

Delet e R55 6, R5 57.

R103 6

Con nec t R 1046 to J P36.3 and c onnec t R10 47 t o JP3 6.9

Conne ct VFI X_EN to EC pin 110.

Remov e reserve circuit for Webcam and Digital MIC.01/0 8

Cha nge L61, L63, L66, L60, L67, L68, L69 t o 0 o hm res istor .
Cha nge C5 28 , C543 , C56 6, C50 4 to MLCC t pye.
Change C552 from 22uF to 4. 7uF.

Fin e-t une R 302, R303, R308 from 22 oh m to 33 oh m.

Add re serve cap. C1088 ~C1091

Y4 Cha nge Fo otpri nt to the same as Y2.

Change Y5 Fo otpri nt to the same as Y2.

Add C7 38, C739, C740 , C75 0, C75 1 as 39pF

Conne ct AC_ LED# to PQ3

Add scr ew hole.

Remov e +1.2 V and +3V circuit.

Add R1 065 an d R 10 66 for O PP po wer b utton board01/1 0

Change Keybo ard co nnec tor same as JBK00.

Change Lid s witch conn ector type.

Cha nge R1 048 and R 1049 from 0 ohm to be ad.

Stu ff R26 , R28 an d R41 .

2007/08/02 2008/08/02

C

Compal Secret Data

D

lu ti o n D e sc ri p t io n

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

Deciphered Date

D

E

R ev .

R ev .P a

R ev .R ev .

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

0.3

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

50 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a ge #

I t emI te m

1 1

g e #

P aP a

g e #g e#

TTTT it le

it le

it leit le

37 25 LAN
38 33 EC
39 11 NB
40 17 LVDS
41 15 Clock GEN.
42 15 Clock GEN.

2 2

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

01/1 4

01/1 4

01/1 5

01/1 5

01/1 5

01/1 5

u e stu e st

O w n

O w n e r

O w nO w n

HW
HW
HW
HW
HW

Vendor

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

810 2E (10 /100M 48 pi n) can not suppor t DSM funct ion.

810 2E (10 /100M 48 pi n) can not suppor t DSM funct ion.

No sup port daul channel panel. Remove L VDS s ignal of Channel B.

No sup port daul channel panel.

To slove noise issue.

Clock Gen. spec. update Cha nge R3 79 to 15 8 oh m and R380 to 9 0.9 oh m.

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

C

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

Reser ve Q1 056, Q1057 , C10 77 an d Q14 4. Cha nge P JP605 to R 1067.

Reser ve R544

Remov e LVDS signa l of Channel B (remove C1061~C1063)

Cha gne C1 074~ C1076 to 1 2pF

D

E

R ev .

R ev .P a

R ev .R ev .

0.3

0.3

0.3

0.3

0.3

0.3

3 3

4 4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

51 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a ge #

I t emI te m

1 1

g e #

P aP a

g e #g e#

TTTT it le

it le

it leit le

01 25 LAN

S/W board connector

3402

03 06 CPU

06 CPU

04

06 CPU

05

06 CPU

06

07 CPU

07

12 NB

08

12 NB

09

13 NB

10

13 NB

11

24 Multibay connector

12

2 2

27 Card Reader

13

27

14
15
16
17
18

31 BT
31 BT
33 EC
33 EC

Card Reader

19 34 Debug SW
20 34 TP LED
21 11 NB
22 11 NB

3 3

23 19 SB
24 21 SB
25 32 SPI BIOS
26 34 WL/BT LED control
27 33 EC
28 35 Screw hole
29 34
30 34
31
32 11
33 16

4 4

35 34

S/W board connector

S/W board connector

S/W board connector

34

CRT connector

1634

CRT connector

Lid switch connector

NB

A

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

02/1 2

02/1 2 Reser ve R558.

02/1 2

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5

02/1 5 Remov e SW2.

02/1 5 Add D1 9 for PR sk u.

02/1 8 Cha nge R371 from 10K t o 300 ohm.

02/1 8 Add pul l lo w resi stor R1072.

02/1 8 Reser ve C1 085 a nd R303.

02/1 8 To solv e can 't powe r on when first plug i n AC adapter. Add R1 071 an d D56 to co nnect to A C_IN.

02/1 8 Rem ove U3 0, C4 89, R 226, and R2 28. S tuff R 221.

02/1 8 Modify circuit WLAN/WWAN/BT LED control.

02/1 8 Cha nge R51 4 and R515 from 10K t o 4.7 K ohm.

02/1 9

02/1 9

02/1 9

02/2 2

02/2 2

02/2 2

02/2 2

02/2 2

u e stu e st

O w n

O w n e r

O w nO w n

HW
HW
HW
HW
HW
HW
HW 0.4
HW 0.4
HW 0.4
HW 0.4
HW 0.4
ME 0.4
HW 0.4
HW 0.4
ME 0.4
HW 0.4
HW 0.4
HW 0.4
HW 0.4
ME 0.4
HW 0.4
HW 0.4
HW 0.4
HW 0.4
HW 0.4
HW 0.4
HW 0.4
ME
ENE
ENE
HW
HW
HW
HW
HW

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

For E SD pro tect.

To avo id ca p. sen sor board abnormal.

Follow Trinity design.

Change Card Reade r LED active status. Reserve Q53 and R4 54, a dd R10 70.

Change Card Reade r LED active status.

Savin g Powe r con sumption. Change BT power sour ce fr om +3 VALW t o +3VS.

To sol ve ca n't po wer o n whe n fir st plu g in A C adapter. Chang e R 1040 from 100K t o 10K ohm a nd co nnect to +3 VL_EC .

Follow Trinity design.

For ENE cap. board. Add LDO cir cuit (U65, R1073 , C10 97,C1099, J2).

For ENE cap. board.

For c ap. board.

To splve CRT rising/falling fail issue.

To splve CRT rising/falling fail issue.

To splve CRT rising/falling fail issue.

To sol ve sh ort i ssue for lid switch board. Move C1100 and C 1101 from lid sw tich board to M/B

B

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

Reserve D55.

Reser ve R59.

Change CPU S M BUS from EC2 to EC1.

Reserve C16.

Cha nge R1 8 an d R19 from 3 30 t o 2.2 K ohm.Follow Trinity design.

Reserve C54.

Remov e L96.

Cha nge L12 , L13 from bead t o 0 o hm.

Cha nge L1 6, L1 8, L1 9, L2 2 fro m bead to 0 ohm.

Remov e L95.

Change JP10 Foot print.

Reser ve R1 12 an d add pu ll l ow resistor R1069.

Change JP32 Foot print and r everse pin define.

Remov e JP3 4 and reser ve R1 068 for EC debug.

Add H57 .To slo ve TP on/o ff butt on fe eling no go od whe n pre ss.

Cha nge R 554 pi n 1 p ower p lan fr om +3 VL to +3VL_ CAP.

Add C1 098.

Reser ve R6 2, R6 3, R64.

Cha nge R2 11 , R2 14 an d R21 7 fro m 150 ohm t o 75 ohm

Cha nge C4 72, C 476, C858 from 2 2pF t o 6pF.

2007/08/02 2008/08/02

C

Compal Secret Data

Deciphered Date

D

D

E

R ev .

R ev .P a

R ev .R ev .

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

Title

Size Doc ument Number Re v

Cus tom

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

52 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a ge #

P aP a

36 25
37 35
38 34
39 34
40 33
41 33
42 36
43 31
44 15
45 16
46 17
47 32
48 17
49 34
50 06
51 34
52 11
53 31
54 22
55 13
56 35
57 11
58 11
59 33
60 06
61 19
62 20
63 21
64 21
65 31
66 17
67 15
68 20
67 15
67 15

g e #

g e #g e#

TTTT it le

it le

it leit le

LAN

Screw hole

S/W board connector

S/W board connector

DC/DC

USB connector

Clock GEN.

CRT Connector

LCD Connector

Debug connector

WEBcam LDO

Lid switch connector

S/W board connector

USB connector

Docking connector

eSATA connector

LCDVCC circuit

Clock GEN.

WWAN connector

WWAN/WLAN

EC

EC

CPU

NB

SB

NB

NB

NB

EC

CPU

SB

SB

SB

SB

SB

I t emI te m

1 1

2 2

3 3

4 4

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

02/2 2

02/2 2

02/2 2

02/2 2

02/2 2

02/2 2

02/2 5

02/2 5

02/2 5

u e stu e st

O w n

O w n e r

O w nO w n

DFB
DFB
EMI
EMI
EMI
EMI
EMI
EMI
EMI
EMI

02/2 5

02/2 6

02/2 6

02/2 6

02/2 7

03/0 3

03/0 3

03/0 3

03/0 3

03/0 3

03/0 3

03/0 3

03/0 3

03/0 3

03/0 4

03/0 4

03/0 5

03/0 6

03/0 6

03/0 6

03/0 6

03/0 6

03/0 6

03/0 6

03/0 6

EMI
EMI
HW
HW

POWER

EMI
EMI
EMI
HW
HW
DFB
AMD
AMD
AMD
AMD
AMD
EMI
AMD
AMD
AMD
HW
HW
HW
HW
HW

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

To sol ve ki nk pin to i nterfere with PCB. Update JRJ4 5 PCB Footp rint.

To sol ve EM I issue for ENE cap. board.

To sol ve EM I issue for ENE cap. board.

To sol ve EM I issue for ENE cap. board.

For EMI request.

For EMI request.

For EMI request.

For EMI request. Add C1 108.

For EMI request. Add C1 118.

To re duce p ower consu mptio n in S3 mode. Add PJ P6 to co nne ct to +5VS . Stuf f R10 13 an d rese rve R 1014 .

For EMI request.

For EMI request. Change C112 1 (0.1uF)

To sup port VariB right feature.

To sup port VariB right feature.

To sol ve ca n not power on w hen u se single core CPU.

For EMI request

For eSATA GEN1 fail issue. Chan ge C52 0 and C521 from 0.01u F to 1000p F.

For eSATA GEN1 fail issue. Chan ge C79 2 and C793 from 0.01u F to 1000p F.

To sol ve LC D powe r up sequence fail. Cha nge R2 25 fr om 47 0 ohm to 22 0 ohm .

For IDT CLOCK GEN.

To avo id CMO S dat a los e when shut down s uddenly.

To sup port wake o n WWAN feature.

To avo id le akage power from SB.

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

C

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

Change H53 a nd H54 from non P TH to PTH h ole.

Cha nge R1 048 and R 1049 from bead t o 0 oh m.

Reser ve R1 074/C 1102 for E SB_CL K1 an d R107 5/C11 03 for ESB_DAT1.

Add R1 076 , C 1104 and R 1077 .

Add C1 105.

Add C1 110~C 1117.

Add C1 109.

Add C1 106.

Add C1 107.02/2 5 Fo r EMI request.

Con nec t JP 40 pi n 4 t o +3VA LW.

Change net name ENTRIP2 to EN0.

Change R558 to C 1119 (0.1u F)

Change C112 0 (0.1uF)For EMI request.

Cha nge L6 0, L61, L63, L66, L67, L68, L69 f rom 0 ohm t o bead .

Remov e L20 , L21 and u se PJ P604 to replace.

Change JDOC K conn ecto r Footprint.

Add D58 and c onne ct to INV_P WM.

Change backl ight infor m sign al (R 70, R1072) from LVDS_BLON to LVDS_ENA_BL.To sup port VariB right feature.

Change JDOC K conn ecto r Footprint.

Reser ve R1 75, R 814, C939, Q127 and Q 129.

Change net name f rom H_ PWRGD to H_PWRGD_SB.

Add SS C cir cuit (U66, R108 0, R1 081, R1082 , R10 83, C1 122) for HDA_BITCLK.

Chan ge C52 0 and C521 from 0.01u F to 1000p F.For eSATA GEN1 fail issue.

Add C1 123.

Add D5 8 an d conn ect t o 3/5 V_OK.

Add pow er on /off c ontr ol ci rcuit (Q16 7, R1 087).

Add D5 9 and D60.

D

E

R ev .

R ev .P a

R ev .R ev .

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

53 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a

P a ge #

P aP a

68 20
69 11
70 25
71 33
72 18
73 18

g e #

g e #g e#

TTTT it le

it le

it leit le

SB

NB

LAN

LAN

HDMI

HDMI

I t emI te m

1 1

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

03/0 6

03/0 6

03/0 6

03/0 6

03/0 7

03/0 7

u e stu e st

O w n

O w n e r

O w nO w n

HW
HW
HW
HW
HW
HW

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

To sol ve ca n not power on i f use CPU with single core Stu ff R83 .

To pas s HDMI test.

For EMI request.

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

C

D

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

Add R1 085 and R108 6.To sup port VariB right feature.

Stu ff Q 144, R105 6, R1 057, C1077 and r eser ve R10 67.To re duce p ower consu mptio n in S3 mode.

Stu ff R54 4.To re duce p ower consu mptio n in S3 mode.

Chagng e R315 , R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.

Reserv e 0 ohm and s tuff common choke.

E

R ev .

R ev .

R ev .R ev .

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

2 2

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

3 3

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

4 4

0.4

0.4

0.4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

54 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a

P a ge #

P aP a

68 20
69 11
70 25
71 33
72 18

g e #

g e #g e#

TTTT it le

it le

it leit le

SB

NB

LAN

LAN

HDMI

I t emI te m

1 1

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

03/0 6

03/0 6

03/0 6

03/0 6

03/0 7

u e stu e st

O w n

O w n e r

O w nO w n

HW
HW
HW
HW
HW

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

To sol ve ca n not power on i f use CPU with single core Stu ff R83 .

To pas s HDMI test.

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

C

D

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

Add R1 085 and R108 6.To sup port VariB right feature.

Stu ff Q 144, R105 6, R1 057, C1077 and r eser ve R10 67.To re duce p ower consu mptio n in S3 mode.

Stu ff R54 4.To re duce p ower consu mptio n in S3 mode.

Chagng e R315 , R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.

E

R ev .

R ev .

R ev .R ev .

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

2 2

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

3 3

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

4 4

0.4

0.4

0.4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

55 56Monday, March 16, 2009

E

1.C

A

V e rsion C h a n g e L ist

V e rsion C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it

V e rsion C h a n g e L istV e rsion C h a n g e L ist

I t em

I t em I s su e D

P a

P a ge #

I t emI te m

1 1

g e #

P aP a

g e #g e#

68 20
69 11
70 25
71 33
72 18

33

73 HW

TTTT it le

it le

it leit le

SB

NB

LAN

LAN

HDMI

EC

( P . I . R . L ist ) for H W C ircu it

( P . I . R . L ist ) for H W C ircu it ( P . I . R . L ist ) for H W C ircu it

R eq

R eq u e st

u e st

R eqR eq

D a t e

D a t eD a te

03/0 6

03/0 6

03/0 6

03/0 6

03/0 7

09/1 0

u e stu e st

O w n

O w n e r

O w nO w n

HW
HW
HW
HW
HW

B

I s su e D e sc r ip ti o n

I s su e DI ss ue D

e r

e re r

To sol ve ca n not power on i f use CPU with single core Stu ff R83 .

To pas s HDMI test.

Avoid DOCK_ VOL_UP # and DOCK_VOL_down# folating

e s cri p ti o nD a t e

e s cri p ti o ne sc ri pt io n

C

D

S o

S o lu tio n D es cr ip tio n

lu ti o n D e sc ri p t io n

S oS o

lu ti o n D e sc ri p t io nlu ti o n D e sc ri p t io n

Add R1 085 and R108 6.To sup port VariB right feature.

Stu ff Q 144, R105 6, R1 057, C1077 and r eser ve R10 67.To re duce p ower consu mptio n in S3 mode.

Stu ff R54 4.To re duce p ower consu mptio n in S3 mode.

Chagng e R315 , R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.

R589 R 590 use 10k ohm pull high

E

R ev .

R ev .

R ev .R ev .

0.4

0.4

0.4

0.4

0.4

1.0

0.4

0.4

0.4

0.4

2 2

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

3 3

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

4 4

0.4

0.4

0.4

Secur ity Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Doc ument Number Re v

Cus tom

D

Date: Sheet of

Compal Electronics, Inc.

HW Changed-List History-2

LA-4117P

56 56Monday, March 16, 2009

E

1.C