HP IA-32 visualize fx5, IA-32 visualize fx10 Supplementary Manual
hp IA-32
visualize
fx5and fx
10
Windows
graphics
accelerators
Leadership Graphics Technology
HP set the standard for Windows NT®3D graphics performance and functionality
with the introduction of the hpvisualize fx4graphics accelerator in 1997. The subsequent introduction of the hpvisualize fx+family for Windows workstations provided
further gains in performance at a wide range of price points.
white
paper
Now, HP continues to evolve its hpvisualize family of graphics adapters with the
introduction of the hpvisualize fx5and hpvisualize fx
hpfx5and fx
typically found on much more expensive high-end graphics workstations. The hardware is designed for Windows NT®and Windows 2000 Professional
support for OpenGL 1.1, GDI, DirectDraw, and Direct3D.
Significant features of the hpfx5and fx
• 3D and depth texture mapping for volume visualization and real-time shadows.
• Texture maps up to 16384 × 16384 in size.
• A hardware-accelerated accumulation buffer for full scene antialiasing and
motion blur effects.
• Parallel visibility testing of bounding boxes for fast occlusion culling.
• Support for multiple display syncs for "cave" and "cove" displays.
• Up to 64MB of fully configurable shared framebuffer/texture memory. The
flexible shared memory design allows the user to balance texture map storage
requirements with pixel depth and desktop size.
• Identical software interfaces and device drivers for both the hpfx5and fx
graphics accelerators to reduce ISV certification expenses.
• Designed with the entire computer system in mind to maximize high-end 3D
application performance.
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feature industry-leading application performance, with a feature set
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:
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graphics accelerators. The
®
, providing full
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A Detailed Look at the Architecture and Features
Host interface chip 1 1
Geometry engines 3 6
Rasterizer/texture/display chip 1 1
Shared framebuffer/texture memory 64MB SDR 64MB SDR
Software interface/device driver Identical for both devices
Architectural Summary
Both the hpfx5and hpfx
memory to support an identical list of pixel formats. The hpfx
geometry performance of the hpfx5.
A detailed look at the individual components of the hpfx5and fx
Host Interface Chip
Communication between the host computer system and the graphics device is via a
host interface chip residing on the hpfx5and fx
In order to operate at peak performance levels, the hpfx5and fx
AGP 2X DMA (Direct Memory Access) to transfer geometric, pixel, and texture data
from the application to the graphics device. Unlike other data transfer methods,
DMA is the only method which utilizes 100% of the available AGP bus cycles.
Using AGP 2X DMA, data is transferred to the graphics device at 400MB/sec.
Assuming an average triangle size of 29 bytes1, this is sufficient bandwidth to transmit over 14 million triangles/sec to the graphics device.
5
hp fx
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graphics accelerators contain sufficient frame-buffer
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.
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hp fx
provides twice the
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follows.
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support 133MHz
AGP 2X DMA is in perfect balance with the hp visualize personal workstation. The
state of the art 133MHz front side bus provides a gross bandwidth of 1.06GB/sec.
Since real applications simultaneously access their own internal data structures
while generating graphics data, the maximum sustainable geometry data bandwidth
is only half of that, or 530MB/sec. Inherent front side bus latencies and application
overhead further limit the net geometry bandwidth to 400MB/sec or less. Any excess
bandwidth to the graphics device would be wasted, and any less would create a bottleneck.
The hpfx5and fx
for real applications, which can not afford to sit idle while data is being transmitted to
the graphics device. Once the device driver initiates a DMA data transfer, the host
interface chip retrieves the data from main memory asynchronously, freeing the host
CPU for other tasks. Compared to PIO (Programmed I/O) and AGP 4X with Fast
Writes, this results in vastly improved application performance.
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A triangle strip primitive containing 10 triangles will have four bytes of overhead, followed by 12 24-byte vertices, for a
total of 292 bytes. This is an average of 29 bytes/triangle.
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graphics accelerators are designed to provide peak performance
When comparing AGP 2X DMA to AGP 4X with Fast Writes, keep the following in
mind:
• AGP 4X with Fast Writes occupies the CPU while writing data to the graphics
device, preventing your application from doing other useful work. AGP 2X DMA
frees the host CPU while writing data to the graphics device, resulting in superior
application performance.
• Claims that 900MB/sec bandwidth is required for today's graphics applications is
simply wrong. In fact, 400MB/sec is sufficient to transmit over 14 million
triangles/sec to the graphics device. Furthermore, a 900MB/sec data transfer rate is
unattainable by real applications on systems with a 133MHz front side bus. AGP 4X
with Fast Writes does nothing to alleviate this bottleneck.
• AGP 2X DMA is a reliable data transfer mechanism that is known to produce excellent application performance. AGP 4X with Fast Writes provides no performance
benefit over AGP 2X DMA, and its complexity compromises system reliability.
An additional DMA engine in the host interface chip uses 66MHz PCI protocol to
transfer data from the graphics device to main memory. This is especially useful for
reading the contents of the framebuffer, a critical operation for many Digital Content
Creation, Video Editing, and Visualization applications.
The host interface chip also supports fast hardware state switching for acceleration of
multiple concurrent rendering applications. Applications that use multiple OpenGL
rendering contexts will also benefit from this feature. An application that caches state
for different rendering scenarios in multiple OpenGL contexts will be able to rapidly
switch between them.
Geometry Engines
The geometry engines perform geometric transformations, lighting, model clipping,
and other vertex operations on incoming geometric data. This frees the host CPU,
leaving more processing power available for application work.
The geometry engines use floating point units based on hpPA-RISC processor tech-
nology to achieve maximum floating-point performance.
There are three geometry engines per geometry accelerator chip. The hpfx5has a
single geometry accelerator chip containing three full geometry engines, while the hp
fx
Each hardware geometry engine supports a rich geometry feature set, including:
• Lighting and shading for up to eight separate OpenGL light sources
• All OpenGL primitive types
• Transformations
• View volume and model space clipping
• Material properties for accelerated rendering of lit surfaces
• Texture coordinate generation, useful in Scientific Visualization applications
• Environment mapping for fast realistic surface reflections
• Texture coordinate generation, useful in Scientific Visualization applications
• Environment mapping for fast realistic surface reflections
• Second generation hardware occlusion culling implementing faster rejection of
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has two chips for a total of six full geometry engines.
invisible geometry based on its bounding volume.
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