Chip Size:2980 x 620 µm (74 x 24.4 mils)
Chip Size Tolerance:± 10 µm (± 0.4 mils)
Chip Thickness:127 ± 15 µm (5.0 ± 0.6 mils)
Pad Dimensions:80 x 80 µm (3.1 x 3.1 mils), or larger
Description
The HMMC-5023 MMIC is a highgain low-noise amplifier (LNA)
that operates from 21 GHz to over
30 GHz. By eliminating the
complex tuning and assembly
processes typically required by
hybrid (discrete-FET) amplifiers,
the HMMC-5023 is a cost-effective
alternative in 21.2 – 23.6 GHz and
24.5 – 26.5 GHz communications
receivers. The device has good
input and output match to
50␣ ohms and is unconditionally
stable to more than 40 GHz. The
backside of the chip is both RF
and DC ground. This helps
simplify the assembly process
and reduces assembly related
performance variations and costs.
It is fabricated using a PHEMT
integrated circuit structure that
provides exceptional noise and
gain performance.
Absolute Maximum Ratings
[1]
SymbolParameters/ConditionsUnitsMin.Max.
VD1, V
VD1, V
I
D1
I
D2
P
in
T
ch
T
A
T
STG
T
max
Notes:
1. Absolute maximum rating for continuous operation unless otherwise noted.
2. Operating at this power level for extended (continuous) periods is not
recommended.
3. Refer to DC Specifications/Physical Properties table for derating information.
Drain Supply VoltageV38
D2
Gate Supply VoltageV0.42
D2
Drain Supply CurrentmA35
Drain Supply CurrentmA35
RF Input Power
Operating Channel Temp.
[2]
[3]
dBm15
°C+150
Backside Ambient Temp.°C-55+140
Storage Temperature°C- 65+165
Maximum Assembly Temp.°C+300
5965-5448E
6-34
HMMC-5023 DC Specifications/Physical Properties
[1]
SymbolParameters and Test ConditionsUnitsMin.Typ.Max.
VD1, V
VG1, V
ID1, I
D2
Recommended Drain Supply VoltageV357
D2
Gate Supply VoltageV0.40.8
G2
[VD1 ≤ VD1(max), V
D2
≤ V
(max)]
D2
Input and Output Stage Drain Supply CurrentmA1235
[2]
(VG1 = VG2 = Open, VD1 = VD2 = 5 Volts)
ID1 + I
Total Drain Supply CurrentmA132430
D2
(VG1 = VG2 = Open, VD1 = VD2 = 5 Volts)
θ
ch-bs
Thermal Resistance
(Channel-to-Backside at T
T
ch
Notes:
1. Backside ambient operating temperature T
2. Open circuit voltage at VG1 and VG2 when VD1 and VD2 are 5 volts.
3. Thermal resistance (in °C/Watt) at a channel temperature T (°C) can be estimated using this equation:θ(T) @ 75 x [T(°C)+ 273] / [150°C+ 273].
4. Derate MTTF by a factor of two for every 8°C above T
Channel Temperature
V
= VG2 = Open, V
G1
[3]
= 150° C)
ch
[4]
(T
= 140° C, MTTF = 106 hrs,°C150
A
= VD = 5 Volts)
D1
= 25°C unless otherwise noted.
A
° C/Watt75
.
ch
HMMC-5023 RF Specifications,
T
= 25°C, V
op
Symbol Parameters and Test ConditionsUnitsMin.Typ.Max.Min.Typ.Max.
BWOperating BandwidthGHz21.223.624.526.5
GainSmall Signal GaindB212428172125
∆ GainSmall Signal Gain FlatnessdB±1±1.5
(RLin)
MIN
(RL
out)MIN
IsolationReverse IsolationdB40504048
P
-1dB
P
sat
2nd Harm.Second Harmonic Power LeveldBc-30-30
NF
= V
D1
= 5 V, VG1 = VG2= Open, Z
D2
= 50 Ω, unless otherwise noted
O
21.2–23.6 GHz24.5–26.5 GHz
Minimum Input Return LossdB10121220
Minimum Output Return LossdB810810
Output Power @ 1 dB Gain CompressiondBm1010
Output Power @ 1 dB Gain CompressiondBm1414
(VD = 5 V, VG1= Open, VD2 = 7 V,
VG2 set for ID2 = 35 mA)
Saturated Output PowerdBm1212
(@ 3 dB Gain Compression)
[f = 2 fo, P
(fo) = P
out
-1dB
,
21.2 GHz ≤ fo ≤ 23.6 GHz]
Noise Figure, 22 GHz
Noise Figure, 25 GHz2.83.3
dB
2.53.0
2
6-35
HMMC-5023 Applications
The HMMC-5023 low noise
amplifier (LNA) is designed for
use in digital radio communication systems that operate within
the 21.2 GHz to 23.6 GHz frequency band. High gain and low
noise temperature make it ideally
suited as a front-end gain stage.
The MMIC solution is a cost
effective alternative to hybrid
assemblies.
Biasing and Operation
The HMMC-5023 has four cascaded gain stages as shown in
Figure 1. The first two gain stages
at the input are biased with the
VD1 drain supply. Similarly the
two output stages are biased with
the VD2 supply. Standard LNA
operation is with a single positive
DC drain supply voltage
(VD1=VD2=5 V) using the assembly diagram shown in Figure 9(a).
If desired, the output stage DC
supply voltage (VD2) can be
increased to improve output
power capability while maintaining optimum low noise bias
conditions for the input section.
The output power may also be
adjusted by applying a positive
voltage at VG2 to alter the operating bias point for both output
FETs. Increasing the voltage
applied to VG2 (more positively)
results in a more negative gate-tosource voltage and, therefore,
lower drain current. Figures 9(b)
and 9(c) illustrate how the device
can be assembled for both
independent drain supply operation and for output-stage gate
bias control.
No ground wires are required
since ground connections are
made with plated through-holes
to the backside of the device.
Assembly Techniques
Solder die attach using a fluxless
gold-tin (AuSn) solder preform is
the recommended assembly
method. A conductive epoxy such
as ABLEBOND® 71-1LM1 or
ABLEBOND® 36-2 may also be
used for die attaching provided
the Absolute Maximum Thermal
Ratings are not exceeded. The
device should be attached to an
electrically conductive surface to
complete the DC and RF ground
paths. Ground path inductance
should be minimized (<10 pH) to
assure stable operation. The
backside metallization on the
device is gold.
It is recommended that the RF
input and RF output connections
be made using either 500 line/inch
(or equivalent) gold wire mesh, or
dual 0.7 mil diameter gold wire.
The RF wires should be kept as
short as possible to minimize
inductance. The bias supply wire
can be a 0.7 mil diameter gold
wire attached to either of the
VDD bonding pads.
Thermosonic wedge is the
preferred method for wire
bonding to the gold bond pads.
Mesh wires can be attached using
a 2 mil round tacking tool and a
tool force of approximately
22␣ grams with an ultrasonic
power of roughly 55 dB for a
duration of 76 ± 8 msec. A guided-
wedge at an ultrasonic power
level of 64 dB can be used for the
0.7 mil wire. The recommended
wire bond stage temperature is
150 ± 2 °C.
For more detailed information
see HP application note #999
“GaAs MMIC Assembly and
Handling Guidelines.”
GaAs MMICs are ESD sensitive.
Proper precautions should be used
when handling these devices.
INPUT STAGEOUTPUT STAGE
IN
92 Ω
V
G1
Figure 1. HMMC-5023 Simplified Schematic.
V
D1
92 Ω
6-36
OUT
V
G2
V
D2
HMMC-5023 Typical Performance
V
= VD2 = 5.0 V
D1
30
Gain
26
22
18
14
SMALL-SIGNAL GAIN (dB)
10
19.020.221.422.623.825.0
Figure 2. Gain and Isolation vs.
Frequency.
Spec Range
21.2 – 23.6 GHz
FREQUENCY
Isolation
(GHz)
0
10
20
30
40
50
REVERSE ISOLATION (dB)
60
70
V
= VD2 = 5.0 V
D1
0
Spec Range
5
10
15
20
INPUT RETURN LOSS (dB)
25
19.020.221.422.623.825.0
Figure 3. Input and Output Return
Loss vs. Frequency.
Figure 4. Small-Signal Gain vs.
Frequency and Ambient Temperature
V
= VD2 = 5.0 V
D1
20
21 GHz
25
Gain
20
GAIN (dB)
15
10
24681012
Figure 6. Gain Compression and
Efficiency Characteristics
23 GHz
OUTPUT POWER (dBm)
[2]
η
added
.
[1]
.
20
15
10
5
POWER-ADDED EFFICIENCY (%)
0
0
19.020.221.422.623.825.0
FREQUENCY
(GHz)
Figure 5. Noise Figure vs. Frequency
V
= VD2 = 5.0 V, fO = 22 GHz
D1
0
–15
–30
–45
2nd Harmonic
SMALL HARMONIC DISTORTION (dBc)
–60
24681012
OUTPUT POWER (dBm)
Figure 7. Second Harmonic and Gain
Compression Characteristics
Gain
[2]
.
30
25
20
15
10
Notes:
1. Device tested while mounted on a HP83040 Modular Microcircuit Fixture calibrated at the coaxial
connectors. Test results shown have been degraded by the fixture due to loss and impedance mismatch
errors. The temperature coefficient of the fixture alone is approximately 0.003 dB/°C at 20 GHz.
2. Data obtained from wafer-probed measurements.
3. The temperature coefficient of noise figure was measured for one device mounted on a HP83040 Modular
Microcircuit Fixture. The uncorrected result, <0.014 dB/°C, includes the effects of the fixture.
[2]
.
GAIN (dB)
600
520
RF INPUT
300
80
0
0435755123515551880
Figure 8. HMMC-5023 Bonding Pad Locations. (Dimensions are in micrometers)
6-38
RF OUTPUT
300
105 (VG2 Y-axis)
0
Gold Plated Shim (Optional)
RF
RF
IN
IN
V
D1
V
D2
RF
OUT
V
G2
RF
OUT
≥20 pF Capacitor
≥20 pF Capacitor
To V
DC Power Supply
DD
V
D1
R
R
V
D2
R (typ.) ≥90 Ω
Figure 9a. Single DC Drain Supply.Figure 9b. Assembly for custom biasing of output gain
stages using an external chip resistor.
To V
(Optional)
RF
IN
G2
≥20 pF Capacitor
RF
IN
V
G2
V
RF
OUT
V
V
D1
D2
V
D1
G2
RF
OUT
V
D2
DC Power Supply
≥20 pF Capacitor
To V
DC Power Supply
D1
To VD2
DC Power Supply
Figure 9c. A VG2 DC supply or a resistive divider network can also be used to bias the output stages for custom applications.
Figure 9. HMMC-5023 Assembly Diagram Examples.
This data sheet contains a variety of typical and guaranteed performance data. The
information supplied should not be interpreted as a complete list of circuit specifications. In this data sheet the term typical refers to the 50th percentile performance. For
additional information contact your local HP sales representative.
6-39
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