HP HMMC-2027 Datasheet

Silicon Bipolar RFIC
900 MHz Vector Modulator

Technical Data

HPMX-2003

Features

• 800–1000 MHz Output
Frequency Range

• +6 dBm Peak P

out

• Unbalanced 50 Ω Output

• Internal 90° Phase Shifter

• 5 Volt, 36 mA Bias

•

SO-16 Surface Mount Package

Applications

• Direct Modulator for 900
MHz Cellular Telephone
Handsets, Including GSM,
JDC, and NADC

• Direct Modulator for
900␣ MHz ISM Band Spread­Spectrum Transmitters and
LANs

Functional Block Diagram

Plastic SO-16 Package

Pin Configuration

V

CC

V

CC

GROUND 3

GROUND 4

Q

ref

Q

mod

LO

in

LO

gnd

1

2

5

6

7

8

16 V

CC

15 RF

14 GROUND

13 GROUND

12 I

ref

11 I

mod

10 GROUND

9 DO NOT CONNECT

Description

Hewlett Packard’s HPMX-2003 is a
Silicon RFIC direct conversion
vector modulator designed for use
at output frequencies between
800␣ MHz and 1 GHz. Housed in a
SO-16 surface mount plastic pack­age, the IC contains two matched
Gilbert cell mixers, an RC phase
shifter, a summer, and an output
amplifier complete with 50 Ω

L

out

impedance match and DC block.

This device is suitable for use in
direct and offset-loop modulated
portable and mobile telephone
handsets for cellular systems such
as GSM, North American Digital
Cellular and Japan Digital Cellu­lar. It can also be used in digital
transmitters operating in the
900 MHz ISM (Industrial-Scien­tific-Medical) band, including use
in Local Area Networks (LANs).

I

mod

I

ref

LO +
LO –

Q

ref

Q

mod

5965-9103E

The HPMX-2003 is fabricated with
Hewlett-Packard’s 25 GHz
ISOSAT-II process, which

0°

I MIXER

V

CC

V

L

CC

combines stepper lithography,

PHASE

φ

SHIFTER

90°

Q MIXER

Σ

SUMMER

OUTPUT
AMPLIFIER

•

RF

out

50 Ω ZO
unbalanced

ion-implantation, self-alignment
techniques, and gold metallization
to produce RFICs with superior
performance, uniformity and
reliability.

7-38

HPMX-2003 Absolute Maximum Ratings, T

= 25° C

A

Absolute

Symbol Parameter Units Maximum

P

diss

LO

in

V

CC

∆V

Imod

∆V

Qmod

V

, V

Iref

T

STG

T

j

Power Dissipation
LO Input Power dBm 15
Supply Voltage V 10

, Swing of V

or V
Reference Input Levels

Qref

Qmod

Imod

about V

Storage Temperature °C -65 to +150
Junction Temperature °C 150

[2,3]

about V

Qref

Iref

[4]

[4]

m W 500

V

p-p

V5

Thermal Resistance

[1]

Notes:

1. Operation of this device above any one
of these parameters may cause
permanent damage.

2. TC = 25°C (TC is defined to be the

[4]

5

[4]

temperature at the end of pin 3 where it
contacts the circuit board).

3. Derate at 8 mW/°C for TC > 88°C.

4. Do not exceed VCC by more than 0.8 V.

θjc =125°C/W

[2]

:

HPMX-2003 Guaranteed Electrical Specifications, T

VCC = 5 V, LO= -12 dBm at 900 MHz (Unbalanced Input), V

Iref

= V

= 25° C, ZO = 50 Ω

A

= 2.5 V (Unless Otherwise Noted).

Qref

Symbol Parameters and Test Conditions Units Min. Typ. Max.

LO

ε

P

I

d

out

leak

mod

Device Current mA 36 44
Output Power V
P

- LO at Output V

out

Average % 4 7

√

(V

- 2.5)2 + (V

Imod

= V

Imod

Qmod

Qmod

= V

Imod

Qmod

- 2.5)2= 1.25 V

= 3.75 V dBm +4.0 +6

= 2.5 V dBc +30 +37

Modulation
Error

HPMX-2003 Summary Characterization Information, T

VCC = 5 V, LO = -12 dBm at 900 MHz (Unbalanced Input), V

Iref

= V

Qref

= 25°C, ZO = 50 Ω

A

= 2.5 V (Unless Otherwise Noted).

Symbol Parameters and Test Conditions Units Typ.

R

in

R

in-gnd

VSWR

Input Resistance (I

mod

to I

ref

or Q

mod

to Q

) Ω 10 k

ref

Input Resistance to Ground (Any I, Q Pin to Ground) Ω 10 k
LO VSWR (50 Ω) GSM: 890-915 MHz Bandwidth 1.5:1

LO

NADC: 824-850 MHz Bandwidth 1.5:1

JDC: 940-960 MHz Bandwidth 1.5:1

VSWR

IM

A

i

P

i

Output VSWR (50 Ω) (Tuned by GSM: 890-915 MHz Bandwidth 1.2:1

O

Placement of V

Capacitor – NADC: 824-850 MHz Bandwidth 1.1:1

ccL

See Figures 22, 32, and 42) JDC: 940-960 MHz Bandwidth 1.2:1
Output Noise Floor

V

= V

Imod

DSB Third Order Intermodulation Products dBc +34

3

= 3.75 V dBm/Hz -134

Qmod

RMS Amplitude Error dB 0.3
RMS Phase Error degrees 2

7-39

HPMX-2003 Pin Description

VCC (pins 1,2)

These two pins provide DC power
to the mixers in the RFIC, and are
connected together internal to the
package. They should be con­nected to a 5 V supply, with appro­priate AC bypassing (1000 pF typ.)
used near the pins, as shown in
figures 1 and 2. The voltage on

these pins should always be
kept at least 0.8 V more posi-
tive than the DC level on any
of pins 5, 6, 11, or 12. Failure to

do so may result in the modulator
drawing sufficient current
through the data or reference
inputs to damage the IC.

Ground (pins 3, 4, 10, 13 & 14)

These pins should connect with
minimal inductance to a solid
ground plane (usually the back­side of the PC board). Recom­mended assembly employs
multiple plated through via holes
where these leads contact the PC
board.

I

(pin 12) and Q

ref

I␣ (pin 11) and Q (pin 6) Inputs

The I and Q inputs are designed
for unbalanced operation but can
be driven differentially with simi-

(pin 5),

ref

lar performance. The recom­mended level of unbalanced I and
Q signals is 2.5 V

with an aver-

p-p

age level of 2.5 V above ground.
The reference pins should be DC
biased to this average data signal
level (VCC/2 or 2.5 V typ.). For
single ended drive, pins 5 and 12
can be tied together. For balanced
operation, 2.5 V
applied across the I
Q

mod/Qref

pairs. The average level

signals may be

p-p

mod/Iref

and the

of all four signals should be about

2.5 V above ground. The imped­ance between any I or Q and
ground is typically 10 K Ω and the
impedance between I
Q

mod

and Q

is typically 10 KΩ.

ref

mod

and I

ref

or

The input bandwidth typically
exceeds 40 MHz. It is possible to
reduce LO leakage through the IC
by applying slight DC imbalances
between I
and Q

and I

mod

(see section entitled

ref

and/or Q

ref

mod

“HPMX-2003 Using Offsets to Im­prove Lo Leakage”). All perfor­mance data shown on this data
sheet was taken with unbalanced
I/Q inputs.

LO Input (pins 7 and 8)

The LO input of the HPMX-2003 is
balanced and matched to 50 For
drive from an unbalanced LO, pin
7 should be AC coupled to the LO

using a 50 Ω transmission line and
a blocking capacitor (1000 pF
typ.), and pin 8 should be AC
grounded (1000 pF capacitor
typ.), as shown in figure 1. For
drive from a balanced LO source,
50 Ω transmission lines and block­ing capacitors (1000 pF typ.) are
used on both pins 7 and 8, as
shown in figure 2. The internal
phase shifter allows operation
from 800 - 1000 MHz. The recom­mended LO input level is -12 dBm.
All performance data shown on
this data sheet was taken with un­balanced LO operation.

RF Output (pin15)

The RF output of the HPMX-2003
is configured for unbalanced
operation. The output is internally
DC blocked and matched to 50 Ω,
so a simple 50 Ω microstrip line is
all that is required to connect the
modulator to other circuits.

V

(pin 16)

CCL

Pin 16 is the VCC input for the out­put stage of the IC. It is not inter­nally connected to the other V

CC

pins. The external connection al­lows the addition of a small induc­tor (0 - 6 nH) to tune the output
for minimum VSWR, depending
upon the operating frequency.

+5 V

1000 pF

Q

ref

Q

mod

LO

in

1000 pF

1000 pF

Figure 1. HPMX-2003 Connections Showing Unbalanced LO
and I, Q Inputs.

1000 pF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

OPTIONAL INDUCTOR

9

DO NOT CONNECT

I

I

RF

ref

mod

out

7-40

1000 pF

Q

mod I

1000 pF

LO

+

in

LO

–

in

1000 pF

Figure 2. HPMX-2003 Connections Showing Balanced LO
and I, Q Inputs.

+5 V

Q

ref

1000 pF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OPTIONAL INDUCTOR

DO NOT CONNECT

I

ref

mod

RF

out

HPMX-2003 Typical Data Measurement

Direct measurement of the ampli­tude and phase error at the output
is an accurate way to evaluate
modulator performance. By mea­suring the error directly, all the
harmonics, LO leakage, etc. that
show up in the output signal are
accounted for. Figure 3, below,
shows the test setup that was used
to create the amplitude and phase
error plots (figures 12 and 13).

Amplitude and phase error are
measured by using the four chan­nel power supply to simulate I and
Q input signals. Real 2.5 V
Q signals would swing 1.25 volts
above and below an average 2.5 V
level, therefore, a “high” level in­put is simulated by applying

3.75␣ V, and a “low” level by apply­ing 1.25 V to the I and/or Q inputs.

p-p

I and

Amplitude and phase are
measured by setting the network
analyzer for an S21 measurement
at frequency of choice. Set the
port 1 stimulus level to the LO
level you intend to use in your cir­cuit (-12 dBm for the data sheet).
A 6-10 dB attenuator can be
placed in the line to port 2 to pre­vent network analyzer overload,
depending upon the network ana­lyzer you are using.

By adjusting the V

Imod

and V

Qmod

settings you can step around the
I, Q vector circle, reading mag­nitude and phase at each point.
The relative values of phase and
amplitude at the various points
will indicate the accuracy of the
modulator. Note: you must use
very low ripple power supplies
for the reference, V

Imod

, and V

Qmod

supplies. Ripple or noise of only a
few millivolts will appear as wob-

bling phase readings on the net­work analyzer.

The same test setup shown below
is used to measure input and out­put VSWR, reverse isolation, and
power vs. frequency. V
V

are set to 3.75 V and the

Qmod

Imod

and

appropriate frequency ranges are
swept. S11 provides input VSWR
data, S22 provides output VSWR
data. S21 provides power output
(add source power to S21 derived
gain).

LO leakage data shown in figures
18, and 19 is generated by setting
V

Imod

= V

Qmod

= V

Iref

= V

Qref

= 2.5 V
then performing an S21 sweep.
Since phase is not important for
these measurements, a scalar net­work analyzer or a signal genera­tor and spectrum analyzer could
be used.

HP-8753C VECTOR NETWORK ANALYZER

PORT 1

Q

5 V

HP-6626A
SYSTEM DC POWER SUPPLY
(FOUR OUTPUTS)

2.5 V

Figure 3. Test Setup for Measuring Amplitude and Phase Error, Input and Output
VSWR, Power Output and LO Leakage of the Modulator.

V

Qmod

V

Imod

VER 1

H

HPMX-2003/5

I

R

C

LO

C

C

C

OUT

PORT 2

R

V

CC

5 V

7-41

HPMX-2003 Typical Performance

45

42

39

36

DEVICE CURRENT (mA)

33

30

-55

-35 -15

5

25 45 65 85

TEMPERATURE (°C)

Figure 4. HPMX-2003 Device Current
vs. Temperature, V

10

8

6

4

OUTPUT POWER (dBm)

2

0

-55

-35 -15

= 5 V.

CC

5

25 45 65 85

TEMPERATURE (°C)

Figure 6. HPMX-2003 Power Output
vs. Temperature at 900 MHz,
LO␣ =␣ -12␣ dBm, V
V

= V

Iref

= 2.5 V, V

Qref

Imod

= V

CC

Qmod

= 5 V.

= 3.75 V,

50

45

40

35

DEVICE CURRENT (mA)

30

25

4.5

4

V

CC

5

(VOLTS)

5.5 6

Figure 5. HPMX-2003 Device Current
vs. VCC, T

OUTPUT POWER (dBm)

= 25° C.

A

10

8
6

4
2
0

-2

-4

-6

-8

-10

4.5

4.25 4.75 5.25 5.75

4

V

CC

5

(VOLTS)

4.25 V

3.75 V

3.25 V

3.0 V

2.75 V

5.5 6

Figure 7. HPMX-2003 Power Output
vs. V

and I, Q Level at 900 MHz,

CC

LO␣ =␣ -12 dBm, V

Imod

= V

Qmod

, T

A

= 25° C.

10

8

6

4

OUTPUT POWER (dBm)

2

0

-25

-20

-15 -10 -5 0

LO INPUT POWER (dBm)

Figure 8. HPMX-2003 Power Output
vs. LO Level at 900 MHz, VCC = 5 V,
V

= V

Imod

Qmod

= 3.75 V , T

= 25° C.

A

5:1

4:1

3:1

INPUT VSWR

2:1

1:1

750

-55 °C

85 °C

850

FREQUENCY (MHz)

950 1050

Figure 9. HPMX-2003 LO Input VSWR
vs. Frequency and Temperature,
V

=␣ 5 V.

CC␣

5:1

4:1

3:1

OUTPUT VSWR

2:1

-55 °C

1:1

750

850

85 °C

950 1050

FREQUENCY (MHz)

Figure 10. HPMX-2003 Output VSWR
vs. Frequency and Temperature.

7-42

2:1

1.8:1

1.6:1

1.4:1

OUTPUT VSWR

1.2:1

1:1

4

4.5

V

CC

5

(VOLTS)

5.5 6

Figure 11. HPMX-2003 Output VSWR
vs. V

at 900 MHz, T

CC

= 25° C.

A