100VG-AnyLAN Multimode
Fiber Transceivers in Low Cost
1x9 Package Style
Technical Data
Features
• Full Compliance with the
Optical Performance
Requirements of the IEEE
802.12
• Multisourced 1x9 Package
Style with Choice of Duplex
SC or ST® Receptacles
• Wave Solder and Aqueous
Wash Process Compatible
• Manufactured in an ISO
9002 Certified Facility
• 820 nm and 1300 nm LED
Based Transceivers
Applications
• Multimode Fiber Backbone
Links
• Multimode Fiber Wiring
Closet to Desktop Links
Description
The HFBR-5106 and HFBR-5107
series transceivers from HewlettPackard provide system designers
with products to implement a
range of multimode fiber
100VG-AnyLAN physical layer
solutions. The transceivers are all
supplied in the new industry
standard 1x9 SIP package style
with a choice of duplex SC or
ST® connector interface.
100VG-AnyLAN Backbone Links
The HFBR-5106/-5106T are 1300
nm products with optical
performance compliant with the
100VG-AnyLAN PMD developed
by IEEE 802.12. These
transceivers are suitable for link
lengths up to 2 km.
Alternative 800 nm, Lower Cost 500 m Desktop Links
The HFBR-5107 is a lower cost
800 nm alternative to the HFBR5106 for 100VG-AnyLAN links
from the wiring closet to the
desktop. It complies with the
performance requirements of
802.12 as implemented by
Hewlett-Packard at 800 nm
wavelength. This transceiver will
transfer the full range of
100VG-AnyLan Signals at the
required 1x10–8 Bit Error Rate
over distances up to 500 meters
using 62.5/125 µm multimode
fiber cables. This product is
intended for use in cost sensitive
applications where the benefits of
fiber optic links are important.
Transmitter Sections
The transmitter sections of the
HFBR-5106 utilize 1300 nm
HFBR-5106/5106T
1300 nm
HFBR-5107/5107T
820 nm
Surface Emitting InGaAsP LEDs
and the HFBR-5107 uses a low
cost 820 nm AlGaAs LED. These
LEDs are packaged in the optical
subassembly portion of the
transmitter section. They are
driven by a custom silicon IC
which converts differential PECL
logic signals, ECL referenced
(shifted) to a +5 Volt supply, into
an analog LED drive current.
Receiver Sections
The receiver section of the
HFBR-5106 utilizes InGaAs PIN
photodiodes coupled to a custom
silicon transimpedance preamplifier IC. The HFBR-5107 series
uses the same preamplifier IC in
conjunction with an inexpensive
silicon PIN photodiode. These are
packaged in the optical
subassembly portion of the
receiver.
150
5965-7785E (4/97)
These PlN/preamplifier combinations are coupled to a custom
quantizer IC which provides the
final pulse shaping for the logic
output and Signal Detect
function. The data output is
differential. The signal detect
output is single-ended. Both data
and signal detect outputs are
PECL compatible, ECL
referenced (shifted) to a +5 Volt
power supply.
Package
The overall package concept for
the HP transceivers consists of
the following basic elements; two
optical subassemblies, an
electrical subassembly, and the
housing with integral duplex SC
connector receptacles. This is
illustrated in Figure 1.
The package outline and pinout
are shown in Figures 2 and 3.
The details of this package
outline and pinout are compliant
with the multisource definition of
the 1x9 SIP. The low profile of
the Hewlett- Packard transceiver
design complies with the maximum height allowed for the
duplex SC connector over the
entire length of the package.
The optical subassemblies utilize
a high volume process together
DIFFERENTIAL
DATA OUT
SINGLE-ENDED
SIGNAL
DETECT OUT
DIFFERENTIAL
DATA IN
Figure 1. Block Diagram.
ELECTRICAL SUBASSEMBLY
QUANTIZER IC
DRIVER IC
PREAMP
TOP VIEW
with low cost lens elements which
result in a cost effective
transceiver.
The electrical subassembly consists of a high volume multi-layer
printed circuit board on which
the IC chips and various surface
mount passive circuit elements
are attached.
The package includes internal
shields for the electrical and
optical subassemblies to ensure
low EMI and high immunity to
electromagnetic fields.
The outer housing, including the
duplex SC connector receptacle,
is molded of filled non-conductive
plastic to provide mechanical
strength and electrical isolation.
The solder posts of the HewlettPackard design are isolated from
the circuit design of the
transceiver and do not require
connection to a ground plane on
the circuit board.
The transceiver is attached to a
printed circuit board with the
nine signal pins and the two
solder posts which exit the
bottom of the housing. The two
solder posts provide the primary
mechanical strength to withstand
the loads imposed on the duplex
DUPLEX SC
RECEPTACLE
PIN
PHOTODIODE
IC
OPTICAL
SUBASSEMBLIES
LED
or simplex SC connectored fiber
cables.
Application Information
The Application Engineering
group in the Hewlett-Packard
Optical Communications Division
is available to assist you with the
technical understanding and
design trade-offs associated with
these transceivers. You can
contact them through your
Hewlett-Packard sales
representative.
The following information is
provided to answer some of the
most common questions about
the use of these parts.
Transceiver Optical Power
Budget versus Link Length
Optical Power Budget (OPB) is
the available optical power for a
fiber optic link to accommodate
fiber cable losses plus losses due
to inline connectors, splices,
optical switches, and to provide
margin for link aging and
unplanned losses due to cable
plant reconfiguration or repair.
Figure 4 illustrates the predicted
OPB associated with the two
transceivers specified in this data
sheet at the Beginning of Life
(BOL). These curves represent
the attenuation and chromatic
plus modal dispersion losses
associated with the 62.5/125 µm
and 50/125 µm fiber cables only.
The area under the curve represents the remaining OPB at any
link length, which is available for
overcoming non-fiber cable
related losses.
Hewlett-Packard LED technology
has produced 800 nm LED and
1300 nm LED devices with lower
aging characteristics than
151
DIFFERENTIAL
DATA OUT
SINGLE-ENDED
SIGNAL
DETECT OUT
ELECTRICAL SUBASSEMBLY
QUANTIZER IC
PREAMP
DUPLEX ST
RECEPTACLE
PIN PHOTODIODE
IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
DATA IN
DRIVER IC
TOP VIEW
Figure 1a. ST Block Diagram.
HFBR-510X
DATE CODE (YYWW)
COUNTRY OF ORIGIN
+ 0.08
0.75
3.30 ± 0.38
(0.130 ± 0.015)
(
0.030
- 0.05
+ 0.003
- 0.002
)
25.40
(1.000)
10.35
(0.407)
MAX.
MAX.
LED
39.12
(1.540)
MAX.
AREA
RESERVED
FOR
PROCESS
PLUG
12.70
(0.500)
12.70
(0.500)
2.92
(0.115)
0.46
(9x)ø
(0.018)
NOTE 1
23.55
(0.927)
NOTE 1: THE SOLDER POSTS AND ELECTRICAL PINS ARE PHOSPHOR BRONZE WITH TIN LEAD OVER NICKEL PLATING.
DIMENSIONS ARE IN MILLIMETERS (INCHES).
20.32
(0.800)
[8x(2.54/.100)]
16.70
(0.657)
0.87
(0.034)
23.24
(0.915)
18.52
(0.729)
4.14
(0.163)
15.88
(0.625)
(
0.050
1.27
+ 0.010
- 0.002
NOTE 1
(0.682)
+ 0.25
- 0.05
17.32
)
20.32
(0.800)
23.32
(0.918)
Figure 2. Package Outline Drawing.
152
24.8
(0.976)
42
(1.654)
MAX.
5.99
(0.236)
HFBR-5106T
HFBR-510XT
DATE CODE (YYWW)
DATE CODE (YYWW)
COUNTRY OF ORIGIN
SINGAPORE
20.32
(0.800)
22.86
(0.900)
25.4
MAX.
(1.000)
+ 0.08
0.5
- 0.05
(0.020)
+ 0.003
(
(
12.0
MAX.
(0.471)
3.2
(0.126)
± 0.38
20.32
0.46
φ
(0.022)
NOTE 1
[(8x (2.54/0.100)]
3.6
(0.142)
NOTE 1: PHOSPHOR BRONZE IS THE BASE MATERIAL FOR THE POSTS & PINS
WITH TIN LEAD OVER NICKEL PLATING.
DIMENSIONS IN MILLIMETERS (INCHES).
21.4
(0.843)
(0.051)
17.4
(0.685)
1.3
(± 0.015)
2.6
φ
(0.102)
23.38
(0.921)
18.62
(0.733)
- 0.002
3.3 ± 0.38
(0.130) (± 0.015)
(
20.32
(0.800)
+ 0.25
- 0.05
+ 0.010
- 0.002
(
12.7
(0.500)
Figure 2a. ST Package Outline Drawing.
1 = V
2 = RD
3 = RD
4 = SD
5 = V
6 = V
7 = TD
8 = TD
9 = V
EE
CC
CC
EE
N/C
N/C
TOP VIEW
Figure 3. Pin Out Diagram.
153
normally associated with these
technologies in the industry. The
Industry convention is 3 dB aging
for 800 nm and 1.5 dB for 1300
nm LEDs. The HP LEDs will
normally experience less than
1 dB of aging over normal commercial equipment mission life
periods. Contact your
Hewlett-Packard sales representatives for additional details.
Figure 4 was generated with a
Hewlett-Packard fiber optic link
module containing the current
industry conventions for fiber
cable specifications and the
100VG-AnyLAN Optical Parameters. These parameters are
reflected in the guaranteed
performance of the transceiver
specifications in this data sheet.
This same model has been used
extensively in the ANSI X3T and
IEEE committees, including the
ANSI X3T12 committee, to
establish the optical performance
requirements for various fiber
optic interface standards. The
cable parameters used come from
the ISO/IEC JTCI/SC 25/WG3
Generic Cabling for Customer
Premises per DIS 11801
document and the EIA/TIA568-A
Commercial Building Telecommunications Cabling Standard per
SP-2840.
Transceiver Signaling Operating Rate Range and BER Performance
For purposes of definition, the
symbol (Baud) rate, also called
signaling rate, is the reciprocal of
the shortest symbol time. Data
rate (bits/sec) is the symbol rate
divided by the encoding factor
used to encode the data
(symbols/bit).
When used in 100VG AnyLAN
100 Mbps applications, the
performance of the 1300 nm
transceiver is guaranteed over the
signaling rate of 10 MBd to
120 MBd to the full conditions
listed in the individual product
specification tables.
The transceivers may be used for
other applications at signaling
rates outside of the 10 MBd to
120 MBd range with some
penalty in the link optical power
budget primarily caused by a
reduction of receiver sensitivity.
Figure 5 gives an indication of
the typical performance of these
1300 nm products at different
rates.
These transceivers can also be
used for applications which
require different Bit Error Rate
(BER) performance. Figure 6
illustrates the typical trade-off
between link BER and the
receivers input optical power
level.
Table 1 lists the hub control
signals defined in IEEE 802.12,
section 18.5.4.1. These signal
rates are below 10 MBd but they
are transported with adequate
accuracy for hub access control.
Transceiver Jitter Performance
The Hewlett-Packard 1300 nm
transceivers are designed to
operate per the system interface
jitter specifications listed in Table
27 of section 18.9. of the IEEE
802.12 (100VG-AnyLAN
standards).
14
12
10
8
6
4
2
OPTICAL POWER BUDGET (dB)
0
FIBER OPTIC CABLE LENGTH (km)
Figure 4. Optical Power Budget at
BOL vs. Fiber Optic Cable Length.
HFBR-5106, 62.5/125 µm
HFBR-5107,
62.5/125 µm
HFBR-5107,
50/125 µm
HFBR-5106,
50/125 µm
1.0 3.00.15
0.5 1.5 2.0 2.5
154
3.5
4.0
3.0
2.5
2.0
1.5
1.0
AT CONSTANT BER (dB)
0.5
0
TRANSCEIVER RELATIVE OPTICAL POWER BUDGET
CONDITIONS:
1. PRBS 2
2. DATA SAMPLED AT CENTER OF
DATA SYMBOL.
3. BER = 10
4. TA = 25° C
5. V
CC
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 5. Transceiver Relative Optical
Power Budget at Constant BER vs.
Signaling Rate.
50 150
0 200
25 75 100 125
SIGNAL RATE (MBd)
7
-1
-6
= 5 V
dc
175
-2
1 x 10
-3
1 x 10
-4
1 x 10
-5
1 x 10
-6
1 x 10
-7
1 x 10
-8
1 x 10
BIT ERROR RATE
-10
2.5 x 10
-11
1 x 10
-12
1 x 10
-6 4
RELATIVE INPUT OPTICAL POWER – dB
CONDITIONS:
1. 125 MBd
2. PRBS 2
3. CENTER OF SYMBOL SAMPLING.
4. T
5. V
6. INPUT OPTICAL RISE/FALL TIMES
= 1.0/2.1 ns.
Figure 6. Bit Error Rate vs. Relative
Receiver Input Optical Power.
= 25° C
A
= 5 V
CC
HFBR-510X
-4 2-2
7
-1
dc
CENTER OF SYMBOL
0
The HP 1300 nm transmitters are
allowed to generate the worst
case Active Output jitter shown in
Table 27 of section 18.9 when
driven by circuits optimized for
these link applications. The
Active Output Specifications of
the 100VG-AnyLAN standard are
met by the HFBR-5106.
The HP 1300 nm receivers
tolerate the worst case input
optical response time and
systematic jitter shown in
Table 27 of Section 18.9. The
Active Input Specification of the
IEEE 802.12 100VG-AnyLAN
standard are met by the
HBFR-5106.
The jitter specifications stated in
the 1300 nm transceiver
specification tables are derived
from the values in Table 27 of
section 18.9 of the IEEE 802.12
specification. They represent the
worst case jitter contributions
from the transceiver meeting the
overall system jitter in Annex E.
In practice the typical jitter
contribution of the HP transceivers is well below these maximum
allowed values.
Recommended Handling Precautions
It is advised that normal static
precautions be taken in the
handling and assembly of these
transceivers to prevent damage
which may be induced by
electrostatic discharge (ESD).
The HFBR-510X series of
transceivers are certified as
Mil-Std-883C Method 3015.4
Class 1 products.
Care should be used to avoid
shorting the receiver data or
signal detect outputs directly to
NO INTERNAL CONNECTION NO INTERNAL CONNECTION
HFBR-510X
TOP VIEW
Rx Rx Tx Tx
RD RD SD VCCVCCTD TD V
V
EE
123456789
C1 C2
TERMINATION
AT PHY
DEVICE
INPUTS
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS.
R2 = R3 = R5 = R7 = R9 = 82 OHMS.
C1 = C2 = C3 = C5 = C6 = 0.1 µF.
C4 = 10 µF.
L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.
Figure 7. Recommended Decoupling and Termination Circuits.
V
CC
R5 R7
R6 R8
C6
RD RD SD V
ground without proper current
limiting impedance.
L1 L2
C3 C4
VCC FILTER
AT V
CC
TRANSCEIVER
R9
R10
CC
PINS
TD TD
Shipping Container
The transceiver is packaged in a
EE
V
CC
R2 R3
R1 R4
C5
TERMINATION
AT TRANSCEIVER
INPUTS
shipping container designed to
Solder and Wash Process Compatibility
The transceivers are delivered
protect it from mechanical and
ESD damage during shipment or
storage.
with a protective process plug
inserted into the duplex SC
connector receptacle. This
process plug protects the optical
subassemblies during wave solder
and aqueous wash processing and
acts as a dust cover during
shipping. These transceivers are
compatible with either industry
standard wave or hand soldering
processes.
Board Layout –
Decoupling Circuit and
Ground Planes
It is important to take care in the
layout of your circuit board to
achieve optimum performance
from these transceivers. Figure 7
provides a good example of a
schematic for a power supply
decoupling circuit that works
155
Regulatory Compliance Table
Feature Test Method Performance
Electrostatic Discharge MIL-STD-883C Certified to Class 1 (0 to 1999 Volts) Withstand up
(ESD) to the Electrical Pins Method 3015.4 to 1800 V applied between electrical pins.
Electrostatic Discharge Variation of Typically withstand at least 25 kV without damage
(ESD) to the Duplex SC IEC 801-2 when the Duplex SC Connector Receptacle
Receptacle is contacted by a Human Body Model probe.
Electromagnetic FCC Class B Typically provide a 10 dB margin to the noted
Interference (EMC) CENELEC CEN55022 standard limits when tested at a certified test range
Class B (CISPR 22B) with the transceiver mounted to a circuit card
VCCI Class 2 without a chassis enclosure.
Immunity Variation of IEC 801-3 Typically show no measurable effect from a
10 V/m field swept from 10 to 450 MHz applied
to the transceiver when mounted to a circuit card
without a chassis enclosure.
well. It is further recommended
that a contiguous ground plane
be provided in the circuit board
directly under the transceiver to
provide a low inductance ground
for signal return current. This
recommendation is in keeping
with good high frequency board
layout practices.
Board Layout – Hole Pattern
This Hewlett-Packard transceiver
complies with the circuit board
“Common Transceiver Footprint”
hole pattern defined in the
original multisource announcement which defined the 1x9
package style. This drawing is
reproduced in Figure 8 with the
addition of ANSI Y14.5N
compliant dimensioning to be
used as a guide in the mechanical
layout of your circuit board.
Board Layout – Art Work
The Applications Engineering
group has developed Gerber file
artwork for a multilayered printed
circuit board layout incorporating
the above recommendations.
Contact your local Hewlett-
Packard sales representative for
details.
Board Layout –
Mechanical
For applications providing a
choice of either a duplex SC or a
duplex ST connector interface,
while utilizing the same pinout on
the printed circuit board, the ST
port needs to protrude from the
chassis panel a minimum of 9.53
mm for sufficient clearance to
install the ST connector.
Please refer to Figure 8a for a
mechanical layout detailing the
recommended location of the
duplex SC and duplex ST
transceiver packages in relation
to the chassis panel.
Regulatory Compliance
These transceiver products are
intended to enable commercial
system designers to develop
equipment that complies with the
various international regulations
governing certification of Information Technology Equipment.
See the Regulatory Compliance
Table for details. Additional
information is available from your
Hewlett-Packard sales
representative.
Electrostatic Discharge
(ESD)
There are two design cases in
which immunity to ESD damage
is important.
The first case is during handling
of the transceiver prior to
mounting it on the circuit board.
It is important to use normal ESD
handling precautions for ESD
sensitive devices. These precau-
tions include using grounded
wrist straps, work benches, and
floor mats in ESD controlled
areas.
The second case is static
discharges to the exterior of the
equipment chassis containing the
transceiver parts. To the extent
that the duplex SC connector is
exposed to the outside of the
equipment chassis it may be
subject to whatever ESD system
level test criteria that the equip-
ment is intended to meet.
156
(2X)
(9X)
(8X)
20.32
.800
2.54
.100
20.32
.800
TOP VIEW
Figure 8. Recommended Board Layout Hole Pattern.
42.0
1.9 ± 0.1
ø
.075 ± .004
Ø0.000
0.8 ± 0.1
ø
.032 ± .004
Ø0.000
MA
–A–
MA
6.79
9.53
(NOTE 1)
12.09
12.0
0.51
11.1
0.75
NOTE 1: MINIMUM DISTANCE FROM FRONT
OF CONNECTOR TO THE PANEL FACE.
24.8
25.4
39.12
25.4
Figure 8a. Recommended Common Mechanical Layout for SC and ST 1x9 Connectored Transceivers.
157
Electromagnetic Interference (EMI)
Most equipment designs utilizing
these high speed transceivers
from Hewlett-Packard will be
required to meet the requirements of FCC in the United
States, CENELEC EN55022
(CISPR 22) in Europe and VCCI
in Japan.
Ordering Information
The HFBR-5106 and
HFBR-5106T 1300 nm products
and HFBR-5107 and
HFBR-5107T 820 nm devices are
available for production orders
through the Hewlett-Packard
Component Field Sales Offices
and Authorized Distributors
worldwide.
2. HFBR-BKD010 – A duplex
cable 10 meters long
assembled with 62.5/125 µm
fiber and duplex SC connector
plugs on either end.
5
4
HFBR-5106/5107
SERIES
These devices are suitable for use
in designs ranging from a
desktop computer with a single
transceiver to a concentrator or
switch product with a large
number of transceivers.
Immunity
Equipment utilizing these
transceivers will be subject to
radio frequency electromagnetic
fields in some environments.
These transceivers have a high
immunity to such fields.
Transceiver Reliability and Performance Qualification Data
The 1x9 transceivers have passed
Hewlett-Packard reliability and
performance qualification testing
and are undergoing quality
monitoring. Details are available
from your Hewlett-Packard sales
representative. These
transceivers are manufactured at
the Hewlett-Packard Singapore
location which is an ISO 9002
certified facility.
Applications Support Material
Contact your local
Hewlett-Packard Component
Field Sales Office for information
on how to obtain PCB layouts,
test boards, and demo boards for
the 1x9 transceivers.
Accessory Duplex SC Connectored Cable Assemblies
Hewlett-Packard also offers two
compatible Duplex SC connectored jumper cable assemblies to
assist you in the evaluation of
these transceiver products. These
cables may be purchased from
HP with the following part
numbers. They are available
through the Hewlett-Packard
Component Field Sales Offices
and Authorized Distributors
worldwide.
1. HFBR-BKD001 – A duplex
cable 1 meter long assembled
with 62.5/125 µm fiber and
duplex SC connector plugs on
either end.
3
2
1
0
RELATIVE INPUT OPTICAL POWER (dB)
CONDITIONS:
1.T
= 25° C
A
2. V
CC
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 20 AND 21 APPLY.
Figure 9. Relative Input Optical Power
vs. Eye Sampling Time Position.
-2 2
-4 4
-3 -1 0 1
EYE SAMPLING TIME POSITION (ns)
= 5 Vdc
2.5 x 10
1.0 x 10
-10
BER
-12
BER
3
Table 1. Control Signal Generation
The Hewlett-Packard transceivers are capable of transporting the following five control signals defined in
IEEE 802.12, section 18.5.4.1.
Control Signal NRZ Encoded Pattern Frequency
Control Signal 1 (CS1) <HCS1a> and <HCS1b> 1.875 MHz
Control Signal 2 (CS2) <HCS2a> and <HCS2b> 2.069 MHz
Control Signal 3 (CS3) <HCS3a> and <HCS3b> 2.308 MHz
Control Signal 4 (CS4) <HCS4a> and <HCS4b> 2.609 MHz
Control Signal 5 (CS5) <HCS5a> and <HCS5b> 3.000 MHz
158
AVERAGE OPTICAL POWER
AT Al (dBm)
Pm +4 dB
Pm
-45 dB
HIGH_LIGHT
LOW_LIGHT
VALID IEEE 802.12 OPTICAL SIGNALS
TIME
100 µs
AVERAGE OPTICAL POWER
AT Al (dBm)
Pm +4 dB
Pm
VALID IEEE 802.12 OPTICAL SIGNALS
-45 dB
HIGH_LIGHT
LOW_LIGHT
TIME
1 µs
350 µs
Figure 10.
159
HFBR-5106, -5107 Series Absolute Maximum Ratings
Parameter Symbol Min. Typ. Max. Unit Reference
Storage Temperature T
Lead Soldering Temperature T
Lead Soldering Time t
Supply Voltage V
Data Input Voltage V
Differential Input Voltage V
Output Current I
S
SOLD
SOLD
CC
I
D
O
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit Reference
Ambient Operating Temperature T
Supply Voltage V
Data Input Voltage - Low V
Data Input Voltage - High V
Data and Signal Detect Output Load R
IL
IH
–40 100 °C
260 °C
10 sec.
–0.5 7.0 V
–0.5 V
CC
1.4 V Note 1
50 mA
A
CC
- V
- V
L
CC
CC
070°C
4.75 5.25 V
–1.810 –1.475 V
–1.165 –0.880 V
50 Ω Note 2
V
Transmitter Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Supply Current I
Power Dissipation P
Data Input Current - Low I
Data Input Current - High I
CC
DISS
IL
IH
Receiver Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Supply Current I
Power Dissipation P
Data Output Voltage - Low VOL - V
Data Output Voltage - High VOH - V
Data Output Rise Time t
Data Output Fall Time t
Signal Detect Output Voltage - Low VOL - V
Signal Detect Output Voltage - High VOH - V
Signal Detect Output Rise Time t
Signal Detect Output Fall Time t
CC
DISS
r
f
r
f
145 185 mA Note 3
0.76 0.97 W
-350 0 µA
14 350 µA
102 145 mA Note 4
0.3 0.5 W Note 5
–1.840 –1.620 V Note 6
CC
–1.045 –0.880 V Note 6
CC
0.35 2.2 ns Note 7
0.35 2.2 ns Note 7
–1.840 –1.620 V Note 6
CC
–1.045 –0.880 V Note 6
CC
0.35 2.2 ns Note 7
0.35 2.2 ns Note 7
160
HFBR-5106/5106T Transmitter Optical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Output Optical Power P
O
-21.0 -14 dBm avg. Note 9
62.5/125 µm, NA = 0.275 Fiber BOL
Output Optical Power P
O
-24.8 -14 dBm avg. Note 9
50/125 µm, NA = 0.20 Fiber BOL
Output Optical Power at PO (“0”) -45 dBm avg. Note 11
Logic “0” State
Center Wavelength λ
C
1270 1380 nm Note 12
Spectral Width - FWHM ∆λ 200 nm Note 12
Optical Rise Time t
Optical Fall Time t
r
f
3.0 ns Note 12, 13
3.0 ns Note 12, 13
Systematic Jitter Contributed by the SJ 1.2 ns p-p Note 23
Transmitter
Random Jitter Contributed by the RJ 0.69 ns p-p Note 15
Transmitter
HFBR-5106/5106T Receiver Optical and Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Input Optical Power P
(W) –29 dBm avg. Note 16
IN Min.
Minimum at Window Edge Figure 9
Input Optical Power P
(C) –33.5 dBm avg. Note 17
IN Min.
Minimum at Eye Center Figure 9
Input Optical Power Maximum P
IN Max.
–14 dBm avg. Note 16
Operating Wavelength λ 1270 1380 nm
Systematic Jitter Contributed SJ 1.4 ns p-p Note 23
by the Receiver
Random Jitter Contributed RJ 2.90 ns p-p Note 24
by the Receiver
Signal Detect - Asserted P
A
PD + 1.5 dB –31 dBm avg. Note 18, 19
(high_light) Figure 10
Signal Detect - Deasserted P
D
–45 dBm avg. Note 21, 22
(lo_light) Figure 10
Signal Detect - Hysteresis PA – P
D
1.5 dB Figure 10
Signal Detect Assert Time AS_MAX 0 100 µs Note 8, 19
(off to on) Figure 10
Signal Detect Deassert Time ANS_MAX 0 350 µs Note 21, 22
(off to on) Figure 10
Control Signal Detect CS1-5 –14 –29 dBm avg. See Table 1
161
HFBR-5107/5107T Transmitter Optical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Output Optical Power P
O
–17.0 –12 dBm avg. Note 10
62.5/125 µm, NA = 0.275 Fiber BOL
Output Optical Power P
O
–20.8 –12 dBm avg. Note 10
50/125 µm, NA = 0.20 Fiber BOL
Output Optical Power at PO (“0”) –45 dBm avg. Note 11
Logic “0” State
Center Wavelength λ
C
800 900 nm Note 12
Spectral Width - FWHM ∆λ 100 nm Note 12
Optical Rise Time t
Optical Fall Time t
r
f
4.5 ns Note 12, 14
4.5 ns Note 12, 14
Systematic Jitter Contributed by the SJ 1.7 ns p-p Note 23
Transmitter
Random Jitter Contributed by the RJ 0.69 ns p-p Note 24
Transmitter
HFBR-5107/5107T Receiver Optical and Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.75 V to 5.25 V)
Parameter Symbol Min. Typ. Max. Unit Reference
Input Optical Power P
(W) –27.5 dBm avg. Note 16a
IN Min.
Minimum at Window Edge
Input Optical Power P
(C) –28 dBm avg. Note 17a
IN Min.
Minimum at Eye Center
Input Optical Power Maximum P
IN Max.
–12 dBm avg. Note 16a
Operating Wavelength λ 800 900 nm
Systematic Jitter Contributed SJ 1.2 ns p-p Note 23
by the Receiver
Random Jitter Contributed RJ 2.6 ns p-p Note 24
by the Receiver
Signal Detect - Asserted P
A
PD + 1.5 dB –29.5 dBm avg. Note 18
Figure 10
Signal Detect - Deasserted P
D
–45 dBm avg. Note 21
Figure 10
Signal Detect - Hysteresis PA – P
D
1.5 dB Figure 10
Signal Detect Assert Time AS_MAX 0 100 µs Note 18
(off to on) Figure 10
Signal Detect Deassert Time ANS_MAX 0 350 µs Note 21
(off to on) Figure 10
Control Signal Detect CS1-5 –14 –27.5 dBm avg. See Table 1
162
Notes:
1. This is the maximum voltage that can
be applied across the Differential
Transmitter Data Inputs to prevent
damage to the input ESD protection
circuit.
2. The outputs are terminated with 50 Ω
connected to VCC –2 V.
3. The power supply current needed to
operate the transmitter is supplied to
differential ECL circuitry. This
circuitry maintains a nearly constant
current from the power supply.
Constant current operation helps to
prevent unwanted electrical noise from
being generated and conducted or
emitted to neighboring circuitry.
4. This value is measured with the
outputs terminated into 50 Ω
connected to VCC –2 V and an Input
Optical Power Level of –14 dBm
average.
5. The power dissipation value is the
power dissipated in the receiver itself.
Power dissipation is calculated as the
sum of the products of supply voltage
and currents, minus the sum of the
products of the output voltages and
currents.
6. This value is measured with respect to
VCC with the output terminated into
50 Ω connected to VCC –2 V.
7. The output electrical rise and fall times
are measured between 20% and 80%
levels with the output connected to
VCC –2 V through 50 Ω.
8. Random Jitter contributed by the
receiver is specified with a 120 MBd
(60 MHz square-wave) input signal.
The input optical power level is at
maximum "P
9. These optical power values are
measured with the following
conditions:
• At the Beginning of Life (BOL). The
actual FDDI specification is 1.5 dB
lower power at the End of Life for
the equipment. The definition of
Beginning of Life (BOL) to the End
of Live (EOL) optical power
degradation is assumed to be 1.0 dB
per the industry convention for
1300 nm LEDs. The actual
degradation observed in normal
commercial environments is
considerably less than this amount
with Hewlett-Packard’s 1300 nm
LED products.
• At the end of one meter of noted
fiber with cladding modes removed.
• Over the specified operating voltage
and temperature ranges.
• (12.5 MHz square-wave) input
IN MIN
. (W)".
signal. The average power value can
be converted to a peak power value
by adding 3 dB. Higher output
optical power transmitters are
available upon special request.
10. The same comments of Note 9 apply
except that industry convention for
800 nm LED BOL to EOL aging is 3
dB. This value for Output Optical
Power provides a minimum of 7.5 dB
optical power budget at the EOL,
which provides at least 500 meter link
lengths with margin left over for
overcoming normal passive losses,
such as in-line connectors in the cable
plant. The actual degradation observed
in normal commercial environments is
considerably less than this amount
with Hewlett-Packard 800 nm LED
products.
11. The transmitter provides compliance
with 802.12. An Output Optical Power
level of <–45 dBm average in
response to a logic "0" input. This
specification applies to either
62.5/125 µm or 50/125 µm fiber
cables.
12. This parameter complies with 802.12.
13. The optical rise and fall times are
measured from 10% to 90% when the
transmitter is driven by a 12.5 MHz
square-wave input signal.
14. The optical rise and fall times are
measured from 10% to 90% when the
transmitter is driven by a 12.5 MHz
square-wave input signal.
15. Random Jitter contributed by the
transmitter is specified with a 60 MBd
square-wave input signal.
16. This specification is intended to indicate the performance of the receiver
section of the transceiver when Input
Optical Power signal characteristics
are present per the following
definitions. The Input Optical Power
dynamic range from the minimum
level (with a window time-width) to
the maximum level is the range over
which the receiver is guaranteed to
provide output data with a Bit Error
Ratio (BER) better than or equal
to 10-8.
• At the Beginning of Life (BOL).
• Over the specified operating
temperature and voltage ranges.
• Receiver data window opening time-
width is 2.2 ns or greater and
centered at mid-symbol. This worst
case window opening time-width is
the minimum allowed eye-opening
presented to the PHY input per
802.12. This minimum window
time-width of 2.2 ns is based upon
the worst case 802.12 Active Input
Interface optical conditions peak-topeak SJ (1.6 ns) and RJ (0.77 ns)
presented to the receiver.
To test a receiver with the worst
case 802.12 Active Input Jitter
condition requires exacting control
over SJ and RJ jitter components.
This is difficult to implement with
production test equipment. The
receiver can be equivalently tested
to the worst case 802.12 input jitter
conditions and meet the minimum
output data window time-width of
2.2 ns This is accomplished by
using a nearly ideal input optical
signal (No DCD, insignificant DDJ
and RJ) and measuring for a wider
window time-width of 4.0 ns. This is
possible due to the cumulative addition of jitter components through
their superposition. (SJ is directly
additive and RJ components are rms
additive). Specifically, when a
nearly ideal input optical test signal
is used and the maximum receiver
peak-to-peak jitter contributions of
SJ (X.Xns), and RJ (X.Xns) exist,
the minimum window time-width
becomes 4.4 ns. This wider window
time-width of 4.4 ns guarantees the
802.12 time-width of 2.2 ns under
worst case input jitter conditions to
the Hewlett-Packard receiver.
• Transmitter operating with a 120
MBd (60 MHz square-wave), input
signal to simulate any cross-talk
present between the transmitter and
receiver sections of the transceiver.
16a. All conditions of Note 16 apply except
that the BER requirement is tightened
to 1x10-8 and the minimum window
time-width test condition is adjusted to
5.2 ns to reflect the HFBR-5107 trans-
mitter contributed jitter values per the
specification table.
17. All conditions of Note 16 apply except
that the measurement is made at the
center of the symbol with no window
time-width.
17a. All conditions of Note 17 apply
except that the BER requirement is
tightened to 1x10-8.
18. This value is measured during the
transition from low to high levels of
input optical power.
19. The high_light (Signal Detect) output
shall be asserted within 100 µs after a
step increase of the Input Optical
Power. The step will be from a low
Input Optical Power ≤ –45 dBm, into
the range between greater than Pm
and (Pm + 4 dB). Pm is the relevant
163
minimum allowed input average optical
power for the PMD at the AI as defined
in Figure 10. (The input optical power
is averaged over a period of 1 µs or
more).
20. The high_light (Signal Detect) output
shall be asserted within 100 µs after a
step increase of the Input Optical
Power. The step will be from a low
Input Optical Power ≤ –45 dBm, into
the range between greater than Pm
and (Pm + 4 dB). Pm is the relevant
minimum allowed input average
optical power for the PMD at the AI as
defined in Figure 10. (The input
optical power is averaged over a
period of 1 µs or more).
21. This value is measured during the
transition from high to low levels of
input optical power. The maximum
value will occur when the input optical
power is –45 dBm average or when the
input optical power yields a BER of 10
2
or better, whichever power is higher.
22. The low_light (Signal Detect) output
shall be deasserted within 350 µs after
valid IEEE 802.12 optical signals cease
to be present at the AI and the input
average optical power at AI has fallen
monitonically from a level between (Pm
+4 dB) and Pm to a level below –45
dBm and remain below –45 dBm (see
Figure 10). (The input optical power is
averaged over a period of 1 µs or
more.)
22. The low_light (Signal Detect) output
shall be deasserted within 350 µs after
valid IEEE 802.12 optical signals cease
to be present at the AI and the input
average optical power at AI, has fallen
monitonically from a level between
-
(Pm +4 dB) and Pm to a level below –
45 dBm and remain below –45 dBm
(see Figure 10). (The input optical
power is averaged over a period of 1
µs or more.)
23. Systematic Jitter (SJ) contributed by
the 800 and 1300 nm transmitter is a
combination of Duty Cycle Distortion
(DCD) and Data Dependent Jitter
(DDJ).
24. Random Jitter contributed by the 800
and 1300 nm transmitter is specified
with an IDLE Line State, 125 MBd
(62.5 MHz square-wave), input signal.
164
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