HP DV7t Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Penryn uFCPGA with Intel
Cantiga_PM+ICH9-M core logic

3 3

LA-4082P Vader Discrete (NB9P-GS,NB9M-GE)

2007-12-26 Rev 0.4

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4082P Vader Discrete

E

0.2

of

158Wednesday, December 26, 2007

A

B

C

D

E

Compal confidential

1 1

2 2

Realtek 8111C
(GLAN)

P31 P32,35

RJ45/11 CONN

3 3

P31

ACCELEROMETER-1

ACCELEROMETER-2

RTC CKT.LED

P41

Capsense switch Conn

4 4

VRAM DDR2
256/512MB

128 bits

Discrete

Nvidia NB9P-GE
Nvidia NB9M-GE

LVDS Panel
Interface

CRT

Support V1.3

HDMI

Mini-Card*3

WLAN & Robson &TV

USB2.0*2
PCIE*3

P39

P39

P27

P41

P22,23,24,25

P18,19,20,21

P16

P44

New Card

USB2.0*1
PCIE*1

P17

PCI-E BUS*5 & USB2.0 *3

Montevina Consumer Discrete

Dual-Core Thermal Sensor
EMC1402
Quad-Core Thermal Sensor
EMC1403

Fan conn

Discrete

Flash Memory Card /
1394 Controller

P32

JM380
CardReader/1394

1394 port

Discrete only

P33

5 in1 Slot

Touch Pad CONN.

P4

P4

DMI X4

P33

P33

Mobile Penryn

uFCPGA-478 CPU

P4, 5, 6

H_A#(3..35)
H_D#(0..63)

FSB

667/800/1066 MHz 1.05V

Intel Cantiga MCH

FCBGA 1329

P7, 8, 9, 10, 11, 12

Intel ICH9-M

mBGA-676

P26,27,28,29

LPC BUS

ENE

KB926

Int.KBD

P41

SPI ROM
25LF080A

SPI

P39

C-Link

USB2.0 X1

P40

DDR2 667MHz 1.8V

Dual Channel

Azalia
SATA Master-1
SATA Master-2
SATA Slave
SATA Slave

P40

CK505

72QFN

Clock Generator
SLG8SP553V

USB2.0*7

P15

DDR2 SO-DIMM X2

BANK 0, 1, 2, 3

P13, 14

USB conn x3

BT Conn

USB Camera

Audio CKT

Codec_IDT9271B7

MDC

SATA HDD Connector

SATA 2nd HDD
Option Connector

SATA ODD Connector

e-SATA Combo Connector

USB2.0*1 & SATA*1

P17

P38

P38

P34

P35

P30

P30

P30

P38

Touch Screen Conn

P38

FPR Conn

P42

AMP & Audio Jack

MIC & SPKR
TPA6020

P36

Sub-woofer & EQ

P37

Dock

USB2.0*1
RGB
RJ45
SPDIF
CIR

MIC*1
LINE-OUT*1
SPDIF

P42

K/B backlight Conn

P41

DC/DC Int erface CKT.

P43

A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-4082P Vader Discrete

E

0.2

of

258Wednesday, December 26, 2007

A

Voltage Rails

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

O MEANS ON X MEANS OFF

power
plane

+5VS
+3VS
+1.5VS
+0.9V

+B

O
O
O
O
O

X

+5VALW

+3VALW

O
O
O
O

X
XX X

+1.8V

O

XX
X

+VCCP
+CPU_CORE

+VGA_CORE
+2.5VS
+1.8VS
+1.2VS
+0.9VGA

OO
OO

X

X

SMBus Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
DDC2_CLK
DDC2_DATA

KB926

KB926

ICH9

NB9M

USB
assignment:

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express

card

USB-10 X
USB-11 X

INVERTER BATT

SERIAL
EEPROM

X VV
X
X
X

X

X

X

X

X

X

PCIe
assignment:

PCIe-1 TV tuner/WWAN/Robeson
PCIe-2 X
PCIe-3 WLAN
PCIe-4 New Card
PCIe-5 Card

reader

PCIe-6 GLAN (Marvell)

Thermal
Sensor

X

V

X
X

SODIMM CLK CHIP

X
X

X
X

MINI
CARD

X

X

VVV

X

X

X

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : me ans just reserve
for debug.

LCD

X
X
X

V

Sensor
board

V

X
X
X

EC SM Bus1 address

Device

Smart Battery

24C16

CAP BOARD -- Cypress

CAP BOARD -- ST

HEX HEX

Address Address

0001 011X

16H

1010 000X

A0H
38H
b0H

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

HEX

A0

D2

EC SM Bus2 address

Device

CPU EMC1402

VGA

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

4CH
4DH

1001 1000b
1001 1010b

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-4082P Vader Discrete

of

358Wednesday, December 26, 2007

0.2

5

4

3

2

1

R730

ITP-XDP Connector

CONN@

JP42

1

QC@

C2113

+3VS

1

2

0.1U_0402_16V4Z

FAN_PWM40

Deciphered Date

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030-01-L-D-A

QC@

QC@

C1

C2

1 2

+3VS

ITPCLK/HOOK4

ITPCLK#/HOOK5

RESET#/HOOK6

C2114

1 2

2200P_0402_50V7K

C2115

1 2

2200P_0402_50V7K

2200P_0402_50V7K

R10

1 2

10K_0402_5%

RB751V_SOD323

3

2

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

VCC_OBS_CD

DBR#/HOOK7

H_THERMDA2
H_THERMDC2

G

D D

H_A#[3..16]7

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47

C C

B B

A A

H_A#[17..35]7

H_ADSTB#17

H_A20M#27

H_FERR#27

H_IGNNE#27
H_STPCLK#27

H_INTR27
H_NMI27
H_SMI#27

R2088 0_0402_5%QC@

H_THERMDA2

1 2

H_THERMDC2

1 2

R2089 0_0402_5%QC@

1 2

+VCCP

51_0402_1%
R53

QC@

H_THERMDA2, H_THERMDC2 routing
together, Trace width / Spacing = 10 / 10
mils

+VCCP

12

+H_GTLREF2

12

R44

QC@

2K_0402_5%

XDP_BPM2#1
XDP_BPM2#0
H_THERMDA2_R
H_THERMDC2_R
XDP_BPM2#2

+H_GTLREF2

1 2

R54 0_0402_5%

QC@

QC@

R43
1K_0402_5%

13

D

S

BSS138_SOT23~D

QC@

Q4

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

+3VS

12

2

G

JCPUA

J4

ADDR GROUP_0

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

ADDR GROUP_1

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]/BPM_2#[1]

N5

RSVD[02]/BPM_2#[0]

T2

RSVD[03]/THRMDA_2

V3

RSVD[04]/THRMDC_2

B2

RSVD[05]/BPM_2#[2]

D2

RSVD[06]

D22

RSVD[07]/GTLREF_2

D3

RSVD[08]/TDO_M

F6

RSVD[09]/TDI_M

DC_RESERVED/QC

Penryn

1025 For Support Dual core and Quad core

CPU
Dual core (DC)
Quad core (QC)

QC@

R45
100K_0402_5%

QC@

10K_0402_5%

C

Q3

1 2

2

B

E

3 1

MMBT3904_NL_SOT23-3

QC@

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

GTLREF_C

GND 0V

Floating 2/3Vtt

+VCCP

R51
10K_0402_5%

QC@

1 2

R49

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

GTLREF2 6

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

H_PROCHOT#
H_THERMDA_R

H_THERMDC_R
H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

GTLREF2

H_ADS# 7
H_BNR# 7

H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

H_INIT# 27
H_LOCK# 7
H_RESET# 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

H_TRDY# 7

H_HIT# 7
H_HITM# 7

10/08 follow Intel suggestion to change value

R7 49.9_0402_1%
R8 0_0402_5%

R9 0_0402_5%

H_THERMTRIP# 7,27,40

CLK_CPU_BCLK 15
CLK_CPU_BCLK# 15

4

1025 For Support Dual core and Quad core

T1

Place TP with a
GND 0.1" away

Delete H_PROCHOT# off-page due to
VR doesn't have it's input pin @08/31

XDP_DBRESET# 28

1 2
1 2

1 2

H_THERMDA, H_THERMDC routing
together, Trace width / Spacing = 10 / 10
mils

H_PROCHOT# OCP#

H_IERR#

+VCCP

+VCCP

12

@

R12
56_0402_5%

B

2

E

3 1

C

Q2

@

MMBT3904_NL_SOT23-3

+VCCP

12

R1
56_0402_5%

H_THERMDA
H_THERMDC

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

XDP_BPM2#36
H_PWRGOOD5,27 CLK_CPU_XDP 15

OCP# 28

Removed at
5/30.(Follow
Chimay)

R738

C851 0.1U_0402_16V4Z

Issued Date

3

XDP_BPM#5
XDP_BPM#4

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

XDP_BPM2#0
XDP_BPM2#1

XDP_BPM2#2
XDP_BPM2#3

1K_0402_5%

H_PWRGOOD_R

1 2

XDP_HOOK1

12

XDP_TCK

+3VS

1

2

0.1U_0402_16V4Z

PWM Fan Control circuit

2006/02/13 2006/03/10

Compal Secret Data

GND1
OBSFN_C0
OBSFN_C1

GND3

GND5

GND7
OBSFN_D0
OBSFN_D1

GND9

GND11

GND13

GND15

TD0

TRST#

TDI

TMS

GND17

H_THERMDA
H_THERMDC

H_THERMDA
H_THERMDC
THERM#

+5VS

D1

2 1

6

2

1

S

4 5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

D

Q1

SI3456BDV-T1-E3_TSOP6

XDP_DBRESET#_R

XDP_TDI
XDP_TMS
XDP_TDO
XDP_BPM#5
XDP_HOOK1
XDP_TRST#
XDP_TCK

CLK_CPU_XDP
CLK_CPU_XDP#

H_RESET#_R

XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE

Place R191 within 200ps (~1")
to CPU

QC@

U78

1

VDD

2

DP1

3

DN1

4

DP2

5

DN2

EMC1403-1-AIZL-TR_MSOP10
U55

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

SMCLK

SMDATA

ALERT#

THERM#

SMCLK

SMDATA

ALERT#

Address:100_1100

1

C3

4.7U_0805_10V4Z

2

+FAN

Title

Size Document Number Rev

Custom

LA-4082P Vader Discrete

Date: Sheet

@

1 2

Change value in 5/02

R731 54.9_0402_1%

1 2

R732 54.9_0402_1%

1 2

R733 54.9_0402_1%

1 2

R734 54.9_0402_1%

1 2

R735 54.9_0402_1%@

1 2

R792 54.9_0402_1%

1 2

R737 54.9_0402_1%

1 2

This shall place near CPU

CLK_CPU_XDP# 15

+VCCP+VCCP

R739 1K_0402_1%

1 2

R740 0_0402_1%

1 2

0_0402_5%

R741

1 2

SMB_EC_CK2

10

SMB_EC_DA2

9
8

THERM#

7
6

GND

SMB_EC_CK2

8

SMB_EC_DA2

7
6
5

GND

1

C4

0.1U_0402_16V4Z

2

12

D2

@

RLZ5.1B_LL34

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

1

+3VS

1K_0402_5%

+VCCP

H_RESET#
XDP_DBRESET#XDP_DBRESET#_R

SMB_EC_CK2 20,40
SMB_EC_DA2 20,40

CONN@

JP2

1

1

2

2

3

GND

4

GND

ACES_88231-02001

458Wednesday, December 26, 2007

0.2

of

5

4

3

2

1

H_D#[0..15]7

D D

H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_D#[16..31]7

C C

* Route the T E S T 3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via th at is near a GND via and is
accessible through an oscilloscope
connection.

B B

CPU_BSEL CPU_BSEL2 CPU_BSEL1

R15 1K_0402_5%@
R16 1K_0402_5%@

166

H_DSTBN#17
H_DSTBP#17
H_DINV#17

1 2
1 2

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

T2
T3
T4
T5
T6

01

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

AD26

AF26

E22
F24
E26

G22

F23

G25

E25
E23
K24

G24

J24
J23
H22
F26
K22
H23

J26
H26
H25

N22

K25

P26

R23

L23
M24

L22
M23

P25

P23

P22

T24
R24

L25

T25
N25

L26
M26
N24

C23
D25
C24

AF1

A26

C3
B22
B23

C21

JCPUB

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

MISC

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]

Penryn

CPU_BSEL0

1

DATA GRP 0

DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#

DATA GRP 2DATA GRP 3

D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

Resistor placed within 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.

H_D#[32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,27,51

H_DPSLP# 27
H_DPWR# 7
H_PWRGOOD 4,27

H_CPUSLP# 7
H_PSI# 51

R17

54.9_0402_1%

12

R18

27.4_0402_1%

12

+VCC_CORE +VCC_CORE

R20

R19

27.4_0402_1%

54.9_0402_1%

12

12

R52 0_0402_5%DC@

1 2

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

A7

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9

C10
C12
C13
C15
C17
C18

D9

D10
D12
D14
D15
D17
D18

E7

E9

E10
E12
E13
E15
E17
E18
E20

F7

F9

F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AB9

JCPUC

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]/BR1#
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VCCSENSE

VSSSENSE

1025 For Support Dual core and Quad core

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

+VCCPA
+VCCPB

VCCSENSE

VSSSENSE

R13

1 2
1 2

R14

0_0402_5%
0_0402_5%

CPU_VID0 51
CPU_VID1 51
CPU_VID2 51
CPU_VID3 51
CPU_VID4 51
CPU_VID5 51
CPU_VID6 51

VCCSENSE 51

VSSSENSE 51

+VCCP

1

+

C5
330U_D2E_2.5VM_R7

2

1

C6

2

10U_0805_6.3V6M

1

C7

2

0.01U_0402_16V7K

Near pin B26

+1.5VS

Length match within 25 mils.

200

266

10

0000

+V_CPU_GTLREF

+VCCP

12

R21
1K_0402_1%

12

R23
2K_0402_1%

The trace width/space/other
is 20/7/25.

+VCC_CORE

R22 100_0402_1%

1 2

R24 100_0402_1%

1 2

VCCSENSE

VSSSENSE

Close to CPU pin within

A A

Close to CPU pin
AD26 within

500mils.

500mils.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

LA-4082P Vader Discrete

1

0.2

of

558Wednesday, December 26, 2007

5

D D

DC@

R2055

1 2

1 2

0_0402_5%

0_0402_5%

GTLREF2

C C

DC@

R2033

B B

JCPUD

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]/RSVD_0

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]/GTLREF_C

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]

P3

VSS[081]

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]

RSVD_1/VSS[111]

VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]

RSVD_2/VSS[129]

VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]

BPM_2#[3]/VSS[147]

VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

DC@

R2056

DC@

R2057

XDP_BPM2#3

4

1 2

1 2

DC@

0_0402_5%

0_0402_5%

R2054

1 2

0_0402_5%

3

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C8
10U_0805_6.3V6M

C16
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

Place these
capacitors on L8
(North
side,Secondary
Layer)

Place these
capacitors on L8
(North
side,Secondary
Layer)

Place these
capacitors on L8
(North
side,Secondary
Layer)

Place these
capacitors on L8
(North
side,Secondary
Layer)

Mid Frequence Decoupling

Near CPU CORE regulator

+VCC_CORE

330U_D2E_2.5VM_R7

+VCCP

1

2

C40

C45

0.1U_0402_10V6K

1

C9
10U_0805_6.3V6M

2

1

C17
10U_0805_6.3V6M

2

1

C25
10U_0805_6.3V6M

2

1

C33
10U_0805_6.3V6M

2

1

C10
10U_0805_6.3V6M

2

1

C18
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

1

C34
10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor >
1980uF

330U_D2E_2.5VM_R7

1

1

+

+

C42

@

C41

2

2

330U_D2E_2.5VM_R7

Inside CPU center cavity in 2 rows

1

C46

0.1U_0402_10V6K

2

1

2

1

+

C43

2

330U_D2E_2.5VM_R7

C47

0.1U_0402_10V6K

1

+

2

1

2

1

2

1

2

1

2

1

2

C48

0.1U_0402_10V6K

2

C11
10U_0805_6.3V6M

C19
10U_0805_6.3V6M

C27
10U_0805_6.3V6M

C35
10U_0805_6.3V6M

5

1

C49

0.1U_0402_10V6K

2

5

1

C12
10U_0805_6.3V6M

2

5

1

C20
10U_0805_6.3V6M

2

5

1

C28
10U_0805_6.3V6M

2

5

1

C36
10U_0805_6.3V6M

2

1

2

1

2

1

2

C50

0.1U_0402_10V6K

1

C13
10U_0805_6.3V6M

2

1

C21
10U_0805_6.3V6M

2

C29
10U_0805_6.3V6M

C37
10U_0805_6.3V6M

1

1

C14
10U_0805_6.3V6M

2

1

C22
10U_0805_6.3V6M

2

1

C30
10U_0805_6.3V6M

2

1

C38
10U_0805_6.3V6M

2

1

C15
10U_0805_6.3V6M

2

1

C23
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

1025 For Support Dual core and Quad core

A A

GTLREF2
XDP_BPM2#3

5

GTLREF2 4
XDP_BPM2#3 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

LA-4082P Vader Discrete

1

0.2

of

658Wednesday, December 26, 2007

5

H_D#[0..63]5

D D

C C

H_RESET#4

H_CPUSLP#5

B B

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+H_SWNG
H_RCOMP

H_RESET#
H_CPUSLP#

+H_VREF

layout note:
Route H_SCOMP and H_SCOMP# with trace width,

spacing and impedance (55 ohm) same as FSB data
traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

12

R39

1K_0402_1%

A A

12

2K_0402_1%

+H_VREF +H_SWNG

1

R46

C58

2

0.1U_0402_16V4Z

U57A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32

AD14

H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41

AA13

H_D#_42

AA9

H_D#_43

AA11

H_D#_44

AD11

H_D#_45

AD10

H_D#_46

AD13

H_D#_47

AE12

H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54

AE14

H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59

AE11

H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

H_RCOMP

12

R47

24.9_0402_1%

+VCCP

12

221_0603_1%

12

100_0402_1%

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

HOST

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

R40

1

R48

C59

2

0.1U_0402_16V4Z

Near B3 pinwithin 100 mils from NB

5

4

H_A#3

A14

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#
H_DBSY#

H_DRDY#

H_HIT#
H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H_ADS#

H12

H_ADSTB#0

B16

H_ADSTB#1

G17

H_BNR#

A9

H_BPRI#

F11

H_BR0#

G12

H_DEFER#

E9

H_DBSY#

B10

CLK_MCH_BCLK

AH7

CLK_MCH_BCLK#

AH6

H_DPWR#

J11

H_DRDY#

F9

H_HIT#

H9

H_HITM#

E12

H_LOCK#

H11

H_TRDY#

C9

H_DINV#0

J8

H_DINV#1

L3

H_DINV#2

Y13

H_DINV#3

Y1

H_DSTBN#0

L10

H_DSTBN#1

M7

H_DSTBN#2

AA5

H_DSTBN#3

AE6

H_DSTBP#0

L9

H_DSTBP#1

M8

H_DSTBP#2

AA6

H_DSTBP#3

AE5

H_REQ#0

B15

H_REQ#1

K13

H_REQ#2

F13

H_REQ#3

B13

H_REQ#4

B14

H_RS#0

B6

H_RS#1

F12

H_RS#2

C8

Layout Note: V_DDR_MCH_REF trace
width and spacing is 20/20.

+V_DDR_MCH_REF generated by DC-DC

+V_DDR_MCH_REF13,14

4

H_A#[3..35] 4

SMRCOMP_VOH

80% of 1.8V VCC_SM

20% of 1.8V VCC_SM

SMRCOMP_VOL

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

PLT_RST#18,26,31,32,33,35

H_THERMTRIP#4,27,40

DPRSLPVR28,51

+V_DDR_MCH_REF

1

2

0.1U_0402_16V4Z

3

T7
T8
T9

+1.8V

1

1

C52

0.01U_0402_25V7K

2

1

C54

2

0.01U_0402_25V7K

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_7

R943
R35

+1.8V

12

R38
1K_0402_1%

12

R41
1K_0402_1%

12

R25
1K_0402_1%

12

R26

3.01K_0402_1%

12

R27
1K_0402_1%

R32 10K_0402_5%

1 2

R33 10K_0402_5%

1 2

R34 10K_0402_5%

1 2

MCH_CLKSEL015
MCH_CLKSEL115
MCH_CLKSEL215

CFG59
CFG69
CFG79
CFG89

CFG99
CFG109
CFG119
CFG129
CFG139
CFG149
CFG159
CFG169
CFG179
CFG189
CFG199
CFG209

PM_BMBUSY#28

H_DPRSTP#5,27,51
PM_EXTTS#013
PM_EXTTS#114
PM_PWROK28,40

1 2

100_0402_5%

1 2

0_0402_5%

C51

2.2U_0603_6.3V4Z

2

1

C53

2

2.2U_0603_6.3V4Z

C57

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20

T21
T22
T23

T24

T26
T27
T28
T29

+3VS

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK

THERMTRIP#
DPRSLPVR

@

1

C55

2

0.1U_0402_16V4Z

2006/02/13 2006/03/10

U57B

M36

RESERVED

N36

RESERVED

R33

RESERVED

T33

RESERVED

AH9

RESERVED

AH10

RESERVED

AH12

RESERVED

AH13

RESERVED

K12

RESERVED

AL34

RESERVED

AK34

RESERVED

AN35

RESERVED

AM35

RESERVED

T24

RESERVED

B31

RESERVED

B2

RESERVED

M1

RESERVED

AY21

RESERVED

BG23

RESERVED

BF23

RESERVED

BH18

RESERVED

BF18

RESERVED

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC

BF48

NC

BD48

NC

BC48

NC

BH47

NC

BG47

NC

BE47

NC

BH46

NC

BF46

NC

BG45

NC

BH44

NC

BH43

NC

BH6

NC

BH5

NC

BG4

NC

BH3

NC

BF3

NC

BH2

NC

BG2

NC

BE2

NC

BG1

NC

BF1

NC

BD1

NC

BC1

NC

F1

NC

A47

NC

CANTIGA ES_FCBGA1329

Compal Secret Data

Deciphered Date

RSVD

CFG

PM

NC

2

M_CLK_DDR0

AP24

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

DMI

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

MEHDA

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

MISC

HDA_BCLK
HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

+V_DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17

TP_SM_DRAMRST#

BC36
B38

A38
E41
F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33
B32
G33
F33
E33

C34

CL_CLK0

AH37

CL_DATA0

AH36

M_PWROK

AN36

CL_RST#

AJ35

+CL_VREF

AH34

0621 add CLK and DAT for DVI

N28
M28
G36
E36

CLKREQ#_7

K36

MCH_ICH_SYNC#

H36

TSATN#

B12

B28
B30
B29
C29
A28

56_0402_5%

1 2

R42

0830 Add pull-up and pull-down resistor.

Title

Size Document Number Rev

Custom

LA-4082P Vader Discrete

2

Date: Sheet

1

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14

DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

R28 80.6_0402_1%

1 2

R29 80.6_0402_1%

1 2

Follow Design Guide
For Cantiga: 80.6ohm

1009 Follow Design Guide

R30 0_0402_5%

1 2

R31 499_0402_1%

1 2

T30 PAD

1015 Follow Design Guide

CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15

DMI_TXN0 28
DMI_TXN1 28
DMI_TXN2 28
DMI_TXN3 28

DMI_TXP0 28
DMI_TXP1 28
DMI_TXP2 28
DMI_TXP3 28

DMI_RXN0 28
DMI_RXN1 28
DMI_RXN2 28
DMI_RXN3 28

DMI_RXP0 28
DMI_RXP1 28
DMI_RXP2 28
DMI_RXP3 28

T31
T32
T33
T34
T35

T36

T37
T38

0906 delete

CL_CLK0 28
CL_DATA0 28
M_PWROK 28,40
CL_RST# 28

0.1U_0402_16V4Z

CLKREQ#_7 15
MCH_ICH_SYNC# 28

+VCCP

+VCCP

1

C56

2

*R37*Follow Intel
feedback

Delete Off-page
@1028

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

1

+1.8V

12

R36
1K_0402_1%

12

R37
499_0402_1%

758Wednesday, December 26, 2007

0.2

of

5

D D

DDR_A_D[0..63]13

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U57D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA ES_FCBGA1329

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

4

DDR_A_BS0

BD21
BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0 13
DDR_A_BS1 13
DDR_A_BS2 13

DDR_A_RAS# 13
DDR_A_CAS# 13
DDR_A_WE# 13

DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..14] 13

3

DDR_B_D[0..63]14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40

DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U57E

AK47
AH46
AP47
AP46
AJ46
AJ48

AM48

AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8
BH12
BF11

BF8

BG7

BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1

AH1
AM2
AM3

AH3

AJ3

CANTIGA ES_FCBGA1329

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

2

DDR_B_BS0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3DDR_B_D41
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

1

DDR_B_BS0 14
DDR_B_BS1 14
DDR_B_BS2 14

DDR_B_RAS# 14
DDR_B_CAS# 14
DDR_B_WE# 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..14] 14

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

LA-4082P Vader Discrete

1

0.2

of

858Wednesday, December 26, 2007

5

4

3

2

1

U57C

PEGCOMP tr ace width
and spacing is 20/25 mils.

PEG_RXN0 18
PEG_RXN1 18
PEG_RXN2 18
PEG_RXN3 18
PEG_RXN4 18
PEG_RXN5 18
PEG_RXN6 18
PEG_RXN7 18
PEG_RXN8 18
PEG_RXN9 18
PEG_RXN10 18
PEG_RXN11 18
PEG_RXN12 18
PEG_RXN13 18
PEG_RXN14 18
PEG_RXN15 18

PEG_RXP0 18
PEG_RXP1 18
PEG_RXP2 18
PEG_RXP3 18
PEG_RXP4 18
PEG_RXP5 18
PEG_RXP6 18
PEG_RXP7 18
PEG_RXP8 18
PEG_RXP9 18
PEG_RXP10 18
PEG_RXP11 18
PEG_RXP12 18
PEG_RXP13 18
PEG_RXP14 18
PEG_RXP15 18

PEG_M_TXN0 18
PEG_M_TXN1 18
PEG_M_TXN2 18
PEG_M_TXN3 18
PEG_M_TXN4 18
PEG_M_TXN5 18
PEG_M_TXN6 18
PEG_M_TXN7 18
PEG_M_TXN8 18
PEG_M_TXN9 18
PEG_M_TXN10 18
PEG_M_TXN11 18
PEG_M_TXN12 18
PEG_M_TXN13 18
PEG_M_TXN14 18
PEG_M_TXN15 18

PEG_M_TXP0 18
PEG_M_TXP1 18
PEG_M_TXP2 18
PEG_M_TXP3 18
PEG_M_TXP4 18
PEG_M_TXP5 18
PEG_M_TXP6 18
PEG_M_TXP7 18
PEG_M_TXP8 18
PEG_M_TXP9 18
PEG_M_TXP10 18
PEG_M_TXP11 18
PEG_M_TXP12 18
PEG_M_TXP13 18
PEG_M_TXP14 18
PEG_M_TXP15 18

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

D D

C C

B B

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

LVDS

TV VGA

PEG_COMPI

PEG_COMPO

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13

PCI-EXPRESS GRAPHICS

PEG_TX#_14
PEG_TX#_15

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

R50

PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15

PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

1 2

C1289 0.1U_0402_16V4Z
C1290 0.1U_0402_16V4Z
C1291 0.1U_0402_16V4Z
C1292 0.1U_0402_16V4Z
C1293 0.1U_0402_16V4Z
C1294 0.1U_0402_16V4Z
C1295 0.1U_0402_16V4Z
C1296 0.1U_0402_16V4Z
C1297 0.1U_0402_16V4Z
C1298 0.1U_0402_16V4Z
C1299 0.1U_0402_16V4Z
C1300 0.1U_0402_16V4Z
C1301 0.1U_0402_16V4Z
C1302 0.1U_0402_16V4Z
C1303 0.1U_0402_16V4Z
C1304 0.1U_0402_16V4Z

C1305 0.1U_0402_16V4Z
C1306 0.1U_0402_16V4Z
C1307 0.1U_0402_16V4Z
C1308 0.1U_0402_16V4Z
C1309 0.1U_0402_16V4Z
C1310 0.1U_0402_16V4Z
C1311 0.1U_0402_16V4Z
C1312 0.1U_0402_16V4Z
C1313 0.1U_0402_16V4Z
C1314 0.1U_0402_16V4Z
C1315 0.1U_0402_16V4Z
C1316 0.1U_0402_16V4Z
C1317 0.1U_0402_16V4Z
C1318 0.1U_0402_16V4Z
C1319 0.1U_0402_16V4Z
C1320 0.1U_0402_16V4Z

49.9_0402_1%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

+VCC_PEG

CFG[2:0] FSB Freq select

CFG[4:3] Reserved

CFG5 (DMI select)

CFG6

CFG6

CFG7 (Intel Management
Engine Crypto strap)

CFG8

CFG9
(PCIE Graphics Lane Reversal)

CFG10 (PCIE Lookback enable)

CFG11
CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

CFG19 (DMI Lane Reversal)

CFG20 (PCIE/SDVO concurrent)

+3VS

R59

4.02K_0402_1%

CFG57

CFG5

@

R63

2.21K_0402_1%

12

12

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

1 = The iTPM Host Interface is disable
0 =(TLS)chip e r s u i t e with no confidentiality

Selected By CPU

*

*

1 =(TLS)chip e r s uite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in order

0 = Enable
1 = Disable
Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

*

ReservedCFG[15:14]

(Default)11 = Normal Operation

*

*

0 = Disabled
1 = Enabled

*

ReservedCFG[18:17]

0 = Normal Operation

(Lane number in Order)

*

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.

*

1 = PCIE/SDVO a r e o p e r a t ing simu.

R65

R68

R71

R74

R77

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%@

1 2

2.21K_0402_1%@

1 2

2.21K_0402_1%@

1 2

2.21K_0402_1%

CFG77

CFG97

CFG107

CFG117

CFG127

*

Strap Pin Table

+3VS

R64

CFG197

CFG207

CFG167

CFG67

CFG87 CFG187

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

2

1 2

4.02K_0402_1%@

R67

1 2

4.02K_0402_1%@

R70

1 2

4.02K_0402_1%

R73

1 2

2.21K_0402_1%@

R76

1 2

2.21K_0402_1%@

Title

Size Document Number Rev

Custom

LA-4082P Vader Discrete

Date: Sheet

CFG137

CFG147

CFG157

CFG177

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

R66

1 2

2.21K_0402_1%

R69

1 2

2.21K_0402_1%@

R72

1 2

2.21K_0402_1%@

R75

1 2

2.21K_0402_1%@

R78

1 2

2.21K_0402_1%@

0.2

of

958Wednesday, December 26, 2007

1

5

4

3

2

1

U57H

73mA

B27

VCCA_CRT_DAC

A26

VCCA_CRT_DAC

2.68mA

A25

VCCA_DAC_BG

B25

D D

+1.05VS_HPLL
+1.05VS_MPLL

R87

@

1 2

+3VS

0_0603_5%

R88

1 2

+1.5VS

0_0603_5%

+VCCP

R91

R94

1 2

0_0805_5%

1 2

0_0603_5%

1U_0603_10V4Z

C C

10/08 add this power rail

B B

1

C122

0.1U_0402_16V4Z

2

+1.05VS_A_SM

10U_0805_10V4Z

+1.05VS_A_SM_CK

1

C135

2

10U_0805_10V4Z

+1.5VS_PEG_BG

1

C128

2

1U_0603_10V4Z

1

C136

2

4.7U_0805_10V4Z

1

C129

2

1

C137

2

+1.05VS_HPLL
+1.05VS_PEGPLL

+1.05VS_PEGPLL

1

C130

2

1U_0603_10V4Z

1

C138

2

0.1U_0402_16V4Z

R2090 0_0402_5%

1 2

+1.5VS_TVDAC

+1.5VS_QDAC

1212 Montevina DG

+1.5VS_QDAC

0.01U_0402_16V7K

C2116

1

2

C2117

0.1U_0402_16V4Z

1

2

R2093

1 2

100_0603_1%

+1.5VS

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

414uA

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM_CK

AN28

VCCA_SM_CK

AP25

VCCA_SM_CK

AN25

VCCA_SM_CK

AN24

VCCA_SM_CK

AM28

VCCA_SM_CK_NCTF

AM26

VCCA_SM_CK_NCTF

AM25

VCCA_SM_CK_NCTF

AL25

VCCA_SM_CK_NCTF

AM24

VCCA_SM_CK_NCTF

AL24

VCCA_SM_CK_NCTF

AM23

VCCA_SM_CK_NCTF

AL23

VCCA_SM_CK_NCTF

B24

VCCA_TV_DAC

A24

VCCA_TV_DAC

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS

L37

VCCD_LVDS

60.31mA

CANTIGA ES_FCBGA1329

64.8mA

64.8mA
24mA

139.2mA

720mA

26mA

26mA

TVA 24.15mA
TVB 39.48mA
TVX 24.15mA

50mA

58.67mA

48.363mA

157.2mA
50mA

CRTPLLA PEGA SMTV

A LVDSHDA

POWER

A CK

105.3mA

1732mA

D TV/CRT

LVDS

852mA

AXF

SM CK

118.8mA

VCC_TX_LVDS

HV

PEG

DMI

456mA

VTT

321.35mA

VCC_AXF
VCC_AXF
VCC_AXF

124mA

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

VCC_HV
VCC_HV
VCC_HV

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI

VTTLF
VTTLF
VTTLF

VTTLF

+VCCP

U13

VTT

T13

VTT

U12

VTT

T12

VTT

U11

VTT

T11

VTT

U10

VTT

T10

VTT

U9

VTT

T9

VTT

U8

VTT

T8

VTT

U7

VTT

T7

VTT

U6

VTT

T6

VTT

U5

VTT

T5

VTT

V3

VTT

U3

VTT

V2

VTT

U2

VTT

T2

VTT

V1

VTT

U1

VTT

B22
B21
A21

BF21
BH20
BG20
BF20

K47
C35

B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

C143

0.47U_0603_10V7K

+V1.05VS_AXF

+1.8V_SM_CK

+VCC_PEG

+1.05VS_DMI

0.47U_0603_10V7K

C144

1

2

1

C107

+

2

1

C113

2

1

2

4.7U_0805_10V4Z

220U_6.3V_M

C110

1

2

2.2U_0805_16V4Z

4.7U_0805_10V4Z

0.47U_0603_10V7K

0.47U_0603_10V7K

C145

C114

+3VS_HV

1

2

1

2

C139

0.1U_0402_16V4Z

1

2

1

C115

2

+1.05VS_HPLL

0.1U_0402_16V4Z

+1.05VS_MPLL

0.1U_0402_16V4Z

+1.05VS_PEGPLL

0.1U_0402_16V4Z

C123

C133

C140

1

2

1

2

1

2

1

C124
10U_0805_10V4Z

2

1

C134
10U_0805_10V4Z

2

L7

1 2

BLM18PG121SN1D_0603

1

C141

2

10U_0805_10V4Z

R89

1 2

MBK2012121YZF_0805

R93

1 2

MBK2012121YZF_0805

D3

2 1

+VCCP

CH751H-40PT_SOD323-2

+3VS

10U_0805_10V4Z

+VCCP

0.1U_0402_16V4Z

+VCCP

+VCCP

+VCCP_D

+V1.05VS_AXF

1

2

1U_0603_10V4Z

10U_0805_10V4Z

1

C117

2

0.1U_0402_16V4Z

1

C125
10U_0805_10V4Z

2

1

1

2

2

R95

1 2

0_0603_5%

1

C142

0.1U_0402_16V4Z

2

1

C109

2

1

C118

2

R90

1 2

0_0805_5%

R92

1 2

C132
10U_0805_10V4Z

+VCCP

+3VS_HV

C108

10U_0805_10V4Z

+1.8V_SM_CK

@

1

C116

2

+1.5VS_TVDAC +1.5VS

1

C126

2

+VCC_PEG

+

C131

220U_6.3V_M

+1.05VS_DMI

R96

1 2

10_0402_5%

R97

1 2

0_0402_5%

R82

1 2

0_0603_5%

R85

1 2

0_0805_5%

0_0805_5%

+VCCP

+1.8V

+VCCP

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(4/6)-PWR

LA-4082P Vader Discrete

1

0.2

of

10 58Wednesday, December 26, 2007

5

+VCCP

D D

0.1U_0402_16V4Z

0.22U_0402_10V4Z

220U_6.3V_M

C162

C C

B B

0.22U_0402_10V4Z

10U_0805_10V4Z

1

C163

C164

1

+

2

1

2

2

C166

C165

1

1

2

2

U57F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33

VCC

AC33

VCC

AA33

VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC

AH28

VCC

AF28

VCC

AC28

VCC

AA28

VCC

AJ26

VCC

AG26

VCC

AE26

VCC

AC26

VCC

AH25

VCC

AG25

VCC

AF25

VCC

AG24

VCC

AJ23

VCC

AH23

VCC

AF23

VCC

T32

VCC

CANTIGA ES_FCBGA1329

4

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

VCC CORE

AM32

VCC_NCTF

AL32

VCC_NCTF

AK32

VCC_NCTF

AJ32

VCC_NCTF

AH32

VCC_NCTF

AG32

VCC_NCTF

AE32

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

POWER

VCC NCTF

+VCCP

+1.8V

3

C158

330U_4V_M

10U_0805_10V4Z

1

1

+

2

2

0317 change value

C159

2

U57G

3000mA

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

0.01U_0402_16V7K

10U_0805_10V4Z

C161

C160

1

1

2

2

T43PAD
T44PAD

BF32
BD32
BC32
BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21
AG21
AE21
AC21
AA21

AH20
AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15
AH15
AG15
AF15
AB15
AA15

AN14

AM14

AJ14
AH14

Y26

Y24

Y21

T17
T16

Y15
V15

U15

U14

T14

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC

6326.84mA

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC SMVCC GFX

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

POWER

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC GFX NCTF

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC SM LF

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

1

2

1

C178 0.1U_0402_16V4Z

C177 0.1U_0402_16V4Z

1

1

2

2

C174 0.47U_0402_6.3V6K

C172 0.22U_0603_10V7K

1

2

C175 1U_0603_10V4Z

C173 0.22U_0603_10V7K

1

2

C176 1U_0603_10V4Z

1

1

2

2

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

CANTIGA ES_FCBGA1329

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

LA-4082P Vader Discrete

1

0.2

of

11 58Wednesday, December 26, 2007

5

4

3

2

1

U57I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

D D

C C

B B

A A

VSS

AD47

VSS

AB47

VSS

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA ES_FCBGA1329

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

U57J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17

VSS

M17

VSS

H17

VSS

C17

VSS

BA16

VSS

AU16

VSS

AN16

VSS

N16

VSS

K16

VSS

G16

VSS

E16

VSS

BG15

VSS

AC15

VSS

W15

VSS

A15

VSS

BG14

VSS

AA14

VSS

C14

VSS

BG13

VSS

BC13

VSS

BA13

VSS

AN13

VSS

AJ13

VSS

AE13

VSS

N13

VSS

L13

VSS

G13

VSS

E13

VSS

BF12

VSS

AV12

VSS

AT12

VSS

AM12

VSS

AA12

VSS

J12

VSS

A12

VSS

BD11

VSS

BB11

VSS

AY11

VSS

AN11

VSS

AH11

VSS

Y11

VSS

N11

VSS

G11

VSS

C11

VSS

BG10

VSS

AV10

VSS

AT10

VSS

AJ10

VSS

AE10

VSS

AA10

VSS

M10

VSS

BF9

VSS

BC9

VSS

AN9

VSS

AM9

VSS

AD9

VSS

G9

VSS

B9

VSS

BH8

VSS

BB8

VSS

AV8

VSS

AT8

VSS

CANTIGA ES_FCBGA1329

VSS

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS NCTF

VSS_NCTF
VSS_NCTF

VSS SCB

NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS

VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB

AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4

BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1

U24
U28
U25
U29

AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17

BH48
BH1
A48
C1
A3

E1

NC

D2

NC

C3

NC

B4

NC

A5

NC

A6

NC

A43

NC

A44

NC

B45

NC

C46

NC

D47

NC

B47

NC

A46

NC

F48

NC

E48

NC

C48

NC

B48

NC

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

LA-4082P Vader Discrete

1

0.2

of

12 58Wednesday, December 26, 2007

5

DDR_A_DQS#[0..7]8
DDR_A_D[0..63]8
DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..14]8

D D

C C

B B

A A

Layout Note:
Place near
JP3

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

Layout Note:
Place one cap close to every
2 pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_A_MA8
DDR_A_MA5

DDR_A_MA1
DDR_A_MA3

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_BS0
DDR_A_MA10

DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

DDR_A_MA11

1

2

1

2

C182

C191

1

2

0.1U_0402_16V4Z

1

2

C192

R108 56_0402_5%

5

C183

0.1U_0402_16V4Z

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

1 2

1

2

RP156_0404_4P2R_5%

RP356_0404_4P2R_5%

RP556_0404_4P2R_5%

RP756_0404_4P2R_5%

RP956_0404_4P2R_5%

RP1156_0404_4P2R_5%

2.2U_0805_16V4Z

C193

2.2U_0805_16V4Z

C184

1

2

0.1U_0402_16V4Z

1

2

C194

+0.9V

C186

1

2

0.1U_0402_16V4Z

1

1

2

2

C197

C196

DDR_A_BS2

14

DDR_CKE0_DIMMA

23

DDR_A_MA7

14

DDR_A_MA6

23

DDR_A_MA9

14

DDR_A_MA12

23

DDR_A_MA4

14

DDR_A_MA2

23

DDR_A_MA0

14

DDR_A_BS1

23

M_ODT0

14

DDR_A_MA13

23

DDR_CKE1_DIMMA

14

DDR_A_MA14

23

0.1U_0402_16V4Z
C187

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C198

2.2U_0805_16V4Z

C185

1

2

510

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C195

RP2 56_0404_4P2R_5%

RP4 56_0404_4P2R_5%

RP6 56_0404_4P2R_5%

RP8 56_0404_4P2R_5%

RP10 56_0404_4P2R_5%

RP12 56_0404_4P2R_5%

RP13 56_0404_4P2R_5%

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C188

1

2

0.1U_0402_16V4Z

1

2

C199

1

2

C200

0.1U_0402_16V4Z

C189

C190

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C201

C202

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

1

+

C181
330U_D2_2.5VM_R15

2

1113 Change type for layout

0.1U_0402_16V4Z

1

2

C203

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9 DDR_A_D11
DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA7

DDR_A_BS28

DDR_A_BS08

DDR_A_WE#8

DDR_A_CAS#8
DDR_CS1_DIMMA#7

M_ODT17

CLK_SMBDATA14,15
CLK_SMBCLK14,15

+3VS

3

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1
DDR_A_D37

DDR_A_D36
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D32
DDR_A_D40

DDR_A_D44
DDR_A_DM5
DDR_A_D41

DDR_A_D46
DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60
DDR_A_DM7
DDR_A_D59

DDR_A_D58
CLK_SMBDATA

CLK_SMBCLK

1

2

2.2U_0603_6.3V4Z

2006/02/13 2006/03/10

C204

C205

Compal Secret Data

1

2

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

0.1U_0402_16V4Z

Deciphered Date

+V_DDR_MCH_REF

JDIMM1

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
G1

FOX_AS0A426-N4RN-7F~D

SO-DIMM A

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

+1.8V

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

G2

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_A_DM2
DDR_A_D23

DDR_A_D22
DDR_A_D28DDR_A_D29

DDR_A_D25DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D31

DDR_A_D30
DDR_CKE1_DIMMA

DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D39
DDR_A_D38

DDR_A_DM4
DDR_A_D34

DDR_A_D33
DDR_A_D45

DDR_A_D43
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D47

DDR_A_D42
DDR_A_D52

DDR_A_D53
M_CLK_DDR1

M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51DDR_A_D54

DDR_A_D55

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12

R107

R106

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C179

1

2

M_CLK_DDR0 7
M_CLK_DDR#0 7

PM_EXTTS#0 7

DDR_CKE1_DIMMA 7

DDR_A_BS1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

LA-4082P Vader Discrete

1

C180

1

+V_DDR_MCH_REF 7,14

of

13 58Wednesday, December 26, 2007

0.2

0.1U_0402_16V4Z

1

2

5

DDR_B_DQS#[0..7]8
DDR_B_D[0..63]8
DDR_B_DM[0..7]8
DDR_B_DQS[0..7]8
DDR_B_MA[0..14]8

D D

C C

B B

A A

Layout Note:
Place near
JP10

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C208

1

2

Layout Note:
Place one cap close to every
2 pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

1

2

C217

DDR_B_MA1
DDR_B_MA3

DDR_B_BS0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

DDR_CKE3_DIMMB

C209

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C218

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

1 2

R111 56_0402_5%

5

1

2

RP1456_0404_4P2R_5%

RP1656_0404_4P2R_5%

RP1856_0404_4P2R_5%

RP2056_0404_4P2R_5%

RP2256_0404_4P2R_5%

RP2456_0404_4P2R_5%

2.2U_0805_16V4Z

C219

C210

1

2

0.1U_0402_16V4Z

1

2

C220

+0.9V

5

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C212

C211

1

1

2

2

330U_4V_M

510

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C221

C222

RP15 56_0404_4P2R_5%

14
23

RP17 56_0404_4P2R_5%

14
23

RP19 56_0404_4P2R_5%

14
23

RP21 56_0404_4P2R_5%

14
23

RP23 56_0404_4P2R_5%

14
23

RP25 56_0404_4P2R_5%

14
23

RP26 56_0404_4P2R_5%

14
23

0.1U_0402_16V4Z

1

+

C244

2

0.1U_0402_16V4Z

1

1

2

2

C224

C223

DDR_B_MA9
DDR_B_MA12

DDR_B_MA14
DDR_B_MA11

DDR_B_MA5
DDR_B_MA8

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA13

DDR_B_BS2
DDR_CKE2_DIMMB

0.1U_0402_16V4Z

C213

1

2

0.1U_0402_16V4Z

1

2

C225

4

0.1U_0402_16V4Z

C214

C215

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C227

C226

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

4

3

+1.8V

+V_DDR_MCH_REF

JDIMM2

1

VREF

3

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

0.1U_0402_16V4Z

Deciphered Date

5
7
9

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

SO-DIMM B

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

0.1U_0402_16V4Z
C216

1

2

DDR_CKE2_DIMMB7

DDR_B_BS28

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C229

C228

DDR_B_BS08
DDR_B_WE#8

DDR_B_CAS#8

DDR_CS3_DIMMB#7

M_ODT37

CLK_SMBDATA13,15
CLK_SMBCLK13,15

+3VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_D20
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7
DDR_B_D59

DDR_B_D58
CLK_SMBDATA

CLK_SMBCLK

1

C230

2

2.2U_0603_6.3V4Z

2006/02/13 2006/03/10

1

C231

2

Compal Secret Data

2

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

NC
DM2
VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

A7

A6
VDD

A4

A2

A0
VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

NC
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS
CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS

SA0
SA1

G1

FOX_AS0A426-N8RN-7F

201G2202

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+1.8V

DDR_B_D5
DDR_B_D4

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1
M_CLK_DDR2

M_CLK_DDR#2
DDR_B_D14

DDR_B_D15

DDR_B_D21DDR_B_D17
DDR_B_D16

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D26

DDR_B_D24DDR_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D29

DDR_B_D27
DDR_CKE3_DIMMB

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D39

DDR_B_D38
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
M_CLK_DDR3

M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

1

+V_DDR_MCH_REF 7,13

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

1

C207

C206

2

2

M_CLK_DDR2 7
M_CLK_DDR#2 7

PM_EXTTS#1 7

DDR_CKE3_DIMMB 7

0612 add

DDR_B_BS1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2 7

M_CLK_DDR3 7
M_CLK_DDR#3 7

R109

1 2

10K_0402_5%

12

10K_0402_5%

R110

Title

Size Document Number Rev

Custom

Date: Sheet

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

LA-4082P Vader Discrete

1

0.2

of

14 58Wednesday, December 26, 2007

5

PCI

SRC

CPU

CLKSEL1

0

FSA

CLKSEL0

MHz

266

MHz

1000

MHz

MHz

33.30

14.318 96.0 48.0

DOT_96
MHz

FSC FSB REF

CLKSEL2

01000 133 33.31 14.318 96.0 48.0

01001 200 33.30 14.318 96.0 48.0

D D

01001 166 33.31 14.318 96.0 48.0

11000 333 33.30 14.318 96.0 48.0

11000 100 33.31 14.318 96.0 48.0

11001 400 33.30 14.318 96.0 48.0

111

12

CLRP1

R121

FSA

1 2

2.2K_0402_5%
R124

CPU_BSEL05

C C

CPU_BSEL15

B B

CPU_BSEL25

ITP_EN

PCI_CLK3

A A

1 2

0_0402_5%

FSB

R151

1 2

0_0402_5%

R170

FSC

1 2

10K_0402_5%
R174

1 2

0_0402_5%

0 = SRC8/SRC8#
1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
1 = Enable SRC0 & 27MHz(DIS)

+3VS +3VS

12

@

R176
10K_0402_5%

12

R179
10K_0402_5%

NO SHORT PADS

1 2

R122
1K_0402_5%

12

@

R130
1K_0402_5%

+VCCP

@

R142
1K_0402_5%

1 2

1 2

R148
1K_0402_5%

12

@

R154

0_0402_5%

+VCCP

12

@

R169
1K_0402_5%

1 2

R171
1K_0402_5%

12

@

R175
0_0402_5%

ITP_EN PCI_CLK3

5

Reserved

R118

1 2

56_0402_5%

MCH_CLKSEL0 7

MCH_CLKSEL1 7

1025 Add R127 to meet Intel CLK design

MCH_CLKSEL2 7

12

R178
10K_0402_5%

12

@

R181
10K_0402_5%

+VCCP

CLK_DEBUG_PORT139
CLK_DEBUG_PORT032
CLK_PCI_EC40

CLK_PCI_ICH26

VGA (Discrete)

CLK_ENABLE#51

CK_PWRGD28

CLK_14M_ICH28

CLK_SMBDATA13,14
CLK_SMBCLK13,14

VGATE28,51

USB
MHz

4

Routing the t race at least 10mil

18P_0402_50V8J

CLKREQ#_77

NB
CPU

R119 0_0402_5%@

1 2

R120 0_0402_5%@

1 2

R123 0_0402_5%

1 2

R140 33_0402_1%

1 2

@

R127 33_0402_1%

1 2

R126 33_0402_1%

1 2

R131 33_0402_1%

1 2

R133 33_0402_1%

1 2

CLK_48M_ICH28

CLK_PCIE_VGA18
CLK_PCIE_VGA#18

SB, MINI PCI

4

R112

1 2

+3VS

0_0805_5%

03/02 change

CLK_XTAL_OUT
CLK_XTAL_IN

Y1

14.31818MHZ_16P

12

2

C251

2

C252

1

18P_0402_50V8J

1

Vendor suggests 22pF

R863 475_0402_1%

1 2

CLK_MCH_BCLK7
CLK_CPU_BCLK#4
CLK_CPU_BCLK4

R_CKPWRGD
FSB

CLK_XTAL_OUT
CLK_XTAL_IN

FSC
CLK_SMBDATA

CLK_SMBCLK

PCI2_TME
27_SEL
PCI_CLK3
ITP_EN

R136 33_0402_1%

1 2

CLK_PCIE_VGA
CLK_PCIE_VGA#

ICH_SMBDATA28,32,35,39

ICH_SMBCLK28,32,35,39

R2006 0_0402_5%
R2007 0_0402_5%

3

3

+3VS_CK505

+3VS_CK505

CLK_VGA
CLK_VGA#

3

72

VDD_CPU

1

C235

0.1U_0402_16V4Z

2

+VCCP

70

67

66

69

71

68

CPU_0

CPU_1

CPU_0#

CPU_1#

VSS_CPU

VDD_CPU_IO

VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_96

24

+3VS

R158

2.2K_0402_5%

2006/02/13 2006/03/10

1

C234
10U_0805_10V4Z

2

R_CLKREQ#_7
CLK_MCH_BCLK#
CLK_MCH_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK

U51

+3VS_CK505

1

CKPWRGD/PD#

2

FS_B/TEST_MODE

3

VSS_REF

4

XTAL_OUT

5

XTAL_IN

6

VDD_REF

7

REF_0/FS_C/TEST_

8

REF_1

9

SDA

10

SCL

11

NC

12

VDD_PCI

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

+3VS_CK505

FSA

+1.05VS_CK505

1 2
1 2

+3VS

+3VS

2

6 1

5

2N7002DW-7-F_SOT363-6
Q75A

4

2N7002DW-7-F_SOT363-6
Q75B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C236

0.1U_0402_16V4Z

2

R113

1 2

0_0805_5%

+1.05VS_CK505

64

65

CLKREQ_7#

SRC_0#/DOT_96#

25

1

C245

2

10U_0805_10V4Z

63

60

56

62

58

59

61

57

SRC_7

SRC_6

SRC_7#

VSS_SRC

CLKREQ_6#

VDD_SRC_IO

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

VSS_IO26VDD_PLL327LCDCLK/27M28LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#

+1.05VS_CK505

27M_SSC_CLOCK
27M_CLK_CLOCK

R159

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

Compal Secret Data

1

C237

0.1U_0402_16V4Z

2

Place close to U51

0.1U_0402_16V4Z

1

C246

2

0.1U_0402_16V4Z

CLK_SRC
CLK_SRC#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
R_CLKREQ#_6

+3VS_CK505

55

SRC_6#

VDD_SRC

PCI_STOP#

CPU_STOP#

VDD_SRC_IO

SRC_10#

SRC_10

CLKREQ_10#

SRC_11

SRC_11#

CLKREQ_11#

SRC_9#

SRC_9

CLKREQ_9#

VSS_SRC

CLKREQ_4#

SRC_4#

SRC_4

VDD_SRC_IO

CLKREQ_3#

SLG8SP553VTR_QFN72_10x10

36

CLK_PCIE_SATA#
CLK_PCIE_SATA

CLK_PCIE_ICH#
CLK_PCIE_ICH

1 2
1 2

1212 Add R and R

Deciphered Date

2

1

C238

0.1U_0402_16V4Z

2

10U_0805_10V4Z

1

2

1 2
1 2
1 2
1 2

1 2

+1.05VS_CK505

H_STP_PCI#
H_STP_CPU#

CLK_PCIE_MCARD0#
CLK_PCIE_MCARD0
R_CLKREQ#_10
CLK_PCIE_MCARD1
CLK_PCIE_MCARD1#
R_CLKREQ#_11
CLK_PCIE_LAN#
CLK_PCIE_LAN
R_CLKREQ#_9

R_CLKREQ#_4
CLK_PCIE_NCARD#
CLK_PCIE_NCARD

R_CLKREQ#_C

CLK_PCIE_SATA# 27
CLK_PCIE_SATA 27

CLK_PCIE_ICH# 28
CLK_PCIE_ICH 28

2

C248

27M_SSC
27M_CLK

1

C247

2

R2002 0_0402_5%
R2003 0_0402_5%
R2004 0_0402_5%@
R2005 0_0402_5%@

R862 475_0402_1%

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

R2102
33_0402_1%
33_0402_1%
R2103

1

C239

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

1

C249

C250

2

0.1U_0402_16V4Z

2

R865 475_0402_1%

1 2

R866 475_0402_1%

1 2

R864 475_0402_1%

1 2

R861 475_0402_1%

1 2

R860 475_0402_1%

1 2

SATA

ICH

27M_SSC 19
27M_CLK 19

1

1

C240

0.1U_0402_16V4Z

2

+1.05VS_CK505

1

C944

2

0.1U_0402_16V4Z

CLK_PCIE_CR# 33
CLK_PCIE_CR 33
CLK_CPU_XDP 4
CLK_CPU_XDP# 4
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7CLK_MCH_BCLK#7
CLKREQ#_6 32
CLK_PCIE_MCARD2 32
CLK_PCIE_MCARD2# 32

H_STP_PCI# 28
H_STP_CPU# 28

Card Reader

XDP/ITP

3G_PLL

TV

CLK_PCIE_MCARD0# 32
CLK_PCIE_MCARD0 32

CLKREQ#_10 32

CLK_PCIE_MCARD1 35
CLK_PCIE_MCARD1# 35

CLKREQ#_11 35

CLK_PCIE_LAN# 31
CLK_PCIE_LAN 31

CLKREQ#_9 31
CLKREQ#_4 32

CLK_PCIE_NCARD# 32
CLK_PCIE_NCARD 32

CLKREQ#_C 28

WLAN

Robson

GLAN

New Card

27MHZ For VGA

C232

@

5P_0402_50V8C

C233

@

4.7P_0402_50V8C
C241

@

4.7P_0402_50V8C
C242

@

4.7P_0402_50V8C
C243

@

5P_0402_50V8C

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Clock Generator CK505

LA-4082P Vader Discrete

CLK_48M_ICH

12

CLK_14M_ICH

12

CLK_PCI_ICH

12

CLK_PCI_EC

12

CLK_DEBUG_PORT0

12

1

of

15 58Wednesday, December 26, 2007

0.2

A

B

C

D

E

0.1U_0402_16V4Z
C253

JCRT

CONN@

SUYIN_070546FR015S265ZR

12

R198

+CRTVDD+RCRT_VCC+5VS

1

2

+3VS+CRTVDD +CRTVDD

5

3

4

Q69B

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

BLUE_CRT
GREEN_CRT
RED_CRT

6 1

Q69A

2

2.2K_0402_5%

2

Place close to

DAN217_SC59

JCRT

1

D7

@

+5VS

2

3

DAN217_SC59

M_DDCDATA 18

M_DDCCLK 18

1

@

3

R199

1

D5

DAN217_SC59

+3VS

12

D6

@

2

3

12

R200

2.2K_0402_5%

CRT
Connector

D4

2 1

CH491D_SC59

F1

1.1A_6VDC_FUSE

W=40mils

21

1106 EMI request

1 1

+5VS +5VS

C254

0.1U_0402_16V4Z

1 2

1

5

U6
SN74AHCT1G125GW_SOT353-5

P

M_HSYNC18

M_VSYNC18

12

12

@

R204

2 2

51K_0402_5%

@

R205
51K_0402_5%

A2Y

G

3

4

OE#

C255

0.1U_0402_16V4Z

1 2

HSYNC_G_A D_HSYNC

1

5

P

VSYNC_G_A

4

OE#

A2Y

G

U7
SN74AHCT1G125GW_SOT353-5

3

RED42

GREEN42

BLUE42

D_HSYNC42

D_VSYNC42

1020 change size to meet NV request

R193

0_0603_5%

1 2

R196

0_0603_5%

1 2

R2069 0_0603_5%

RED RED_CRT

1 2

R2070 0_0603_5%

GREEN GREEN_CRT

1 2

R2071 0_0603_5%

BLUE BLUE_CRT

1 2

D_VSYNC

@

1

C262
5P_0402_50V8C

2

@

1

C263
5P_0402_50V8C

2

2.2K_0402_5%

D_DDCDATA

D_DDCCLK

1102 R204,R205 no stuff

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5
16

17

12

R197

2.2K_0402_5%

D_DDCDATA 42
D_DDCCLK 42

GND
GND

CRT Termination/EMI Filter

3 3

4 4

VGA_RED18

VGA_GRN18

VGA_BLU18

A

12

150_0402_1%

150_0402_1%

R241

12

150_0402_1%

R242

12

R243

C314

22P_0402_50V8J

1

1

C315

C316 22P_0402_50V8J

2

2

22P_0402_50V8J

L13 HLC0603CSCCR11JT_0603

1 2

L15 HLC0603CSCCR11JT_0603

1 2

L17 HLC0603CSCCR11JT_0603

1 2

1

2

B

Note: CRT / TV-out should route to JP30
first then to the JP1 & JP2 on system side.

RED

GREEN

BLUE

1

10P_0402_50V8J

1

C317

@

2

10P_0402_50V8J

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C318

@

2

Issued Date

1

C319

@

10P_0402_50V8J

2

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

LA-4082P Vader Discrete

E

0.2

of

16 58Wednesday, December 26, 2007

5

4

3

2

1

1108 EMI request

DMIC_CLK
DMIC_DAT

1

2

1 2

100_0805_5%

1

1

2

2

C273

R212

2.2K_0402_5%

DDC2_CLK
DDC2_DATA

1

C2111
220P_0402_25V8J

2

1

C2120
470P_0402_50V8J

2

LVDS_A2- 18
LVDS_A2+ 18
LVDS_A1- 18
LVDS_A1+ 18
LVDS_A0- 18
LVDS_A0+ 18
LVDS_ACLK- 18
LVDS_ACLK+ 18

DMIC_DAT 34
DMIC_CLK 34

+5VS

INV_PWM 40

BKOFF# 40

DAC_BRIG 40

+USB_CAM

DDC2_CLK 20
DDC2_DATA 20

1212 EMI request

+3VS

R213

2.2K_0402_5%

1 2

1 2

Logo LED

1102 Change size to 0805

C2110

@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

220P_0402_25V8J

LVDS_A2­LVDS_A2+
LVDS_A1­LVDS_A1+
LVDS_A0­LVDS_A0+
LVDS_ACLK­LVDS_ACLK+

DMIC_DAT
DMIC_CLK
+5V_LOGO
INV_PWM
BKOFF#
DAC_BRIG

DDC2_DATA

C272

470P_0402_50V8J

470P_0402_50V8J

R462

C270

1

2

680P_0402_50V7K

@

D17

4

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4

INVPWR_B++LCDVDD

C271

12

680P_0402_50V7K

USB20_P4_R
USB20_N4_R

LVDS_BCLK+
LVDS_BCLK-

LVDS_B0+
LVDS_B0­LVDS_B1+
LVDS_B1­LVDS_B2+ DDC2_CLK
LVDS_B2-

USB20_P4_R

2

IO1

1

LVDS CONN

JLVDS

1

1

2

3

3

4

5

5

6

7

7

8

9

9

10

11

11

12

13

13

14

15

15

16

17

17

18

19

19

20

21

21

22

23

23

24

25

25

26

27

27

28

29

29

30

31

31

32

33

33

34

35

35

36

37

37

38

39

39

40

GND41GND

ACES_88242-4001

CONN@

D D

R565 0_0402_5%

USB20_P428

USB20_N428

+3VS

C C

680P_0402_50V7K

1 2

R564 0_0402_5%

1 2

LVDS_BCLK+18
LVDS_BCLK-18

LVDS_B0+18

12

C269

LVDS_B0-18
LVDS_B1+18
LVDS_B1-18
LVDS_B2+18
LVDS_B2-18

USB20_N4_R

+5VALW

C266

0.1U_0402_16V4Z

+LCDVDD

1

1

C267

0.1U_0402_16V4Z

2

2

2N7002DW-7-F_SOT363-6

Limited Current < 1A
Avoid Panel display garbage after

power on.

change to 0805

12

R207

Q71A

470_0805_5%

61

ENAVDD20

2

R210

2.2K_0402_5%

@

L8 0_0805_5%

1 2

L9

1 2

FBMA-L11-201209-221LMA30T_0805

0308_Reserve L8 and
install L9.

+5VALW+LCDVDD

12

R208
1M_0402_5%

R209 100K_0402_5%

1 2

3

2N7002DW-7-F_SOT363-6

5

Q71B

4

12

INVPWR_B+B+

C264

4.7U_0805_10V4Z

SI2301BDS-T1-E3_SOT23-3

1

2

C268
1000P_0402_25V

Q7

1 3

D

+3VS+LCDVDD

S

G

C265

1

2

4.7U_0805_10V4Z

2

B B

USB Camera Power

1106 Add SB control pin

+5VALW

PJP5

@

PAD-OPEN 2x2m

10U_0805_10V4Z

A A

GPIO2028

PAD-OPEN 2x2m

2 1
1

C1288

2

@

R2073 0_0402_5%

1 2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+5VS

PJP4

R2072

0_0402_5%

2 1

1 2

U54

1

IN

OUT

2

GND

3

SHDN

BYP

G916-390T1UF_SOT23-5

5

4

SA000025F00

S IC G916T1UF SOT23 5P ADJUSTABLE
LDO

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

12

R891

53.6_0402_1%

12

R892

24.9_0402_1%

2

+USB_CAM

1

C952

4.7U_0805_10V4Z

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LCD CONN.

LA-4082P Vader Discrete

1

of

17 58Wednesday, December 26, 2007

0.2

A

B

C

D

E

1

C1025

2

1

C1031

2

4.7U_0603_6.3V6K

E

+PCIE

+PCIE

1

C1026

2

22U_0805_6.3VAM

+PCIE

1

C1032

2

22U_0805_6.3VAM

0.2

of

18 58Wednesday, December 26, 2007

U71A

AM16
AR13

AJ17
AJ18

AR16
AR17

AL17
AM17

AP17
AN17

AM18
AM19

AN19
AP19

AL19
AK19

AR19
AR20

AL20
AM20

AP20
AN20

AM21
AM22

AN22
AP22

AL22
AK22

AR22
AR23

AL23
AM23

AP23
AN23

AM24
AM25

AN25
AP25

AL25
AK25

AR25
AR26

AL26
AM26

AP26
AN26

AM27
AM28

AN28
AP28

AL28
AK28

AR28
AR29

AK29
AL29

AP29
AN29

AM29
AM30

AN31
AP31

AM31
AM32

AR31
AR32

AN32
AP32

AR34
AP34

Issued Date

1/16 PCI_EXPR ESS

PEX_RST

PEX_CLKREQ

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

PEX_REFCLK
PEX_REFCLK

PEX_TX0
PEX_TX0

PEX_RX0
PEX_RX0

PEX_TX1
PEX_TX1

PEX_RX1
PEX_RX1

PEX_TX2
PEX_TX2

PEX_RX2
PEX_RX2

PEX_TX3
PEX_TX3

PEX_RX3
PEX_RX3

PEX_TX4
PEX_TX4

PEX_RX4
PEX_RX4

PEX_TX5
PEX_TX5

PEX_RX5
PEX_RX5

PEX_TX6
PEX_TX6

PEX_RX6
PEX_RX6

PEX_TX7
PEX_TX7

PEX_RX7
PEX_RX7

PEX_TX8
PEX_TX8

PEX_RX8
PEX_RX8

PEX_TX9
PEX_TX9

PEX_RX9
PEX_RX9

PEX_TX10
PEX_TX10

PEX_RX10
PEX_RX10

PEX_TX11
PEX_TX11

PEX_RX11
PEX_RX11

PEX_TX12
PEX_TX12

PEX_RX12
PEX_RX12

PEX_TX13
PEX_TX13

PEX_RX13
PEX_RX13

PEX_TX14
PEX_TX14

PEX_RX14
PEX_RX14

PEX_TX15
PEX_TX15

PEX_RX15
PEX_RX15

2006/02/13 2006/03/10

D

500 mA

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

1600 mA

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

110 mA

VDD_SENSE
GND_SENSE

PEX_PLLVDD

100mA

PEX_TERMP

NB9P-GS_B GA 969~D

Compal Secret Data

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8

NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19

VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5

PEX_RFU1

PEX_RFU2

TESTMODE

Deciphered Date

AK16
AK17
AK21
AK24
AK27

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24

AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

A2
AB7
AD6
AF6
AG6
AJ5
AK15
AL7
D35
E35
E7
F7
H32
M7
P6
P7
R7
U7
V6

J10
J11
J12
J13
J9

AD20
AD19

AG14

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V7K

C1058

1

C1260

2

0.01U_0402_16V7K

1

2

1

2

1U_0603_10V4Z

AG19

AG20

R1043 2.49K_0402_1%

AG21

1 2

R949 10K_0402_5%

AP35

1 2

0.1U_0402_16V4Z

C1021

4700P_0402_16V7K

C1027

1

C1054

2

0.1U_0402_16V4Z

VDD_SENSE 52

1

C1057

2

0.1U_0402_16V4Z

1

C1022

2

1

C1028

2

+3VS

1

C1073

2

4700P_0402_16V7K

4700P_0402_16V7K

1

2

1

C1023

C1024

2

2

4.7U_0603_6.3V6K

1U_0603_10V4Z

1

1

C1029

C1030

2

2

C1055

1U_0603_10V4Z

L64

1 2

10NH_LQG 15HS10NJ 02D_5%_0402

1

C1071

4.7U_0603_6.3V6M

2

Compal Electronics, Inc.

Title

PEG & LVDS & DAC

Size Document Number Rev

Custom

LA-4082P Vader Discrete

Date: Sheet

1U_0603_10V4Z

1

LVDS & DAC Interface

U71I

7/16 IFPAB

+1.8VS

1 1

2 2

3 3

4 4

L61 BLM18PG181SN1D_0603

1 2

1

C1018

4.7U_0603_6.3V6K

2

+1.8VS

L62 BLM18PG181SN1D_0603

1 2

1

C1035

4.7U_0603_6.3V6K

2

L63 BLM18PG181SN1D_0603

1 2

+3VS

IFPAB_PLLVDD

AK9

IFPAB_PLLVDD

IFPAB_RSET

4700P_0402_25V7K

1U_0402_6.3V4Z

1

C1033

2

4.7U_0603_6.3V6K

1

C1020

2

220P_0402_50V7K

1

1

12

C1034

C1019

2

2

4700P_0402_25V7K

1

2

10K_0402_5%

C1037

220P_0402_50V7K

1

2

1U_0402_6.3V4Z

1

C1036

2

R945

1 2

@

R1044
1K_0402_1%

IFPAB_IOVDD

C1038

U71G

AG7
AK6
AH7

6/16 DACC

DACC_VDD

DACC_VREF

DACC_RSET

AJ11

AG9

AG10

DAC C

U71F

124_0402_1%

12

R1042

4/16 DACA

AJ12

DACA_VDD

AK12

DACA_VREF

AK13

DACA_RSET

DACA_VDD
DACA_VREF

4700P_0402_16V7K

4.7U_0603_6.3V6K

1

1

C1065

C1172

2

2

0.1U_0402_16V4Z

470P_0402_50V7K

1

1

C1067

C1066

2

2

DAC A

U71H

R948

1 2

10K_0402_5%

1009 disable TV function

A

5/16 DACB(TV)

AC6

DACB_VDD

AC5

DACB_VREF

AB6

DACB_RSET

IFPAB_RSET

IFPA_IOVDD

IFPB_IOVDD

150 mA

NB9P-GS_B GA 969~D

32 mA

145 mA

I2CB_SCL
I2CB_SDA

DACC_HSYNC
DACC_VSYNC

DACC_RED

DACC_GREEN

DACC_BLUE

NB9P-GS_B GA 969~D

I2CA_SCL
I2CA_SDA

DACA_HSYNC

DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

NB9P-GS_B GA 969~D

DAC B

DACB_CSYNC

DACB_RED

DACB_GREEN

DACB_BLUE

NB9P-GS_B GA 969~D

G3
G2

AM1
AM2

1009 change HDMI I2C channel for Nvidia suggestion
1105 nVIDIA suggetion, add R

AK4

1108 nVIDIA suggestion -- change HDMI DDC to I2CD

AL4
AJ4

G1
G4

AM13
AL13

AM15
AM14
AL14

150_0402_1%

150_0402_1%

12

R1590

1009 disable TV function

AB5

AA4
AB4
Y4

B

AM12

IFPA_TXC

AM11

IFPA_TXC

AL8

IFPA_TXD0

AM8

IFPA_TXD0

AM9

IFPA_TXD1

AM10

IFPA_TXD1

AL10

IFPA_TXD2

AK10

IFPA_TXD2

AL11

IFPA_TXD3

AK11

IFPA_TXD3

AN13

IFPB_TXC

AP13

IFPB_TXC

AP8

IFPB_TXD4

AN8

IFPB_TXD4

AN10

IFPB_TXD5

AP10

IFPB_TXD5

AR10

IFPB_TXD6

AR11

IFPB_TXD6

AP11

IFPB_TXD7

AN11

IFPB_TXD7

150_0402_1%

12

12

R1592

R1591

M_DDCCLK 16
M_DDCDATA 16

M_HSYNC 16
M_VSYNC 16

VGA_RED 16
VGA_GRN 16
VGA_BLU 16

LVDS_ACLK- 17
LVDS_ACLK+ 17

LVDS_A0- 17
LVDS_A0+ 17

LVDS_A1- 17
LVDS_A1+ 17

LVDS_A2- 17
LVDS_A2+ 17

LVDS_BCLK- 17
LVDS_BCLK+ 17

LVDS_B0- 17
LVDS_B0+ 17

LVDS_B1- 17
LVDS_B1+ 17

LVDS_B2- 17
LVDS_B2+ 17

CLK_PCIE_VGA15

CLK_PCIE_VGA#15

PEG Interface

PEG_RXP09
PEG_RXN09

PEG_M_TXP09
PEG_M_TXN09

PEG_RXP19
PEG_RXN19

PEG_M_TXP19
PEG_M_TXN19

PEG_RXP29
PEG_RXN29

PEG_M_TXP29
PEG_M_TXN29

PEG_RXP39

PEG_RXN39
PEG_M_TXP39

PEG_M_TXN39

PEG_RXP49
PEG_RXN49

PEG_M_TXP49
PEG_M_TXN49

PEG_RXP59
PEG_RXN59

PEG_M_TXP59
PEG_M_TXN59

PEG_RXP69
PEG_RXN69

PEG_M_TXP69
PEG_M_TXN69

PEG_RXP79
PEG_RXN79

PEG_M_TXP79
PEG_M_TXN79

PEG_RXP89
PEG_RXN89

PEG_M_TXP89
PEG_M_TXN89

PEG_RXP99
PEG_RXN99

PEG_M_TXP99
PEG_M_TXN99

PEG_RXP109
PEG_RXN109

PEG_M_TXP109
PEG_M_TXN109

PEG_RXP119
PEG_RXN119

PEG_M_TXP119
PEG_M_TXN119

PEG_RXP129
PEG_RXN129

PEG_M_TXP129
PEG_M_TXN129

PEG_RXP139
PEG_RXN139

PEG_M_TXP139
PEG_M_TXN139

PEG_RXP149
PEG_RXN149

PEG_M_TXP149
PEG_M_TXN149

PEG_RXP159
PEG_RXN159

PEG_M_TXP159
PEG_M_TXN159

C

C1039 0.1U_0402_16V4Z
C1040 0.1U_0402_16V4Z

C1041 0.1U_0402_16V4Z
C1042 0.1U_0402_16V4Z

C1043 0.1U_0402_16V4Z
C1044 0.1U_0402_16V4Z

C1045 0.1U_0402_16V4Z
C1046 0.1U_0402_16V4Z

C1047 0.1U_0402_16V4Z
C1048 0.1U_0402_16V4Z

C1049 0.1U_0402_16V4Z
C1050 0.1U_0402_16V4Z

C1051 0.1U_0402_16V4Z
C1052 0.1U_0402_16V4Z

C1053 0.1U_0402_16V4Z
C1056 0.1U_0402_16V4Z

C1059 0.1U_0402_16V4Z
C1060 0.1U_0402_16V4Z

C1061 0.1U_0402_16V4Z
C1062 0.1U_0402_16V4Z

C1063 0.1U_0402_16V4Z
C1064 0.1U_0402_16V4Z

C1068 0.1U_0402_16V4Z
C1069 0.1U_0402_16V4Z

C1070 0.1U_0402_16V4Z
C1072 0.1U_0402_16V4Z

C1074 0.1U_0402_16V4Z
C1075 0.1U_0402_16V4Z

C1076 0.1U_0402_16V4Z
C1077 0.1U_0402_16V4Z

C1078 0.1U_0402_16V4Z
C1079 0.1U_0402_16V4Z

PLT_RST#7,26,31,32,33,35

NB9M & NB9P-GS stuff

R944 200_0402_1%

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PEG_C_RXP0
PEG_C_RXN0

PEG_C_RXP1
PEG_C_RXN1

PEG_C_RXP2
PEG_C_RXN2

PEG_C_RXP3
PEG_C_RXN3

PEG_C_RXP4
PEG_C_RXN4

PEG_C_RXP5
PEG_C_RXN5

PEG_C_RXP6
PEG_C_RXN6

PEG_C_RXP7
PEG_C_RXN7

PEG_C_RXP8
PEG_C_RXN8

PEG_C_RXP9
PEG_C_RXN9

PEG_C_RXP10
PEG_C_RXN10

PEG_C_RXP11
PEG_C_RXN11

PEG_C_RXP12
PEG_C_RXN12

PEG_C_RXP13
PEG_C_RXN13

PEG_C_RXP14
PEG_C_RXN14

PEG_C_RXP15
PEG_C_RXN15

Security Classification

THIS SHEET OF ENGIN EERING DR AWING IS TH E PROPRIETARY PR OPERTY OF CO MPAL ELECTRO NICS, IN C. AND C ONTAINS CO NFIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF TH E COMPETENT DI VISION O F R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC . NEITHER THIS SHEET NO R THE INF ORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITH OUT PRIOR WRITTEN CO NSENT OF COMPAL ELECTRON ICS, INC .