HP DV7 AMD Schematics

A

1 1

B

C

D

E

2 2

Compal confidential

JBK00 LA-4091P Schematics Document

Mobile AMD S1G2 CPU with ATI
RS780M & SB700 core logic

3 3

2007-10-30

REV:0.2

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-4091P

LA-4091P

LA-4091P

E

of

of

of

153Thursday, November 08, 2007

153Thursday, November 08, 2007

153Thursday, November 08, 2007

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

B

C

D

E

Compal

Consumer AMD UMA 17"

confidential

1 1

Thermal Sensor

AMD S1G2 CPU

DDR2 800MHz 1.8V

ADM1032ARMZ

638-PIN uFCPGA 638

P4, 5, 6, 7

Htper Transport Link

16X16

Dual Channel

Fan conn

P6

P4

ATI RS780M

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

P8, 9

Finger Print

Clock Generator
SLG8SP626

P36

LVDS Panel

USB Camera
with Digital MIC

USB conn x3

BT Conn

Touch Screen

Dock

P36

P36

P36

P43

P21

P21

P29

P22

PCI-E BUS*5

Mini-Card*2

WLAN & TV Tunner

P30

Express Card

P30

A-Link Expr ess II

4X PCI-E

ATI SB700

P23, 24, 25, 26, 27

P10, 11, 12

USB2.0 X12

Azalia

SATA Master-1

SATA Master-2

SATA Slave

SATA Slave

2 2

Interface

CRT

HDMI

Realtek
8102E(10/100M)
8111C(GbE)

72QFN

P20

3 3

LED

P41

RTC CKT.

P19

Power OK CKT.

RJ45 Conn.

P29

JMOB385

CardReader

P30

P30

SPI ROM
25LF080A

SPI

P37

Touch Pad CONN. Int.KBD

Power On/Off CKT.

4 4

DC/DC Interface CKT.

P43

DC/DC Interface CKT.

P43

A

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

ENE

KB926

CIR

P38

C

LPC BUS

P38

P38

Compal Secret Data

Compal Secret Data

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Audio CKT AMP & Audio Jack

Codec_IDT9271

MDC V1.5

SATA HDD Connector

SATA ODD Connector

SATA 2nd HDD Option Connector

P33 P35

P29

P28

P28

P28

e-SATA Connector

P36

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

LA-4091P

LA-4091P

LA-4091P

TPA6020A2

Subwoofer

E

P35

0.1

0.1

253Thursday, November 08, 2007

253Thursday, November 08, 2007

253Thursday, November 08, 2007

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

B

C

D

E

Voltage Rails

O MEANS ON X MEANS OFF

Symbol Note :

+5VS

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

State

S0

S1

S3

S5 S4/AC

power
plane

+B

+3VL

O

O

O

O

O

X

+5VALW
+3VALW
+1.2VALW

+1.8V

+0.9V

O

O

O

O

X

O

XX

X

XX X

+3VS

+2.5VS

+1.8VS

+1.5VS

+1.1VS

+VGA_CORE

+1.2V_HT

+CPU_CORE_NB

+CPU_CORE_0

+CPU_CORE_1

OO

OO

X

X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG @ : means just reserve for debu g.

Layout Notes

L

UMA@ : means for RS780M.

I2C / SMBUS ADDRESSING

DEVICE

3 3

DDR SO-DIMM 0

DDR SO-DIMM 1

CLOCK GENERATOR (EXT.)

HEX

A0

D2

3AACCELEROMETER 0 0 1 1 1 0 1 0

EC SM Bus1 address

Device

Smart Battery

24C16

CPU SIC interface

4 4

HEX HEX

Address Address

0001 011X b

16H

1010 000X b

A0H

1001 100X b

98H

A

ADDRESS

1 0 1 0 0 0 0 0

1 0 1 0 0 1 0 0A4

1 1 0 1 0 0 1 0

EC SM Bus2 address

Device

ADI1032-2 CPU

9AH

1001 101X b

B

SMBUS Control Table

SOURCE

SMB_EC_CK1

SMB_EC_DA1

SMB_EC_CK2

SMB_EC_DA2

I2C_CLK

I2C_DATA

DDC_CLK0

DDC_DATA0

DDC_CLK1

DDC_DATA1

SCL0

SDA0

SCL1

SDA1

SCL2

SDA2

SCL3

SDA3

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

KB926

KB926

RS780M

RS780M

RS780M

SB700

SB700

SB700

SB700

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

C

X
X

X

XX

Compal Secret Data

Compal Secret Data

Compal Secret Data

EEPROMBATTINVERTER

V

XX

XXX
XX XXXX
XXXX XX

Deciphered Date

Deciphered Date

Deciphered Date

THERMAL
SENSORSERIAL

CPU &

I / II

ADM1032

V

XXXXXX

V

CLK CHIPSODIMM

MINI CARD

Slot 2

X
X

XXXXX

XXXX

VVXX

XXX

XX

VXX

X

XX

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

X

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-4091P

LA-4091P

LA-4091P

LCD

XX
X

VXX

XXX
XXXX
XXX

G-Sensor

HDMI

X

X

X

X
X

X

VXXX

X
X

V

X
X
X

0.1

0.1

353Thursday, November 08, 2007

353Thursday, November 08, 2007

353Thursday, November 08, 2007

E

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

1 1

B

C

D

E

+1.2V_HT

250 mil

1

C1

H_CADIP[0..15]10

H_CADIP[0..15]

H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

H_CADOP[0..15] 10

H_CADON[0..15] 10H_CADIN[0..15]10

C1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C2

C2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

VLDT CAP.

1

C3

C3

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

2

C4

C4

0.22U_0603_16V4Z

0.22U_0603_16V4Z

1

C5

C5
180P_0402_50V8J

180P_0402_50V8J

2

1

C6

C6
180P_0402_50V8J

180P_0402_50V8J

2

Near CPU Socket

+1.2V_HT

2 2

3 3

VLDT=500mA

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

H_CLKIP010
H_CLK IN010
H_CLKIP110
H_CLK IN110

H_CTLIP010

H_CTLIP110 H_CTLOP1 10
H_CTLIN110

CONN@

CONN@

D1
D2
D3
D4

E3
E2
E1

F1
G3
G2
G1

H1

J1
K1
L3
L2
L1

M1

N3
N2
E5
F5
F3
F4

G5

H5
H3
H4
K3
K4
L5

M5
M3
M4

N5
P5

J3

J2

J5
K5

N1
P1
P3
P4

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

6090022100G_B

6090022100G_B

JP1A

JP1A

HT LINK

HT LINK

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9

L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

+VLDT_B

AE2
AE3
AE4
AE5

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

Y1
W1
Y4
Y3

R2
R3
T5
R5

1 2

C7 4.7U_0805_10V4ZC7 4.7U_0805_10V4Z

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CLKOP0 10
H_CLK ON0 10
H_CLKOP1 10
H_CLK ON1 10

H_CTLOP0 10
H_CTLON0 10H_CTLIN010

H_CTLON1 10

PWM Fan Control circuit

CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

FAN_PWM33

+5VS

JP2

JP2

1

C8

D1

D1

2 1

6

2

1

D

D

Q1

Q1

G

G

3

S

S

SI3456BDV-T1-E3_TSOP6

SI3456BDV-T1-E3_TSOP6

4 5

C8

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+VCC_FAN

1

C9

C9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

12

D2

@D2

@

RLZ5.1B_LL34

RLZ5.1B_LL34

1

1

2

2

3

GND

4

GND

ACES_88231-02001

ACES_88231-02001

CONN@

CONN@

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

AMD CPU S1G2 HT I/F

AMD CPU S1G2 HT I/F

LA-4091P

LA-4091P

LA-4091P

453Thursday, November 08, 2007

453Thursday, November 08, 2007

453Thursday, November 08, 2007

E

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

B

C

D

E

Processor DDR2 Memory Interface

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

AD10

AF10
AE10

AA16

D10
C10
B10

H16

T19
V22
U21
V19

T20
U19
U20
V20

J22

J20

N19
N20
E16
F16

Y16

P19
P20

N21
M20
N22
M19
M22

L20
M24

L21

L19
K22
R21

L22
K20
V24
K24
K19

R20
R23

J21

R19

T22

T24

DDR_A_CLK0

DDR_A_CLK#0

DDR_A_CLK1

DDR_A_CLK#1

DDR_B_CLK0

DDR_B_CLK#0

DDR_B_CLK1

DDR_B_CLK#1

VTT1
VTT2
VTT3
VTT4

MEMZP
MEMZN

RSVD_M1

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_CKE0
MA_CKE1

MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CLK_H2
MA_CLK_L2
MA_CLK_H3
MA_CLK_L3

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_RAS_L
MA_CAS_L
MA_WE_L

JP1B

JP1B

MEM:CMD/CTRL/CLK

MEM:CMD/CTRL/CLK

VTT_SENSE

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CLK_H2
MB_CLK_L2
MB_CLK_H3
MB_CLK_L3

MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

1

2

1

2

1

2

1

2

VTT5
VTT6
VTT7
VTT8
VTT9

MEMVREF

RSVD_M2

MB_CKE0
MB_CKE1

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9

MB_WE_L

C10

C10

1.5P_0402_50V9C

1.5P_0402_50V9C

C11

C11

1.5P_0402_50V9C

1.5P_0402_50V9C

C14

C14

1.5P_0402_50V9C

1.5P_0402_50V9C

C15

C15

1.5P_0402_50V9C

1.5P_0402_50V9C

W10
AC10
AB10
AA10
A10

Y10

W17

B18

W26
W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

+0.9V+0.9V

VTT_SENSE

+MCH_RE F

DDR_B_ODT0
DDR_B_ODT1

DDR_CS1_DIMMB#

DDR_CKE0_DIMMB
DDR_CKE1_DIMMB

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1DDR_A_CLK#1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

T1PAD T1PAD

T3PAD T3PAD

DDR_B_ODT0 9
DDR_B_ODT1 9

DDR_CS1_DIMMB# 9

DDR_CKE0_DIMMB 9
DDR_CKE1_DIMMB 9

DDR_B_CLK0 9
DDR_B_CLK#0 9
DDR_B_CLK1 9
DDR_B_CLK#1 9

DDR_B_BS#0 9
DDR_B_BS#1 9
DDR_B_BS#2 9

DDR_B_RAS# 9
DDR_B_CAS# 9
DDR_B_WE# 9

1 1

2 2

R1

R1

1K_0402_1%

1K_0402_1%

R2

R2

1K_0402_1%

1K_0402_1%

+1.8V

1 2

1 2

+MCH_RE F

1

C12

C12

2

1

C13

C13

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1000P_0402_25V8J

1000P_0402_25V8J

Place them close to CPU within 1"

R4 39.2_0402_1%R4 39.2_0402_1%

1 2

DDR_A_BS#08
DDR_A_BS#18
DDR_A_BS#28

DDR_A_RAS#8
DDR_A_CAS#8
DDR_A_WE#8

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

T2 PADT2 PAD

DDR_A_ODT0
DDR_A_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA# DDR_CS0_DIMMB#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

CONN@

CONN@

+1.8V

DDR_A_ODT08
DDR_A_ODT18

DDR_CS0_DIMMA#8
DDR_CS1_DIMMA#8 DDR_CS0_DIMMB# 9

DDR_CKE0_DIMMA8
DDR_CKE1_DIMMA8

DDR_A_CLK08

DDR_A_CLK#08

DDR_A_CLK18

3 3

DDR_A_CLK#18

DDR_A_MA[15..0]8 DDR_B_MA[15..0] 9

DDR_B _D[63..0 ]9

DDR_B_DM[7..0]9 DDR_A_DM[7..0] 8

DDR_B_DQS09
DDR_B_DQS#09
DDR_B_DQS19
DDR_B_DQS#19
DDR_B_DQS29
DDR_B_DQS#29
DDR_B_DQS39
DDR_B_DQS#39
DDR_B_DQS49
DDR_B_DQS#49
DDR_B_DQS59
DDR_B_DQS#59
DDR_B_DQS69
DDR_B_DQS#69
DDR_B_DQS79
DDR_B_DQS#79

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11

AE14
AF14
AF11
AD11

AB26
AE22
AC16
AD12

AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24

Y11

A12
B16
A22
E25

C12
B12
D16
C16
A24
A23
F26
E26

JP1C

JP1C

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

6090022100G_BCONN@

6090022100G_BCONN@

MEM:DATA

MEM:DATA

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

DDR_A_D[63..0] 8

DDR_A_DQS0 8
DDR_A_DQS#0 8
DDR_A_DQS1 8
DDR_A_DQS#1 8
DDR_A_DQS2 8
DDR_A_DQS#2 8
DDR_A_DQS3 8
DDR_A_DQS#3 8
DDR_A_DQS4 8
DDR_A_DQS#4 8
DDR_A_DQS5 8
DDR_A_DQS#5 8
DDR_A_DQS6 8
DDR_A_DQS#6 8
DDR_A_DQS7 8
DDR_A_DQS#7 8

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

AMD CPU S1G2 DDRII I/F

AMD CPU S1G2 DDRII I/F

LA-4091P

LA-4091P

LA-4091P

553Thursday, November 08, 2007

553Thursday, November 08, 2007

553Thursday, November 08, 2007

E

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

A:Need to re-Link "SGN00000200"

1 1

CLK_CPU_BCLK15

CLK_CPU_BCLK#15

+1.8VS

R15

R15
300_0402_5%

300_0402_5%

1 2

+1.8VS

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C27

C27

1 2

2200P_0402_50V7K

2200P_0402_50V7K

LDT_ RST#

1

C22

C22

0.01U_0402_25V4Z

0.01U_0402_25V4Z

@

@

2

R21

R21
300_0402_5%

300_0402_5%

1 2

H_PWRGD

1

C23

C23

0.01U_0402_25V4Z

0.01U_0402_25V4Z

@

@

2

+1.8VS

R36

R36
300_0402_5%

300_0402_5%

1 2

LDT_STOP#

1

C25

C25

0.01U_0402_25V4Z

0.01U_0402_25V4Z

@

@

2

1

C26

C26

2

THERMDA_CPU

THERMDC_CPU

LDT_ RST#19

2 2

H_PWRGD19

3 3

4 4

LDT_STOP#11,19

2200p change to
1000p for ADT7421

+2.5VS

C16

C16

100U_D2_10VM

100U_D2_10VM

1 2

C20

C20

1 2

C21 3900P_0402_50V7KC21 3900P_0402_50V7K

Place close to CPU wihtin 1.5"

+CPU_CORE_0

+CPU_CORE_1

+1.8VS

R30

R30

1 2

CPU_LDT_REQ#

1

C24

C24

0.01U_0402_25V4Z

0.01U_0402_25V4Z

2

+1.8V

+1.8V

U2

U2

1

VDD

2

D+

SDATA

3

ALERT#

D-

THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

ADM1032ARMZ-2REEL_MSOP8

FBM_L11_201209_300L_0805

FBM_L11_201209_300L_0805

1

+

+

2

3900P_0402_50V7K

3900P_0402_50V7K

12

R8

R8
169_0402_1%

169_0402_1%

R487 10_0402_5%R487 10_0402_5%

1 2
1 2

R486 10_0402_5%R486 10_0402_5%

R489 10_0402_5%R489 10_0402_5%

1 2
1 2

R488 10_0402_5%R488 10_0402_5%

300_0402_5%

300_0402_5%

@

@

+3VS

20K_0402_5%

20K_0402_5%

R18

R18

390_0402_5%

390_0402_5%

CPU_SID

R19

R19

390_0402_5%

390_0402_5%

CPU_SIC

8

SCLK

7

6

5

1 2

CPU_VDD1_FB_H
CPU_VDD1_FB_L

R175

R175

12

12

SMB_EC_CK2

SMB_EC_DA2

Address:100_1101

A

B

+2.5VDDA

L1

L1

VDDA=300mA

3300P_0402_50V7K

3300P_0402_50V7K

1

C174.7U_0805_10V4Z C174.7U_0805_10V4Z

2

Address:100_1100

R13 44.2_0402_1%R13 44.2_0402_1%
R14 44.2_0402_1%R14 44.2_0402_1%

+1.2V_HT

CPU_VDD0_FB_H
CPU_VDD0_FB_L

Close to CPU

CPU_LDT_REQ# 11,19

12

S

S

Q127 FDV301N_NL_SOT23-3

Q127 FDV301N_NL_SOT23-3

S

S

Q129 FDV301N_NL_SOT23-3

Q129 FDV301N_NL_SOT23-3

T4 PADT4 PAD

T9 PADT9 PAD
T11 PADT11 PAD

1 2

C939 0.1U_0402_16V4ZC939 0.1U_0402_16V4Z

R814

R814

34.8K_0402_1%~N

34.8K_0402_1%~N

G

G

2

13

D

D

G

G

2

13

D

D

SMB_EC_CK2 33

SMB_EC_DA2 33

B

12

1

1

C19

C19

C18

C18

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

1 2
1 2

CPU_VDD0_FB_H43
CPU_VDD0_FB_L43

CPU_VDD1_FB_H43
CPU_VDD1_FB_L43

CPU_TEST23_TSTUPD

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN

1 2

2.09V for Gate

SMB_EC_DA1 32,33,34,37

EC is PU to 5VALW

SMB_EC_CK1 32,33,34,37

LDT_ RST#
H_PWRGD
LDT_STOP#
CPU_LDT_REQ#

CPU_SIC
CPU_SID

CPU_ HTR EF0
CPU_ HTR EF1

CPU_VDD0_FB_H
CPU_VDD0_FB_L

CPU_VDD1_FB_H
CPU_VDD1_FB_L

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

R25 0_0402_5%R25 0_0402_5%

FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V

C

JP1D

JP1D

F8

VDDA1

F9

VDDA2

A9

CLKIN_H

A8

CLKIN_L

B7

RESET_L

A7

PWROK

F10

LDTS TOP_L

C6

LDTREQ_L

AF4

SIC

AF5

SID

AE6

ALERT_L

R6

HT_REF0

P6

HT_REF1

F6

VDD0_FB_H

E6

VDD0_FB_L

Y6

VDD1_FB_H

AB6

VDD1_FB_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

AD7

TEST23

H10

TEST18

G9

TEST19

E9

TEST25_H

E8

TEST25_L

AB8

TEST21

AF7

TEST20

AE7

TEST24

AE8

TEST22

AC8

TEST12

AF8

TEST27

C2

TEST9

AA6

TEST6

A3

RSVD1

A5

RSVD2

B3

RSVD3

B5

RSVD4

C1

RSVD5

CONN@

CONN@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

6090022100G_B

6090022100G_B

C

THERMTRIP_L

VDDNB_FB_H
VDDNB_FB_L

M11

KEY1

W18

KEY2

CPU_SVC

A6

SVC

CPU_SVD

A4

SVD

AF6
AC7

PROCHOT_L

AA8

MEMHOT_L

THERMDC_CPU

W7

THERMD C

THERMD A

VDDIO_FB_H
VDDIO_FB_L

DBREQ_L

TEST28_H
TEST28_L

TEST29_H
TEST29_L

RSVD10

THERMDA_CPU

W8

W9
Y9

VDD_NB_FB_H

H6

VDD_NB_FB_L

G6

CPU_DBREQ#

E10

CPU_TDO

AE9

TDO

CPU_TEST28_H_PLLCHRZ_P

J7

CPU_TEST28_L_PLLCHRZ_N

H8

CPU_TEST17_BP3

D7

TEST17

CPU_TEST16_BP2

E7

TEST16

CPU_TEST15_BP1

F7

TEST15

CPU_TEST14_BP0

C7

TEST14

C3

TEST7

K8

TEST10

C4

TEST8

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

H18
H19

RSVD9

AA7

RSVD8

D5

RSVD7

C5

RSVD6

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR RE V. Ax SIL ICON ONLY .

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

CPU_SVC 43
CPU_SVD 43

CPU_THE RMTRIP#_R
CPU_PROCHOT#_1.8

+1.8V sense no support

T22PAD T22PAD
T21PAD T21PAD

VDD_NB_FB_H 43
VDD_NB_FB_L 43

+1.8V

R39220_0402_5%@ R39220_0402_5%@

R37220_0402_5%@ R37220_0402_5%@

R38220_0402_5%@ R38220_0402_5%@

R40220_0402_5%@ R40220_0402_5%@

12

12

Compal Secret Data

Compal Secret Data

Compal Secret Data

12

12

Deciphered Date

Deciphered Date

Deciphered Date

12

D

+1.8V

T7PAD T7PAD
T8PAD T8PAD
T10PAD T10PAD
T12PAD T12PAD

R41220_0402_5%@ R41220_0402_5%@

1 2

R10 10K_0402_5%R10 10K_0402_5%

1 2

R5 300_0402_5%R5 300_0402_5%

CPU_THE RMTRIP#_R

+1.8V

route as diffe rential

T5PAD T5PAD

as short as possible

T6PAD T6PAD

testpoint under package

T13PAD T13PAD
T14PAD T14PAD

HDT Connector

CONN@ SAMTEC_ASP-68200-07

CONN@

D

R11 10K_0402_5%@R11 10K_0402_5%@

1 2

R9 300_0402_5%R9 300_0402_5%

CPU_PROC HOT#_1.8

VDD_NB_FB_H
VDD_NB_FB_L

Close to CPU

CPU_SVC
CPU_SVD

CPU_TEST27_SINGLECHAIN

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

JP3

JP3

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

E

B

B

2

E

E

3 1

C

C

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

12

MMBT3904_NL_SOT23-3@

MMBT3904_NL_SOT23-3@

R484 10_0402_5%R484 10_0402_5%

1 2
1 2

R485 10_0402_5%R485 10_0402_5%

0718 AMD --> 1K ohm

HDT_RST#

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

R6

1 2

Q3

Q3

B

B

2

E

E

3 1

+CPU_CORE_NB

R22 1K_0402_5%R22 1K_0402_5%
R23 1K_0402_5%R23 1K_0402_5%

R24 300_0402_5%R24 300_0402_5%

R26 300_0402_5%R26 300_0402_5%
R27 300_0402_5%R27 300_0402_5%
R28 300_0402_5%R28 300_0402_5%
R29 300_0402_5%R29 300_0402_5%
R31 300_0402_5%R31 300_0402_5%
R32 300_0402_5%R32 300_0402_5%
R33 300_0402_5%R33 300_0402_5%
R34 300_0402_5%R34 300_0402_5%
R35 300_0402_5%R35 300_0402_5%

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

AMD CPU S1G2 CTRL

AMD CPU S1G2 CTRL

1 2

Q2

Q2

C

C

1 2
1 2

1 2

1 2

U1

4

Y

LA-4091P

LA-4091P

LA-4091P

R7

R7

+3VS

12
12
12
12
12
12
12
12

5

P

G

3

0_0402_5%@R60_0402_5%@

0_0402_5%

0_0402_5%

2

B

1

A

NC7SZ08P5X_NL_SC70-5@U1NC7SZ08P5X_NL_SC70-5@

+1.8V

LDT_ RST#

E

ENTRIP2 37,39

H_THERMTRIP# 20,33

H_PROCHOT# 1 9

SB_PWRGD 20,33,43

653Thursday, November 08, 2007

653Thursday, November 08, 2007

653Thursday, November 08, 2007

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

VDD(+CPU_CORE) decoupling.

+CPU_CORE_0

1

+

+

C30

1 1

C30
330U_X_2VM_R6M

330U_X_2VM_R6M

2

1

+

+

C28

C28
330U_X_2VM_R6M

330U_X_2VM_R6M

2

Near CPU Socket

+CPU_CORE_0

1

C32

C32
22U_0805_6.3V6M

22U_0805_6.3V6M

2

+CPU_CORE_0

1

C40

C40

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

2 2

1

C33

C33
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C41

C41

0.01U_0402_25V4Z

0.01U_0402_25V4Z

2

1

C34

C34
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

2

C42

C42
180P_0402_50V8J

180P_0402_50V8J

1

C35

C35
22U_0805_6.3V6M

22U_0805_6.3V6M

2

Under CPU Socket

VDDIO decoupling.

+1.8V

1

C46

C46
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C47

C47
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C48

C48

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

Under CPU Socket

1

C49

C49

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

B

+CPU_CORE_1

+CPU_CORE_1

1

C36

C36
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C50

C50

180P_0402_50V8J

180P_0402_50V8J

2

1

+

+

C31

C31
330U_X_2VM_R6M

330U_X_2VM_R6M

2

+CPU_CORE_1

1

C51

C51

180P_0402_50V8J

180P_0402_50V8J

2

1

C37

C37
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C43

C43

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

C

JP1E

G4
H2

J9
J11
J13
J15

K6
K10
K12
K14

L4
L7

L9
L11
L13
L15

M2
M6
M8

M10

N7
N9

N11

K16
M16
P16

T16

V16

H25

J17

K18
K21
K23
K25

L17

M18
M21
M23
M25
N17

6090022100G_B

6090022100G_B

Athlon 64 S1
Processor Socket

CONN@

CONN@

JP1E

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

1

+

+

C29

C29
330U_X_2VM_R6M

330U_X_2VM_R6M

2

1

C38

C38
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C44

C44

0.01U_0402_25V4Z

0.01U_0402_25V4Z

2

1

C39

C39
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C45

C45
180P_0402_50V8J

180P_0402_50V8J

2

+CPU_CORE_0

+CPU_CORE_NB

+1.8V

+CPU_CORE_NB decoupling.

+CPU_CORE_NB

1

C52

C52
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C53

C53
22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C54

C54
22U_0805_6.3V6M

22U_0805_6.3V6M

2

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8

VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

D

JP1F

JP1F

AA4

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+CPU_CORE_1

+1.8V

AA11
AA13
AA15
AA17
AA19

AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21

AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23

AB2
AB7
AB9

AD6
AD8

B4
B6
B8

B9
B11
B13
B15
B17
B19
B21
B23
B25

D6
D8

D9
D11
D13
D15
D17
D19
D21
D23
D25

E4

F2
F11
F13
F15
F17
F19
F21
F23
F25

H7

H9

H21
H23

J4

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

6090022100G_B

6090022100G_B

Athlon 64 S1
Processor Socket

CONN@

CONN@

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

E

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

3 3

4 4

+1.8V

1

C55

C55

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C60

C60

0.01U_0402_25V4Z

0.01U_0402_25V4Z

2

+1.8V

1

2

Between CPU Socket and DIMM

1

C57

C57

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

1

C62

C62
180P_0402_50V8J

180P_0402_50V8J

2

1

C76

C76

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

C74

C74

4.7U_0805_10V4Z

4.7U_0805_10V4Z

1

C56

C56

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C61

C61

0.01U_0402_25V4Z

0.01U_0402_25V4Z

2

1

C75

C75

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C58

C58

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C63

C63
180P_0402_50V8J

180P_0402_50V8J

2

A: Add C165 and C176
to follow AMD Layout
review recommand for
EMI

1

C77

C77

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C64

C64
180P_0402_50V8J

180P_0402_50V8J

2

1

C: Change to NBO CAP

+

+

C78

C78
220U_Y_4VM

220U_Y_4VM

@

@

2

1

C65

C65
180P_0402_50V8J

180P_0402_50V8J

2

VTT decoupling.

+0.9V

1

C66

C66

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+0.9V

1

C79

C79

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C67

C67

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C68

C68

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

Near CPU Socket Right side.

1

C80

C80

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

1

C81

C81

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

+0.9V

Near Power Supply

1

C: Change to NBO CAP

+

+

C59

C59
220U_Y_4VM

220U_Y_4VM

2

1

C69

C69

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C82

C82

0.22U_0603_16V4Z

0.22U_0603_16V4Z

2

1

C70

C70
1000P_0402_25V8J

1000P_0402_25V8J

2

1

C83

C83
1000P_0402_25V8J

1000P_0402_25V8J

2

1

C71

C71
1000P_0402_25V8J

1000P_0402_25V8J

2

1

C84

C84
1000P_0402_25V8J

1000P_0402_25V8J

2

1

C72

C72
180P_0402_50V8J

180P_0402_50V8J

2

1

C85

C85
180P_0402_50V8J

180P_0402_50V8J

2

1

C73

C73
180P_0402_50V8J

180P_0402_50V8J

2

1

C86

C86
180P_0402_50V8J

180P_0402_50V8J

2

Near CPU Socket Left side.

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

AMD CPU S1G2 PWR & GND

AMD CPU S1G2 PWR & GND

LA-4091P

LA-4091P

LA-4091P

753Thursday, November 08, 2007

753Thursday, November 08, 2007

753Thursday, November 08, 2007

E

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

+V_DDR_MCH_REF

JP4

JP4

1

VREF

3

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0

1 1

2 2

3 3

4 4

DDR_CKE0_DIMMA5

DDR_A_BS#25

DDR_A_BS#05
DDR_A_WE#5

DDR_A_CAS#5
DDR_CS1_DIMMA#5

DDR_A_ODT15

SMB_CK_DAT09,15,20,28
SMB_CK_CLK09,15,20,28

+3VS

DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16 DDR_A_D20
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1 DDR_A_MA0

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS# DDR_A_ODT0
DDR_CS1_DIMMA#

DDR_A_ODT1

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7

DDR_A_D58
DDR_A_D59

1

C103

C103

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

P-TWO_A5692B-A0G16-P

CONN@

CONN@

DQS3#

NC/CKE1

NC/A15
NC/A14

NC/A13

DQS5#

DQS7#

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3

DQ30
DQ31

RAS#

ODT0

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7

DQ62
DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS

DM2
VSS

VSS

VSS

VSS

VSS

VDD

VDD

VDD

VDD
BA1

VDD

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

B

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D4
DDR_A_D5

DDR_A_DM0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1

DDR_A_D14
DDR_A_D15

DDR_A_D21

DDR_A_DM2

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_DM6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_A _DQS[0..7]

DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_CLK0 5
DDR_A_CLK#0 5

+V_DDR_MCH_REF

1

2

DDR_CKE1_DIMMA 5

DDR_A_BS#1 5
DDR_A_RAS# 5
DDR_CS0_DIMMA# 5

DDR_A_ODT0 5

DDR_A_CLK1 5
DDR_A_CLK#1 5

C

DDR_A_D[0..63] 5

DDR_A_DM[0..7] 5

DDR_A _DQS[0..7] 5

DDR_A_MA[0..15] 5

DDR_A_DQS#[0..7] 5

+1.8V

R43

R43
1K_0402_1%

1K_0402_1%

1 2

1

C96

C96

C95

C95

2

1 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1000P_0402_25V8J

1000P_0402_25V8J

R44

R44
1K_0402_1%

1K_0402_1%

+V_DDR_MCH_REF 9

D

DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_A_MA14

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA15
DDR_CKE1_DIMMA

DDR_A_MA0
DDR_A_BS#1
DDR_A_MA2
DDR_A_MA4

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

DDR_A_BS#0
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3

DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_WE#
DDR_A_CAS#

DDR_A_ODT0
DDR_A_MA13
DDR_A_RAS#
DDR_CS0_DIMMA#

RP1

RP1

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

RP2

RP2

47_0804_8P4R_5%

47_0804_8P4R_5%

RP3

RP3

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

RP4

RP4

47_0804_8P4R_5%

47_0804_8P4R_5%

RP5

RP5

47_0804_8P4R_5%

47_0804_8P4R_5%

RP6

RP6

47_0804_8P4R_5%

47_0804_8P4R_5%

RP7

RP7

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

+0.9V

1 2

C87 0.1U_0402_16V4ZC87 0.1U_0402_16V4Z

1 2

C88 0.1U_0402_16V4ZC88 0.1U_0402_16V4Z

1 2

18

C90 0.1U_0402_16V4ZC90 0.1U_0402_16V4Z

27

1 2

36

C89 0.1U_0402_16V4ZC89 0.1U_0402_16V4Z

45

1 2

C91 0.1U_0402_16V4ZC91 0.1U_0402_16V4Z

1 2

C92 0.1U_0402_16V4ZC92 0.1U_0402_16V4Z

1 2

18

C93 0.1U_0402_16V4ZC93 0.1U_0402_16V4Z

27

1 2

36

C94 0.1U_0402_16V4ZC94 0.1U_0402_16V4Z

45

1 2

18

C98 0.1U_0402_16V4ZC98 0.1U_0402_16V4Z

27

1 2

36

C97 0.1U_0402_16V4ZC97 0.1U_0402_16V4Z

45

1 2

18

C100 0.1U_0402_16V4ZC100 0.1U_0402_16V4Z

27

1 2

36

C99 0.1U_0402_16V4ZC99 0.1U_0402_16V4Z

45

1 2

C102 0.1U_0402_16V4ZC102 0.1U_0402_16V4Z

1 2

C101 0.1U_0402_16V4ZC101 0.1U_0402_16V4Z

E

+1.8V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRII SO-DIMM 0

DDRII SO-DIMM 0

DDRII SO-DIMM 0

LA-4091P

LA-4091P

LA-4091P

853Thursday, November 08, 2007

853Thursday, November 08, 2007

853Thursday, November 08, 2007

E

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

B

C

D

E

+1.8V

+V_DDR_MCH_REF8

1

1 1

2 2

3 3

4 4

2

DDR_CKE0_DIMMB5

DDR_B_BS#25

DDR_B_BS#05
DDR_B_WE#5

DDR_B_CAS#5
DDR_CS1_DIMMB#5

DDR_B_ODT15

SMB_CK_DAT08,15,20,28
SMB_CK_CLK08,15,20,28

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

C104

C104

DDR_B_D2
DDR_B_D3

DDR_B_D8

1000P_0402_25V8J

1000P_0402_25V8J

DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS#2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS# DDR_B_ODT0
DDR_CS1_DIMMB#

DDR_B_ODT1

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43 DDR_B_D47

DDR_B_D48
DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7

DDR_B_D58
DDR_B_D59

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C119

C119

1

2

JP5

JP5

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

PTI_A5652D-A0G16-P

PTI_A5652D-A0G16-P

CONN@

CONN@

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

NC

A11

A7
A6

A4
A2
A0

S0#

NC

+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_D4
DDR_B_D5

DDR_B_DM0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE1_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46

DDR_B_D52

DDR_B_DM6

DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

+3VS

DDR_B_D[0..63]

DDR_B_DM[0..7]

DDR_B _DQS[0..7]

DDR_B_MA[0..15]

DDR_B_DQS#[0..7]

DDR_B_CLK0 5
DDR_B_CLK#0 5

DDR_CKE1_DIMMB 5

DDR_B_BS#1 5
DDR_B_RAS# 5
DDR_CS0_DIMMB# 5

DDR_B_ODT0 5

DDR_B_CLK1 5
DDR_B_CLK#1 5

DDR_B_D[0..63] 5

DDR_B_DM[0..7] 5

DDR_B _DQS[0..7] 5

DDR_B_MA[0..15] 5

DDR_B_DQS#[0..7] 5

DDR_B_BS#1
DDR_B_MA2
DDR_B_MA0
DDR_B_MA6

DDR_B_MA4
DDR_B_MA14
DDR_B_MA7
DDR_B_MA11

DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA10
DDR_B_MA3
DDR_B_MA1

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_B_MA13
DDR_B_ODT0
DDR_B_RAS#
DDR_CS0_DIMMB#

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

1 8
2 7
3 6
4 5

47_0804_8P4R_5%

47_0804_8P4R_5%

RP10

RP10

RP11

RP11

RP12

RP12

RP13

RP13

RP14

RP14

RP8

RP8

RP9

RP9

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

+0.9V

12

C105 0.1U_0402_16V4ZC105 0.1U_0402_16V4Z

1 2

C106 0.1U_0402_16V4ZC106 0.1U_0402_16V4Z

12

C108 0.1U_0402_16V4ZC108 0.1U_0402_16V4Z

1 2

C107 0.1U_0402_16V4ZC107 0.1U_0402_16V4Z

12

C109 0.1U_0402_16V4ZC109 0.1U_0402_16V4Z

1 2

C110 0.1U_0402_16V4ZC110 0.1U_0402_16V4Z

12

C111 0.1U_0402_16V4ZC111 0.1U_0402_16V4Z

1 2

C112 0.1U_0402_16V4ZC112 0.1U_0402_16V4Z

12

C114 0.1U_0402_16V4ZC114 0.1U_0402_16V4Z

1 2

C113 0.1U_0402_16V4ZC113 0.1U_0402_16V4Z

12

C116 0.1U_0402_16V4ZC116 0.1U_0402_16V4Z

1 2

C115 0.1U_0402_16V4ZC115 0.1U_0402_16V4Z

12

C118 0.1U_0402_16V4ZC118 0.1U_0402_16V4Z

1 2

C117 0.1U_0402_16V4ZC117 0.1U_0402_16V4Z

+1.8V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRII SO-DIMM 1

DDRII SO-DIMM 1

DDRII SO-DIMM 1

LA-4091P

LA-4091P

LA-4091P

953Thursday, November 08, 2007

953Thursday, November 08, 2007

953Thursday, November 08, 2007

E

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

U3B

U3B

D4

GFX_RX0 P

C4

GFX_RX0 N

A3

GFX_RX1 P

B3

1 1

PCIE_PTX_C_IRX_P026
PCIE_PTX_C_IRX_N026

2 2

3 3

4 4

PCIE_PTX_C_IRX_P127
PCIE_PTX_C_IRX_N127
PCIE_PTX_C_IRX_P226
PCIE_PTX_C_IRX_N226
PCIE_PTX_C_IRX_P325
PCIE_PTX_C_IRX_N325

PCIE_PTX_C_IRX_P526
PCIE_PTX_C_IRX_N526

SB_RX0P19
SB_RX0N19
SB_RX1P19
SB_RX1N19
SB_RX2P19
SB_RX2N19
SB_RX3P19
SB_RX3N19

GFX_RX1 N

C2

GFX_RX2 P

C1

GFX_RX2 N

E5

GFX_RX3 P

F5

GFX_RX3 N

G5

GFX_RX4 P

G6

GFX_RX4 N

H5

GFX_RX5 P

H6

GFX_RX5 N

J6

GFX_RX6 P

J5

GFX_RX6 N

J7

GFX_RX7 P

J8

GFX_RX7 N

L5

GFX_RX8 P

L6

GFX_RX8 N

M8

GFX_RX9 P

L8

GFX_RX9 N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS780M_FCBGA528

RS780M_FCBGA528

RS780M Display Port Support (muxed on GFX)

DP0

DP1

PART 2 OF 6

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F GPP

PCIE I/F SB

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

GFX_TX0,TX1,TX2 and TX3

AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7

AUX1 and HPD1

GFX_TX0 P
GFX_TX0 N
GFX_TX1 P
GFX_TX1 N
GFX_TX2 P
GFX_TX2 N
GFX_TX3 P
GFX_TX3 N
GFX_TX4 P
GFX_TX4 N
GFX_TX5 P
GFX_TX5 N
GFX_TX6 P
GFX_TX6 N
GFX_TX7 P
GFX_TX7 N
GFX_TX8 P
GFX_TX8 N
GFX_TX9 P

GFX_TX9 N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

B

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_ITX_PRX_P0

AC1

PCIE_ITX_PRX_N0

AC2

PCIE_ITX_PRX_P1

AB4

PCIE_ITX_PRX_N1

AB3

PCIE_ITX_PRX_P2

AA2

PCIE_ITX_PRX_N2

AA1

PCIE_ITX_PRX_P3

Y1

PCIE_ITX_PRX_N3

Y2
Y4
Y3

PCIE_ITX_PRX_P5

V1

PCIE_ITX_PRX_N5

V2

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

AC8
AB8

TMDS_B_DATA2 18
TMDS_B_DATA2# 18
TMDS_B_DATA1 18
TMDS_B_DATA1# 18
TMDS_B_DATA0 18
TMDS_B_DATA0# 18
TMDS_B_CLK 18
TMDS_B_CLK# 18

C152 0.1U_0402_16V7KC152 0.1U_0402_16V7K
C153 0.1U_0402_16V7KC153 0.1U_0402_16V7K
C154 0.1U_0402_16V7KC154 0.1U_0402_16V7K
C155 0.1U_0402_16V7KC155 0.1U_0402_16V7K
C156 0.1U_0402_16V7KC156 0.1U_0402_16V7K
C157 0.1U_0402_16V7KC157 0.1U_0402_16V7K
C158 0.1U_0402_16V7KC158 0.1U_0402_16V7K
C159 0.1U_0402_16V7KC159 0.1U_0402_16V7K

C160 0.1U_0402_16V7KC160 0.1U_0402_16V7K

SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C

R55 1.27K_0402_1%R55 1.27K_0402_1%
R56 2K_0402_1%R56 2K_0402_1%

C161 0.1U_0402_16V7KC161 0.1U_0402_16V7K

C162 0.1U_0402_16V7KC162 0.1U_0402_16V7K
C163 0.1U_0402_16V7KC163 0.1U_0402_16V7K
C164 0.1U_0402_16V7KC164 0.1U_0402_16V7K
C165 0.1U_0402_16V7KC165 0.1U_0402_16V7K
C166 0.1U_0402_16V7KC166 0.1U_0402_16V7K
C168 0.1U_0402_16V7KC168 0.1U_0402_16V7K
C169 0.1U_0402_16V7KC169 0.1U_0402_16V7K
C167 0.1U_0402_16V7KC167 0.1U_0402_16V7K

1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

+1.1VS

C

PCIE_ITX_C_PRX_P0 26
PCIE_ITX_C_PRX_N0 26
PCIE_ITX_C_PRX_P1 27
PCIE_ITX_C_PRX_N1 27
PCIE_ITX_C_PRX_P2 26
PCIE_ITX_C_PRX_N2 26
PCIE_ITX_C_PRX_P3 25
PCIE_ITX_C_PRX_N3 25

PCIE_ITX_C_PRX_P5 26
PCIE_ITX_C_PRX_N5 26

SB_TX0P 19
SB_TX0N 19
SB_TX1P 19
SB_TX1N 19
SB_TX2P 19
SB_TX2N 19
SB_TX3P 19
SB_TX3N 19

New Card

Cardreader

WLAN

GLAN

TV Tuner

H_CLKOP04
H_CLK ON04
H_CLKOP14
H_CLK ON14

H_CTLOP 04

H_CTLON04

H_CTLON14

0718 Place within 1"
layout 1:2

H_CADOP[0..15]4

H_CADON[0..15]4 H_CADIN[0..15] 4

R57 301_0402_1%R57 301_0402_1%

1 2

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9

H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CTLOP 0
H_CTLON0
H_CTLOP 1
H_CTLON1

D

H_CADON[0..15]

U3A

U3A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCTL1N

C23

HT_RXCALP

A24

HT_RXCALN

RS780M_FCBGA528

RS780M_FCBGA528

PART 1 OF 6

PART 1 OF 6

HYPER TRANSPORT CPU I/F

HYPER TRANSPORT CPU I/F

H_CADIP[0..15]H_CADOP[0..15]

H_CADIN[0..15]

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

HT_TXCALP
HT_TXCALN

H_CADIP[0..15] 4

H_CADIP0

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18

H24
H25
L21
L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1

R18

B24
B25

0718 Place within 1"
layout 1:2

E

H_CLKIP0 4
H_CLK IN0 4
H_CLKIP1 4
H_CLK IN1 4

H_CTLIP0 4

H_CTLIN0 4

H_CTLIP1 4H_CTLOP 14

H_CTLIN1 4

R58 301_0402_1%R58 301_0402_1%

1 2

NEED CHECK R68 & R69 WITH AMD

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet

Compal Electronics, Inc.

RS780-HT/PCIE

RS780-HT/PCIE

RS780-HT/PCIE

LA-4091P

LA-4091P

LA-4091P

E

of

10 53Thursday, November 08, 2007

10 53Thursday, November 08, 2007

10 53Thursday, November 08, 2007

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

B

C

D

E

+1.8VS

L6

L6

1 2

C175

C175

+NB_PLLVDD

1

2

LCD_DDC_DAT17

+3VS

1

2

R67 0_0402_5%R67 0_0402_5%

1 2

NBGFX_ CLK15
NBGFX_CLK#15

CLK_SBLINK_BCLK15
CLK_SBLINK_BCLK#15

1

C176

C176

2

+VDDA18HTPLL

1

C179

C179

2

+VDDA18PCIEPLL

1

C180

C180

2

1 2

R71

R71

4.7K_0402_5%

4.7K_0402_5%

RED

GREEN

BLUE

+1.8VS

+NB_HTPVDD+1.8VS

+1.1VS

1 2

R72

R72

4.7K_0402_5%

4.7K_0402_5%

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

L9

L9

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

C178

C178

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

PLT_ RST#14,19,25,26,27,32,33

NB_OSC_14.318M15

LCD_DDC_CLK17

HDMIDAT_UM A18
HDMICLK _UMA18

1 2

R62 150_0402_1%R62 150_0402_1%

1 2

1 1

+1.8VS

2 2

+1.8VS

1 2

R371 300_0402_5%R371 300_0402_5%

+1.8VS

NB_PW RGD

R63 150_0402_1%R63 150_0402_1%

1 2

R64 150_0402_1%R64 150_0402_1%

L7

L7

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

L10

L10

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

L11

L11

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

+1.1VS

For SB700 A12 use

3 3

L2

L2

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

L4

L4

0_0603_5%

0_0603_5%

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

+AVDDQ

CRT_HSYNC14,16

CRT_VSYNC14,16
UMA_CRT_CLK16
UMA_CRT_DAT16 LVDS_BCLK- 17

NB_PW RGD20

LDT_STOP#6,19

CPU_LDT_REQ#6,19

CLK_ NBHT15
CLK_ NBHT#15

+3VS

1

C172

C172

2

RED16

GREEN16

BLUE16

R65 715_0402_1%R65 715_0402_1%

1 2

+NB_PLLVDD

+NB_HTPVDD

+VDDA18HTPLL

+VDDA18PCIEPLL

R88 10K_0402_5%R88 10K_0402_5%

AUX_CAL14

Strap pin

+AVDD1

+AVDD2

RED

GREEN

BLUE

+NB_PLLVDD
+NB_HTPVDD

NB_PW RGD

AVDD=100mA

1

2

CRT_HSYNC
CRT_VSYNC

NB_RESET#

12

C170

C170

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

U3C

U3C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(D FT _G PI O2 )

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb (NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTS TOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REF CLKP

T1

GFX_REF CLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

RS780M_FCBGA528

PART 3 OF 6

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVTM

PM

PM

CLOCKs PLL PWR

CLOCKs PLL PWR

MIS.

MIS.

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U 0P(NC )
TXOUT_U0N(NC )

TXOUT_U 2P(NC )
TXOUT_U2N(NC )

TXOUT_U3N(NC )

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)

VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

HPD(NC )

THERMALDIODE_P
THERMALDIODE_N

TESTMODE

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

+VDDLTP18

A13
B13

+VDDLT18

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9

R69 0_0402_5%R69 0_0402_5%

F7

R70 0_0402_5%R70 0_0402_5%

G12

D9
D10

1 2

D12

R77 0_0402_5%R77 0_0402_5%

AE8
AD8

1 2

D13

R80

R80

1.8K_0402_5%

1.8K_0402_5%

LVDS_A0+ 17
LVDS_A0- 17
LVDS_A1+ 17
LVDS_A1- 17
LVDS_A2+ 17
LVDS_A2- 17

LVDS_B0+ 17
LVDS_B0- 17
LVDS_B1+ 17
LVDS_B1- 17
LVDS_B2+ 17
LVDS_B2- 17

LVDS_ACLK+ 17
LVDS_ACLK- 17
LVDS_BCLK+ 17

1 2
1 2

+VDDLTP18

+VDDLT18

0.1U_0402_16V4Z

0.1U_0402_16V4Z

HPD 18

SUS_STAT# 20
SUS_STAT_R# 14

1

C173

C173

2

UMA_ENVDD 17
ENBKL 33

Strap pin

L3

L3

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

C171

C171

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

1 2

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1

C174

C174

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

+1.8VS

L5

L5

+1.8VS

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

RS780 VEDIO/CLK GEN

RS780 VEDIO/CLK GEN

RS780 VEDIO/CLK GEN

LA-4091P

LA-4091P

LA-4091P

11 53Thursday, November 08, 2007

11 53Thursday, November 08, 2007

11 53Thursday, November 08, 2007

E

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

2

U3D

U61

MEM_BA0
MEM_BA1

MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2 MEM_A12
MEM_A1

12

R91

R91

100_0402_1%

100_0402_1%

B B

SIDE@

SIDE@

MEM_A0

MEM_CLK N
MEM_CLK P

MEM_CKE

MEM_CS#

MEM_WE#

MEM_RAS#

MEM_CAS #

MEM_DM0
MEM_DM1

MEM_ODT

MEM_DQS_P 0
MEM_DQS_N0

MEM_DQS_P 1
MEM_DQS_N1

+MEM_VREF

MEM_BA2

U61

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC

E2

NC

L1

NC

R3

NC

R7

NC

R8

NC

HY5PS561621AFP-25_FBGA84

HY5PS561621AFP-25_FBGA84

SIDE@

SIDE@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD

VDDL

VSSDL

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VSS
VSS
VSS
VSS
VSS

MEM_DQ15

B9

MEM_DQ11

B1

MEM_DQ13 ME M_A1

D9

MEM_DQ12 ME M_A2

D1

MEM_DQ8

D3

MEM_DQ10

D7

MEM_DQ9

C2

MEM_DQ14

C8

MEM_DQ3

F9

MEM_DQ7

F1

MEM_DQ1

H9

MEM_DQ6

H1

MEM_DQ5

H3

MEM_DQ0

H7

MEM_DQ4

G2

MEM_DQ2

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

+1.8V_MEM_ VDDQ

+VDDL

+1.8V_MEM_ VDDQ

+1.8V_MEM_ VDDQ

1U_0603_10V6K

1U_0603_10V6K

1

Layout No te: 50 mil for VSSDL

C184

C184

SIDE@

SIDE@

2

SIDE@

SIDE@

12

R92 40.2_0402_1%

R92 40.2_0402_1%

12

R93 40.2_0402_1%

R93 40.2_0402_1%

SIDE@

SIDE@

MEM_A0

MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS #
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLK P
MEM_CLK N

MEM_COMP_P

MEM_COMP_N

AB12
AE16

V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14

Y14

AD16
AE17
AD17

W12

Y12
AD18
AB13
AB18

V14

V15

W14

AE12
AD12

RS780M_FCBGA528

RS780M_FCBGA528

<BOM Structure>

<BOM Structure>

U3D

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC )
MEM_A11(NC )
MEM_A12(NC )
MEM_A13(NC )

MEM_BA0 (NC)
MEM_BA1 (NC)
MEM_BA2 (NC)

MEM_RASb(NC )
MEM_CAS b(NC)
MEM_WEb(NC)
MEM_CSb (NC)
MEM_CKE (NC)
MEM_ODT(NC)

MEM_CKP (NC)
MEM_CKN(NC)

MEM_COMPP (NC)
MEM_COMPN(NC)

PAR 4 OF 6

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC )

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P (NC)
MEM_DQS1N(NC )

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

MEM_VREF(NC )

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23

AE18

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS_P 0
MEM_DQS_N0
MEM_DQS_P 1
MEM_DQS_N1

MEM_DM0
MEM_DM1

+NB_IOPLLVDD

+MEM_VREF1

1

MEM_COMP_ P and ME M_COMP_N tra ce
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

0_0603_5%

0_0603_5%

+1.8V_IOPLLVDD

1

2

1 2

1

C181

C181

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

SIDE@

SIDE@

L13

L13

+1.1VS

C182

C182

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SIDE@

SIDE@

L12

L12

1 2

1

C183

C183

2.2U_0603_6.3V4Z

2.2U_0603_6.3V4Z

2

SIDE@

SIDE@

+1.8VS

0_0603_5%

0_0603_5%

+1.8V_MEM_ VDDQ+1.8V_ME M_VDDQ

1

SIDE@

A A

SIDE@

SIDE@

SIDE@

C195

C195

2

1

C199

C199

2

SIDE@

SIDE@

R96

R96

1 2

1K_0402_1%

1K_0402_1%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+MEM_VREF

SIDE@

SIDE@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R98

R98

1 2

1K_0402_1%

1K_0402_1%

SIDE@

SIDE@

SIDE@

SIDE@

1

C196

C196

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C200

C200

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

R97

R97

1 2

R99

R99

1 2

SIDE@

SIDE@

1K_0402_1%

1K_0402_1%

+MEM_VREF1

SIDE@

SIDE@

1K_0402_1%

1K_0402_1%

SIDE@

SIDE@

+1.8V_MEM_ VDDQ

SIDE@

SIDE@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

C607

C607

1

2

C608

C608

1

1

SIDE@

SIDE@

1U_0402_6.3V4Z

1U_0402_6.3V4Z

SIDE@

SIDE@

C201

C201

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Issued Date

Issued Date

Issued Date

C202

C202

1

1

C203

C203

SIDE@

SIDE@

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

L15

L15

1 2

0_0805_5%SIDE@

0_0805_5%SIDE@

220 ohm @ 100MHz,2A

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.8VS

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

1

Date: Sheet of

Compal Electronics, Inc.

RS780 SIDE PORT

RS780 SIDE PORT

RS780 SIDE PORT

LA-4091P

LA-4091P

LA-4091P

12 53Thursday, November 08, 2007

12 53Thursday, November 08, 2007

12 53Thursday, November 08, 2007

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

1 1

2 2

3 3

+1.1VS

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

+1.2V_HT

+1.35VS

+1.8VS

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805@

FBMA-L11-201209-221LMA30T_0805@

L16

L16

L18

L18

L19

L19

L43

L43

L22

L22

4.7U_0805_10V4Z

4.7U_0805_10V4Z

12

C209

C209

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2A

12

1

C215

C215

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2A

12

12

C225

C225

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2A

12

1

C246

C246

C235

C235

2

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2A

1

1

C206

C206

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C216

C216

C214

C214

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C226

C226

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C236

C236

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C207

C207

C208

C208

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C217

C217

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C227

C227

C228

C228

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C238

C238

C237

C237

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.8VS

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

C210

C210

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+VDDHTRX

1

C218

C218

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C229

C229

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C239

C239

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C251

C251

+VDDHT

1

2

+VDDHTTX

1

2

+VDDA18PCIE

1

2

1

2

+1.8VS

B

AE25
AD24
AC23
AB22
AA21

AE11
AD11

1

C252

C252
1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

SIDE@

SIDE@

U3E

U3E

J17

VDDHT_1

K16

VDDHT_2

L16

VDDHT_3

M16

VDDHT_4

P16

VDDHT_5

R16

VDDHT_6

T16

VDDHT_7

H18

VDDHTRX_1

G19

VDDHTRX_2

F20

VDDHTRX_3

E21

VDDHTRX_4

D22

VDDHTRX_5

B23

VDDHTRX_6

A23

VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5

Y20

VDDHTTX_6

W19

VDDHTTX_7

V18

VDDHTTX_8

U17

VDDHTTX_9

T17

VDDHTTX_10

R17

VDDHTTX_11

P17

VDDHTTX_12

M17

VDDHTTX_13

J10

VDDA18PCIE_1

P10

VDDA18PCIE_2

K10

VDDA18PCIE_3

M10

VDDA18PCIE_4

L10

VDDA18PCIE_5

W9

VDDA18PCIE_6

H9

VDDA18PCIE_7

T10

VDDA18PCIE_8

R10

VDDA18PCIE_9

Y9

VDDA18PCIE_10

AA9

VDDA18PCIE_11

AB9

VDDA18PCIE_12

AD9

VDDA18PCIE_13

AE9

VDDA18PCIE_14

U10

VDDA18PCIE_15

F9

VDD18_1

G9

VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS780M_FCBGA528

RS780M_FCBGA528

PART 5/6

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

VDDA_12=2.5A

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

C

L17

L17

1 2

FBMA-L11-201209-221LMA30T_0805

+VDDA11PCIE

FBMA-L11-201209-221LMA30T_0805

10U_0805_10V4Z

10U_0805_10V4Z

C211

C211

10U_0805_10V4Z

10U_0805_10V4Z

C212

C212

C220 1U_0402_6.3V4ZC220 1U_0402_6.3V4Z

1 2

C219 1U_0402_6.3V4ZC219 1U_0402_6.3V4Z

1 2

C222 1U_0402_6.3V4ZC222 1U_0402_6.3V4Z

1 2

C221 1U_0402_6.3V4ZC221 1U_0402_6.3V4Z

1 2

C224 0.1U_0402_16V4ZC224 0.1U_0402_16V4Z
C223 0.1U_0402_16V4ZC223 0.1U_0402_16V4Z

+1.1VS +NB_VDDC

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12
12

L20

L20

1 2

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805
L21

L21

1 2

VDD_CORE=5A

1

1

1

1

1

1

1

1

C2470.1U_0402_16V4Z C2470.1U_0402_16V4Z

2

+3VS

C2400.1U_0402_16V4Z C2400.1U_0402_16V4Z

2

1

C2420.1U_0402_16V4Z C2420.1U_0402_16V4Z

C2410.1U_0402_16V4Z C2410.1U_0402_16V4Z

C2430.1U_0402_16V4Z C2430.1U_0402_16V4Z

C2310.1U_0402_16V4Z C2310.1U_0402_16V4Z

C2300.1U_0402_16V4Z C2300.1U_0402_16V4Z

2

2

2

2

+1.8VS

1 2

1 2

1

C2440.1U_0402_16V4Z C2440.1U_0402_16V4Z

C2320.1U_0402_16V4Z C2320.1U_0402_16V4Z

C23310U_0805_10V4Z C23310U_0805_10V4Z

2

2

2

2

12
12
12
12
12

C2500.1U_0402_16V4Z C2500.1U_0402_16V4Z

C2530.1U_0402_16V4Z C2530.1U_0402_16V4Z

+1.1VS

330U_D2E_2.5VM

330U_D2E_2.5VM

1

C234

C234

1

C24510U_0805_10V4Z C24510U_0805_10V4Z

+

+

2

2

C2491U_0402_6.3V4Z SIDE@C2491U_0402_6.3V4Z SIDE@
C2481U_0402_6.3V4Z SIDE@C2481U_0402_6.3V4Z SIDE@
C5970.1U_0402_16V4Z SIDE@C5970.1U_0402_16V4Z SIDE@
C5980.1U_0402_16V4Z SIDE@C5980.1U_0402_16V4Z SIDE@
C5990.1U_0402_16V4Z SIDE@C5990.1U_0402_16V4Z SIDE@

D

U3F

U3F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS780M_FCBGA528

RS780M_FCBGA528

PART 6/6

PART 6/6

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30

GROUND

GROUND

VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

E

+1.8VS

U67

U67

VIN1VCNTL

1

C903

C903

10U_0805_10V4Z@

10U_0805_10V4Z@

Q56

Q56

2N7002_SOT23-3@

4 4

VLDT_EN#36

R601 0_0402_5%@R601 0_0402_5%@

A

1 2

2N7002_SOT23-3@

2

G

G

2

C703

C703

0.1U_0402_16V7K@

0.1U_0402_16V7K@

1

12

2

R599

R599
1K_0402_1%@

1K_0402_1%@

+VREF1.35V

12

R600

R600

@

@

3K_0402_5%

3K_0402_5%

13

D

D

S

S

0.1U_0402_16V7K@

0.1U_0402_16V7K@

2

GND

3

VREF

4

VOUT

G2992F1U_SO8@

G2992F1U_SO8@

2

1

C702

C702

C905

C905

1

2

10U_0805_10V4Z@

10U_0805_10V4Z@

B

+1.35VS

6

5

NC

7

NC

8

NC

9

TP

+3VS

1

C463

C463
1U_0603_10V6K@

1U_0603_10V6K@

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet

Compal Electronics, Inc.

RS780 PWR/GND

RS780 PWR/GND

RS780 PWR/GND

LA-4091P

LA-4091P

LA-4091P

E

of

13 53Thursday, November 08, 2007

13 53Thursday, November 08, 2007

13 53Thursday, November 08, 2007

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

B

C

D

E

RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K

CRT_VSYNC11,16

1 1

12

R101 1K_0402_5%@R101 1K_0402_5%@

12

R102 1K_0402_5%R102 1K_0402_5%

+3VS

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.
1 : Enable (RX780, RS780)
0 : Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These pin straps are used to configure PCI-E GPP mode.
000 : 00001
001 : 00010

RS780 use register to control PCI-E configure

2 2

010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011

DFT_GPIO1: LOAD_EEPROM_STRAPS

1 2

R104 150_0402_1%@R104 150_0402_1%@

D4 CH751H-40PT_SOD323-2@D4 CH751H-40PT_SOD323-2@

2 1

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RS780 DFT_GPIO1

AUX_CAL11

SUS_STAT_R#11 PLT_RST# 11,19,25,26,27,32,33

3 3

RS780 use HSYNC to enable SIDE PORT (internal pull high)

CRT_HSYNC11,16

4 4

A

12

R107 1K_0402_5%SIDE@ R107 1K_0402_5%SIDE@

B

DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb

RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS780)
0 : Enable (RS780)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECT RONICS, INC.

C

2007/08/02 2008/08/02

2007/08/02 2008/08/02

2007/08/02 2008/08/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Numbe r Rev

Size Document Numbe r Rev

Size Document Numbe r Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

RS780 STRAPS

RS780 STRAPS

RS780 STRAPS

LA-4091P

LA-4091P

LA-4091P

14 53Thursday, November 08, 2007

14 53Thursday, November 08, 2007

14 53Thursday, November 08, 2007

E

0.1

0.1

0.1

http://laptop-motherboard-schematic.blogspot.com/