April 2001
Compaq Computer
Corporation
Prepared by
ISSG Technology
Communications
ONTENTS
C
Introduction.....................3
Cache Architecture ..........3
The Function of Cache
Memory................................. 3
The Pentium III X eon
Cache Architecture ................ 3
Benchmark Test Results ..4
On-Line Transaction
Processing Testing in a
SQL Server Enviro nment........ 4
SAP Central Server
Running a SQL7
Database...............................7
Microsoft Exchange 2000
Test ......................................9
ServerBench T est ................11
Terminal Serve r Test............13
Conclusions ...................14
Appendix: ServerBench
Disclosure Information ..15
T
ECHNOLOGY
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Performance Comparison of Pentium III
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Xeon Cache Options
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Many factors determine the performance of an industry-standard server, and processor
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cache size is one that can have a dramatic effect. However, processors with larger
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caches also carry a significantly higher cost, raising the question as to whether the
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performance gained will justify the expense. Making sound purchasing decisions requires
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understanding how much performance gain to expect from an increase in cache size in a
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specific computing environment. This paper reports the results of benchmarking tests
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performed by Compaq laboratories to determine the effect of cache size on system
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performance.
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Please direct comments regarding this communication to the ISSG Technology Communications Group at this Internet
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address: TechCom@compaq.com
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B
RIEF
1
TC010401TB
TC010401TB
ECHNOLOGY BRIEF
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OTICE
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The information in this publication is subject to change without notice and is provided “AS IS”
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WITHOUT WARRANTY OF ANY KIND. THE ENTIRE RISK ARISING OUT OF T HE USE
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OF THIS INFORMATION REMAINS WITH RECIPIENT. IN NO EVENT SHALL COMPAQ
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BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, SPECIAL, PUNITIVE
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OR OTHER DAMAGES WHATSOEVER (INCLUDING WITHOUT LIMITATION,
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DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION OR LOSS OF
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BUSINESS INFORMATION), EVEN IF COMPAQ HAS BEEN ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGES.
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The limited warranties for Compaq products are exclusively set forth in the documentation
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accompanying such products. Nothing herein should be construed as constituting a further or
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additional warranty.
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This publication does not constitute an endorsement of the product or products that were tested.
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The configuration or configurations tested or described may or may not be the only available
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solution. This test is not a determination of product quality or correctness, nor does it ensure
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compliance with any federal state or local requirements.
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Compaq and ProLiant are registered with the United States Patent and Trademark Office.
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Intel and Pentium are registered trademarks and Pentium II Xeon and Pentium III Xeon are
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trademarks of Intel Corporation.
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Other product names mentioned herein may be trademarks and/or registered trademarks of their
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respective companies.
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©2001 Compaq Computer Corporation.
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Printed in the U.S.A.
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Performance Comparison of Pentium III Xeon Cache Options
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First Edition (April 2001)
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TC010401TB
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(cont.)
Cache: a relatively small
local memory that stores a
copy of recently used
instructions and data
Coherency:
Maintaining a
consistent relationship
among the contents of
multiple caches,
keeping each cache
informed of any
changes that affect its
data
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TC010401TB
ECHNOLOGY BRIEF
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NTRODUCTION
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Although for years pro cessor speed ha s been considered the prime indica t or of system
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performance, cache size can also dramatically affect system performance in some application
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environments. For example, the performance of memory-intensive applications ordinarily benefit
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from increased cache memory. While some applications can take advantage of more cache to gain
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better performance, others achieve their peak performance from a smaller cache and realize no
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improvement from a larger one. Where a choice exists, selecting the optimum cache size for a
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given environment gives cust omers the best value for their computi ng dollar.
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This paper reports the results of five benchmark tests performed by Compaq laboratories to
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determine the effect of cache size on system performance. These tests represent several types of
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computing environments for which customers often purchase servers. The results of these tests
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underscore the importance of understanding the relationship of the cache size to system
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performance in specific computing environments and of weighing the trade-offs involved to
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determine the best cache solution.
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ACHE ARCHITECTURE
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For those unfamiliar with the basic concepts, some background information on cache memory will
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be helpful in understanding the discussion of the test results.
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The Function of Cache Memory
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Cache memory improves system performance by keeping a copy of recently used data in a small,
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fast memory near the processor. Since cache memory typically runs at the same speed as the
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processor, access to information stored in cache memory is much faster than access to the same
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information stored in main memory. Caching is effective because most programs use the same
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instructions and data repeatedly, and these repetitions allow a processor to run from its cache most
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of the time. The more a processor can run from its cache, the more system performance increases.
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In fact, to increase performance, processor designers today include multiple levels of cache
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typically, a small primary (level one or L1) cache and a larger secondary (level two or L2) cache.
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When requesting data, the processor first accesses the L1 cache. If the requested data is not found
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in the L1 cache, the processor then accesses the L2 cache before going to slower main memory.
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Logically, larger caches should improve scalability and performance in multiprocessor systems
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because each processor keeps more data in its local cache, reducing competition with other
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processors in the system for access to resources. However, increasing the cache size also increases
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the likelihood that another processor will need access to some of the data stored there. Managing
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and maintaining coherency between the caches adds system bus traffic, and this overhead is
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increased with the use of more processors and larger caches.
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The Pentium III Xeon Cache Architecture
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Intel Pentium III Xeon processors have two levels of cache memory, a relatively small L1 cache
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and a much larger L2 cache that varies in size. The L2 cache connects to the processor through a
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64-bit dedicated, transaction-oriented bus that supports up to four concurrent cache accesses. The
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earliest Pentium III processor (code named Katmai) used an external L2 cache running at half the
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processor frequency, but Pentium III Xeon processors use integrated caches that run at the full
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speed of the processor bus.
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For more information on the recent history of Intel processors, refer to The Intel Microprocessor
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Roadmap at http://www.compaq.com/support/techpubs/whitepapers/tc000808tb.html.
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(cont.)
1
Normalized: A method to
simplify comparison of a
set of values, in which the
lowest number divides into
all the numbers. The
lowest number is then
shown as a “normalized”
value of 1.0, while a
number that is twice as
much as the lowest number
is shown as 2.0, and so on.
MB: megabyte
TC010401TB
ECHNOLOGY BRIEF
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ENCHMARK TEST RESULTS
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Benchmark tests simulate real-world application environments in a controlled and repeatable
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fashion. Results of these standardized tests are certifiable by a standards body and therefore
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provide a ready means for comparing the performance of different configurations or solutions from
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different vendors. Several industry-standard benchmarks exist to evaluate server performance, each
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emphasizing different applications or areas of interest. This paper summarizes the results of such
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benchmark tests conducted by Compaq engineers to establish the effect of cache size on server
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performance.
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On-Line Transaction Processing Testing in a SQL Server Environment
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The on-line tr ansaction-pro cessing (OLTP ) test demonstrates how well a system’s throughput
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responds to a transaction-processing load. The goal for this test was to compare cache size
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performance rather than to obtain certifiable data, so only normalized data is presented here
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Figure 1 gives the normalized OLTP performance results for a Compaq ProLiant 8500 server using
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Pentium III Xeon 700-MHz processors with L2 caches of 1 MB (lower curve) and 2 MB (upper
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curve). The load placed on the system affects OLTP test performance, so tuning the load to
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optimize the performance of the configuration under test is part of the usual process. In this case,
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however, the load was kept constant so meaningful comparisons coul d be made.
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2
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The OLTP test results in this paper were loosely based on TPC benchmark testing. Refer to
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http://www.tpc.org
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results.
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Normalized Transactions/Second
(cont.)
Relative Performance Scaling
3.50
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2.50
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1.50
1.00
0.50
2468
Number of Processo rs
Figure 1 - OLTP Performance Improvement Between 1-MB
and 2-MB Caches in a ProLiant 8500 Server
to learn more about certified TPC testing and to see Compaq’s published
2 MB ca che
1 MB ca che
2
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TC010401TB
ECHNOLOGY BRIEF
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Figure 1 shows that, in each configuration, processors with 2-MB caches provided better system
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performance than the processors with 1-MB caches. In addition, it shows that both cache
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configurations followed the same non-linear scalability pattern—scalability did not improve with
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the larger cache. Table 1 summarizes the performance increases measured due to replacing 1-MB
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caches with 2-MB caches. Even though the difference in absolute system performance increased
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slightly with additional processors, that increase actually declined as a percentage of overall
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performance. The larger cache still provides improved performance for the configurations with a
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higher number of processors, but not as much improvement as it does for systems with fewer
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processors.
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Figure 2 demonstrates the difference larger caches can make in a four-processor OLTP
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environment using a Compaq ProLiant ML570 server. A set of 2-MB caches yields a 16 percent
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performance improvement over the 1-MB caches, and an even mix of 1-MB and 2-MB caches
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yields a performance gain of about half as much. Because Compaq supports mixing of cache sizes
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under certain conditions
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For details about Compaq support for mixing Intel processo rs in Compaq industry-standard
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servers, see http://www.compaq.com/support/techpubs/whitepapers/tc000703tb.html
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5
Normalized Transactions/Second
(cont.)
Table 1 – OLTP Performance Gain in an 8-Processor System
When 1-MB Caches Are Replaced by 2-MB Caches
Number of
Processors
2 20.1 %
4 14.6 %
6 15.8 %
8 12.8 %
3
, customers have another option for increasing system performance.
1.20
1.15
1.10
1.05
1.00
1.00
0.95
0.90
4 x 1MB 2 x 1MB + 2 x 2MB 4 x 2MB
Number and Cache S ize of Processors
Figure 2 - Cache Performance in a Four-Processo r System
Performance gained
from the larger cache
1.16
1.09
TC010401TB
ECHNOLOGY BRIEF
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Interestingly, Figure 3 indicates that increasing the system memory from 2GB to 4GB can also
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boost performance by 9 or 10 percent. This illustrates the need to address all potential system
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bottlenecks in the search for better performance.
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Figure 4 is a price/performance chart for six configurations of the Compaq ProLiant ML570 server.
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The chart was developed using the pricing information available on the Compaq web site.
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Although every installation will have a different overall cost, Figure 4 pro vides examples
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representative of the trade-offs in cost and performance. Clearly, a range of options is open to
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customers for increasing system performance in an OLTP environment.
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http://www.directpluspro.compaq.com/default.asp?page=ctoBases&Product_Line_Id=431&Famil
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y_Id=648
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6
Normalized Transactions/Second
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
(cont.)
1.26
2GB Memory
4GB Memory
1.09
1.00
4 x 1MB 2 x 1MB + 2 x 2MB 4 x 2MB
Number and Cache Size of Processors
Figure 3 – Memory and Cache Size Comparison
1.09
1.18
1.16
4
Write-back transactions:
When a cache line (block of
data) that has been
modified needs to be
replaced with other data,
the modified data must first
be written back to main
memory.
Bus invalidate: the process
by which a line of cache
data is marked as stale by
another processor.
Bus read for ownership:
occurs when a processor
needs to fetch data from the
system bus and at the same
time ensure that no other
cache has a copy of it.
Coherency transactions:
bus activity between
different processors to
ensure that changes to any
data are kept up to date
throughout all caches in the
system.
TC010401TB
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SAP Central Server Running a SQL7 Database
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In an SAP central server configuration, the SAP application and the database both reside on the
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same server. This SAP benchmark test was run on an early version of the ProLiant 8500 server
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using eight 450-MHz Pentium III Xeon processors with 512-KB, 1-MB, and 2-MB cache sizes.
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The SAP Sales and Distribution benchmark module was used to emulate customer orders,
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performing a number of steps to process each order. The test adds simulated users to increase the
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transaction load until the system response time reaches a threshold of two seconds.
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Figure 5 shows that increasing the cache size does yield a performance boost but at a diminishing
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rate, probably due to the increasing number of bus coherency transactions needed with larger cache
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configurations. Figure 6 gives some evidence for this asser t ion by showing bus transactions that
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measure the distribution of bus activity. As expected, the larger L2 cache reduces bus-burst-read
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transactions and instruction fetches because the processor does not have to go as often to main
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memory to retrieve data or instructions. Likewise, the bus write-back transactions diminish because
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the larger cache does not need to write back as many lines to main memory to free up space for new
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data. However, bus-invalidate and bus read-for-ownership transactions increase as cache size
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grows. This interprocessor communication reduces the benefits of larger cache size because it
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offsets the reduction in other bus traffic.
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7
1.30
1.20
1.10
1.00
Normalized Transactions/Second
0.90
(cont.)
2G Memory 4G Memory
4 x 2MB
2 x 1MB
+ 2 x 2MB
4 x 1MB
0.90 1.00 1.10 1.20 1.30
Figure 4 – Price/Performance for Six Configurations of the
Compaq ProLiantML570 Server in an OLTP Environment
4 x 1MB
Price
2 x 1MB
+ 2 x 2MB
4 x 2MB
SD User: Sales and
%
Distribution user
module
TC010401TB
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SD Users (Normalized)
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1.02
1.00
0
% Bus
Burst-Read
Tra n s ac tio n
(cont.)
1.09
1.00
512KB 1MB 1.5MB 2MB
L2 Cache Si z e
Figure 5 – Cache Performance Comparison for SAP Benchmark
512
1MB
2MB
% Bus
Write-b a ck
Tra n s ac tio n
Figure 6 – Distribution of SAP Bus Activity
% Bus
Instru ctio n
Fetches
% Bus
Read for
Ow nership
% Bus
Invalidate
Tra n s ac tio n
1.16
MAPI: mail application
program interface - a
message format used by
an application program
to communicate with the
operating system.
POP3: Post Office
Protocol version 3
SMTP: Simple Mail
Transfer Protocol
IMAP4: Internet
Message Access
Protocol version 4
MMB2: Microsoft
MAPI Benchmark-2
(developed by Compaq
in cooperation with
Microsoft)- each MMB2
represents the load of a
heavy corporate mail
user.
Latency: the response
time of the server to
requests made by the
clients; measured in
milliseconds.
TC010401TB
ECHNOLOGY BRIEF
T
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Microsoft Exchange 2000 Test
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Microsoft Exchange 2000 Server is a messaging and collaborative application server that runs
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under Microsoft Windows 2000 and supplies various messaging clients (such as Outlook MAPI
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clients, POP3/SMTP clients, web clients, and IMAP4 clients) with e-mail, calendar, scheduling,
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task management, instant messaging, c onferencing, and streaming media storage management.
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Benchmark tests conducted by Compaq’s Solutions Engineering Performance Gr oup determined
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that using 2-MB caches instead of 1-MB caches with Intel Pentium III Xeon processors could result
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in incremental performance gains.
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The Exchange 2000 MAPI messaging benchmark, MMB2, measures the number of workload units
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a server can handle while considering general performance metrics such as response time and send
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and disk queues. To facilitate comparison, the test used the same conservative load with both 1-MB
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and 2-MB cache sizes, in dual- and quad-processor configurations. The system provided sufficient
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bandwidth to prevent other resources (such as memor y, disk, or app l ication constraints) from
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becoming a performance bottleneck and skewing the results.
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Figure 7 shows the results for a ProLiant 8500 server with two 700-MHz Pentium III Xeon
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processors. For a load of 3,600 MMB2s, a 2-MB cache demonstrated improvements in latency of
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about 41 percent when compared to the same load on a 1-MB cache configuration. However, this
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result may have been exaggerated by the fact that the CPU utilization reached such a high level (92
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percent). The general best practice maximum for Exchange Server CPU utilization is 80 percent,
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which also functions as a guideline for ensuring the validity of the other measurements. The latency
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results therefore may not be accurate for the 1-MB cache test because the CPU increasingly
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becomes a performance bottleneck as its utilization exceeds 80 percent. The Send Queue (the
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average number of messages i n the queue) also showed improvement, although the overall number
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of threads allocated to the send queue has more effect on this than cache size, and that is the reason
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for the smaller difference in this measurement. Overall processor utilization (shown in the chart as
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a percentage) improved by 11.5 percent.
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(cont.)
100
90
80
70
60
50
40
30
20
10
0
Figure 7 – Performance Comparison of 1-MB and 2-MB Caches
with 3600 MMB2 Loads on a Dual-Processor Exchange Server
92
81.4
CPU - Percent
Utilization
1MB Cache 2MB Cache
58.6
34.8
32
Send Queue -
Avg # of
Messages
Latency -
milliseconds
34.7
TC010401TB
ECHNOLOGY BRIEF
T
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Figure 8 summarizes the results for the quad-processor configuration of 700-MHz Pentium III
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Xeon processors supporting a load of 6,000 MMB2s. The measurements in this test give a better
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representation of cache performance than those in the dual-processor test because the CPU
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utilization stayed in the 80 percent range and the processors did not limit the performance. For the
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load and total amount of work performed by the server (for example, the number of messages sent,
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received, and users serviced), the use of 2-MB caches improved CPU utilization by 12 percent and
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reduced latency by 15 percent over the 1-MB caches. Since the overall CPU utilization for this test
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did not exceed testing best practices, the send queue difference was much greater (34 percent).
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It is important to note that other factors besides cache size affect the Latency and Send Queue
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results. However, processor utilization is directly tied to cache performance. Consequently Co mpaq
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test engineers considered the 12 percent gain in processor utilization to be the most important and
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representative result for this test.
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10
with 6000 MMB2 Loads on a Quad-Processor Exchange Server Results
(cont.)
90
80
70
60
50
40
30
20
10
0
Figure 8 – Performance Comparison of 1-MB and 2-MB Caches
82
72
CPU - Percent
Utilization
1MB Cache 2MB Cache
39
32
21.2
Send Queue -
Avg # of
Messages
Latency -
milliseconds
33
TC010401TB
ECHNOLOGY BRIEF
T
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ServerBench Test
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The ServerB ench test, run on a ProLiant 8500 server using 700-MHz Pentium III Xeon processors
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and Microsoft Windows 2000, measures the throughput of a system as the number of clients
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increases. In this environment, a client is a test file that runs on the system and represents a user
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load on the system’s network. Adding clients simply means adding more test files or threads to run
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concurrently on the system. Actual user loads are difficult to model because the activity level varies
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widely between individuals and depends on how active their application is on the network. One
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client in this test can represent anywhere from 10 to 100 actual system users, depending on the
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characteristics of the users. Refer to the appendix for the full disclosure on the ServerBench test
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setup.
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Figure 9 shows the system throughput using four processo rs, measured in transactions per sec ond,
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and indicates the ability of the system to respond to the client load. When the load is relatively
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small, the limiting factors are the number of processors and the size of their caches. Increasing the
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number of simultaneously running test files eventually uses more memory than the cache has
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available, and the amount of main memory available to the system becomes the next bottleneck.
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Adding still more clients will eventually saturate main memory as well and the next limiting factor
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becomes the disk drive subsystem. Overall, the performance improvement for the larger cache is
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greater in a more lightly loaded system, and the gain diminishes with increasing loads.
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Figure 10 shows a more detailed view of the chart in Figure 9, making it easier to see the difference
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in performance in the peak range where the performance is highest and the difference is greatest.
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Table 2 summarizes the results for the four system configurations tested. The table shows both the
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average performance gain for the entire range of client loads in the test and for the peak range only.
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11
4500.00
4000.00
3500.00
3000.00
2500.00
2000.00
1500.00
Throughput (Transaction/sec)
1000.00
500.00
0.00
124681216202836445260
(cont.)
4P - 2MB Cache
4P - 1MB Cache
Number of Clients
Figure 9 – ServerBench Results with Four Processors
TC010401TB
ECHNOLOGY BRIEF
T
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3500.00
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3300.00
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3100.00
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2900.00
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2700.00
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2500.00
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2300.00
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2100.00
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1900.00
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Throughput (Transactions/sec)
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1700.00
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1500.00
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12
8 12162028
Table 2 - Throughput Advantage of 2-MB vs. 1-MB Cache in ServerBench Tests
(cont.)
4P - 2MB Cache
4P - 1MB Cache
Number of Clients
Figure 10 – Detail of ServerBench Results in Peak Area
Number of
Processors in
System
2 12.21% 17.31%
4 13.88% 22.62%
6 14.49% 15.95%
8 14.81% 14.94%
Average Improvement
Over the Full
Performance Ra nge
Average Improvement
Over the Peak
Performance Ra nge
TC010401TB
ECHNOLOGY BRIEF
T
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.
.
Terminal Server Test
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Terminal Server is a Microsoft Windows 2000 option that allows multiple users at different
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Windows-based terminals to run the same application. The server becomes a centralized, shared-
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.
compute resource that handles data processing, while the clients display only the user interface. The
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.
Terminal Server test had perhaps the most surprising results, as it wa s the only test that showed no
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.
performance advantage in using 2-MB caches.
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.
Tests run on a ProLiant 8500 server with 2 GB of main memory and four 700-MHz Pentium III
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.
Xeon processors showed no discernable change in response time for the end user when cache size
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.
.
was increased from 1 MB to 2 MB . The performance data indicated better kernel and interrupt
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.
.
handling with the larger cache, but this did not translate into an increase in performance or server
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.
density (the number of users per processor).
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.
Analysis by the testing lab indicated that the operating system, Microsoft Windows 2000 Advanced
.
.
.
Server using Windows Terminal Service (WTS), was most likely the reason performance did not
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.
.
improve with the 2-MB cache. Although increased CPU frequency provides modest gains in end-
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.
.
user response time and density improvements in WTS servers, increasing cache sizes beyond 512
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.
KB has shown little to no improvement in the WTS server space.
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.
This result emphasizes the need to understand the application environment of any customer
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searching for higher performance. Some configurations will not benefit from caches larger than a
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certain minimum s ize.
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13
(cont.)
TC010401TB
ECHNOLOGY BRIEF
T
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.
ONCLUSIONS
C
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In the five benchmark tests conducted in Compaq laboratories, increasing cache size from 1 MB to
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2 MB improved system performance in all but the Terminal Server test. Where the tests showed
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.
improvement, the benefit ranged from 10 percent to mo re than 22 percent in the peak range of the
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.
lightly loaded ServerBench test. In the OLTP and ServerBench tests, systems with higher processor
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.
counts did not benefit as much from the larger cache as those with fewer processors did, so
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scalability was not improved.
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According to information available on Compaq’s web site
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processor with a 2-MB cache costs about 87 percent more than one with a 1-MB cache does.
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However, that amount would usually represent only a small part of the overall cost of a server
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.
system. For example, to upgrade half of the processors in a relatively small four-processor system
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.
to a 2-MB cache may represent only about a five percent increase in the hardware cost. Customers
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.
whose application can benefit from the larger cache may consider a potential gain in system
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performance of 10 percent or more to be well worth the extra cost.
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.
Another aspect to consider is the total cost of ownership for a given system, especially since the
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.
price of many enterprise-edition software packages depends on the number of processors in the
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system. When the cost of the software per processor is very high, simply replacing some 1-MB
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.
cache processors with fewer of the 2-MB cache processors to reduce the overall processor count
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could provide a price/performance benefit. For example, at the time of this writing Oracle 8i
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Enterprise Edition had a listed price per processor of $100 times the Megahertz of the processor.
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For that case, each 700-MHz processor wo uld need a license costing $70,000 (minus a volume
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.
discount). For Microsoft SQL Server 2000 Enterprise Edition, the listed processor-licensing fee
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was just under $20,000 per processor.
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database (Figure 1), choosing six processors with 2-MB caches instead of eight processo rs with 1-
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.
MB caches would decrease the performance by about 6 percent but save about $40,000 in license
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fees.
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In summary, the use of larger processor caches is often beneficial to system performance, but not in
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.
all environments. In some cases, a mixed-processor solution would be more cost effective.
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Customers need to carefully consider all the trade-offs involved to determine the best cache
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solution for their system.
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http://www.directpluspro.compaq.com/default.asp?page=ctoBases&Product_Line_Id=431&Famil
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y_Id=648
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6
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http://oraclestore.oracle.com
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7
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http://www.microsoft.com/sql/productinfo/pricing.htm
.
14
(cont.)
5
, a 700-MHz Pentium III Xeon
7
For the Compaq b enchmark test of OLTP running on a SQL
6
TC010401TB
ECHNOLOGY BRIEF
T
.
.
PPENDIX
A
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Server Configurations Disclosure
.
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DL 570
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Number and type of processors
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Size of hardware CPU cache
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Amount of memory
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Type of I/O bus
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Number and type of hard disk controller
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Number and type of hard disks
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Disk organization
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Disk controller driver version
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Number and type of Network Controller
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Network controller driver version
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Network operating system and version
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Testbed Disclosure
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Number of clients 4 real clients emulating 120
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Network type
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Number and types of hubs
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Number of clients/segments
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Client CPU type and speed
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Client network controller
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Client network software name and version
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Client network software name and version
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Size of any client network cache
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Disk controller software
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Network controller software
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ServerBench Disclosure
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ServerBench Version
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Description of the test parameter for each mix
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in the test
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15
(cont.)
ERVERBENCH DISCLOSURE INFORMATION
: S
2/4/6/8xPentium III Xeon 700 MHz
1/2 MB
1024MB
PCI
1x SA-5302
7x9GB Fujitsu U3
RAID 0
cpqcissm.sys 5.3.34.0
1xDual-port NC 3131
N100NT5.sys 5.29.4.67
Windows 2000 AS with SP1
ServerBench clients
100 Base-TX
2x Netelligent hubs
60 on each of 2 segments
2x Pentium II 300 MHz
Compaq Netelligent 10/100
Windows 98
Native Win98 drivers, TCP/IP only
N/A
Native Win98 IDE drivers
Native Win98 NIC drivers
4.10
120g_ent.tst
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