HP LA-1701, Compaq nx7000, Compaq nx7010, Compaq Presario X1000, Pavilion zt3000 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Banias uFCBGA/uFCPGA with Intel
ODEM_MCH+ICH4-M core logic

3 3

4 4

A

B

2003-05-12

REV:1.0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

LA-1701

Cover Sheet

E

1 49Monday, May 12, 2003

1.0

A

B

C

D

E

Compal confidential

File Name : LA-1701

1 1

CRT & TV-OUT Conn.

page 14

VGA Board Connector

page 13

2 2

3.3V 33 MHz

IDSEL:AD17
(PIRQB#,GNT#1,REQ#1)

IEEE 1394
VT6307S

page 20

IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)

Mini PCI
socket

page 25

IDSEL:AD18,AD22
(PIRQC/D#,GNT#3/4,REQ#3/4)

LAN

RTL 8139CL+

RJ45/11 CONN

3 3

RTC CKT.

page 16

Power OK CKT.

page 32

Power On/Off CKT.

page 28

Touch Pad

EC I/O Buffer

DC/DC Interface CKT.

4 4

page 34

page 19

page 19

page 28

page 30

Fan Control

page 4

AGP BUS

PCI BUS

IDSEL:AD20
(PIRQA#,GNT#2,REQ#2)

CardBus Controller

ENE CB1410

page 21

Slot 0

page 21

EC NS87591L

page 29

Int.KBD

BIOS

Mobile Banias

uFCBGA-479/uFCPGA-478 CPU

page 4,5

H_A#(3..31)

PSB

400MHz

Intel ODEM MCH-M

uFCBGA-593

Intel ICH4-M

BGA-421

page 28

page 30

page 6,7,8

Hub-Link

page 15,16,17

LPC BUS

SD Connector

H_D#(0..63)

page 31

Thermal Sensor
ADM1032AR

page 4

Memory BUS(DDR)

2.5V DDR- 200/266

USB2.0

AC-LINK

Primary IDE

ATA-100

Secondary IDE

ATA-100

PARALLEL

Clock Generator

ICS 950810

DDR-SO-DIMM X2

BANK 0, 1, 2, 3

page 9,10,11

USB conn

page 27

Audio CKT

AD1981B

page 23

MDC & BT Conn

page 28

page 31

Mini-PCI solt

page 25

HDD
Connector

page 18

CDROM
Connector

page 18

SMsC LPC47N227

Super I/O

page 26

page 12

page 22

AMP & Audio Jack

FIR

page 26

page 24

SPR CONN.

page 33

*RJ45 CONN
*PS2 x2 CONN
*CRT CONN
*LINE IN JACK
*LINE OUT JACK
*1394 CONN
*SPDIF CONN
*DVI CONN
*DC JACK
*TVOUT CONN
*PRINTER PORT
*COM PORT
*USB CONN x2

Power Circuit DC/DC

page
35,36,37,38,39,40,41,42

A

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

LA-1701

Block Diagram

E

2 49Monday, May 12, 2003

1.0

A

Voltage Rails

Power Plane

VIN
B+
+CPU_CORE
+VCCP
+1.25VS
+1.2VS
+1.5VALW
+1.5VS
+1.8VS
+2.5V
+2.5VS
+3VALW
+3V

+5VALW
+5V
+5VS
+12VALW
+12V
+12VS
RTCVCC

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

1 1

Internal PCI Devices

DEVICE

HUB
USB
AC97 MODEM
AC97
ATA 100
ETHERNET
LPC I/F
SMBUS

Description

Adapter power supply (19V)
AC or battery power rail for power circuit
Core voltage for CPU

1.05V rail for Processor I/O

1.25V switched power rail for DDR Vtt

1.2V switched power rail for MCH core power

1.5V always on power rail

1.5V switched power rail for AGP interface

1.8V switched power rail for CPU PLL & Hub-Link

2.5V power rail for DDR

2.5V switched power rail

3.3V always on power rail
3V power rail

3.3V switched power rail+3VS
5V always on power rail
5V power rail
5V switched power rail
12V always on power rail
12V power rail
12Vswitched power rail on power rail
RTC power

PCI Device ID

D30
D29
D31
D31
D31
D8 (AD24)
D31
D31

S0-S1

N/A

ON OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

S3

N/A
N/A

OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON

S5

N/A
N/AN/A
OFF
OFF
OFF
OFF
ON*
OFF
OFF
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ON*
OFF
OFF
ONON

Symbol note:

:means digital ground.

:means analog ground.

:means reserved.@

External PCI Devices

DEVICE

1394
LAN
CARD BUS
Wireless LAN
Mini-PCI
AGP BUS

PCI Device ID

D0
D1
D4
D2
D6
N/A

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

HEX

A0
A2
D2

IDSEL #

AD16
AD17
AD20
AD18
AD22
AGP_DEVSEL#

ADDRESS

1 0 1 0 0 0 0 X
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X

REQ/GNT #

0
1
2
3
4

N/A

PIRQ

A
B
C
D
D
A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

LA-1701

Notes List

3 49Monday, May 12, 2003

1.0

A

H_A#[3..31]<6>

4 4

H_REQ#[0:4]<6>

CLK_CPU_ITP<12>
CLK_CPU_ITP#<12>

3 3

1 2

+VCCP

R112
56_0402_5%

+3VALW

ITP_DBRESET#<16>

2 2

+VCCP

H_CPUPWRGD<15>

1 1

330_0402_5%

PROCHOT#<29>

MMBT3904_SOT23

H_A#[3..31]

H_REQ#[0..4]

H_ADSTB#0<6>
H_ADSTB#1<6>

R137 0_0402_5%

1 2

R136 0_0402_5%

1 2

CLK_CPU_BCLK<12>
CLK_CPU_BCLK#<12>

H_ADS#<6>
H_BNR#<6>
H_BPRI#<6>
H_BR0#<6>

H_DEFER#<6>

H_DRDY#<6>

H_HIT#<6>

H_HITM#<6>

H_LOCK#<6>

H_CPURST#<6>

H_RS#0<6>

H_RS#1<6>

H_RS#2<6>

H_TRDY#<6>

R110

1 2

150_0402_5%

ITP_DBRESET#

1 2

+3VALW

R124

R111 0_0402_5%

H_DBSY#<6>
H_DPSLP#<7,15>

H_DPWR#<7>

R121
330_0402_5%

H_CPUSLP#<15>

R105 @1K_0402_5%
R107 @1K_0402_5%

R120

1 2

1K_0402_5%

1 2

Q22

2

3 1

Q21

MMBT3904_SOT23

3 1

A

1 2

1 2

2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

CLK_CPUITP
CLK_CPUITP#

H_IERR#
H_CPURST#

H_RS#0
H_RS#1
H_RS#2

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

ITP_BPM#4
ITP_BPM#5
H_PROCHOT#

H_CPUPWRGD
H_CPUSLP#

ITP_TCK
ITP_TDI
ITP_TDO

TEST1

TEST2
ITP_TMS
ITP_TRST#

H_THERMDA
H_THERMDC
H_THERMTRIP#

+VCCP

R109

1 2

330_0402_5%

P4
U4
V3
R3
V2

W1

T4

W2

Y4
Y1
U1

AA3

Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

R2

P3

T2

P1

T1

U3
AE5

A16
A15

B15
B14

N2

L1

J3

N4

L4

H2

K3

K4

A4

J2
B11

H1

K1

L2

M3

C8

B8

A9

C9

A7

M2

B7
C19
A10
B10
B17

E4

A6
A13
C12
A12

C5
F23
C11
B13

B18
A18
C17

R102
56 _0402_1%

H_PROCHOT#

U9A

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#

ADDR GROUP

A25#
A26#
A27#
A28#
A29#
A30#
A31#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADSTB0#
ADSTB1#

ITP_CLK0
ITP_CLK1

BCLK0
BCLK1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

RS0#
RS1#
RS2#
TRDY#

BPM0#
BPM1#
BPM2#
BPM3#

DBR#
DBSY#
DPSLP#
DPWR#
PRDY#
PREQ#
PROCHOT#

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

THERMDA
THERMDC
THERMTRIP#

mFCBGA479

HOST CLK

CONTROL GROUP

Banias

MISC

THERMAL
DIODE

B

DATA GROUP

LINT0/INTR

LEGACY CPU

B

D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DINV0#
DINV1#
DINV2#
DINV3#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

A20M#
FERR#

IGNNE#

INIT#

LINT1/NMI

STPCLK#

SMI#

H_D#[0..63]

H_D#0

A19

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#

+VCCP

A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

D25
J26
T24
AD20

C23
K24
W25
AE24
C22
L24
W24
AE25

C2
D3
A3
B5
D1
D4

C6
B4

+VCCP

H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_DINV#0 <6>
H_DINV#1 <6>
H_DINV#2 <6>
H_DINV#3 <6>

H_DSTBN#0 <6>
H_DSTBN#1 <6>
H_DSTBN#2 <6>
H_DSTBN#3 <6>
H_DSTBP#0 <6>
H_DSTBP#1 <6>
H_DSTBP#2 <6>
H_DSTBP#3 <6>

H_A20M#
H_IGNNE#

H_INIT#
H_INTR
H_NMI

H_STPCLK#
H_SMI#

1 2

R101
330_0402_5%

1 2

C139
1U_0603_10V6K

1 2

H_THERMTRIP#

H_A20M# <15>
H_FERR# <15>
H_IGNNE# <15>
H_INIT# <15>
H_INTR <15>
H_NMI <15>

H_STPCLK# <15>
H_SMI# <15>

2

B

R108
56_0402_5%

C

H_D#[0..63] <6>

ITP700FLEX FOR BANIAS

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO_R

RESETITP#
ITP_TCK
CLK_CPU_ITP#

CLK_CPU_ITP

1

C

E

3

MAINPWON <35,37,42>

Q20

@2SC2411K_SOT23

12

R118
56_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

THRMTRIP# <16>

JP29

1

TDI

2

TMS

5

TCK

7

TDO

3

TRST#

12

RESET#

11

FBO

8

BCLK#

9

BCLK

10

GND0

14

GND1

16

GND2

18

GND3

20

GND4

22

GND5

@ITP700-FLEXCON

VTT0
VTT1
VTAP

DBR#
DBA#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

NC1
NC2

27
28
26

25
24

23
21
19
17
15
13

4
6

12

R114
@10K_0402_5%

2200P_0402_25V7K

13K_0603_1%

D

+VCCP

C145

1 2

R138

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

@0.1U_0402_16V7K

ITP_DBRESET#ITP_TRST#

@0_0402_5%

+VCCP

R104

54.9_0402_1%

1 2

H_CPURST# RESETITP# ITP_TDO

1 2

R135 39.2_0603_1%

1 2

R134 150_0402_1%

Thermal Sensor ADM1032AR

+3VS

C129

W=15mil

1

2

H_THERMDA
H_THERMDC

2

C131

1

0.1U_0402_10V6K

1
2
3

U13

VDD
D+
D­THERM#4GND

ADM1032AR_SOP8

Address:1001_100X

Fan Control circuit

+12VS

2

C140

0.1U_0402_10V6K

EN_FAN1<29>

R342

1 2

D

1

5

U14

1

P

+

O

3

-

G

LM321MF_SOT23-5

2

C448

1 2

@2200P_0603_16V7K

1 2

R340 7.32K_0603_1%

D23

RB751V_SOD323

1

G

FAN1_ON

3

4

2 1

Title

Size Document Number Rev

Date: Sheet of

E

+VCCP+VCCP

12

R119

22.6_0402_1%

ITP_TMS

ITP_TDI

SCLK

SDATA

ALERT#

+5VS

6

2

D

S

4 5

FAN1_VOUT

1

C422
10U_1206_10V4Z

2

8
7
6
5

Q23

SI3456DV-T1_TSOP6

FANSPEED1<29>

1 2

R129 680_0402_5%

1 2

R154 27.4_0402_1%

1

C427

@10000P

2

C439

@10000P

Compal Electronics, Inc.

INTEL CPU BANIAS (1 of 2)

LA-1701

Monday, May 12, 2003

E

1 2

+5VS

12

1

2

R149
@54.9_0402_1%

12

R153

@22.6_0402_1%

ITP_TRST#

ITP_TCK

EC_SMC_2 <29>
EC_SMD_2 <29>

R341
10K_0402_5%

JP15

53398-0310

4 49

ITP_TDO_R

1
2
3

1.0

A

B

C

D

E

1

C92
10U_1206_6.3V7K

2

0.1U_0402_16V7K

1

C428

2

+CPU_CORE

1

C372

2

0.1U_0402_16V7K

Title

Size Document Number Rev

Date: Sheet of

C564

C

+CPU_CORE

+CPU_CORE

+CPU_CORE

10U_1206_6.3V7K

+CPU_CORE

10U_1206_6.3V7K

+CPU_CORE

10U_1206_6.3V7K

+CPU_CORE

10U_1206_6.3V7K

Vcc-core
Decoupling
SPCAP,Polymer

+CPU_VCCA

1

C64

2

+VCCP

1

+

2

1

+

C280
220U_D2_2VM

2

10U_1206_6.3V7K

1

1

C67

2

2

10U_1206_6.3V7K

10U_1206_6.3V7K

1

1

C105

2

2

10U_1206_6.3V7K

1

1

C328

2

2

10U_1206_6.3V7K

1

1

C385

2

2

10U_1206_6.3V7K

1

1

C121

2

2

10U_1206_6.3V7K

1

C126

2

0.01U_0402_16V7K

0.1U_0402_16V7K

1

C348

2

0.1U_0402_16V7K

1

2

C68

10U_1206_6.3V7K

C104

10U_1206_6.3V7K

C327

10U_1206_6.3V7K

C386

10U_1206_6.3V7K

C117

10U_1206_6.3V7K

1

C356

2

1

C359

2

+

C281
220U_D2_2VM

1

C69

2

1

C103

2

1

C326

2

1

C387

2

1

C50

2

10U_1206_6.3V7K

1

2

0.1U_0402_16V7K

1

+

2

10U_1206_6.3V7K

1

C70

2

10U_1206_6.3V7K

10U_1206_6.3V7K

1

C102

2

10U_1206_6.3V7K

10U_1206_6.3V7K

1

C325

2

10U_1206_6.3V7K

10U_1206_6.3V7K

1

C388

2

10U_1206_6.3V7K

10U_1206_6.3V7K

1

C350

2

10U_1206_6.3V7K

1

C127

C362

2

0.01U_0402_16V7K

0.1U_0402_16V7K

1

1

C363

2

2

C110
220U_D2_2VM

10U_1206_6.3V7K

1

C71

2

1

C101

2

10U_1206_6.3V7K

1

C324

2

10U_1206_6.3V7K

1

C389

2

1

C349

2

ESR, mohm

12m ohm/4
5m ohm/35MLCC 0805 X5R

10U_1206_6.3V7K

1

C72

2

0.01U_0402_16V7K

1

C430

C431

2

0.1U_0402_16V7K

1

+

C62
220U_D2_2VM

2

1

C82

2

10U_1206_6.3V7K

1

C81

2

1

C351

2

1

C365

2

10U_1206_6.3V7K

1

C122

2

1

C98

2

0.1U_0402_16V7K

1

C429

2

D

1

C88
10U_1206_6.3V7K

2

1

C87
10U_1206_6.3V7K

2

1

C364
10U_1206_6.3V7K

2

1

C352
10U_1206_6.3V7K

2

1

C49
10U_1206_6.3V7K

2

ESL,nHC,uF

3.5nH/44X220uF

0.6nH/3535X10uF

0.1U_0402_16V7K

AC26

AD26

AE7

AF6

F26

B1
N1

P23

W4

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16

K6
L5

L21

M6

M22

N5

N21

P6

P22

R5

R21

T6
T22
U21

D6

D8
D18
D20
D22

E5

E7

E9
E17
E19
E21

F6

F8
F18

E1

E2

F2

F3

G3

G4

H4

E26

G1

AC1

P25
P26

AB2
AB1

B2
AF7
C14

C3
C16

U9B

VCCSENSE
VSSSENSE

VCCA0
VCCA1
VCCA2
VCCA3

VCCQ0
VCCQ1

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

PSI#
VID0

VID1
VID2
VID3
VID4
VID5

GTLREF0
GTLREF1
GTLREF2
GTLREF3

COMP0
COMP1
COMP2
COMP3

RSVD
RSVD
RSVD
RSVD

TEST3

mFCBGA479

A2

VSS

A5

VSS

A8

VSS

A11

VSS

A14

VSS

A17

VSS

A20

VSS

A23

VSS

A26

VSS

B3

VSS

B6

VSS

B9

VSS

B12

Banias

VSS

B16

VSS

B19

VSS

B22

VSS

B25

VSS

C1

VSS

C4

VSS

C7

VSS

C10

VSS

C13

VSS

C15

VSS

C18

VSS

C21

VSS

C24

VSS

D2

VSS

D5

VSS

D7

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E10

VSS

E12

VSS

E14

VSS

E16

VSS

E18

VSS

E20

VSS

E22

VSS

E25

VSS

F1

VSS

F4

VSS

F5

VSS

F7

VSS

F9

VSS

F11

VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

F13

VSS

F15

VSS

F17

VSS

F19

VSS

F21

VSS

F24

VSS

G2

VSS

G6

VSS

G22

VSS

G23

VSS

G26

VSS

H3

VSS

H5

VSS

H21

VSS

H25

VSS

J1

VSS

J4

VSS

J6

VSS

J22

VSS

J24

VSS

K2

VSS

K5

VSS

K21

VSS

K23

VSS

K26

VSS

L3

VSS

L6

VSS

L22

VSS

L25

VSS

M1

VSS

0.01U_0402_16V7K

100U_6.3V_M

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R290 @54.9_0402_1%

1 2
1 2

R288 @54.9_0402_1%

1 1

2 2

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

+VCCP

12

R36
1K_0402_1%

3 3

2K_0402_1%

4 4

1

R32

C34
1U_0603_10V6K

2

1 2

1

C37
220P_0402_50V8K

2

12

R57

27.4_0402_1%

A

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

+1.8VS

12

R56

27.4_0402_1%

R296

1 2

12

54.9_0402_1%

R79

0_1206_5%

+CPU_CORE

R293

CPU_VID0<41>
CPU_VID1<41>
CPU_VID2<41>
CPU_VID3<41>
CPU_VID4<41>
CPU_VID5<41>

+CPU_VCCA

+VCCP

PSI#<41>

12

VCCSENSE
VSSSENSE

GTL_REF0

COMP0
COMP1
COMP2
COMP3

R103

@1K_0402_5%

B

U9C

F20

VCC

F22

VCC

G5

VCC

G21

VCC

H6

VCC

H22

VCC

J5

VCC

J21

VCC

K22

VCC

U5

VCC

V6

VCC

V22

VCC

W5

VCC

W21

VCC

Y6

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

mFCBGA479

1

C341

0.1U_0402_16V7K

2

Banias

POWER, GROUND

Y22
AA5
AA7

AA9
AA11
AA13
AA15
AA17
AA19
AA21

AB6

AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC9
AC11
AC13
AC15
AC17
AC19

AD8
AD10
AD12
AD14
AD16
AD18

AE9
AE11
AE13
AE15
AE17
AE19

AF8
AF10
AF12
AF14
AF16
AF18

M4

M5
M21
M24

N3

N6
N22
N23
N26

P2

P5
P21
P24

R1

R4

R6
R22
R25

T3

T5
T21
T23

1

C346

2

T26

VSS

U2

VSS

U6

VSS

U22

VSS

U24

VSS

V1

VSS

V4

VSS

V5

VSS

V21

VSS

V25

VSS

W3

VSS

W6

VSS

W22

VSS

W23

VSS

W26

VSS

Y2

VSS

Y5

VSS

Y21

VSS

Y24

VSS

AA1

VSS

AA4

VSS

AA6

VSS

AA8

VSS

AA10

VSS

AA12

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA20

VSS

AA22

VSS

AA25

VSS

AB3

VSS

AB5

VSS

AB7

VSS

AB9

VSS

AB11

VSS

AB13

VSS

AB15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

AB23

VSS

AB26

VSS

AC2

VSS

AC5

VSS

AC8

VSS

AC10

VSS

AC12

VSS

AC14

VSS

AC16

VSS

AC18

VSS

AC21

VSS

AC24

VSS

AD1

VSS

AD4

VSS

AD7

VSS

AD9

VSS

AD11

VSS

AD13

VSS

AD15

VSS

AD17

VSS

AD19

VSS

AD22

VSS

AD25

VSS

AE3

VSS

AE6

VSS

AE8

VSS

AE10

VSS

AE12

VSS

AE14

VSS

AE16

VSS

AE18

VSS

AE20

VSS

AE23

VSS

AE26

VSS

AF2

VSS

AF5

VSS

AF9

VSS

AF11

VSS

AF13

VSS

AF15

VSS

AF17

VSS

AF19

VSS

AF21

VSS

AF24

VSS

Compal Electronics, Inc.

INTEL CPU BANIAS (2 of 2)

LA-1701

5 49Monday, May 12, 2003

E

1.0

5

H_RS#[0..2]<4>

H_A#[3..31]<4>

H_REQ#[0..4]<4>

D D

C C

B B

A A

H_RS#[0..2]
H_A#[3..31]
H_REQ#[0..4]

U12A

H_A#3

U6

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_ADSTB#0<4>
H_ADSTB#1<4>

CLK_MCH_BCLK#<12>

CLK_MCH_BCLK<12>

H_ADS#<4>

H_TRDY#<4>

H_DRDY#<4>

H_DEFER#<4>

H_HITM#<4>
H_HIT#<4>
H_LOCK#<4>
H_BR0#<4>
H_BNR#<4>

H_BPRI#<4>

H_DBSY#<4>

H_CPURST#<4>

H_DSTBN#0<4>
H_DSTBN#1<4>
H_DSTBN#2<4>
H_DSTBN#3<4>
H_DSTBP#0<4>
H_DSTBP#1<4>
H_DSTBP#2<4>
H_DSTBP#3<4>

H_DINV#0<4>
H_DINV#1<4>
H_DINV#2<4>
H_DINV#3<4>

5

H_RS#0
H_RS#1
H_RS#2

HA#3

T5

HA#4

R2

HA#5

U3

HA#6

R3

HA#7

P7

HA#8

T3

HA#9

P4

HA#10

P3

HA#11

P5

HA#12

R6

HA#13

N2

HA#14

N5

HA#15

N3

HA#16

J3

HA#17

M3

HA#18

M4

HA#19

M5

HA#20

L5

HA#21

K3

HA#22

J2

HA#23

N6

HA#24

L6

HA#25

L2

HA#26

K5

HA#27

L3

HA#28

L7

HA#29

K4

HA#30

J5

HA#31

U2

HREQ#0

T7

HREQ#1

R7

HREQ#2

U5

HREQ#3

T4

HREQ#4

R5

HADSTB#0

N7

HADSTB#1

K8

BCLK#

J8

BCLK

U7

ADS#

V4

HTRDY#

W2

DRDY#

Y4

DEFER#

Y3

HITM#

Y5

HIT#

W3

HLOCK#

V7

BR0#

V3

BNR#

Y7

BPRI#

V5

DBSY#

W7

RS#0

W5

RS#1

W6

RS#2

AE17

CPURST#

AD4

HDSTBN#0

AF6

HDSTBN#1

AD11

HDSTBN#2

AC15

HDSTBN#3

AD3

HDSTBP#0

AG6

HDSTBP#1

AE11

HDSTBP#2

AC16

HDSTBP#3

AD5

DBI#0

AG5

DBI#1

AH9

DBI#2

AD15

DBI#3

RG82P4300M_FCBGA593

Odem

HOST

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8

HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HVREF0
HVREF1
HVREF2
HVREF3
HVREF4

HSWNG1
HSWNG0

HRCOMP1
HRCOMP0

4

AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AE5
AF3
AC6
AC3
AF4
AE2
AG4
AG2
AE7
AE8
AH2
AC7
AG3
AD7
AH7
AE6
AC8
AG8
AG7
AH3
AF8
AH5
AC11
AC12
AE9
AC10
AE10
AD9
AG9
AC9
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16

M7
P8
AA9
AB12
AB16

220P_0402_50V7K

H_SWNG1

AD13

H_SWNG0

AA7
AC13

AC2

4

H_D#[0..63]

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

C333

H_RCOMP1
H_RCOMP0

R55

27.4_0402_1%

1

1

2

2

220P_0402_50V7K

1 2

H_D#[0..63] <4>

MGH_GTLREF

1

C392

C335

1U_0603_10V6K

2

R302

27.4_0402_1%

1 2

3

+VCCP

+VCCP

3

AGP_AD[0..31]
AGP_C/BE#[0..3]
AGP_SBA[0..7]

1

2

1

2

AGP_ST0<13>
AGP_ST1<13>
AGP_ST2<13>

12

12

12

12

AGP_SBSTB<13>
AGP_SBSTB#<13>

AGP_RBF#<13>
AGP_WBF#<13>

CLK_MCH_66M<12>

R303
301_0402_1%

R299
150_0402_1%

R304
301_0402_1%

R306

150_0402_1%

AGP_FRAME#<13>
AGP_DEVSEL#<13>
AGP_IRDY#<13>
AGP_TRDY#<13>
AGP_STOP#<13>
AGP_PAR<13>

AGP_REQ#<13>
AGP_GNT#<13>

AGP_ADSTB0<13>
AGP_ADSTB0#<13>
AGP_ADSTB1<13>
AGP_ADSTB1#<13>

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

CLK_MCH_66M

12

R314
@22_0402_5%

1

C381
@10P_0402_50V8K

2

AA28
AB25
AB27
AA27
AB26

AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

AA23

W28
W27
W24
W23

W25
AG24
AH25

AC27
AC28

AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25

AF27
AF26

AE22
AE23

AF22

AG25

AF24

AG26

R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26

Y23

V25
V23
Y25

Y24

R24
R23

P22

AGP_AD[0..31]<13>
AGP_CBE#[0..3]<13>
AGP_SBA[0..7]<13>

C334

0.1U_0402_10V6K

H_SWNG1

C330

0.1U_0402_10V6K

H_SWNG0

+VCCP

12

R66

49.9_0402_1%

12

R77
100_0402_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

U12B

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GCBE#0
GCBE#1
GCBE#2
GCBE#3

GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#

AD_STB0
AD_STB#0
AD_STB1
AD_STB#1

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

SB_STB
SB_STB#

RBF#
WBF#
PIPE#

ST0
ST1
ST2

66IN

RG82P4300M_FCBGA593

Odem

AGP

2

HUB

HLRCOMP

GND

1

HUB_PD[0..10]

HUB_PD0

P25

HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9

HI_10

HI_STB

HI_STB#

HI_REF

VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141

GRCOMP

AGPREF

Note:
Placement R308,R305

close to MCH

Title

Size Document Number Rev

Date: Sheet of

P24
N27
P23
M26
M25
L28
L27
M27
N28
M24

N25
N24

P27
P26

AB9
AD10
AF9
AJ9
A7
F8
J7
L8
N8
R8
U8
W8
AA8
AD8
AF7
AJ7
D5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
AF5
AJ5
A3
J4
L4
N4
R4
U4
W4
AA4
AC4
AE4
AJ3
E1
J1
L1
N1
R1
U1
W1
AA1
AC1
AE1
AG1

AD25
AA21

LA-1701

HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

HUB_PSTRB <15>

AGP_RCOMP

+AGPREF

1

C340

0.1U_0402_16V4Z

2

HUB_PSTRB# <15>

1 2

1

C379

0.01U_0402_16V7K

2

1 2

HUB_RCOMP

Compal Electronics, Inc.

ODEM(1/3)

HUB_PD[0:10] <15>

R315 36.5_0402_1%

HUB_VREF

+1.5VS

AGP_ST2

+1.5VS

AGP_ST1

ST1

X
0
1

R300

36.5_0603_1%

+AGPREF

MCH STRAPST2
DDR

1

TEST MODE

X

400 Mhz PSB

X

+AGPREF

1

+1.8VS

12

R287
@1K_0402_5%

12

R291
@1K_0402_5%

12

R292
@1K_0402_5%

+1.5VS

6 49Monday, May 12, 2003

12

12

R308
1K_0402_1%

R305
1K_0402_1%

1.0

5

4

3

2

1

DDR_MMA[0..12]<9,10>
DDR_SDQ[0..63]<9>
DDR_SDQS[0..8]<9>

DDR_CB[0..7]<9>

D D

C C

B B

+1.25VS_SMVREF

R328

+SDREF

0.1U_0402_16V4Z

0_0805_5%

C405

12

1

1

2

2

DDR_MMA[0..12]
DDR_SDQ[0..63]
DDR_SDQS[0..8]

DDR_CB[0..7]

C404

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C403

+1.25VS

1

2

R326

1 2

30.1_0603_1%

U12C

DDR_MMA0
DDR_MMA1
DDR_MMA2
DDR_MMA3
DDR_MMA4
DDR_MMA5
DDR_MMA6
DDR_MMA7
DDR_MMA8
DDR_MMA9
DDR_MMA10
DDR_MMA11
DDR_MMA12

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

DDR_SWE#<9,10>
DDR_SRAS#<9,10>
DDR_SCAS#<9,10>

DDR_CLK0<9>
DDR_CLK0#<9>
DDR_CLK1<9>
DDR_CLK1#<9>
DDR_CLK2<9>
DDR_CLK2#<9>
DDR_CLK3<10>
DDR_CLK3#<10>
DDR_CLK4<10>
DDR_CLK4#<10>
DDR_CLK5<10>
DDR_CLK5#<10>

DDR_CKE0<9,10>
DDR_CKE1<9,10>
DDR_CKE2<10>
DDR_CKE3<10>

DDR_SCS#0<9,10>
DDR_SCS#1<9,10>
DDR_SCS#2<10>
DDR_SCS#3<10>

DDR_SBS0<9,10>
DDR_SBS1<9,10>

DDR_RCOMP

H_DPSLP#<4,15>
H_DPWR#<4>

M_RCV#

G17
G18
E18

G20
G19

E20
G21
G22

C26
C23
B19
D12

E15

G11

K25

G24
E24
G25

K23

G23
E22
H23

G12
G13

G15
G14

AD26
AD27

E12
F17
E16

F19

F21
F13

F26

F11

J25

J24

J23

F23

J21
J28

C8
C5
E3

G8

G5

F5

G6
G7

E9
F7
F9
E7

J9

V8
Y8

SMA0
SMA1
SMA2
SMA3
SMA4
SMA5
SMA6
SMA7
SMA8
SMA9
SMA10
SMA11
SMA12
RSVD2

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

SWE#
SRAS#
SCAS#

SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2
SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5

SCKE0
SCKE1
SCKE2
SCKE3

SCS#0
SCS#1
SCS#2
SCS#3

SBS0
SBS1

SMVREF0
SMVREF1

SMRCOMP
RCVENIN#
RCVENOUT#
DPSLP#

DPWR#
NC0
NC1

Odem

MEMORY

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8

SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63
SDQ64
SDQ65
SDQ66
SDQ67
SDQ68
SDQ69
SDQ70
SDQ71

RSTIN#

RSVD1

TESTIN#

G28
F27
C28
E28
H25
G27
F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10
C9
D8
E8
E11
B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E4
C3
D3
F4
F3
B2
C2
E2
G4
C16
D16
B15
C14
B17
C17
C15
D14

J27
H27
H26

DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63
DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7

MCH_TEST#

PCIRST# <13,15,19,20,21,22,25,31>

1 2

R91 @4.7K_0402_5%

+1.5VS

A A

5

4

NOTE:1.M_RCV# max 2Via

2.G15 to Via max=40mils

3.G14 to Via max=40mils

4.Via to Via must = 100mils +-5mils

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

RG82P4300M_FCBGA593

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ICH4-M(2/3)

LA-1701

Monday, May 12, 2003

1

7 49

1.0

5

4

3

2

1

U12D

Odem

POWER GND

4

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90

RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

ETS#

E29
J29
N29
U29
AA29
AE29
A27
K27
AJ27
E26
G26
J26
L26
R26
W26
AC26
AF25
A23
F24
L24
M23
AC23
AH23
D21
H21
J22
L22
N22
T22
V22
Y22
AB22
AC21
AD22
AF21
AG22
AH21
A19
F20
H19
AB19
AC20
AD19
AE20
AF19
AG20
AH19
D17
H17
N17
R17
U17
AB17
AC18
AE18
AF17
AG18
AJ17
A15
F15
H15
N15
P16
R15
T16
U15
AB15
AD16
AF15
AJ15
D13
E14
H13
N13
P14
R13
T14
U13
AB13
AD14
AF13
AJ13
A11
F12
H11
AB11
AD12
AF11
AJ11
D9
H9

G16
G10
G9
H7
G2
G3
H3

H4

R327

1 2

10K_0603_0.5%

150U_D2_6.3VM

150U_D2_6.3VM

150U_D2_6.3VM

+2.5V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

C382
10U_1206_10V4Z

2

R29

VCCAGP0

W29

VCCAGP1

AC29

VCCAGP2

AG29

VCCAGP3

U26

VCCAGP4

AA26

VCCAGP5

AE26

VCCAGP6

AJ25

VCCAGP7

AD23

VCCAGP8

AF23

VCCAGP9

R22

VCCAGP10

U22

VCCAGP11

W22

VCCAGP12

AA22

VCCAGP13

AB21

VCCAGP14

AD21

VCCAGP15

P17

VCC0

N16

VCC1

P15

VCC2

R16

VCC3

T15

VCC4

U16

VCC5

N14

VCC6

P13

VCC7

R14

VCC8

U14

VCC9

L29

VCCHL0

L25

VCCHL1

N26

VCCHL2

N23

VCCHL3

M22

VCCHL4

AG23

VCCP0

AJ23

VCCP1

AE21

VCCP2

AG21

VCCP3

AJ21

VCCP4

AB20

VCCP5

AC19

VCCP6

AD20

VCCP7

AE19

VCCP8

AF20

VCCP9

AG19

VCCP10

AJ19

VCCP11

AB18

VCCP12

AD18

VCCP13

AF18

VCCP14

AB14

VCCP15

AB10

VCCP16

M8

VCCP17

T8

VCCP18

AB8

VCCP19

C29

VCCSM0

G29

VCCSM1

A25

VCCSM2

D25

VCCSM3

K26

VCCSM4

D23

VCCSM5

H24

VCCSM6

K24

VCCSM7

L23

VCCSM8

A21

VCCSM9

F22

VCCSM10

H22

VCCSM11

K22

VCCSM12

D19

VCCSM13

H20

VCCSM14

A17

VCCSM15

F18

VCCSM16

H18

VCCSM17

D15

VCCSM18

F16

VCCSM19

H16

VCCSM20

A13

VCCSM21

F14

VCCSM22

H14

VCCSM23

D11

VCCSM24

H12

VCCSM25

A9

VCCSM26

F10

VCCSM27

H10

VCCSM28

D7

VCCSM29

H8

VCCSM30

K7

VCCSM31

A5

VCCSM32

E5

VCCSM33

H5

VCCSM34

J6

VCCSM35

C1

VCCSM36

G1

VCCSM37

T17

VCCGA

T13

VCCHA

RG82P4300M_FCBGA593

+1.5VS

D D

+1.2VS

+1.8VS

C C

+VCCP

+2.5V

B B

C368

+1.8VS

1

2

A A

0.1U_0402_16V4Z

5

C563

100U_6.3V_M

C395

10U_1206_10V4Z

C344

C301

C357

+2.5V

1

+

150U_D2_6.3VM

2

+2.5V

1

C411

2

0.1U_0402_16V4Z

+1.8VS

1

2

+1.5VS

1

+

2

+1.2VS

1

+

2

+VCCP

1

+

2

1

+

C401

2

0.1U_0402_16V4Z

1

1

C433

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C383

2

10U_1206_10V4Z

1

C361

2

10U_1206_10V4Z

150U_D2_6.3VM

1

+

C366

2

0.1U_0402_16V4Z

1

C305

2

1

C138

2

22U_1206_10V4Z

0.1U_0402_16V4Z

1

C410

C417

2

1

C396

2

0.1U_0402_16V4Z

1

C373

2

1

C347

2

2.2U_0805_10V6K

1

C311

2

0.1U_0402_16V4Z

22U_1206_10V4Z

1

1

C400

2

2

0.1U_0402_16V4Z

1

C409

2

0.1U_0402_16V4Z

1

C384

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

1

C371

2

2

0.1U_0402_16V4Z

0.22U_0603_10V7K

1

1

C353

2

2

0.015U_0402_16V7K

0.1U_0402_16V4Z

1

1

C315

2

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

C399

C398

2

0.1U_0402_16V4Z

1

1

C416

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C345

C336

2

0.01U_0402_16V7K

1

C374

C380

2

0.1U_0402_16V4Z

1

C338

C320

2

1

C408

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C413

2

1

C321

2

0.1U_0402_16V4Z

1

C393

2

0.022U_0603_16V7K

1

C310

2

0.1U_0402_16V4Z

1

C434

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

1

C402

C406

C419

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C316

C306

0.1U_0402_16V4Z

2

2

1

C394

0.047U_0603_16V7K

2

0.1U_0402_16V4Z

1

1

C367

C337

0.1U_0402_16V4Z

2

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ODEM(3/3)

LA-1701

Monday, May 12, 2003

1

1

C432

2

2

0.1U_0402_16V4Z

C418

0.1U_0402_16V4Z

1

8 49

1.0

5

DDR_SDQ5
DDR_SDQ4

DDR_SDQ3
DDR_SDQ1

D D

DDR_SDQ13
DDR_SDQ8

DDR_SDQ10
DDR_SDQ11 DDR_DQ11

DDR_SDQ15

DDR_SDQ7
DDR_SDQ2

DDR_SDQ14
DDR_SDQ9

DDR_SDQ17

DDR_SDQ18

C C

DDR_SDQ22 DDR_DQ22

DDR_SDQ20
DDR_SDQ16

DDR_SDQ19
DDR_SDQ23 DDR_DQ23

DDR_SDQ25 DDR_DQ25
DDR_SDQ24 DDR_DQ24

DDR_SDQ28 DDR_DQ28
DDR_SDQ29 DDR_DQ29

DDR_CB6

DDR_CB4 DDR_F_CB4

B B

DDR_CB3 DDR_F_CB3

DDR_SDQS8 DDR_DQS8
DDR_CB7

DDR_MMA0
DDR_MMA10

DDR_MMA1
DDR_MMA2

DDR_MMA4
DDR_MMA5

DDR_MMA9
DDR_MMA12

A A

DDR_MMA7

DDR_MMA8

DDR_MMA6 DDR_F_SMA6

DDR_SWE#<7,10>

RP18

1 4
2 3

10_4P2R_0404_5%

RP38

1 4
2 3

10_4P2R_0404_5%

RP37

1 4
2 3

10_4P2R_0404_5%

RP39

1 4
2 3

10_4P2R_0404_5%

RP41

1 4
2 3

10_4P2R_0404_5%

RP20

1 4
2 3

10_4P2R_0404_5%

RP19

1 4
2 3

10_4P2R_0404_5%

RP40

1 4
2 3

10_4P2R_0404_5%

RP42

1 4
2 3

10_4P2R_0404_5%

RP43

1 4
2 3

10_4P2R_0404_5%

RP21

1 4
2 3

10_4P2R_0404_5%

RP22

1 4
2 3

10_4P2R_0404_5%

RP44

1 4
2 3

10_4P2R_0404_5%

RP23

1 4
2 3

10_4P2R_0404_5%

RP46

1 4
2 3

10_4P2R_0404_5%

RP25

1 4
2 3

10_4P2R_0404_5%

RP47

1 4
2 3

10_4P2R_0404_5%

RP26

1 4
2 3

10_4P2R_0404_5%

RP29

1 4
2 3

10_4P2R_0404_5%

RP50

1 4
2 3

10_4P2R_0404_5%

RP28

1 4
2 3

10_4P2R_0404_5%

RP48

1 4
2 3

10_4P2R_0404_5%

RP27

1 4
2 3

10_4P2R_0404_5%

RP49

1 4
2 3

10_4P2R_0404_5%

DDR_F_CB6
DDR_F_CB2DDR_CB2

5

DDR_DQ5
DDR_DQ4

DDR_DQ3
DDR_DQ1

DDR_DQS0DDR_SDQS0
DDR_DQ6DDR_SDQ6

DDR_DQ13
DDR_DQ8

DDR_DQ10

DDR_DQ15
DDR_DQS1DDR_SDQS1

DDR_DQ7
DDR_DQ2

DDR_DQ14
DDR_DQ9

DDR_DQS2DDR_SDQS2
DDR_DQ17

DDR_DQ18

DDR_DQ20
DDR_DQ16

DDR_DQ19

DDR_F_CB5DDR_CB5

DDR_F_CB1DDR_CB1

DDR_F_CB7

DDR_F_SMA10

DDR_F_SMA1
DDR_F_SMA2

DDR_F_SMA4
DDR_F_SMA5

DDR_F_SMA9
DDR_F_SMA12

DDR_F_SMA7
DDR_F_SMA11DDR_MMA11

DDR_F_SMA8

1 4
2 3

10_4P2R_0404_5%

RP51

DDR_SDQ31 DDR_DQ31
DDR_SDQ30 DDR_DQ30

DDR_SDQ35 DDR_DQ35
DDR_SDQ39 DDR_DQ39

DDR_SDQS4 DDR_DQS4
DDR_SDQ36 DDR_DQ36

DDR_SDQ34 DDR_DQ34

DDR_SDQ40 DDR_DQ40
DDR_SDQ44 DDR_DQ44

DDR_SDQ45 DDR_DQ45
DDR_SDQ41 DDR_DQ41

DDR_SDQ46 DDR_DQ46
DDR_SDQ47 DDR_DQ47

DDR_SDQ52 DDR_DQ52

DDR_SDQ50 DDR_DQ50

DDR_SDQ48 DDR_DQ48

DDR_SBS1<7,10>

DDR_SCAS#<7,10>

DDR_SBS0<7,10>

DDR_SRAS#<7,10>

DDR_F_SWE#DDR_SWE#

DDR_F_SMA3DDR_MMA3

RP45

1 4
2 3

10_4P2R_0404_5%

RP24

1 4
2 3

10_4P2R_0404_5%

RP30

1 4
2 3

10_4P2R_0404_5%

RP31

1 4
2 3

10_4P2R_0404_5%

RP52

1 4
2 3

10_4P2R_0404_5%

RP53

1 4
2 3

10_4P2R_0404_5%

RP54

1 4
2 3

10_4P2R_0404_5%

RP55

1 4
2 3

10_4P2R_0404_5%

RP32

1 4
2 3

10_4P2R_0404_5%

RP56

1 4
2 3

10_4P2R_0404_5%

RP33

1 4
2 3

10_4P2R_0404_5%

RP34

1 4
2 3

10_4P2R_0404_5%

RP58

1 4
2 3

10_4P2R_0404_5%

RP57

1 4
2 3

10_4P2R_0404_5%

DDR_SDQ0

DDR_SDQ12

DDR_SDQ26 DDR_DQ26

DDR_SDQ33 DDR_DQ33

DDR_SDQS7 DDR_DQS7

DDR_CB0 DDR_F_CB0

4

DDR_DQ27DDR_SDQ27
DDR_DQS3DDR_SDQS3

DDR_DQ37DDR_SDQ37
DDR_DQ32DDR_SDQ32

DDR_DQ38DDR_SDQ38

DDR_DQ43DDR_SDQ43
DDR_DQ42DDR_SDQ42

DDR_DQ49DDR_SDQ49

DDR_DQ51DDR_SDQ51
DDR_DQ54DDR_SDQ54

DDR_DQS6DDR_SDQS6

DDR_DQ55DDR_SDQ55

12

R203 10_0402_5%

12

R201 10_0402_5%

12

R202 10_0402_5%

12

R221 10_0402_5%

12

R206 10_0402_5%

12

R207 10_0402_5%

12

R208 10_0402_5%

12

R224 10_0402_5%

12

R200 10_0402_5%

R205 10_0402_5%

R222 10_0402_5%

R223 10_0402_5%

R204 10_0402_5%

DDR_F_SBS1DDR_SBS1

12

DDR_F_SCAS#DDR_SCAS#

12

DDR_F_SBS0DDR_SBS0

12

DDR_F_SRAS#DDR_SRAS#

12

4

DDR_SDQ56 DDR_DQ56
DDR_SDQ62 DDR_DQ62

DDR_SDQ63 DDR_DQ63

DDR_SDQ61 DDR_DQ61

DDR_SDQ59 DDR_DQ59
DDR_SDQ57 DDR_DQ57

DDR_DQ21DDR_SDQ21

DDR_DQ0

DDR_DQ12

DDR_DQS5DDR_SDQS5

DDR_DQ53DDR_SDQ53DDR_F_SMA0

RP36

1 4
2 3

10_4P2R_0404_5%

RP59

1 4
2 3

10_4P2R_0404_5%

RP60

1 4
2 3

10_4P2R_0404_5%

RP35

1 4
2 3

10_4P2R_0404_5%

DDR_DQ58DDR_SDQ58

DDR_DQ60DDR_SDQ60

3

+2.5V

JP30

1

VREF

3

VSS

5

DQ0

7

DQ1

9

DDR_DQS0

DDR_DQS1

DDR_CLK0<7>

DDR_CLK0#<7>

DDR_DQS2

DDR_DQS3

DDR_F_CB0
DDR_F_CB1

DDR_DQS8
DDR_F_CB2

DDR_F_CB3

DDR_CLK2<7>
DDR_CLK2#<7>

DDR_CKE1<7,10>

SMB_DATA<10,12,15>

SMB_CLK<10,12,15>

DDR_CKE1

DDR_F_SMA12
DDR_F_SMA9

DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#0

DDR_DQS4

DDR_DQS5

DDR_DQS6

DDR_DQS7

+3VS

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP1565618_1_REVERSE4.0

DU/RESET#

DU/BA2

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

CKE0

RAS#
CAS#

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

VDD
DM1

VSS

VDD
VDD
VSS
VSS

VDD
DM2

VSS

VDD
DM3

VSS

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

VSS
VSS
VDD
VDD

VSS

VDD
BA1

VSS

VDD
DM4

VSS

VDD
DM5

VSS

VDD
CK1

VSS

VDD
DM6

VSS

VDD
DM7

VSS

VDD
SA0
SA1
SA2

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

DIMM0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+2.5V

DDR_DQ4DDR_DQ5
DDR_DQ6DDR_DQ0

DDR_DQ1DDR_DQ3
DDR_DQ2DDR_DQ7

DDR_DQ8DDR_DQ13
DDR_DQ12DDR_DQ9

DDR_DQ14DDR_DQ15
DDR_DQ11DDR_DQ10

DDR_DQ16DDR_DQ20
DDR_DQ17DDR_DQ21

DDR_DQ22DDR_DQ18
DDR_DQ23DDR_DQ19

DDR_DQ24DDR_DQ25
DDR_DQ29DDR_DQ28

DDR_DQ26DDR_DQ27
DDR_DQ30DDR_DQ31

DDR_F_CB4
DDR_F_CB5

DDR_F_CB6
DDR_F_CB7

DDR_CKE0

DDR_F_SMA11
DDR_F_SMA8

DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0

DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#
DDR_SCS#1

DDR_DQ32DDR_DQ37
DDR_DQ36DDR_DQ33

DDR_DQ38DDR_DQ34
DDR_DQ39DDR_DQ35

DDR_DQ44DDR_DQ40
DDR_DQ41DDR_DQ45

DDR_DQ42DDR_DQ43
DDR_DQ47DDR_DQ46

DDR_DQ52DDR_DQ49
DDR_DQ48DDR_DQ55

DDR_DQ53DDR_DQ50
DDR_DQ54DDR_DQ51

DDR_DQ63DDR_DQ58
DDR_DQ57DDR_DQ59

DDR_DQ62DDR_DQ56
DDR_DQ61DDR_DQ60

1

+1.25VS_SDREF_R

1

C222

0.1U_0402_16V4Z

2

DDR_CKE0 <7,10>

DDR_SCS#1 <7,10>DDR_SCS#0<7,10>

DDR_CLK1# <7>
DDR_CLK1 <7>

Title

Size Document Number Rev

Date: Sheet of

DDR_SDQ[0..63]

DDR_DQ[0..63]

DDR_DQS[0..8]
DDR_SDQS[0..8]

DDR_CB[0..7]
DDR_F_CB[0..7]

DDR_MMA[0..12]

Compal Electronics, Inc.

DDR-SODIMM SLOT1

LA-1701

Monday, May 12, 2003

1

DDR_SDQ[0..63] <7>
DDR_DQ[0..63] <10>

DDR_DQS[0..8] <10>
DDR_SDQS[0..8] <7>

DDR_CB[0..7] <7>
DDR_F_CB[0..7] <10>

DDR_MMA[0..12] <7,10>

1.0

9 49

A

DDR_DQ6
DDR_DQ0

1 1

DDR_DQ2
DDR_DQ7

DDR_DQ4
DDR_DQ5

DDR_DQ1
DDR_DQ3

DDR_DQ10
DDR_DQ11

DDR_DQ15
DDR_DQ14

DDR_DQ13
DDR_DQ8

2 2

DDR_DQ9
DDR_DQ12

DDR_DQ16
DDR_DQ20

DDR_DQ23
DDR_DQ19

DDR_DQ17
DDR_DQ21

DDR_DQ22
DDR_DQ18

3 3

DDR_DQ28
DDR_DQ29

DDR_DQ25
DDR_DQ24

DDR_DQ27
DDR_DQ26

DDR_DQ30
DDR_DQ31

DDR_DQ38
DDR_DQ34

DDR_DQ35

4 4

DDR_DQ39

DDR_DQ32
DDR_DQ37

DDR_DQ33
DDR_DQ36

RP110

1 4
2 3

56_4P2R_0404_5%

RP108

1 4
2 3

56_4P2R_0404_5%

RP111

1 4
2 3

56_4P2R_0404_5%

RP109

1 4
2 3

56_4P2R_0404_5%

RP104

1 4
2 3

56_4P2R_0404_5%

RP105

1 4
2 3

56_4P2R_0404_5%

RP107

1 4
2 3

56_4P2R_0404_5%

RP106

1 4
2 3

56_4P2R_0404_5%

RP103

1 4
2 3

56_4P2R_0404_5%

RP100

1 4
2 3

56_4P2R_0404_5%

RP102

1 4
2 3

56_4P2R_0404_5%

RP101

1 4
2 3

56_4P2R_0404_5%

RP98

1 4
2 3

56_4P2R_0404_5%

RP99

1 4
2 3

56_4P2R_0404_5%

RP97

1 4
2 3

56_4P2R_0404_5%

RP96

1 4
2 3

56_4P2R_0404_5%

RP88

1 4
2 3

56_4P2R_0404_5%

RP87

1 4
2 3

56_4P2R_0404_5%

RP90

1 4
2 3

56_4P2R_0404_5%

RP89

1 4
2 3

56_4P2R_0404_5%

A

RP86

14
23

56_4P2R_0404_5%

RP85

14
23

56_4P2R_0404_5%

RP84

14
23

56_4P2R_0404_5%

RP83

14
23

56_4P2R_0404_5%

RP81

14
23

56_4P2R_0404_5%

RP82

14
23

56_4P2R_0404_5%

RP80

14
23

56_4P2R_0404_5%

RP79

14
23

56_4P2R_0404_5%

RP78

14
23

56_4P2R_0404_5%

RP76

14
23

56_4P2R_0404_5%

RP77

14
23

56_4P2R_0404_5%

RP75

14
23

56_4P2R_0404_5%

R228 56_0402_5%
R229 56_0402_5%

R230 56_0402_5%
R231 56_0402_5%

R232 56_0402_5%
R233 56_0402_5%

R234 56_0402_5%
R235 56_0402_5%

R236 56_0402_5%

1 2

12
12

12
12

12
12

12
12

DDR_DQ40
DDR_DQ44

DDR_DQ45
DDR_DQ41

DDR_DQ43
DDR_DQ42

DDR_DQ46
DDR_DQ47

DDR_DQ55
DDR_DQ48

DDR_DQ49
DDR_DQ52

DDR_DQ50
DDR_DQ53

DDR_DQ51
DDR_DQ54

DDR_DQ58
DDR_DQ63

DDR_DQ56
DDR_DQ62

DDR_DQ59
DDR_DQ57

DDR_DQ60
DDR_DQ61

DDR_DQS0
DDR_DQS1

DDR_DQS2
DDR_DQS3

DDR_DQS4
DDR_DQS5

DDR_DQS6
DDR_DQS7

DDR_DQS8

B

+1.25VS+1.25VS

RP67

56 _8P4R_0804_5%
RP94

56 _8P4R_0804_5%
RP95

56 _8P4R_0804_5%
RP93

56 _8P4R_0804_5%

RP66

56_4P2R_0404_5%

56_4P2R_0404_5%

56_4P2R_0404_5%

56_4P2R_0404_5%

56_4P2R_0404_5%
RP61

56_4P2R_0404_5%

56_4P2R_0404_5%

56_4P2R_0404_5%

56_4P2R_0404_5%

RP65

RP68

RP91

RP92

RP63

RP62

RP64

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

DDR_MMA10
DDR_SBS1
DDR_SBS0

DDR_SRAS#

DDR_MMA7

DDR_MMA6

DDR_MMA5

DDR_MMA4

DDR_MMA12

DDR_MMA11

DDR_MMA9

DDR_MMA8

DDR_MMA3

DDR_MMA2

DDR_MMA1

DDR_MMA0

DDR_CKE0
DDR_CKE1

DDR_CKE2
DDR_CKE3

DDR_SWE#

DDR_SCAS#

DDR_SCS#2
DDR_SCS#3

DDR_SCS#1
DDR_SCS#0

DDR_F_CB0
DDR_F_CB4

DDR_F_CB2
DDR_F_CB6

DDR_F_CB1
DDR_F_CB5

DDR_F_CB3
DDR_F_CB7

DDR_SBS1 <7,9>
DDR_SBS0 <7,9>

DDR_CKE0 <7,9>
DDR_CKE1 <7,9>

DDR_SCS#1 <7,9>
DDR_SCS#0 <7,9>

C

+2.5V

JP22

1

VREF

3

DDR_DQ4
DDR_DQ6

DDR_DQS0
DDR_DQ1

DDR_DQ2
DDR_DQ8

DDR_DQ12
DDR_DQS1

DDR_DQ14
DDR_DQ11

DDR_CLK3<7>

DDR_CLK3#<7>

DDR_DQ16
DDR_DQ17

DDR_DQS2
DDR_DQ22

DDR_DQ23
DDR_DQ24

DDR_DQ29
DDR_DQS3

DDR_DQ26
DDR_DQ30

DDR_F_CB0
DDR_F_CB1

DDR_DQS8
DDR_F_CB2

DDR_F_CB3

DDR_CLK5<7>
DDR_CLK5#<7>

DDR_CKE3<7>

DDR_SWE#<7,9> DDR_SCAS# <7,9>

DDR_SCS#2<7> DDR_SCS#3 <7>

SMB_DATA<9,12,15>

DDR_CKE3
DDR_MMA12

DDR_MMA9
DDR_MMA7

DDR_MMA5
DDR_MMA3
DDR_MMA1 DDR_MMA0

DDR_MMA10
DDR_SBS0
DDR_SWE#
DDR_SCS#2

DDR_DQ32
DDR_DQ36

DDR_DQS4
DDR_DQ38

DDR_DQ39
DDR_DQ44

DDR_DQ41
DDR_DQS5

DDR_DQ42
DDR_DQ47

DDR_DQ52
DDR_DQ48

DDR_DQS6
DDR_DQ53

DDR_DQ54
DDR_DQ63

DDR_DQ57
DDR_DQS7

DDR_DQ62
DDR_DQ61

SMB_CLK<9,12,15>

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

AMP11376408_STANDARD5.2

D

VREF

DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET#

VSS

VSS

VDD

VDD
CKE0

DU/BA2

VSS

VDD
RAS#

CAS#

VSS
DQ36
DQ37

VDD

DM4
DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6
DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

+2.5V

2
4

VSS

6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116

BA1

118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194

SA0

196

SA1

198

SA2

200

DU

DDR_DQ5
DDR_DQ0

DDR_DQ3
DDR_DQ7

DDR_DQ13
DDR_DQ9

DDR_DQ15
DDR_DQ10

DDR_DQ20
DDR_DQ21

DDR_DQ18
DDR_DQ19

DDR_DQ25
DDR_DQ28

DDR_DQ27
DDR_DQ31

DDR_F_CB4
DDR_F_CB5

DDR_F_CB6
DDR_F_CB7

DDR_CKE2

DDR_MMA11
DDR_MMA8

DDR_MMA6
DDR_MMA4
DDR_MMA2

DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3

DDR_DQ37
DDR_DQ33

DDR_DQ34
DDR_DQ35

DDR_DQ40
DDR_DQ45

DDR_DQ43
DDR_DQ46

DDR_DQ49
DDR_DQ55

DDR_DQ50
DDR_DQ51

DDR_DQ58
DDR_DQ59

DDR_DQ56
DDR_DQ60

+1.25VS_SDREF_R

1

2

DDR_MMA[0..12]

DDR_CKE2 <7>

DDR_SRAS# <7,9>

DDR_CLK4# <7>
DDR_CLK4 <7>

+3VS

C234

0.1U_0402_16V4Z

DDR_SDQ[0..63]

DDR_DQ[0..63]

DDR_DQS[0..8]
DDR_SDQS[0..8]

DDR_CB[0..7]
DDR_F_CB[0..7]

1 2

R343 0_0805_5%

E

+SDREF

DDR_SDQ[0..63] <7,9>
DDR_DQ[0..63] <9>

DDR_DQS[0..8] <9>
DDR_SDQS[0..8] <7,9>

DDR_CB[0..7] <7,9>
DDR_F_CB[0..7] <9>

DDR_MMA[0..12] <7,9>

DIMM1

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDR-SODIMM SLOT1

LA-1701

Monday, May 12, 2003

E

10 49

1.0

A

B

C

D

E

Layout note :

Distribute as close as possible
to DDR-SODIMM.

+2.5V

1 1

1

C223

0.1U_0402_16V4Z

2

1

C224

0.1U_0402_16V4Z

2

1

C225

0.1U_0402_16V4Z

2

1

C226

0.1U_0402_16V4Z

2

1

C227

0.1U_0402_16V4Z

2

1

C229

0.1U_0402_16V4Z

2

1

C228

0.1U_0402_16V4Z

2

1

C230

0.1U_0402_16V4Z

2

1

C231

0.1U_0402_16V4Z

2

1

C502

0.1U_0402_16V4Z

2

1

C503

0.1U_0402_16V4Z

2

+2.5V

1

0.1U_0402_16V4Z

2

C504

1

C497

0.1U_0402_16V4Z

2

1

C498

0.1U_0402_16V4Z

2

1

C499

0.1U_0402_16V4Z

2

1

C500

0.1U_0402_16V4Z

2

1

C501

0.1U_0402_16V4Z

2

+2.5V

1

+

C221
150U_D2_6.3VM

2

1

+

C505
150U_D2_6.3VM

2

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

2 2

3 3

+1.25VS

1

0.1U_0402_16V4Z

2

+1.25VS

1

0.1U_0402_16V4Z

2

+1.25VS

1

0.1U_0402_16V4Z

2

+1.25VS

1

0.1U_0402_16V4Z

2

C546

C535

C525

C514

1

C545

0.1U_0402_16V4Z

2

1

C534

0.1U_0402_16V4Z

2

1

C524

0.1U_0402_16V4Z

2

1

C241

0.1U_0402_16V4Z

2

1

C544

0.1U_0402_16V4Z

2

1

C533

0.1U_0402_16V4Z

2

1

C523

0.1U_0402_16V4Z

2

1

C512

0.1U_0402_16V4Z

2

1

C543

0.1U_0402_16V4Z

2

1

C531

0.1U_0402_16V4Z

2

1

C522

0.1U_0402_16V4Z

2

1

C511

0.1U_0402_16V4Z

2

1

C542

0.1U_0402_16V4Z

2

1

C240

0.1U_0402_16V4Z

2

1

C521

0.1U_0402_16V4Z

2

1

C510

0.1U_0402_16V4Z

2

1

C541

0.1U_0402_16V4Z

2

1

C530

0.1U_0402_16V4Z

2

1

C520

0.1U_0402_16V4Z

2

1

C242

0.1U_0402_16V4Z

2

1

C540

0.1U_0402_16V4Z

2

1

C529

0.1U_0402_16V4Z

2

1

C519

0.1U_0402_16V4Z

2

1

C508

0.1U_0402_16V4Z

2

1

C539

0.1U_0402_16V4Z

2

1

C528

0.1U_0402_16V4Z

2

1

C518

0.1U_0402_16V4Z

2

1

C507

0.1U_0402_16V4Z

2

1

C538

0.1U_0402_16V4Z

2

1

C527

0.1U_0402_16V4Z

2

1

C517

0.1U_0402_16V4Z

2

1

C236

0.1U_0402_16V4Z

2

1

C536

0.1U_0402_16V4Z

2

1

C526

0.1U_0402_16V4Z

2

1

C515

0.1U_0402_16V4Z

2

1

C237

0.1U_0402_16V4Z

2

+1.25VS

1

C537

0.1U_0402_16V4Z

2

4 4

+1.25VS

1

0.1U_0402_16V4Z

2

C248

1

C238

0.1U_0402_16V4Z

2

1

C249

0.1U_0402_16V4Z

2

A

1

C239

0.1U_0402_16V4Z

2

1

C509

0.1U_0402_16V4Z

2

1

C243

0.1U_0402_16V4Z

2

1

C532

0.1U_0402_16V4Z

2

1

C244

0.1U_0402_16V4Z

2

1

C245

0.1U_0402_16V4Z

2

B

1

C246

0.1U_0402_16V4Z

2

1

C247

0.1U_0402_16V4Z

2

1

C516

0.1U_0402_16V4Z

2

1

C513

0.1U_0402_16V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDR SODIMM Decoupling

LA-1701

Monday, May 12, 2003

E

11 49

1.0

A

SEL1

0

0

VGATE<16,32,41>

SEL0

1

1

+3VS

@10P_0402_50V8K

166.67

200.000

133.33

@1K_0402_5%

CLKEN#<41>

1 2

R198 10K_0402_5%

C171

SEL2 CPUCLKC[0..2]

0

0

0
0 1

1 1

2 2

CLK_ICH_48M<16>

CLK_SD_48M<31>

CLK_ICH_14M<16>
CLK_14M_SIO<22>

CLK_14M_CODEC<23>

3 3

@1K_0402_5%

R139

1 2
1 2

R132
1K_0402_5%

2

G

1

2

B

CPUCLKT[0..2]

166.670

100.00100.00

200.001

133.33

+3VS

12

R133

13

D

Q29
@2N7002 1N_SOT23

S

1

C142
@10P_0402_50V8K

2

+3VS

12

R140
1K_0402_5%

1 2

R366 1K_0402_5%

SLP_S1#<16,29>
STP_PCI#<16>
STP_CPU#<16,41>

+3VS

SMB_DATA<9,10,15>

SMB_CLK<9,10,15>

R364 475_0402_1%

1 2

R180 33_0402_5%

1 2

R186 33_0402_5%

1 2

R128 33_0402_5%

1 2
1 2

R127 33_0402_5%

1 2

R126 33_0402_5%

C151
@10P_0402_50V8K

1 2

1 2

C154
@10P_0402_50V8K

1 2

R362 10K_0402_5%

C

+3VS

1 2

XTALIN

12

Y2

14.318MHZ_16PF_DSX840GA

XTALOUT

CLK_ICH48M

CLK_SD48M

CLK_ICH14M

L13
CHB2012U121_0805

U18

2

XTAL_IN

3

XTAL_OUT

54

SEL0

55

SEL1

40

SEL2

25

PWR_DWN#

34

PCI_STOP#

53

CPU_STOP#

28

VTT_PWRGD#

43

MULT0

29

SDATA

30

SCLK

33

3V66_0

35

3V66_1/VCH_CLK

42

IREF

39

48MHZ_USB

38

48MHZ_DOT

56

REF

+3V_CLK

Width=40 mils

1

14

VDD_REF

VDD_PCI_08VDD_PCI_1

GND_REF4GND_PCI_09GND_PCI_115GND_3V66_0

D

1

2

19

32

37

50

VDD_CPU_046VDD_CPU_1

VDD_48MHZ

VDD_3V66_0

VDD_3V66_1

GND_3V66_131GND_48MHZ36GND_IREF41GND_CPU

20

47

C192
10U_1206_10V4Z

26

VDDA

27

VSSA

45

CPUCLKT2

44

CPU_CLKC2

49

CPUCLKT1

48

CPUCLKC1

52

CPUCLKT0

51

CPUCLKC0

24

3V66_5

23

3V66_4

22

3V66_3

21

3V66_2

7

PCICLK_F2

6

PCICLK_F1

5

PCICLK_F0

18

PCICLK6

17

PCICLK5

16

PCICLK4

13

PCICLK3

12

PCICLK2

11

PCICLK1

10

PCICLK0

ICS950810CG_TSSOP56

1

C186

2

0.1U_0402_16V4Z

+3V_VDD

1

C187

2

0.1U_0402_16V4Z

CLK_BCLK

CLK_BCLK#

CLK_MCH

CLK_MCH#
CLK_ITP

CLK_ITP#

AGP_66M
MCH_66M
ICH_66M

PCI_ICH

PCI_1394
PCI_SD
PCI_LAN
PCI_PCM
PCI_MINI
PCI_SIO
PCI_LPC

E

0.1U_0402_16V4Z

1

C166

2

1

C191
10U_1206_10V4Z

2

1

C144

2

0.1U_0402_16V4Z

L14
CHB2012U121_0805

1 2

1 2

R169
33_0402_5%

R172
33_0402_5%

1 2
1 2

R160
33_0402_5%

R166
33_0402_5%

1 2
1 2

R150
33_0402_5%

R155
33_0402_5%

1 2

1 2
1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

0.1U_0402_16V4Z

1

1

C181

2

2

0.1U_0402_16V4Z

+3VS

R170

49.9_0402_1%

1 2
1 2

R173 49.9_0402_1%

R161

49.9_0402_1%

1 2
1 2

R167

R151

49.9_0402_1%

1 2
1 2

R156

R191 33_0402_5%
R188 33_0402_5%
R185 33_0402_5%

R158 33_0402_5%

R178 33_0402_5%
R179 33_0402_5%
R171 33_0402_5%
R168 33_0402_5%
R165 33_0402_5%
R164 33_0402_5%
R157 33_0402_5%

C177
@10P_0402_50V8K

0.1U_0402_16V4Z

1

C462

2

CLK_CPU_BCLK <4>

CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <6>

49.9_0402_1%

CLK_MCH_BCLK# <6>
CLK_CPU_ITP <4>

49.9_0402_1%

CLK_CPU_ITP# <4>

1

2

F

1

C471

2

0.1U_0402_16V4Z

1

2

@10P_0402_50V8K

C465

C180

0.1U_0402_16V4Z

1

C464

2

1

C184
@10P_0402_50V8K

2

CLK_AGP_66M <13>
CLK_MCH_66M <6>
CLK_ICH_66M <15>

CLK_PCI_ICH <15>

CLK_PCI_1394 <20>

CLK_PCI_SD <31>
CLK_PCI_LAN <19>
CLK_PCI_PCM <21>
CLK_PCI_MINI <25>
CLK_PCI_SIO <22>
CLK_PCI_LPC <29>

G

H

Clock Generator

4 4

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

D

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

F

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Clock Generator

LA-1701

Monday, May 12, 2003

G

12 49

H

1.0

5

4

3

2

1

AGP CONN

JP12

1

GND

D D

C C

CLK_AGP_66M<12> RED<14,33>

AGP_ADSTB1#<6>

AGP_SBSTB<6>

AGP_SBSTB#<6>

AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23

AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27

AGP_AD29
AGP_AD30
AGP_AD31
AGP_CBE#2

AGP_CBE#3
AGP_ADSTB1
AGP_ADSTB1#

AGP_SBA0

AGP_SBA1

AGP_SBA2

AGP_SBA3

AGP_SBA4
AGP_SBSTB

AGP_SBSTB#

AGP_ST0

AGP_ST1

AGP_ST2

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

GND

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

GND

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

GND

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

79

79

81

GND

83

83

85

85

87

87

89

89

91

91

93

93

95

95

97

97
GND99GND

FOXCONN-100P

GND

GND

GND

GND

GND

2
4

4
6

8
10
12
14
16
18
20

24
26
28
30
32
34
36
38
40

44
46
48
50
52
54
56
58
60

64
66
68
70
72
74
76
78
80

84
86
88
90
92
94
96
98

AGP_AD0

6

AGP_AD1

8

AGP_AD2

10

AGP_AD3

12

AGP_AD4

14

AGP_AD5

16

AGP_AD6

18

AGP_AD7

20
22

AGP_AD8

24

AGP_AD9

26

AGP_AD10

28

AGP_AD11

30

AGP_AD12

32

AGP_AD13

34

AGP_AD14

36

AGP_AD15

38

AGP_CBE#0

40
42

AGP_CBE#1

44

AGP_ADSTB0

46

AGP_ADSTB0#

48
50

AGP_SBA5

52

AGP_SBA6

54

AGP_SBA7

56
58

AGP_IRDY#

60
62

AGP_TRDY#

64

AGP_STOP#

66

AGP_PAR

68

AGP_FRAME#

70

AGP_DEVSEL#

72

AGP_RBF#

74

AGP_WBF#

76

AGP_REQ#

78

AGP_GNT#

80
82
84
86
88
90
92
94
96
98
100

PCIRST# <7,15,19,20,21,22,25,31>

AGP_ADSTB0 <6>AGP_ADSTB1<6>
AGP_ADSTB0# <6>

AGP_IRDY# <6>
AGP_TRDY# <6>

AGP_STOP# <6>
AGP_PAR <6>
AGP_FRAME# <6>
AGP_DEVSEL# <6>
AGP_RBF# <6>
AGP_WBF# <6>
AGP_REQ# <6>
AGP_GNT# <6>

PCI_PIRQA# <15,20>

+3VS

AGP_SBA[0..7]<6>

AGP_CBE#[0..3]<6>

AGP_SBA[0..7]
AGP_CBE#[0..3]

C3_STAT#<16>

AGP_BUSY#<16>

DDCDATA<14>

DDCCLK<14>

SUS_STAT#<16,30>

MSEN#<14,29,33>

AGP_AD[0..31]<6>

AGP_ST[0..2]<6>

RED

GREEN<14,33>

HSYNC<14>
VSYNC<14>

LUMA<14,33>
CRMA<14,33>

COMPS<14,33>

PID0<22>
PID1<22>
PID2<22>
PID3<22>

GREEN
BLUE

BLUE<14,33>

HSYNC
VSYNC

LUMA
CRMA
COMPSAGP_AD28
ENAVDD

ENABLT#

+1.5VS

+1.8VS

+2.5VS +2.5VS

VB1<16>

AGP_AD[0..31]
AGP_ST[0..2]

JP13

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

FOXCONN-100P

GND

GND
3
5
7
9
11
13
15
17
19

GND

GND
23
25
27
29
31
33
35
37
39

GND

GND
43
45
47
49
51
53
55
57
59

GND

GND
63
65
67
69
71
73
75
77
79

GND

GND
83
85
87
89
91
93
95
97
GND99GND

CPUB++_L

2
4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

DAC_BRIG

24

24
26
28
30
32
34
36
38
40

44
46
48
50
52
54
56
58
60

64
66
68
70
72
74
76
78
80

84
86
88
90
92
94
96
98

DISPOFF#

26

INVT_PWM

28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

LCDVDD

DAC_BRIG <29>
INVT_PWM <29>

+1.5VS

+1.8VS

VB0 <16>

VB2 <16>

L6

1 2

KC FBM-L11-201209-221LMAT_0805

1

C45
68P_0402_50V8J

2

CPUB++

+3VS

B B

LCD POWER CIRCUIT

LCDVDD

+12VALW

12

R14

100_0402_5%

D

Q7

2N7002 1N_SOT23

A A

S

ENAVDD

5

R15
100K_0402_5%

1 2

13

2

G

13

22K

2

22K

2

G

Q6
DTC124EK_SOT23

+12VALW

R16
100K_0402_5%

1 2

R17

13

D

150K_0402_5%

Q5

S

2N7002 1N_SOT23

0.047U_0402_16V4Z

1

2

1 2

4

LCDVDD

C25

0.1U_0402_16V7K

+3VS

D

S

13

Q8

G

SI2302DS 1N_SOT23

2

1

1

C27

C28

4.7U_0805_10V4Z

2

2

1

C24

4.7U_0805_10V4Z

2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C302

0.1U_0402_16V4Z

2

BKOFF#<29>

ENABLT#<29>

3

RB751V_SOD323

ENABLT#

+2.5VS

1

C111

0.1U_0402_16V4Z

2

+3VS

12

R52

4.7K_0402_5%

D10

DISPOFF#

21

13

D

Q15

2

G

2N7002 1N_SOT23

S

+1.8VS

1

2

2

C94

0.1U_0402_16V4Z

+1.5VS

1

C89

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

Title

Size Document Number Rev
Custom

Date: Sheet of

LA-1701

AGP & LCD CONN

1

13 49Monday, May 12, 2003

1.0

A

B

C

D

E

CRT Connector

D1

DAN217_SOT23

1

1 1

2

3

CRTVDD

RED_L

GREEN_L

BLUE_L

1

C1
18P_0402_50V8J

2

R255

1 2

L22

FCM2012C-800_0805

1 2

L21

FCM2012C-800_0805

1 2

L20

FCM2012C-800_0805

1

C265

2

@22P_0402_25V8K

12

12

R254
@10K_0402_5%

RED<13,33>

GREEN<13,33>

BLUE<13,33>

12

R258

75_0402_1%

75_0402_1%

+5VS

1

+5VS

14

P

A2Y

G

7

14

P

A5Y

G

7

OE

4

OE

2 2

HSYNC<13>

VSYNC<13>

12

12

R256

R257

75_0402_1%

1

C573

0.1U_0402_16V4Z

2

U43A

3

SN74AHCT126PWR_TSSOP14

U43B

6

SN74AHCT126PWR_TSSOP14

1

C263

2

@22P_0402_25V8K

1

C264

@22P_0402_25V8K

2

@10K_0402_5%

D2

DAN217_SOT23

1

2

3

1

C2
18P_0402_50V8J

2

1 2

L19 FBM-L10-160808-300LM-T

1 2

L18 FBM-L10-160808-300LM-T

C3

10P_0402_50V8K

D_VSYNC <33>
D_HSYNC <33>

DAN217_SOT23

1

2

1

2

D3

1

2

3

C4
18P_0402_50V8J

D_HSYNC_L

D_VSYNC_L

1

C5
10P_0402_50V8K

2

+3VS

POLYSWITCH_1A

DDC_MD2

1

C6
100P_0402_50V8J

2

F1

RB411D_SOT23

0.1U_0402_16V7K

MSEN#<13,29,33>

68P_0402_50V8K

D16

2 1

C52

C255

1

2

1

1

2

2

+5VS

TV-Out Connector

DAN217_SOT23

D14

1

DAN217_SOT23

1

D13

DAN217_SOT23

+3VS

D15

1

W=40mils

JP1
CRT-15P

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

C257
68P_0402_50V8K

Unused GATE

CRTVDD+RCRT_VCC

4.7K_0402_5%

D

1 3

2

+5VS+5VS

+3VS

12

12

R264

R265

4.7K_0402_5%

Q1

S

G

R269

1 2

10K_0402_5%

13

14

U43D

P

OE

11

A12Y

G

SN74AHCT126PWR_TSSOP14

7

DDCDATA <13>

DDCCLK <13>

+3VS

CRTVDD

12

R246

2.2K_0402_5%

BSN20_SOT23

D_DDCCLK <33>

D_DDCDATA <33>

10

14

U43C

P

OE

8

A9Y

G

SN74AHCT126PWR_TSSOP14

7

CRTVDD

12

R245

2.2K_0402_5%

D

1 3

BSN20_SOT23

Q2

S

G

2

3 3

C10

1 2

47P_0402_50V8J

1

C13
150P_0402_50V8J

2

1 2

L1 FCM1608C-121T_0603

C12

1 2

47P_0402_50V8J

1 2

L3 FCM1608C-121T_0603

C11

1 2

47P_0402_50V8J

1 2

L2 FCM1608C-121T_0603

270P_0402_50V7K

LUMA<13,33>

CRMA<13,33>

COMPS<13,33>

4 4

A

75_0402_1%

R7

12

R8

75_0402_1%

12

12

R6

150P_0402_50V8J

75_0402_1%

C14

1

2

150P_0402_50V8J

1

C15

2

B

C256

COMPS_CL

1

2

2

3

2

3

LUMA_CL

CRMA_CL

1

C8

2

270P_0402_50V7K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

C7
270P_0402_50V7K

2

2

3

S-Video

S CONN._SUYIN

FM2

1

CF2

1

CF7

1

H1

JP3

1
2
3
4
5
6
7

HOLEA

H11
HOLEA

1

1

H23
HOLEA

1

D

1

1

1

H2
HOLEA

H8
HOLEA

H6
HOLEA

FM1

1

CF9

1

CF11

1

1

1

1

FM5

H18
HOLEA

1

H9
HOLEA

1

H20
HOLEA

1

FM3

CF3

CF15

1

1

1

FM4

1

CF10

1

CF13

1

H16
HOLEA

1

H13
HOLEA

1

H24
HOLEA

1

Title

Size Document Number Rev

Date: Sheet of

FM6

1

CF8

CF12

H22
HOLEA

1

H7
HOLEA

1

H26
HOLEA

1

CF16

1

CF4

H17
HOLEA

1

H10
HOLEA

1

H3
HOLEA

1

H12
HOLEA

1

H25
HOLEA

1

1

CF1

1

Compal Electronics, Inc.

CRT & TVout Connector

LA-1701

Monday, May 12, 2003

1

H14
HOLEA

H4
HOLEA

CF5

H19
HOLEA

1

H5
HOLEA

1

14 49

1

H21
HOLEA

H15
HOLEA

CF6

1

1

1.0

CF14

1

1

1

E

A

PCI_AD[0..31]<19,20,21,25>

1 1

2 2

CLK_PCI_ICH

CLK_ICH_66M

12

R344
10_0402_5%

1

C447
15P_0402_50V8J

2

12

R346
@22_0402_5%

1

C460
@10P_0402_50V8K

2

PCI Pullups

PCI_PERR#
PCI_REQA#
PCI_STOP#
PCI_SERR#

+3VS

3 3

4 4

PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_FRAME#

+3VS

+3VS

RP72

1 8
2 7
3 6
4 5

8.2K _8P4R_0804_5%

1 2

R322 @1K_0402_5%

RP9

1
2
3
4
5

8.2K_10P8R_1206_5%

RP11

1
2
3
4
5

8.2K_10P8R_1206_5%

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

PIDERST#

10

PCI_PIRQA#

9

PCI_PIRQB#

8

PCI_REQ#4

7

PCI_REQB#

6

10

PCI_PIRQC#

9

PCI_PIRQD#

8

SIRQ

7

PCI_LOCK#

6

+3VS

+3VS

PCIRST#

+3VS

5

P

I2O

G

3

1 2

R347 0_0402_5%

B

PCI_AD[0..31]

PCI_CBE#0<19,20,21,25>
PCI_CBE#1<19,20,21,25>
PCI_CBE#2<19,20,21,25>
PCI_CBE#3<19,20,21,25>

PCI_REQ#0<20>
PCI_REQ#1<19>
PCI_REQ#2<21>
PCI_REQ#3<25>
PCI_REQ#4<25>

PCI_GNT#0<20>
PCI_GNT#1<19>
PCI_GNT#2<21>
PCI_GNT#3<25>
PCI_GNT#4<25>

CLK_PCI_ICH<12>

PCI_FRAME#<19,20,21,25>

PCI_DEVSEL#<19,20,21,25>

PCI_IRDY#<19,20,21,25>

PCI_PAR<19,20,21,25>

PCI_PERR#<19,20,21,25>

PCIRST#<7,13,19,20,21,22,25,31>

PCI_SERR#<19,21,25>

PCI_STOP#<19,20,21,25>

PCI_TRDY#<19,20,21,25>

PIDERST#<18>
SIDERST#<18>

1

U37

4

OE#

@74LVC1G125GW_SOT3535

PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#

PCI_PERR#
PCI_LOCK#

PCIRST#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

B_PCIRST# <18,29>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

CLK_PCI_ICH

PCI_REQA#
PCI_REQB#

PIDERST#
SIDERST#

U8A

H5

AD0

J3

AD1

H3

AD2

K1

AD3

G5

AD4

J4

AD5

H4

AD6

J5

AD7

K2

AD8

G2

AD9

L1

AD10

G4

AD11

L2

AD12

H2

AD13

L3

AD14

F5

AD15

F4

AD16

N1

AD17

E5

AD18

N2

AD19

E3

AD20

N3

AD21

E4

AD22

M5

AD23

E2

AD24

P1

AD25

E1

AD26

P2

AD27

D3

AD28

R1

AD29

D2

AD30

P4

AD31

J2

C/BE#0

K4

C/BE#1

M4

C/BE#2

N4

C/BE#3

B1

REQ#0

A2

REQ#1

B3

REQ#2

C7

REQ#3

B6

REQ#4

C1

GNT#0

E6

GNT#1

A7

GNT#2

B7

GNT#3

D6

GNT#4

P5

PCICLK

F1

FRAME#

M3

DEVSEL#

L5

IRDY#

G1

PAR

L4

PERR#

M2

LOCK#

W2

PME#

U5

PCIRST#

K5

SERR#

F3

STOP#

F2

TRDY#

B5

REQA#/GPI0

A6

REQB#/GPI1/REQ5#

E8

GNTA#/GPO16

C5

GNTB#/GPO17/GNT5#

FW82801DBM_BGA421

ICH4

SM I/F

CPU I/F

HUB I/F

PCI I/F

EEPROM I/F

LAN I/F

C

W6

INTRUDER#

AC3

SMLINK0

AB1

SMLINK1

AC4

SMB_CLK

AB4

SMB_DATA

A20GATE

A20M#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

SLP#
SMI#

STPCLK#

HI10
HI11

CLK66

HI_STB

HI_STB#
HICOMP

HUB_VREF

APICCLK

APICD0
APICD1
PIRQA#

PIRQB#
PIRQC#
PIRQD#

PIRQE#/GPI2

PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5

IRQ14
IRQ15

SERIRQ

EE_CS

EE_IN

EE_OUT

EE_SHCLK

LAN_RXD0
LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

LAN_CLK

LAN_RST#

AA5

Y22
AB23
U23
AA21
W21
V22
AB22
V21

NMI

Y23
U22
U21
W23
V23

L19

HI0

L20

HI1

M19

HI2

M21

HI3

P19

HI4

R19

HI5

T20

HI6

R20

HI7

P23

HI8

L22

HI9

N22
K21

T21
P21

N20
R23

M23
R22

J19
H19
K20
D5
C2
B4
A3
C8
D7
C3
C4
AC13
AA19
J22

D10
D11
A8
C12

A10
A9
A11
B10
C10
A12
C11
B11
Y5

SMB_ALERT#/GPI11

CPU_PWRGOOD

HUB_VSWING

Interrupt I/F

LAN_RSTSYNC

INTRUDER#
SMLINK0
SMLINK1
SMB_CLK
SMB_DATA
GPI11

1 2

56_0402_5%

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

1 2

CLK_ICH_66M

HUB_RCOMP_ICH

APICCLK
APICD0
APICD1
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PD_IRQ14
SD_IRQ15
SIRQ

1 2

@1K_0402_5%

1 2

10K_0402_5%

R359

R85

R356

APICCLK
APICD0
APICD1

10K_0402_5%

SMB_CLK <9,10,12>
SMB_DATA <9,10,12>

H_FERR#

HUB_PD[0..10]

R339
@56_0402_5%

CLK_ICH_66M <12>

HUB_PSTRB <6>
HUB_PSTRB# <6>

HUB_VREF

PCI_PIRQA# <13,20>
PCI_PIRQB# <19>
PCI_PIRQC# <21,25>
PCI_PIRQD# <25>

PD_IRQ14 <18>
SD_IRQ15 <18>
SIRQ <21,22,29,31>

R338

1 2

10K_0402_5%

H_IGNNE# <4>
H_INIT# <4>
H_INTR <4>
H_NMI <4>
H_CPUPWRGD <4>
RC# <29>
H_CPUSLP# <4>
H_SMI# <4>
H_STPCLK# <4>

R333

1 2

GATEA20 <29>
H_A20M# <4>
H_DPSLP# <4,7>
H_FERR# <4>

150_0402_1%

HUB_PD[0..10] <6>

R332
0_0402_5%

1 2

+1.8VS

12

R122

150_0402_1%

12

R123

Note:
R122,R123 placement

center of MCH and
ICH4M

SMB_CLK

SMB_DATA

PD_IRQ14

SD_IRQ15

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

HUB_VREF

HUB_VREF

1

C444

0.01U_0402_16V7K

2

INTRUDER#

H_FERR#

HUB_RCOMP_ICH

SMLINK0

SMLINK1

GPI11

D

1

C453

2

0.01U_0402_16V7K

1 2

R373
10K_0402_5%

1 2

R372
10K_0402_5%

1 2

R370

8.2K_0402_5%

1 2

R369

8.2K_0402_5%

RP74

1 8
2 7
3 6
4 5

8.2K _8P4R_0804_5%

1 2

R354

330K_0402_5%

1 2

R358

56_0402_5%

1 2

R131

36.5_0402_1%

R374

1 2

4.7K_0402_5%
R376

1 2

4.7K_0402_5%
R371

1 2

10K_0402_5%

+RTCVCC

+VCCP

+3VALW

1

2

+3VS

+3VS

C141

0.1U_0402_16V4Z

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ICH4-M(1/3)

LA-1701

Monday, May 12, 2003

D

15 49

1.0