HP A900 Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Merom uFCPGA with Satna Rosa Platform

3 3

2007-08-02

REV:0.2

4 4

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/07/26

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

LA-3981P

D

Date: Sheet of

Cover Sheet

E

142Monday, October 22, 2007

0.3

A

B

C

D

E

Compal confidential

File Name : LA-3981P

ZZZ1

PCB

1 1

2 2

LED

page 28

3 3

RTC CKT.

page 19

LEON 1.0 (Merom +Crestline+ICH8)

Mobile Yonah/Merom

uFCPGA-478 CPU

H_A#(3..31)

NB Crestline

Socket P

FSB

533/667/800MHz

page 7,8,9,10,11,12

DMI

SB ICH8

page 18,19,20,21

LPC BUS

H_D#(0..63)

DDR2 -400/533/667

USB2.0

AC-LINK/Azalia

Thermal Sensor
ADM1032AR

Dual Channel

SATA

PATA Master

Clock Generator

ICS9LPRS355

page 4page 4,5,6

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

USB WebCam

USB Card Reader

USB Conn

Audio Conexant

CX20561-12

SATA HDD Connector

IDE ODD Connector

page 15

page 13,14

page 17

page 27

page 27

page 24

page 22

page 22

Realtek

RTL8100CL

page 23

RJ45/11 CONN

page 23

CRT/TV-OUT

page 16

LVDS Conn

page 17

Mini-Card
WLAN

Fan Control

page 4

PCI BUS

PCI-E BUS

page 22

MODEM AMOM
CX20548

page 25

AMP & Audio Jack
TPA6017A2

page 26

SPI ROM

SPI

Power On/Off CKT.

4 4

DC/DC Interface CKT.

Power Circuit DC/DC

page 28

page 31

Page 32,33,34,35,36,37,38

A

Touch Pad CONN.

B

ENE KB926

page 30

Int.KBD

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/07/26

C

25LF080A

page 29

page 30page 28

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

LA-3981P

Date: Sheet of

Block Diagram

E

242Monday, October 22, 2007

0.3

5

4

3

2

1

Voltage Rails

+5VS

power
plane

D D

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

C C

+5VALW

+B

+3VALW

O
O
O
O
O

X

O
O
O
O

X
XX X

+1.8V

O

XX
X

+3VS
+1.5VS
+1.25VS
+0.9V
+VCCP
+CPU_CORE

OO
OO

X

X

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

External PCI Devices

LAN AD22 0 A

IDSEL # PIRQREQ/GNT #DEVICE

B B

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_CK2
SMB_EC_DA2

SMB_CK_CLK1
SMB_CK_DAT1 ICH8

LCD_CLK
LCD_DAT

KB925

KB925

Crestline

INVERTER BATT EEPROM

X
X

X
XX

SERIAL SENSOR

VV

XX
X

X
XX

THERMAL
(CPU)

SODIMM CLK CHIP

ADM1032

XX

X

V

X

VVV

XX

X
X

MINI CARD

LCD

XX
X

X
X

X

V

BOM: 43151732L01(965GM) & 443151732L02(960GML) with card reader

BOM: 43151732L03(965GM) & 43151732L04(960GML) without card reader

A A

Jump-Short: PJP?

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/07/26

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

2

Date: Sheet of

LA-3981P

Notes List

1

342Monday, October 22, 2007

0.3

5

D D

4

3

2

1

H_A#[3..16]7

H_ADSTB#07

H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47

H_A#[17..35]7

C C

H_ADSTB#17

H_A20M#19

H_FERR#19

H_IGNNE#19
H_STPCLK#19

H_INTR19

H_NMI19
H_SMI#19

B B

+VCCP

12

B

2

H_PROCHOT# OCP#

A A

E

3 1

Q2

@

MMBT3904_SOT23

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9

H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_ADSTB#0
H_REQ#0

H_REQ#1
H_REQ#2

H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADSTB#1
H_A20M#

H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

R17

56_0402_5%@

C

OCP# 20

JP2A

J4

ADDR GROUP 0 ADDR GROUP 1

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

CONN@

SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU
SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

H1

ADS#

E2

BNR#

G5

BPRI#

H5

DEFER#

F21

DRDY#

E1

DBSY#

F1

BR0#

D20

IERR#

B3

INIT#

H4

LOCK#

CONTROL

C1

RESET#

F3

RS[0]#

F4

RS[1]#

G3

RS[2]#

G2

TRDY#

G6

HIT#

E4

HITM#

AD4

BPM[0]#

AD3

BPM[1]#

AD1

BPM[2]#

AC4

BPM[3]#

AC2

PRDY#

AC1

PREQ#

AC5

TCK

AA6

TDI

AB3

TDO

AB5

TMS

AB6

TRST#

C20

DBR#

D21
A24
B25

C7

A22

BCLK[0]

A21

BCLK[1]

For Merom, R14 and R15 are 0ohm
For Penryn, R14 and R15 are 100ohm.

H_ADS#H_A#3
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#H_REQ#3

H_HIT#
H_HITM#

XDP_TCK
XDP_TDI

XDP_TMS
XDP_TRST#

DBRESET#

H_PROCHOT#

H_THERMDA_R
H_THERMDC_R

H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS# 7
H_BNR# 7

H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

H_INIT# 19
H_LOCK# 7
H_RESET# 7

H_RS#0 7

H_RS#1 7

H_RS#2 7

H_TRDY# 7

H_HIT# 7
H_HITM# 7

R413

@

1 2

0_0402_5%

R14 0_0402_5%

1 2

R15 0_0402_5%

1 2

R10

56_0402_5%

C2 0.1U_0402_16V4Z

1 2

XDP_DBRESET#

R13

12

68_0402_5%

H_THERMDA
H_THERMDC

H_THERMTRIP# 7,19

CLK_CPU_BCLK 15
CLK_CPU_BCLK# 15

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil

R415 0_0402_5%@

1 2

12

+VCCP

+VCCP

XDP_DBRESET# 20
H_PROCHOT# 37

+3VS

12

R416

@

10K_0402_5%

THERM#L_THERM#

+VCCP

XDP_TDI

R2 15_0402_5%

XDP_TMS

XDP_TRST#
XDP_TCK

1 2

R3 39_0402_1%

1 2

R7 560_0402_5%

1 2

R8 27_0402_5%

1 2

Thermal Sensor ADM1032ARMZ

+3VS

2200P_0402_50V7K

+3VS

R414

1 2

0_0402_5%

0.1U_0402_16V4Z

C4

1 2

R16

1 2

10K_0402_5%

PWM Fan Control circuit

R405 0_0402_5%

1 2

+3VS

@

5

1

THERM#

INB

2

INA

P

O

G

TC7SH00FU_SSOP5

3

FAN_PWM30

C3

H_THERMDA
H_THERMDC

L_THERM#

U2

4

2

1

U1

1

VDD

2

D+

3

D­THERM#4GND

ADM1032ARMZ-2REEL_MSOP8

Address:100_1100

+5VS

2

1

G

3

4 5

SCLK

SDATA

ALERT#

SMB_EC_DA230

SMB_EC_CK230

D1
RB751V_SOD323

2 1

6

D

Q1

S

SI3456BDV-T1-E3_TSOP6

+3VS

SMB_EC_CK2

8

SMB_EC_DA2

7
6
5

SMB_EC_DA2
SMB_EC_CK2

SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P

1

2

C5

4.7U_0805_10V4Z

FAN

1

C6

0.1U_0402_16V4Z

2

12

D26

@

RLZ5.1B_LL34

12

12

R426
10K_0402_5%

@

R427
10K_0402_5%

@

JP3

1

1

2

2

3

G1

4

G2

ACES_85204-02001

CONN@

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Merom(1/3)-AGTL+/XDP

Size Document Number Rev

Custom

LA-3981P

2

Date: Sheet of

442Monday, October 22, 2007

1

0.3

5

4

3

2

1

H_D#[0..15]7

D D

H_DSTBN#07
H_DSTBP#07

H_DINV#07

H_D#[16..31]7

C C

H_DSTBN#17
H_DSTBP#17

H_DINV#17

R20 1K_0402_5%@

1 2

R21 1K_0402_5%@

1 2

C8 0.1U_0402_16V4Z@

1 2

CPU_BSEL015
CPU_BSEL115
CPU_BSEL215

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8

H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1 H_DINV#3

V_CPU_GTLREF

TEST1
TEST2
TEST3

T1

TEST4
TEST5

T2

TEST6

T3

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

JP2B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

CONN@

DATA GRP 1

MISC

D[32]#
D[33]#
D[34]#

DATA GRP 0

D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#

DATA GRP 2DATA GRP 3

D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25

H_DSTBN#2

Y26

H_DSTBP#2

AA26

H_DINV#2

U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23

H_DSTBN#3

AE25

H_DSTBP#3

AF24
AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1

H_DPRSTP#

E5

H_DPSLP#

B5

H_DPWR#

D24

H_PWRGOOD

D6

H_CPUSLP#

D7

SLP#

H_PSI#

AE6

PSI#

H_D#32

Y22

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs

CPU_BSEL CPU_BSEL2 CPU_BSEL1

166

B B

200

V_CPU_GTLREF

01

0

+VCCP

12

R27
1K_0402_1%

12

R29
2K_0402_1%

CPU_BSEL0

1

1

0

H_D#[32..47] 7

H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

H_DPRSTP# 7,19,37
H_DPSLP# 19
H_DPWR# 7
H_PWRGOOD 19
H_CPUSLP# 7
H_PSI# 37

12

12

12

R25

R24

R22

R23

27.4_0402_1%

54.9_0402_1%

54.9_0402_1%

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

+VCC_CORE +VCC_CORE

12

27.4_0402_1%

JP2C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

CONN@

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

R18 0_0402_5%

12

G21

12

V6

R19 0_0402_5%

J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VSSSENSE

AE7

.

Length match within 25 mils.
The trace width/space/other is
20/7/25.

+VCC_CORE

R28
100_0402_1%

1 2

R30
100_0402_1%

1 2

+VCCP

1

+

2

CPU_VID0 37
CPU_VID1 37
CPU_VID2 37
CPU_VID3 37
CPU_VID4 37
CPU_VID5 37
CPU_VID6 37

VCCSENSE 37

VSSSENSE 37

VCCSENSE

VSSSENSE

C7
220U_6.3V_M

C9

1

C10

2

10U_0805_6.3V6M

+1.5VS

1

2

0.01U_0402_16V7K

Near pin B26

Close to CPU pin AD26
within 500mils.

A A

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

2

Close to CPU pin
within 500mils.

Compal Electronics, Inc.

Title

Merom(2/3)-AGTL+/PWR

Size Document Number Rev

Custom

LA-3981P

Date: Sheet of

542Monday, October 22, 2007

1

0.3

5

D D

C C

B B

A A

JP2D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

CONN@

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

+VCCP

4

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(North side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

Place these capacitors on L8
(Sorth side,Secondary Layer)

220U_D2_2V_Y_LESR9M

1

C50

0.1U_0402_16V4Z

2

1

2

+VCC_CORE

1

C11
10U_0805_6.3V6M

2

+VCC_CORE

1

C19
10U_0805_6.3V6M

2

+VCC_CORE

1

C27
10U_0805_6.3V6M

2

+VCC_CORE

1

C35
10U_0805_6.3V6M

2

Near CPU CORE regulator

+VCC_CORE

1

+

C45

2

1

C51

0.1U_0402_16V4Z

C52

0.1U_0402_16V4Z

2

1

C12
10U_0805_6.3V6M

2

1

C20
10U_0805_6.3V6M

2

1

C28
10U_0805_6.3V6M

2

1

C36
10U_0805_6.3V6M

2

220U_D2_2V_Y_LESR9M

1

+

C47

C46

2

220U_D2_2V_Y_LESR9M

1

C13
10U_0805_6.3V6M

2

1

C21
10U_0805_6.3V6M

2

1

C29
10U_0805_6.3V6M

2

1

C37
10U_0805_6.3V6M

2

1

+

C48

2

220U_D2_2V_Y_LESR9M

1

C53

0.1U_0402_16V4Z

2

3

1

C14
10U_0805_6.3V6M

2

1

C22
10U_0805_6.3V6M

2

1

C30
10U_0805_6.3V6M

2

1

C38
10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1000U 2.5V M H80 LESR8M

1

1

+

+

C49

2

2

@

1

C54

0.1U_0402_16V4Z

2

1

C15
10U_0805_6.3V6M

2

1

C23
10U_0805_6.3V6M

2

1

C31
10U_0805_6.3V6M

2

1

C39
10U_0805_6.3V6M

2

Place these inside
socket cavity on L8
(North side
Secondary)

1

C55

0.1U_0402_16V4Z

2

1

C16
10U_0805_6.3V6M

2

1

C24
10U_0805_6.3V6M

2

1

C32
10U_0805_6.3V6M

2

1

C40
10U_0805_6.3V6M

2

2

1

C17
10U_0805_6.3V6M

2

1

C25
10U_0805_6.3V6M

2

1

C33
10U_0805_6.3V6M

2

1

C41
10U_0805_6.3V6M

2

1

C18
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

1

C34
10U_0805_6.3V6M

2

1

C42
10U_0805_6.3V6M

2

1

Mid Frequence Decoupling

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Merom(3/3)-GND&Bypas s

Size Document Number Rev

Custom

LA-3981P

2

Date: Sheet of

642Monday, October 22, 2007

1

0.3

5

H_D#[0..63]5

D D

C C

+VCCP

12

12

R40

R39

54.9_0402_1%

54.9_0402_1%

H_SWNG
H_RCOMP

H_SCOMP
H_SCOMP#

H_RESET#4

H_CPUSLP#5

B B

layout note:
Route H_SCOMP and H_SCOMP# with trace width, spacing and

impedance (55 ohm) same as FSB data traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG

trace width and spacing is 10/20

+VCCP

12

R44

1K_0402_1%

0.1U_0402_16V4Z

A A

12

R49

C62

2K_0402_1%

H_RESET#
H_CPUSLP#

H_VREF

1

2

12

R50

24.9_0402_1%

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57

H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_RCOMP

E2
G2
G7
M6
H7
H3
G4

F3
N8
H2

M10
N12

N9
H5

P13

K9
M2

W10

Y8

V4
M3

J1
N5
N3
W6
W9
N2

Y7

Y9

P4
W3
N1

AD12

AE3
AD9
AC9

AC7
AC14
AD11
AC11

AB2

AD7

AB1

Y3
AC6
AE2
AC5
AG3
AJ9
AH8

AJ14

AE9

AE11
AH12

AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2

AH13

B3

C2
W1

W2

B6

E5

B9

A9

U3A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

+VCCP

R45

R51

12

12

221_0603_1%

100_0402_1%

HOST

H_SWNGH_VREF

1

2

0.1U_0402_16V4Z

C63

Near B3 pinwithin 100 mils from NB

5

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

4

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

V_DDR_MCH_REF13,14,35

4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9

H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#

H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#

H_DPWR#
H_DRDY#
H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0H_D#58
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_A#[3..35] 4

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4

H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5

H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5

H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

V_DDR_MCH_REF

1

C61

2

0.1U_0402_16V4Z

3

+1.8V

2

2

12

R31

C56

C57

1

1

1K_0402_1%

2.2U_0805_16V4Z

2.2U_0805_16V4Z

MCH_CLKSEL015
MCH_CLKSEL115
MCH_CLKSEL215

PM_BMBUSY#20

H_THERMTRIP#4,19

1

C58

2

R36

10K_0402_5%

R37

10K_0402_5%

R38

<>

10K_0402_5%

H_DPRSTP#5,19,37
PM_EXTTS#013
PM_EXTTS#114

PM_PWROK20,30

PLT_RST#18,22

DPRSLPVR20,37

0.01U_0402_16V7K

12

R32

3.01K_0402_1%

NA lead free

12

R33

1

1K_0402_1%

2

C59

0.01U_0402_16V7K

DDR_A_MA1413
DDR_B_MA1414

+3VS

12

12

12

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5

T4

CFG6

T5

CFG7

T6

CFG8

T7

CFG9

T8

CFG10

T9

CFG11

T10

CFG12

T11

CFG13

T12

CFG16

T13

CFG18

T44

CFG19

T14

CFG20

T15

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK
PLT_RST#
H_THERMTRIP#

DPRSLPVR

SMRCOMP_VOH

SMRCOMP_VOL

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_B DMI_TXN0

+1.8V

12

R43
1K_0402_1%

12

R46
1K_0402_1%

AR12
AR13
AM12
AN13

AR37
AM36

AM37

BK22
BF19
BH20
BK18

BF23
BG23
BC23
BD24

BE24
BH39
AW20
BK20

AW49
AV20

BK51
BK50

P36
P37
R35
N35

J12

AL36

D20

H10
B51

BJ20

BJ18

BJ29

C48
D47
B44
C44
A35
B37
B36
B34
C34

P27
N27
N24
C21
C23
F23
N23

G23

J20
C20
R24

L23

J23
E23
E20
K23
M20
M24

L32

N33

L35

G41

L39

L36

J36

N20
G36

BJ51

BL50
BL49

BL3
BL2
BK1
BJ1

E1

A5
C51
B50
A50
A49
BK2

U3B

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

CRESTLINE_1p0

2

DDR MUXINGCLK

CFGRSVD

DMI

PM

GRAPHICS VID

ME

NC

MISC

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3

SM_CK#_4
SM_CKE_0

SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

0925_Stuff R43 and R46.

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

2

For Crestline: 20ohm

M_CLK_DDR0

AV29

M_CLK_DDR1

BB23

M_CLK_DDR2

BA25

M_CLK_DDR3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

DDR_CKE0_DIMMA

BE29

DDR_CKE1_DIMMA

AY32

DDR_CKE2_DIMMB

BD39

DDR_CKE3_DIMMB

BG37

DDR_CS0_DIMMA#

BG20

DDR_CS1_DIMMA#

BK16

DDR_CS2_DIMMB#

BG16

DDR_CS3_DIMMB#

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SMRCOMP

BL15

SMRCOMP#

BK14

SMRCOMP_VOH

BK31

SMRCOMP_VOL

BL31
AR49

V_DDR_MCH_REF

AW4

CLK_MCH_DREFCLK

B42

CLK_MCH_DREFCLK#

C42

MCH_SSCDREFCLK

H48

MCH_SSCDREFCLK#

H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

E35
A39
C38
B39
E36

CL_CLK0

AM49

CL_DATA0

AK50

M_PWROK

AT43

CL_RST#

AN49

CL_VREF CL_VREF

AM50

H35
K36

CLKREQ#_B

G39

MCH_ICH_SYNC#

G40

A37

TEST_1

R32

TEST_2

12

R47

20K_0402_5%

Title

Size Document Number Rev

Custom
Date: Sheet of

For Calero: 80.6ohm

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14

DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14

DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14

M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14

R34
R35 30_0402_1%

0927_Change from 20 ohm to 30 ohm.

CLK_MCH_DREFCLK 15
CLK_MCH_DREFCLK# 15
MCH_SSCDREFCLK 15
MCH_SSCDREFCLK# 15

CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15

DMI_TXN0 20
DMI_TXN1 20
DMI_TXN2 20
DMI_TXN3 20

DMI_TXP0 20
DMI_TXP1 20
DMI_TXP2 20
DMI_TXP3 20

DMI_RXN0 20
DMI_RXN1 20
DMI_RXN2 20
DMI_RXN3 20

DMI_RXP0 20
DMI_RXP1 20
DMI_RXP2 20
DMI_RXP3 20

T16
T17
T18
T19
T20

CL_CLK0 20
CL_DATA0 20
M_PWROK 20,30
CL_RST# 20

0.1U_0402_16V4Z
C60

CLKREQ#_B 15
MCH_ICH_SYNC# 20

12

R48
0_0402_5%

Compal Electronics, Inc.

CRESTLINE(1/6)-AGTL+/DMI/DDR2

LA-3981P

1

+1.8V

30_0402_1%

12
12

+1.25VM_AXD

12

R41
1K_0402_1%

12

1

R42
392_0402_1%

2

742Monday, October 22, 2007

1

0.3

5

D D

DDR_A_D[0..63]13

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8

DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AW44

AW47

BG47

BG50

AW43
BG42

BG40

AW40
AW36

AW41

AW11

BG10

AR43
BA45

AY46
AR41
AR45
AT42

BB45
BF48

BJ45
BB47

BH49
BE45

BE44
BE40

BF44
BH45

BF40
AR40

AT39

AY41
AV38
AT38
AV13
AT13

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BD8
AY9

AW9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AM8

AN10

AT9
AN9

AM9

AN11

U3D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

4

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

BL17

SA_CAS#

AT45

SA_DM_0

BD44

SA_DM_1

BD42

SA_DM_2

AW38

SA_DM_3

AW13

SA_DM_4

BG8

SA_DM_5

AY5

SA_DM_6

AN6

SA_DM_7

AT46

SA_DQS_0

BE48

SA_DQS_1

BB43

SA_DQS_2

BC37

SA_DQS_3

BB16

SA_DQS_4

BH6

SA_DQS_5

BB2

SA_DQS_6

AP3

SA_DQS_7

AT47

SA_DQS#_0

BD47

SA_DQS#_1

BC41

SA_DQS#_2

BA37

SA_DQS#_3

BA16

SA_DQS#_4

BH7

SA_DQS#_5

BC1

SA_DQS#_6

AP2

SA_DQS#_7

BJ19

SA_MA_0

BD20

SA_MA_1

BK27

SA_MA_2

BH28

SA_MA_3

BL24

SA_MA_4

BK28

SA_MA_5

BJ27

SA_MA_6

BJ25

SA_MA_7

BL28

SA_MA_8

BA28

SA_MA_9

BC19

SA_MA_10

BE28

SA_MA_11

BG30

SA_MA_12

BJ16

SA_MA_13

BE18

SA_RAS#

AY20

SA_RCVEN#

DDR SYSTEM MEMORY A

SA_WE#

BA19

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2

DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#

SA_RCVEN#
DDR_A_WE#

3

DDR_A_BS0 13
DDR_A_BS1 13
DDR_A_BS2 13

DDR_A_CAS# 13 DDR_B_CAS# 14
DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..13] 13

DDR_A_RAS# 13

T22

DDR_A_WE# 13

DDR_B_D[0..63]14

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8

DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18DDR_A_DQS3
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41

DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

AW50
AW51

BG12

AP49
AR51

AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12

BJ10

BL9
BK5
BL5
BK9

BK10

BJ8
BJ6
BF4

BH5
BG1
BC2
BK3
BE4
BD3

BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

U3E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

2

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6

DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10DDR_B_D42
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#
SB_RCVEN#

DDR_B_WE#

T21

1

DDR_B_BS0 14
DDR_B_BS1 14
DDR_B_BS2 14

DDR_B_DM[0..7] 14

DDR_B_DQS[0..7] 14

DDR_B_DQS#[0..7] 14

DDR_B_MA[0..13] 14

DDR_B_RAS# 14

DDR_B_WE# 14

A A

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CRESTLINE((2/6)-DDR2 A/B CH

Size Document Number Rev

Custom

LA-3981P

2

Date: Sheet of

842Monday, October 22, 2007

1

0.3

5

4

3

2

1

Strap Pin Table

010 = FSB 800MHz

CFG[2:0] FSB Freq select

D D

ENABLT

ENABLT17

+3VS

LCD_CLK17

For Crestline:2.4kohm
For Calero: 1.5Kohm

C C

B B

LCD_DATA17

LCD_CLK

LCD_DATA

ENAVDD

ENAVDD17

R55 2. 4K_0402_1%

LVDSBC-17
LVDSBC+17

TV_COMPS16
TV_LUMA16
TV_CRMA16

R56

+3VS

3VDDCCL16

3VDDCDA16

CRT_HSYNC16
CRT_VSYNC16

BKLT_CTRL

R53 10K_0402_5%

1 2

R54 10K_0402_5%

1 2

12

LVDSAC-

LVDSAC-17

LVDSAC+

LVDSAC+17

LVDSBC­LVDSBC+

LVDSA0-

LVDSA0-17

LVDSA1-

LVDSA1-17

LVDSA2-

LVDSA2-17

LVDSA0+

LVDSA0+17

LVDSA1+

LVDSA1+17

LVDSA2+

LVDSA2+17

LVDSB0-

LVDSB0-17

LVDSB1-

LVDSB1-17

LVDSB2-

LVDSB2-17

LVDSB0+

LVDSB0+17

LVDSB1+

LVDSB1+17

LVDSB2+

LVDSB2+17

TV_COMPS
TV_LUMA
TV_CRMA

2.2K_0402_5%

1 2

CRT_B

CRT_B16

CRT_G

CRT_G16

CRT_R

CRT_R16

3VDDCCL
3VDDCDA
CRT_HSYNC

CRT_VSYNC

1.3K_0402_1%

U3C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

12

R57

CRESTLINE_1p0

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

R52

24.9_0402_1%

PEGCOMP

1 2

PEGCOMP trace wi dth
and spacing is 20/25 mils.

+VCCP

CFG5 (DMI select)

CFG6

CFG7 (CPU Strap)

CFG8 (Low power PCIE)

CFG9

(PCIE Graphics Lane Reversal)

CFG[11:10]

CFG[13:12] (XOR/ALLZ)

CFG16 (FSB Dynamic ODT)

SDVO_CTRLDATA

CFG19 (DMI La ne Reversal)

CFG20 (PCIE/SDVO concurrent)

CFG[17:3] have internal pull up
CFG[19:18] have internal pull down

011 = FSB 667MHz
Others = Reserved

0 = DMI x 2
1 = DMI x 4

Reserved

0 = Reserved
1 = Mobile CPU

0 = Normal mode
1 = Low Power mode

0 = Reverse Lane
1 = Normal Operation

*

*

*
*

Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation

ReservedCFG[15:14]

0 = Disabled
1 = Enabled

ReservedCFG[18:17]

0 = No SDVO Device Present
1 = SDVO Device Present

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PC I E or SDVO is operational.
1 = PCIE/SDVO a re operating simu.

(Default)

*

*

*

*

*

For Crestline:1.3kohm
For Calero: 255ohm

A A

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CRESTLINE((3/6)-VGA/LVDS/TV

Size Document Number Rev

Custom

LA-3981P

2

Date: Sheet of

942Monday, October 22, 2007

1

0.3

BLM18PG181SN1D_0603

R59

0.1U_0402_16V4Z

1

1

C439

4.7U_0603_6.3V6K

2

2

5

+3VS

12

+3VS_DAC_BG

0.022U_0402_16V7K

1

C65

2

C66

0925_Change C439 from 0.47uF to 4.7uF.

D D

+3VS_DAC_CRT

BLM18PG181SN1D_0603

0.022U_0402_16V7K

1

1

C73

C74

2

2

+1.25VS

C C

220U_6.3V_M

+3VS_TVDACC

B B

0.022U_0402_16V7K

1

C111

2

+3VS_TVDACA

0.022U_0402_16V7K

1

C115

2

A A

+3VS_TVDACB

0.022U_0402_16V7K

1

C121

2

0.1U_0402_16V4Z

+3VS

+

C90

R71

0_0603_5%

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

C112

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

C116

2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

C122

2

+3VS

12

R62

0_0603_5%

0.1U_0402_16V4Z

R68

1 2

0_0805_5%

1

10U_0805_10V4Z

2

+1.25VM_A_SM_CK

12

1U_0603_10V4Z

C99

1

2

R74

R78

R80

5

R66

C100

+3VS_PEG_BG

+3VS

12

+3VS

12

+3VS

12

+3VS

+1.8V_TXLVDS

12

1

C85

2

1

C91

4.7U_0805_10V4Z

2

100mA

10U_0805_10V4Z

C101

1

2

R58

0_0603_5%

10mA

5mA

+1.25VM_A_SM

C92

1U_0603_10V4Z

1

2

+1.25VS_PEGPLL

VCCSYNC

12

C64

+1.25VS_DPLLA
+1.25VS_DPLLB

+1.25VM_HPLL
+1.25VM_MPLL

1000P_0402_50V7K
C82

+1.25VS_PEGPLL

1

2

0.1U_0402_16V4Z

C102

1

2

+1.5VS_TVDAC

+1.25VM_HPLL

+1.8V_LVDS

10mA

0.1U_0402_16V4Z

1

2

+3VS_DAC_CRT

+3VS_DAC_BG

80mA
80mA
50mA
150mA

1

2

950mA

1

C93

2

1U_0603_10V4Z

40mA

+3VS_TVDACA

40mA

+3VS_TVDACB

40mA

+3VS_TVDACC

+1.5VS_QDAC

250mA
100mA

150mA

+1.5VS_QDAC

0.022U_0402_16V7K

1

C113

2

+1.8V_LVDS

10U_0805_10V4Z

C119

1

2

80mA

5mA

20 mils

75mA

C114

1U_0603_10V4Z

4

U3H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

50mA

M32

VCCD_CRT

25mA

L29

VCCD_TVDAC

5mA

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

CRESTLINE_1p0

R77

100_0603_1%

0.1U_0402_16V4Z

1

2

C120

R81

0_0603_5%

1

2

4

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

+1.5VS

12

12

+1.8V

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

VTT

VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5

AXD

VCC_AXD_6

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

PEG

VCC_PEG_5

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

1000P_0402_50V7K

+1.8V_TXLVDS

C118

Security Clas sification

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

850mA

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

1

2

+VCCP

350mA

100mA

120mA

100mA

1200mA

250mA

0.47U_0603_10V7K

C108

1

2

Issued Date

3

220U_6.3V_M

1

+

C71

2

1

C75

2

+1.25VM_AXD

200mA

1U_0603_10V4Z

C83

1

2

+V1.25VS_AXF

+1.25VS_DMI

+1.8V_SM_CK

+1.8V_TXLVDS

100mA

1450mA

+VCC_PEG

20mils

0.47U_0603_10V7K
C110

C109

1

1

2

2

1U_WIM32251R0KZF_10%

C117
10U_0805_10V4Z

3

+1.25VS_DPLLB

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

C72

2

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z

1

1

C76

C77

2

2

R65

1 2

+1.25VS

0_0805_5%

10U_0805_10V4Z

C84

1

2

+3VS_HV

0.1U_0402_16V4Z

C103

1

2

0.47U_0603_10V7K

1

2

R79

12

+1.8V

2007/03/26 2006/03/10

1022_Change R64, R79 from 0 ohm to 1uH/400mA inductor.

Compal Secret Data

+1.25VS_DMI

+1.25VS_PEGPLL

+1.25VS_DPLLA

0.1U_0402_16V4Z

Deciphered Date

1

2

1

2

0.1U_0402_16V4Z

+VCC_PEG

220U_6.3V_M

2

1 2

10U_0805_10V4Z

10U_FLC-453232-100K_0.25A_10%

C67

C68

1

2

1 2

0.1U_0402_16V4Z
R63

0_0603_5%

C81

BLM18PG121SN1D_0603

10U_0805_10V4Z

C86

1

1

2

2

C96

C95

1

1

2

2

1

C104

C105

+

2

2

R60

+1.25VS

+1.25VS

+1.25VS

L1

12

C87

R69

1 2

10U_0805_10V4Z

1

2

+1.25VS

10U_FLC-453232-100K_0.25A_10%

R72

0_0805_5%

10U_0805_10V4Z

+VCCP

+3VS

1

+V1.25VS_AXF

10U_0805_10V4Z

C69

1

2

+1.8V_SM_CK

10U_0805_10V4Z

10U_0805_10V4Z

C78

C79

1

1

2

2

+1.5VS_TVDAC

0.022U_0402_16V7K

1

C88

2

+1.25VM_HPLL

1

C97

0.1U_0402_16V4Z

+VCCP

12

0.1U_0402_16V4Z

+VCCP_D

D2

2 1

CH751H-40PT_SOD323-2

Title

Size Document Number Rev

Custom

LA-3981P

Date: Sheet of

2

+1.25VM_MPLL

1

C106

2

R75

12

10_0402_5%

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C89

2

MBK2012121YZF_0805

1

C98
10U_0805_10V4Z

2

MBK2012121YZF_0805

1

C107
10U_0805_10V4Z

2

R76

0_0402_5%

1

1 2

C70

1

2

R64

1 2

1U_WIM32251R0KZF_10%

C80

1

2

R67

1 2

0_0805_5%

R70

12

+1.25VS

R73

12

12

+3VS_HV

10 42Monday, October 22, 2007

R61

0_0603_5%

+1.25VS

+1.25VS

+1.8V

+1.5VS

0.3

5

4

3

2

1

+VCCP

VCC=1260mA

D D

0.22U_0603_10V7K

220U_6.3V_M

C C

B B

A A

0.22U_0402_10V4Z

10U_0805_10V4Z

1

C126

+

2

0.22U_0402_10V4Z

1

2

C128

C127

1

1

2

2

0.22U_0402_10V4Z

0.1U_0402_16V4Z

C143

C144

C142

1

1

2

2

VCC=1260mA

0.1U_0402_16V4Z

C129

1

2

+VCCP

VCC_AXM=970mA

10U_0805_10V4Z

10U_0805_10V4Z

C135

1

2

0.1U_0402_16V4Z
C145

1

1

2

2

+VCCP

U3F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

C130

1

2

C136

1

2

0.1U_0402_16V4Z
C146

AH37

AJ33

AJ35
AK33
AK35
AK36
AK37
AD33

AJ36
AM35

AL33

AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36

Y32
Y33
Y35
Y36
Y37
T30
T34

T35
U29
U31
U32
U33
U35
U36

V32

V33

V36

V37

AL24
AL26

AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33

AL29

AL31

AL32
AR31
AR32
AR33

VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

CRESTLINE_1p0

VCC NCTF

POWER

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

VCC_AXM=970mA

+VCCP

C138

1U_0603_10V4Z

R82

1 2

0_0603_5%

3720mA

+1.8V

1

+

C131

220U_6.3V_M

2

1

2

1

+

C137

2

220U_6.3V_M

10U_0805_10V4Z

1

C139

2

10U_0805_10V4Z

10U_0805_10V4Z

C132

1

2

VCC_AXG=7700mA

1

C140

2

10U_0805_10V4Z

0.01U_0402_16V7K

C133

1

2

2

1

+VCCP

0.1U_0402_16V4Z

1

C141

2

U3G

AT35

VCC_1

AT34

VCC_2

AH28

VCC_3

AC32

VCC_5

AC31

VCC_4

AK32

VCC_6

AJ31

VCC_7

AJ28

VCC_8

AH32

VCC_9

AH31

VCC_10

AH29

VCC_11

AF32

VCC_12

R30

VCC_13

VCC CORE

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

CRESTLINE_1p0

POWER

AU32
AU33
AU35

AV33
AW33
AW35

AY35

C134

BA32

BA33

BA35

BB33

BC32

BC33

BC35

BD32

BD35

BE32

BE33

BE35

BF33

BF34
BG32
BG33
BG35

BH32

BH34

BH35

BJ32

BJ33

BJ34

BK32

BK33

BK34

BK35

BL33

AU30

R20

T14
W13
W14

Y12

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

VCC_AXG=7700mA

0.1U_0402_16V4Z
C123

1

2

0.22U_0603_10V7K

C147 0.1U_0402_16V4Z

C148 0.1U_0402_16V4Z

1

1

2

2

C124

1

1

C125

2

2

4.7U_0805_10V4Z

C149 0.22U_0603_10V7K

C150 0.22U_0603_10V7K

1

1

2

2

C153 1U_0603_10V4Z

C151 0.47U_0603_10V7K

C152 1U_0603_10V4Z

1

1

1

2

2

2

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CRESTLINE((5/6)-PWR/GND

Size Document Number Rev

Custom

LA-3981P

2

Date: Sheet of

11 42Monday, October 22, 2007

1

0.3

5

U3I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

AW12
AW16

AB23
AB26
AB28
AB31
AC10
AC13

AC3
AC39
AC43
AC47

AD1
AD21
AD26
AD29

AD3
AD41
AD45
AD49

AD5
AD50

AD8
AE10
AE14

AE6
AF20
AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9

AJ11

AJ13

AJ21

AJ24

AJ29

AJ32

AJ43

AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AL1
AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4
AP48
AP50
AR11

AR2
AR39
AR44
AR47

AR7
AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51
AV39
AV48

AW1

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

VSS

D D

C C

B B

A A

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

4

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U3J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35
J39

K12
K47

L17
L20
L24
L28

L33

L49
M28
M42
M46
M49

M5
M50

M9

N11
N14
N17
N29
N32
N36
N39
N44
N49

N7

P19
P23
P50

R49
T39
T43
T47
U41
U45
U50

VSS_242
VSS_243

VSS_245
VSS_246

K8

VSS_247

L1

VSS_248
VSS_249
VSS_250
VSS_251
VSS_252

L3

VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273

P2

VSS_274
VSS_275

P3

VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

2

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

1

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

CRESTLINE((6/6)-PWR/GND

Size Document Number Rev

Custom

LA-3981P

2

Date: Sheet of

12 42Monday, October 22, 2007

1

0.3

5

DDR_A_DQS#[0..7]8

DDR_A_D[0..63]8

DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..14]7,8

D D

Layout Note:
Place near JP34

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_A_MA3
DDR_A_MA10

DDR_A_MA8
DDR_A_MA5

DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA1
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_CS1_DIMMA# M_ODT0
M_ODT1

DDR_A_MA11

1

2

1

2

C166

C157

0.1U_0402_16V4Z

C158

1

2

0.1U_0402_16V4Z

1

2

C167

RP1

1 4
2 3

RP3

1 4
2 3

RP5

1 4
2 3

RP7

1 4
2 3

RP9

1 4
2 3

RP11

2 3
1 4

1 2

R85 56_0402_5%

5

2.2U_0805_16V4Z

1

2

C168

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

56_0404_4P2R_5%

C159

1

2

0.1U_0402_16V4Z

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C169

+0.9V

2.2U_0805_16V4Z

0.1U_0402_16V4Z

C161

C160

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C171

C170

RP2 56_0404_4P2R_5%

DDR_CKE0_DIMMA

14

DDR_A_BS2

23

RP4 56_0404_4P2R_5%

DDR_A_MA7

14

DDR_A_MA6

23

RP6 56_0404_4P2R_5%

DDR_A_MA12

14

DDR_A_MA9

23

RP8 56_0404_4P2R_5%

DDR_A_MA4

14

DDR_A_MA2

23

RP10 56_0404_4P2R_5%

DDR_A_MA0

14

DDR_A_BS1

23

RP12 56_0404_4P2R_5%

14

DDR_A_MA13

23

RP13 56_0404_4P2R_5%

DDR_CKE1_DIMMA

14

DDR_A_MA14

23

0.1U_0402_16V4Z

C162

1

2

0.1U_0402_16V4Z

1

1

2

2

C172

C173

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C164

C163

1

2

0.1U_0402_16V4Z

1

2

C174

1

@

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C175

C165

1

+

C156
220U_6.3V_M

@

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C176

C177

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C443

C444

1

1

2

2

1

2

C178

Security Clas sification

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_CKE0_DIMMA7

DDR_CS1_DIMMA#7

Issued Date

3

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D9 DDR_A_D11

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_DM3

DDR_CKE0_DIMMA

DDR_A_BS28

DDR_A_BS08
DDR_A_WE#8

DDR_A_CAS#8

M_ODT17

CLK_SMBDATA14,15

CLK_SMBCLK14,15

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_DM5

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_DM7

CLK_SMBDATA

+3VS

2007/03/26 2006/03/10

3

+1.8V

JP4

1
3
5
7

9
11
13
15
17
19
21

DDR_A_D14

DDR_A_D15 DDR_A_D10

DDR_A_D16
DDR_A_D17

DDR_A_D18
DDR_A_D19

DDR_A_D26
DDR_A_D27

DDR_A_D37
DDR_A_D36

DDR_A_D35
DDR_A_D32

DDR_A_D40
DDR_A_D44

DDR_A_D41
DDR_A_D46

DDR_A_D49
DDR_A_D48

DDR_A_D50
DDR_A_D61 DDR_A_D57

DDR_A_D60

DDR_A_D59
DDR_A_D58

CLK_SMBCLK

1

C179

2

2.2U_0805_16V4Z

23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

1

C180

FOX_ASOA426-M4R-TR

CONN@

2

SO-DIMM A

SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4
FOX_AS0A426-M4R-TR_200P

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

DQS3#

NC/CKE1

NC/A15
NC/A14

NC/A13

DQS5#

DQS7#

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3
DQ30

DQ31

RAS#

ODT0

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5
DQ46

DQ47
DQ52

DQ53

DQ54
DQ55

DQ60
DQ61

DQS7
DQ62

DQ63

2

+1.8V

V_DDR_MCH_REF

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

CK0#

VSS

VSS

VSS

VSS

NC
DM2
VSS

VSS

VSS

VSS

VSS
VDD

VDD

A11

VDD

VDD
BA1

S0#
VDD

VDD

NC
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

CK1#

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

GND

2

DDR_A_D6

4

DDR_A_D0

6
8

DDR_A_DM0

10
12

DDR_A_D5

14

DDR_A_D7

16
18

DDR_A_D13

20

DDR_A_D12

22
24

DDR_A_DM1

26
28

M_CLK_DDR0

30

M_CLK_DDR#0

32
34
36
38
40

42

DDR_A_D20

44

DDR_A_D21

46
48
50

DDR_A_DM2

52
54

DDR_A_D23

56

DDR_A_D22

58
60

DDR_A_D28DDR_A_D29

62

DDR_A_D25DDR_A_D24

64
66

DDR_A_DQS#3

68

DDR_A_DQS3

70
72

DDR_A_D31

74

DDR_A_D30

76
78

DDR_CKE1_DIMMA

80
82
84

DDR_A_MA14

86
88

DDR_A_MA11

90
92

A7

DDR_A_MA6

94

A6

96

DDR_A_MA4

98

A4

DDR_A_MA2

100

A2

DDR_A_MA0

102

A0

104

DDR_A_BS1

106

DDR_A_RAS#

108

DDR_CS0_DIMMA#

110
112

M_ODT0

114

DDR_A_MA13

116
118
120
122

DDR_A_D39

124

DDR_A_D38

126
128

DDR_A_DM4

130
132

DDR_A_D34

134

DDR_A_D33

136
138

DDR_A_D45

140

DDR_A_D43

142
144

DDR_A_DQS#5

146

DDR_A_DQS5

148
150

DDR_A_D47

152

DDR_A_D42

154
156

DDR_A_D52

158

DDR_A_D53

160
162

M_CLK_DDR1

164

M_CLK_DDR#1

166
168

DDR_A_DM6

170
172

DDR_A_D51DDR_A_D54

174

DDR_A_D55

176
178
180

DDR_A_D56

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198
200
204

12

R84

R83

10K_0402_5%

10K_0402_5%

2.2U_0805_16V4Z
C154

1

2

M_CLK_DDR0 7
M_CLK_DDR#0 7

PM_EXTTS#0 7

DDR_CKE1_DIMMA 7

DDR_A_BS1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7

M_ODT0 7

M_CLK_DDR1 7
M_CLK_DDR#1 7

12

Compal Electronics, Inc.

Title

DDRII-SODIMM SLOT1

Size Document Number Rev

Custom

LA-3981P

Date: Sheet of

0.1U_0402_16V4Z
C155

1

2

1

V_DDR_MCH_REF 7,14,35

13 42Monday, October 22, 2007

1

0.3

5

DDR_B_DQS#[0..7]8

DDR_B_D[0..63]8

DDR_B_DM[0..7]8
DDR_B_DQS[0..7]8
DDR_B_MA[0..14]7,8

D D

Layout Note:
Place near JP10

+1.8V

2.2U_0805_16V4Z

C C

B B

A A

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_B_MA1
DDR_B_MA3

DDR_B_BS0
DDR_B_MA10

DDR_B_MA0
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_B_WE#

DDR_CS3_DIMMB# M_ODT2
M_ODT3

DDR_CKE3_DIMMB

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C183

C184

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

1

2

2

2

C194

C193

C192

RP14

1 4
2 3

RP16

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP18

1 4
2 3

RP20

56_0404_4P2R_5%

1 4
2 3

56_0404_4P2R_5%

RP22

1 4
2 3

RP24

56_0404_4P2R_5%

2 3
1 4

56_0404_4P2R_5%

1 2

R88

56_0402_5%

5

C185

1

2

0.1U_0402_16V4Z

1

2

C195

+0.9V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C186

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C196

RP15 56_0404_ 4P2R_5%

RP17 56_0404_ 4P2R_5%

RP19 56_0404_ 4P2R_5%

RP21 56_0404_ 4P2R_5%

RP23 56_0404_ 4P2R_5%

RP25 56_0404_ 4P2R_5%

RP26

56_0404_4P2R_5%

0.1U_0402_16V4Z

C187

1

2

0.1U_0402_16V4Z

1

2

C197

DDR_B_MA9

14

DDR_B_MA12

23

DDR_B_MA14

14

DDR_B_MA11

23

DDR_B_MA5

14

DDR_B_MA8

23

DDR_B_MA7

14

DDR_B_MA6

23

DDR_B_MA4

14

DDR_B_MA2

23

14

DDR_B_MA13

23

DDR_B_BS2

14

DDR_CKE2_DIMMB

23

0.1U_0402_16V4Z

C188

C189

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C198

C199

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C200

4

0.1U_0402_16V4Z
C191

C190

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C201

C202

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

4

3

DDR_CKE2_DIMMB7

DDR_B_BS28

DDR_B_BS08

0.1U_0402_16V4Z

1

1

2

2

C204

C203

DDR_B_WE#8

DDR_B_CAS#8

DDR_CS3_DIMMB#7

M_ODT37

CLK_SMBDATA13,15

CLK_SMBCLK13,15

+3VS

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

+1.8V

JP5

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D51
DDR_B_D50

DDR_B_D56
DDR_B_D61 DDR_B_D57

DDR_B_DM7

DDR_B_D59
DDR_B_D58

CLK_SMBDATA

CLK_SMBCLK

1

C206

C205

2

2.2U_0805_16V4Z

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

1

FOX_AS0A426-N8RN-7F

CONN@

2

SO-DIMM B

SP07000BZ00 S SOCKET FOXCON AS0A426-N8RN-7F H8 DDR2R
FOX_AS0A426-N8RN-7F_200P

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

2

+1.8V

V_DDR_MCH_REF

2

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS

CK0

CK0#

VSS

VSS

VSS

VSS

NC
DM2
VSS

VSS

VSS

VSS

VSS
VDD

VDD

A11

VDD

VDD

BA1
S0#

VDD

VDD

NC
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS

CK1

CK1#

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SA0
SA1

GND

DDR_B_D5

4

DDR_B_D4

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D7

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28

M_CLK_DDR3

30

M_CLK_DDR#3

32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D21DDR_B_D17

44

DDR_B_D16

46
48
50

DDR_B_DM2

52
54

DDR_B_D22

56

DDR_B_D23

58
60

DDR_B_D26

62

DDR_B_D24DDR_B_D25

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D29

74

DDR_B_D27

76
78

DDR_CKE3_DIMMB

80
82
84

DDR_B_MA14

86
88

DDR_B_MA11

90

DDR_B_MA7

92

A7

DDR_B_MA6

94

A6

96

DDR_B_MA4

98

A4

DDR_B_MA2

100

A2

DDR_B_MA0

102

A0

104

DDR_B_BS1

106

DDR_B_RAS#

108

DDR_CS2_DIMMB#

110
112

M_ODT2

114

DDR_B_MA13

116
118
120
122

DDR_B_D36

124

DDR_B_D37

126
128

DDR_B_DM4

130
132

DDR_B_D39

134

DDR_B_D38

136
138

DDR_B_D44

140

DDR_B_D45

142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D46

152

DDR_B_D47

154
156

DDR_B_D52

158

DDR_B_D53

160
162

M_CLK_DDR2

164

M_CLK_DDR#2

166
168

DDR_B_DM6

170
172

DDR_B_D54

174

DDR_B_D55

176
178

DDR_B_D60

180
182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198
200
202

2

10K_0402_5%

2.2U_0805_16V4Z

1

C181

2

M_CLK_DDR3 7
M_CLK_DDR#3 7

PM_EXTTS#1 7

DDR_CKE3_DIMMB 7

DDR_B_BS1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7

M_ODT2 7

M_CLK_DDR2 7
M_CLK_DDR#2 7

R86

1 2

12

10K_0402_5%

R87

Date: Sheet of

+3VS

Compal Electronics, Inc.

Title

DDRII-SODIMM SLOT2

Size Document Number Rev

0.1U_0402_16V4Z

1

2

LA-3981P

C182

1

V_DDR_MCH_REF 7,13,35

14 42Monday, October 22, 2007

1

0.3

5

PCI

SRC

CPU

CLKSEL1

FSLA

CLKSEL0

MHz

MHz

MHz

FSLC FSLB

CLKSEL2

0 1 1000 133 33.3

0

1 200

CPU Driven

(Default)

*

667MHz

1

Stuff

No Stuff

Stuff

No Stuff

FSB Frequency Selet:

D D

Stuff

800MHz

No Stuff

1019_Change CLRP1 and CLRP2 type like the same as PJP4.

C C

CPU_BSEL05

CPU_BSEL15

B B

CPU_BSEL25

+3VS +3VS +3VS

A A

R97

2.2K_0402_5%

FSA

CLRP2

2 1

PAD-OPEN 2x2m

FSB

1 2

R115

0_0402_5%

R124

10K_0402_5%

FSC

1 2

R126

0_0402_5%

R134
10K_0402_5%

1 2

ITP_EN 27_SEL PCI2_TME

R138
10K_0402_5%

@

1 2

R135
10K_0402_5%

@

1 2

R139
10K_0402_5%

1 2

100

33.30

100

1661

33.30

R1107 R1135 R1083

R1074 R1086 R1098 R1113 R1139

R1139 R1135R1135 R1139

R1083

R1107

R1128

R1098

R1113

R1128

R1074R1086

R1135 R1139

R1086

R1098

R1128

R1113

+VCCP

CLRP4,CLRP5 for 667/800 FSB select
SHORT CLRP5, NO SHORT CLRP4 -- CPU option
SHORT CLRP4, NO SHORT CLRP5 -- FSB 667

MCH_CLKSEL0 7

CLK_DEBUG_PORT_L22,29

MCH_CLKSEL1 7

MCH_CLKSEL2 7

PJP9

SHORT PAD

CLK_14M_DEBUG30

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
For 27_SEL, 0 = Enable DOT96 & SRC1,

1= Enable SRC0 & 27MHz

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed

12

12

5

+VCCP

+VCCP

R1083
R1074

2 1

12

1 2

12

1 2

12

R1107

CLK_LPC_DEBUG30

R93

1 2

56_0402_5%
CLRP1
PAD-OPEN 2x2m

1 2

R98

1K_0402_5%

R102
1K_0402_5%@

R111
1K_0402_5%@

1 2

R114

1K_0402_5%

R116

@

0_0402_5%

R121
1K_0402_5%@

1 2

R125

1K_0402_5%

R129

@

0_0402_5%

R136
10K_0402_5%

1 2

R140
10K_0402_5%

@

1 2

CLK_48M_ICH20

CLK_14M_ICH20

4

+3VS

FBMA-L11-201209-221LMA30T_0805

R412

@

1 2

0_0402_5%

CLKSATAREQ#20

CLKREQ#_B7

12

CLK_PCI_LAN23
CLK_PCI_EC30
CLK_PCI_ICH18

Routing the trace at
least 10mil

18P_0402_50V8J

1

2

4

R89

1 2

PCI2_TMECLK_LPC_DEBUG

14.31818MHZ_16P

2

C230

1

1 2

1 2
1 2

CLK_DEBUG_PORT

C441
39P_0402_50V8J

+3VS_CK505

+1.25VS_CK505

1 2
1 2
1 2
1 2
1 2
1 2

Y1

12

1

C207
10U_0805_10V4Z

2

FBMA-L11-201209-221LMA30T_0805

+3VS_CK505

R1034 75_0402_1%
R1044 75_0402_1%
R1053 9_0402_5%
R1063 9_0402_5%
R1073 9_0402_5%
R1093 9_0402_5%

CLK_XTAL_IN

CLK_XTAL_OUT

2

C231
18P_0402_50V8J

1

R11739_0402_5%

R12033_0402_1%
R40033_0402_1% @

+1.25VS_CK505

3

Place close to U4

1

C216

2

680P_0402_50V7K

NC

SCLK

SDATA

PCI_STOP#

CPU0

CPU0#

CPU1_F

CPU1#_F

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

SRC2/SATA

1

C211
680P_0402_50V7K

2

10U_0805_10V4Z

1

C217

2

48

CLK_SMBCLK

64

CLK_SMBDATA

63
38

37

R_CPU_BCLK

54

R_CPU_BCLK#

53

R_MCH_BCLK

51

R_MCH_BCLK#

50

47
46

35
34

33
32

30
31

44

R_CLKREQ#_G

43

R_CLK_PCIE_MCard

41

R_CLK_PCIE_MCard#

40

R_MCH_3GPLL

27

R_MCH_3GPLL#

28

R_PCIE_ICH

24

R_PCIE_ICH#

25

R_PCIE_SATA

21

R_PCIE_SATA#

22

SSCDREFCLK

17

SSCDREFCLK#

18

R_MCH_DREFCLK

13

R_MCH_DREFCLK#

14

56

Compal Secret Data

Deciphered Date

1

2

0.1U_0402_16V4Z

1

C218

2

680P_0402_50V7K

R94

1 2
1 2

R95
R96

1 2
1 2

R99

For Layout request:

1. Change MINI_CLKREQ# from pin 32 to pin 43.

2. Change CLK_PCIE_MCARD from SRC9 to SRC6.

R112

1 2
1 2

R113
R118

1 2
1 2

R119
R122

1 2
1 2

R123
R127

1 2
1 2

R128

R130 0_0402_5%

1 2

R131 0_0402_5%

1 2

R132

1 2
1 2

R133

1 2

R137 0_0402_5%@

1 2

R367 0_0402_5%@

1 2

R344 0_0402_5%

PCI_CLK1
PCI2_TMECLK_DEBUG_PORT

PCI_LANCLK

27_SEL
ITP_EN

FSA

FSB

FSC

1

C208

0.1U_0402_16V4Z

2

+1.25VS

1

2

R92

1 2

C214
10U_0805_10V4Z

U4

2

VDD_PCI

9

VDD48

16

VDDPLL3

61

VDDREF

39

VDDSRC

55

VDDCPU

12

VDD96_IO

20

VDDPLL3_IO

26

VDDSRC_IO

36

VDDSRC_IO

49

VDDCPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/27_Select

7

PCIF5/ITP_EN

60

X1

59

X2

10

USB_48MHZ/FSLA

57

FSLB/TEST MODE

62

REF0/FSLC/TEST_SEL

45

VDDSRC_IO

42

GNDSRC

8

GNDPCI

11

GND48

15

GND

19

GND

52

GNDCPU

23

GNDSRC

29

GNDSRC

58

GNDREF

* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

0.1U_0402_16V4Z

1

C215

2

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

ICS9LPRS355_TSSOP64

C210

0.1U_0402_16V4Z

2

1

2

CPU_STOP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2#/SATA#

SRC0/DOT96

SRC0/DOT96#

CK_PWRGD/PD#

C209
680P_0402_50V7K

2007/03/26 2006/03/10

3

2

C212

0.1U_0402_16V4Z

+1.25VS_CK505

1

C219

2

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

R108 475_0402_1%

12

R110 10K_ 0402_5%

1 2

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%
0_0402_5%

2

1

C213

0.1U_0402_16V4Z

2

0_0402_5%
0_0402_5%

+3VS

R90

2.2K_0402_5%

Q3

D

S

2N7002_SOT23-3

ICH_SMBDATA20,22

SB, MINI PCI

ICH_SMBCLK20,22

CLK_SMBCLK 13,14
CLK_SMBDATA 13,14

H_STP_PCI# 20
H_STP_CPU# 20

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7

MINI_CLKREQ# 22

+3VS

CLK_PCIE_MCARD 22
CLK_PCIE_MCARD# 22

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_ICH 20

CLK_PCIE_ICH# 20

CLK_PCIE_SATA 19
CLK_PCIE_SATA# 19

MCH_SSCDREFCLK 7

MCH_SSCDREFCLK# 7

CLK_MCH_DREFCLK 7
CLK_MCH_DREFCLK# 7

VGATE 20,37

CLK_ENABLE 30
CK_PWRGD 20

Title

Size Document Number Rev

Date: Sheet of

1 3

G

2

+3VS

2

G

Q4
2N7002_SOT23-3

1 3

D

S

C220
C221
C222
C225
C227
C229

Compal Electronics, Inc.

Clock generator

LA-3981P

1

1

R91

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

CLK_48M_ICH

12

5P_0402_50V8C@

CLK_14M_ICH

12

4.7P_0402_50V8C@

CLK_PCI_ICH

12

4.7P_0402_50V8C@

CLK_PCI_EC

12

4.7P_0402_50V8C@

CLK_PCI_LAN

12

4.7P_0402_50V8C@

CLK_DEBUG_PORT

12

5P_0402_50V8C@

15 42Monday, October 22, 2007

0.3

A

B

C

D

E

1 1

2 2

R146

CRT_HSYNC9

CRT_VSYNC9

3 3

4 4

1 2

R151

1 2

0.1U_0402_16V4Z

0_0402_5%

0_0402_5%

A

C239

1 2

CRTVSYNC

CRTL_B
CRTL_G

CRTL_R

CRT_R9

CRT_G9

CRT_B9

TV_COMPS9

+R_CRT_VCC , + C RTVDD (40mils)

D4

D5

1

DAN217_SC59

@

2

3

D6

1

1

DAN217_SC59@

+CRTVDD

2

3

Place close to JP6

CRT CONNECTOR

DAN217_SC59

@

2

3

1019_Change bead type for meet EMI request.

L2

R143

1 2

75_0402_5%

C245

270P_0402_50V7K

FBMA-L10-201209-121LMT_0805

1 2

L3
FBMA-L10-201209-121LMT_0805

1 2

L4
FBMA-L10-201209-121LMT_0805

1 2

1

2

C235

10P_0402_50V8J

TV-Out Connector
S-Video

L7

MBC1608121YZF_0603

1 2

L8

MBC1608121YZF_0603

1 2

L9

MBC1608121YZF_0603

1 2

1

C246

2

1

2

270P_0402_50V7K

R158

1 2

0_0805_5%

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CRT_R

CRT_G

CRT_B

+5VS

5

1

U5

P

4

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

5

1

U6

P

4

OE#

A2Y

G

74AHCT1G125GW_SOT353-5

3

R152

TV_LUMA9

TV_CRMA9

1 2

R153

1 2

R154

1 2

0_0402_5%

0_0402_5%

0_0402_5%

1

2

R141

1 2

75_0402_5%

C233

10P_0402_50V8J

CRT_HSYNC_R

CRT_VSYNC_R

TVLUMA

TVCRMA

TVCOMPS

12

R155

R156

75_0402_5%

B

12

75_0402_5%

1

2

R142

1 2

75_0402_5%

C234

10P_0402_50V8J

12

1

R157

C244

2

75_0402_5%

270P_0402_50V7K

+5VS

RB411D_SOT23

1

1

2

2

C237

10P_0402_50V8J

C236

10P_0402_50V8J

1 2

L5
FBM-L11-160808-800LMT_0603

1 2

L6
FBM-L11-160808-800LMT_0603

TVGND

2007/03/26 2006/07/26

C

+R_CRT_VCC

D7

2 1

1

2

C238

10P_0402_50V8J

CRT_HSYNCRFLCRTHSYNC

CRT_VSYNCRFL

LUMA_CL

CRMA_CL

COMPS_CL

1

C247

2

330P_0402_50V7K

F1

1.1A_6VDC_FUSE

0.1U_0402_16V4Z

CRTL_R

CRTL_G

CRTL_B

1

C248

2

330P_0402_50V7K

Compal Secret Data

C232

C240

10P_0402_50V8J

21

1

2

R144 4.7K_0402_5%

1

1

2

2

1

C249

2

330P_0402_50V7K

Deciphered Date

+CRTVDD

CONN@

+CRTVDD

SUYIN_070546FR015S200ZR

R145 4.7K_0402_5%

C241 10P_0402_50V8J

D

1 3

G

2

D

1

2

C242 220P_0402_50V8J

1
2
3
4
5
6
7

DC230001300 CONN SUYIN 030107FR007G317ZR 7P S_VIDEO
SUYIN_030107FR007G317ZR_7P

1 3

1

2

C243 220P_0402_50V8J

JP7

1
2
3
4
5

8

6

GND

9

7

GND

SUYIN_030107FR007G317ZR

CONN@

D

JP6

6

11

1
7

12

2
8

13

3
9

14

16

4

17
10
15

5

Q5

S

3V_DDCDA

2N7002_SOT23-3

Q6

S

3V_DDCCL

2N7002_SOT23-3

R150

R149

G

2

2.2K_0402_5%

2.2K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

NZQA5V6AXV5T1_SOT533-5

2

1 5

D3

@

CLOSE TO JP3

R147

+3VS

1 2

R148

1 2

0_0402_5%

0_0402_5%

3VDDCDA 9

3VDDCCL 9

Compal Electronics, Inc.

CRT & TVout Connector

LA-3981P

E

43

16 42Monday, October 22, 2007

0.3

5

+5VALW

J2 JOPEN

1 2

J3 JOPEN

1 2

+5VS

@

Q35

D D

WEBCAM_ON/OFF#30

C C

SI2301BDS-T1-E3_SOT23-3

S

D

13

G

2

+5V_WEBCAM

4

LVDS CONN

INVPWR_B+

+LCDVDD

+3VS

C252680P_0402_50V7K

12

3

0.1U_0402_16V4Z

JP8

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

GND41GND

ACES_88242-4001

CONN@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

+LCDVDD

C250

1

1

C251

0.1U_0402_16V4Z

2

2

LVDSA2+
LVDSA2-

LVDSA1+
LVDSA1-

LVDSA0+
LVDSA0-

LVDSAC+
LVDSAC-

INVTPWM
DISPLAYOFF#
DAC_BRIG

LCD_CLK
LCD_DAT
USB20_R_P6
USB20_R_N6

680P_0402_50V7K

LVDSA2+ 9
LVDSA2- 9
LVDSA1+ 9

LVDSA1- 9
LVDSA0+ 9

LVDSA0- 9

LVDSAC+ 9
LVDSAC- 9

1

1

C255

C256
680P_0402_50V7K

2

2

INVPWR_B+B+

@

L10 0_ 0805_5%

1 2

L11

1 2

FBMA-L11-201209-221LMA30T_0805

1

+5V_WEBCAM

LVDSBC+9
LVDSBC-9

LVDSB0+9
LVDSB0-9

LVDSB1+9

C254

C253680P_0402_50V7K

LVDSB1-9
LVDSB2+9

LVDSB2-9

1

12

2

680P_0402_50V7K

3
5
7

9
11
13
15

LVDSBC+

17

LVDSBC-

19
21

LVDSB0+

23

LVDSB0-

25
27

LVDSB1+

29

LVDSB1-

31
33

LVDSB2+

35

LVDSB2-

37
39

LVDS connector

SP02000EA00 S W-CONN ACES 88242-4001 40P P1
ACES_88242-4001_40P

2

INV_PWM 30
DAC_BRIG 30

LCD_CLK 9

LCD_DATA 9

WCM-2012-900T_4P

443

1

1

L23

1

+3VS

R159

R160

2.2K_0402_5%

2.2K_0402_5%

1 2

1 2

LCD_CLK

LCD_DATA

3

USB20_P6 20

2

2

USB20_N6 20

100_0402_5%

2N7002_SOT23-3

C260

R161

1

2

Q8

+LCDVDD

12

13

D

2

G

S

2N7002_SOT23-3

+5VALW

R163
47K_0402_5%

1 2

13

D

2

G

Q9

4

C259

0.047U_0402_16V7K

S

1

2

Q7

SI2301BDS-T1-E3_SOT23-3

1 3

D

G

2

C257

4.7U_0805_10V4Z

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS+LCDVDD

S

BKOFF#30

4.7U_0805_10V4Z

2

2007/03/26 2006/07/26

3

Compal Secret Data

Deciphered Date

1

C258

ENABLT9

2

R164

1 2

Date: Sheet of

+3VS

R162

4.7K_0402_5%

D8

CH751H-40PT_SOD323-2
D9

CH751H-40PT_SOD323-2
100K_0402_5%

Title

Size Document Number Rev

1 2

21

21

DISPLAYOFF#

Compal Electronics, Inc.

LCD CONN.

LA-3981P

1

17 42Monday, October 22, 2007

0.3

B B

R298

ENAVDD9

100K_0402_5%

A A

Avoid Panel display garbage after power on.

5

1 2

100K_0402_5%

12

0.22U_0402_10V4Z

R308

5

4

3

2

1

+3VS

1 2

R166 8.2K _0402_5%

1 2

R167 8.2K _0402_5%

1 2

R168 8.2K _0402_5%

D D

C C

1 2

R169 8.2K _0402_5%

1 2

R170 8.2K _0402_5%

1 2

R171 8.2K _0402_5%

1 2

R172 8.2K _0402_5%

1 2

R173 8.2K _0402_5%

+3VS

1 2

R175 8.2K _0402_5%

1 2

R176 8.2K _0402_5%

1 2

R177 8.2K _0402_5%

1 2

R179 8.2K _0402_5%

1 2

R180 8.2K _0402_5%

1 2

R181 8.2K _0402_5%

1 2

R182 8.2K _0402_5%
R183 8.2K _0402_5%

1 2

R184 8.2K _0402_5%

1 2

R185 8.2K _0402_5%

1 2

R187 8.2K _0402_5%

1 2

R188 8.2K _0402_5%

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#

PCI_IRDY#
PCI_SERR#
PCI_PERR#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#

PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

12

PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#

PCI_AD[0..31]23

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8

PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15 PCI_PAR
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

U7B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10

PIRQD#

ICH8M REV 1.0

PCI

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PCIRST#
DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI_REQ0#

A4

PCI_GNT0#

D7

PCI_REQ1#

E18
C18

PCI_REQ2#

B19
F18

PCI_REQ3#

A11

PCI_GNT3#

C10

PCI_CBE#0

C17

PCI_CBE#1

E15

PCI_CBE#2

F16

PCI_CBE#3

E17

PCI_IRDY#

C8
D9

PAR

PCI_PCIRST#

G6

PCI_DEVSEL#

D16

PCI_PERR#

A7

PCI_PLOCK#

B7

PCI_SERR#

F10

PCI_STOP#

C16

PCI_TRDY#

C9

PCI_FRAME#

A17

PCI_PLTRST#

AG24

CLK_PCI_ICH

B10

PCI_PME#

G7

F8
G11
F12
B3

PCI_REQ0# 23
PCI_GNT0# 23

T23

PCI_CBE#0 23
PCI_CBE#1 23
PCI_CBE#2 23
PCI_CBE#3 23

PCI_IRDY# 23

PCI_PAR 23
PCI_DEVSEL# 23

PCI_PERR# 23

PCI_STOP# 23
PCI_TRDY# 23
PCI_FRAME# 23

CLK_PCI_ICH 15
PCI_PME# 23,30

PCI_PIRQE#
PCI_PIRQF# CLK_PCI _ICH
PCI_PIRQG#
PCI_PIRQH#

Place closely pin B10

R186

10_0402_5%

C261

10P_0402_50V8J

R174
0_0402_5%

R178
0_0402_5%

PCI_RST#

12

PLT_RST#

12

1 2
1

2

PCI_GNT0#

12

R165

@

1K_0402_5%

PCI_RST# 23,29,30

PCI_SERR# 23,30

PLT_RST# 7,2 2

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

1

0

1

Boot BIOS Location

SPI1

PCI

LPC

*

A16 swap override Strap

Low= A16 swap override Enble

R419 0_0402_5%

PCI_PIRQA#

1 2

PCI_PIRQF#

1 2

R420 0_0402_5%@

B B

PCI_PIRQ# 23

PCI_GNT3# High= Default

*

A A

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

2

Date: Sheet of

ICH8(1/4)-PCI/INT

LA-3981P

1

18 42Monday, October 22, 2007

0.3

5

+RTCVCC

R189 330K_0402_1%

LAN100_SLP

1 2

R191 1M_0402_5%

SM_INTRUDER#

1 2

R193 330K_0402_1%

ICH_INTVRMEN

1 2

D D

15P_0402_50V8J

C C

B B

A A

R197

1 2

10M_0402_5%

2

C262

1

Y2

1

4

IN

OUT

NC3NC

2

1 2

R195

@

0_0402_5%

1 2

ICH_RTCX1

ICH_RTCX2

2

C263
15P_0402_50V8J

1

0925_Change C262 and C263 from 12pF to 15pF.

32.768KHZ_12.5P_Q13MC30610018

ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

R192

@

0_0402_5%

ICH8M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

4

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

High = Internal VR Enabled(Default)

R199

1 2

+RTCVCC

20K_0402_5%

C264

1U_0603_10V4Z

+1.5VS

ACZ_BITCLK24

ACZ_SYNC24

ACZ_RST#24,30

ACZ_SDIN024

ACZ_SDOUT24

SATA_LED#28

SATA_RXN0_C22
SATA_RXP0_C22

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0

SATA_TXN022

SATA_TXP0

SATA_TXP022

CLRP3

2

SHORT PADS

1 2

1

R202 24.9_0 402_1%

1 2

R203 47_ 0402_5%
R205 33_ 0402_5%

R206 33_ 0402_5%

R208 33_ 0402_5%

CLK_PCIE_SATA#15
CLK_PCIE_SATA15

SATA_LED#

1 2
1 2

1 2

1 2

3900P_0402_50V7K

C265

1 2

C266

1 2

3900P_0402_50V7K

CLK_PCIE_SATA#
CLK_PCIE_SATA

1 2

27.4_0402_1%

Within 500 mils

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
SM_INTRUDER#
ICH_INTVRMEN

LAN100_SLP

GLAN_COMP

HDA_BITCLK
HDA_SYNC

HDARST#
ACZ_SDIN0

HDA_SDOUT

SATA_TXN0_C
SATA_TXP0_C

R211

3

U7A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

CPUPWRGD/GPIO49

THRMTRIP#

IHDA

IDE

SATA

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

RCIN#

STPCLK#

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

2

T25 PAD

W=20mils

2

C267
1U_0603_10V4Z

1

LPC_AD[0..3] 22,29,30

LPC_FRAME# 22,29,30
LPC_DRQ#0 30

GATEA20 30
H_A20M# 4

12

R201 0_0402_5%

H_DPSLP# 5

H_FERR# 4
H_PWRGOOD 5
H_IGNNE# 4
H_INIT# 4

H_INTR 4

KB_RST# 30

H_NMI 4
H_SMI# 4

H_STPCLK# 4

1 2

IDE_HDD[0..15] 22

IDE_HDA0 22
IDE_HDA1 22
IDE_HDA2 22

IDE_HDCS1# 22
IDE_HDCS3# 22

IDE_HDIOR# 22

IDE_HDIOW# 22

IDE_HDACK# 22

IDE_HIRQ 22
IDE_HIORDY 22
IDE_HDREQ 22

W=20mils

R212

1 2

0_0402_5%

H_DPRSTP#H_DPRSTP_R#

R207 24_0402_1%

1

DAN202U_SC70

D10

2
3

H_DPRSTP# 5,7,37

+VCCP

placed within 2" from ICH8M

IDE_HIORDY
IDE_HIRQ

+3VL

1

C442

4.7U_0603_6.3V6K

2

BATT1.1

R213

1 2

W=20mils

1K_0402_5%

LPC_AD0

E5

LPC_AD1

F5

LPC_AD2

G8

LPC_AD3

F6

LPC_FRAME#

C4

LPC_DRQ0#

G9
E6

GATEA20

AF13

H_A20M#

AG26
AF26

AE26

H_DPSLP#
H_FERR#

AD24

H_PWRGOOD

AG29

H_IGNNE#

AF27

H_INIT#

AE24

INIT#

H_INTR

AC20

INTR

KB_RST#

AH14

H_NMI

AD23

NMI

H_SMI#

AG28

SMI#

H_STPCLK#

AA24

THRMTRIP_ICH#

AE27
AA23

TP8

IDE_HDD0

V1

DD0

IDE_HDD1

U2

DD1

IDE_HDD2

V3

DD2

IDE_HDD3

T1

DD3

IDE_HDD4

V4

DD4

IDE_HDD5

T5

DD5

IDE_HDD6

AB2

DD6

IDE_HDD7

T6

DD7

IDE_HDD8

T3

DD8

IDE_HDD9

R2

DD9

IDE_HDD10

T4

DD10

IDE_HDD11

V6

DD11

IDE_HDD12

V5

DD12

IDE_HDD13

U1

DD13

IDE_HDD14

V2

DD14

IDE_HDD15

U6

DD15

IDE_HDA0

AA4

DA0

IDE_HDA1

AA1

DA1

IDE_HDA2

AB3

DA2

IDE_HDCS1#

Y6

IDE_HDCS3#

Y5

IDE_HDIOR#

W4

IDE_HDIOW#

W3

IDE_HDACK#

Y2

IDE_HIRQ

Y3

IDE_HIORDY

Y1

IDE_HDREQ

W5

+RTCVCC

1

GATEA20

KB_RST#

H_FERR#

H_DPRSTP#

H_DPSLP#

within 2" from R1557

12

R204
56_0402_5%

H_THERMTRIP# 4,7

R209 4.7K_0 402_5%

1 2

R210 8.2K_0 402_5%

1 2

BATT1

ML1220 MAXELL LITHIUM RTC BATTERY

JBATT1

W=20mils

1

+

SUYIN_060003FA002TX00NL~D

R190

10K_0402_5%

R194

10K_0402_5%

R196

56_0402_5%

R198

@

56_0402_5%

R200

@

56_0402_5%

+3VS

12

12

+VCCP

12

12

12

+3VS

2

-

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

ICH8(2/4)_LAN,HD,IDE,LPC

Size Document Number Rev

Custom

LA-3981P

2

Date: Sheet of

19 42Monday, October 22, 2007

1

0.3

5

LINKALERT#

R214 10K_0402_5%

R215 8.2K_0402_5%

R218 1K_0402_5%

R221 10K_0402_5%

R223 10K_0402_5%

R224 10K_0402_5%

R225 10K_0402_5%

+3VS

R228 10 K_0402_5%

R230 10 K_0402_5%

R231 8.2 K_0402_5%@

R232 8.2 K_0402_5%

R235 8.2 K_0402_5%@

R394 8.2 K_0402_5%

+3VS

R236 10 K_0402_5%@

R237 10 K_0402_5%@

R239 10 K_0402_5%

R241 10 K_0402_5%

R242 8.2 K_0402_5%

R244 8.2 K_0402_5%

1 2

+3VS

R248 1 0K_0402_5%@

1 2

ICH_LOW_BAT#

12

ICH_PCIE_ WAKE#

1 2

ICH_RI#

1 2

XDP_DBRESET# PM_PWROK

1 2

ME_EC_DATA1

12

ME_EC_CLK1

12

GPIO38

1 2

GPIO39

1 2

GPIO18

1 2

GPIO22

1 2

GPIO20

1 2

CLKRUN#

1 2

OCP#

1 2

MCH_ICH_SYNC#

1 2

SIRQ

1 2

CLKSATAREQ#

1 2

IDE_RESET#

1 2

PM_BMBUSY# ICH_RSVD

1 2

SB_SPKR

low-->default
High -->No boot

+3VS

R226

@

@

10K_0402_5%

10K_0402_5%

1 2

H_STP_PCI#15
H_STP_CPU#15

1 2

R395 100K_0402_5%

+3VALW

D D

C C

WLAN

B B

USB_OC#3

1 2

R392 10 K_0402_5%

USB_OC#4

1 2

R385 10 K_0402_5%

USB_OC#5

1 2

R386 10 K_0402_5%

USB_OC#6

1 2

R387 10 K_0402_5%

USB_OC#7

1 2

R388 10 K_0402_5%

1 2

R389 10 K_0402_5%

USB_OC#9

1 2

R390 10 K_0402_5%

USB_OC#2

1 2

A A

R391 10 K_0402_5%

USB_OC#0

5

1 2

R380 10K_ 0402_5%

1 2

R381 0_0 402_5%

+3VALW

USB_OC#1

ICH_SMBCLK15,22
ICH_SMBDATA15,22

R227

R229 0_0 402_5%

12

PCIE_RXN122

PCIE_RXP122
PCIE_TXN122

PCIE_TXP122

4

2.2K_0402_5%

XDP_DBRESET#4
PM_BMBUSY#7

EC_LID_OUT#30

ICH_PCIE_ W AKE#22

THERM_SCI#30

EC_SMI#30
EC_SCI#30

CLKSATAREQ#15

IDE_RESET#22

MCH_ICH_SYNC#7

4

P27
P26
N29
N28

M27
M26
L29
L28

K27
K26
J29
J28

H27
H26
G29
G28

F27
F26
E29
E28

D27
D26
C29
C28

C23
B23
E22

D23
F21

AJ19
AG16
AG15
AE15
AF15
AG17
AD12

AJ18
AD14
AH18

Issued Date

U7D

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

3

AJ12

SATA0GP/GPIO21

AJ10

SATA1GP/GPIO19

AF11

SATA2GP/GPIO36

SATA

GPIO

SMB

Clocks

GPIO

SYS

Power MGTController Link

GPIO

ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

MISC

PCI-Express

SPI

USB

3

DMI_IRCOMP

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

DMI_ZCOMP

Direct Media Interface

USBRBIAS#

AG11

SATA3GP/GPIO37

BATLOW#
PWRBTN#
LAN_RST#
RSMRST#

CK_PWRGD

CLPWROK

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

MEM_LED/GPIO24

WOL_EN/GPIO9

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

USBP0N

USBP0P

USBP1N

USBP1P

USBP2N

USBP2P

USBP3N

USBP3P

USBP4N

USBP4P

USBP5N

USBP5P

USBP6N

USBP6P

USBP7N

USBP7P

USBP8N

USBP8P

USBP9N

USBP9P

USBRBIAS

2007/03/26 2006/03/10

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_RST#

AG9
G5

D3
AG23

AF21
AD18

AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23

AE18
F22

AF19
D24

AH23
AJ23
AJ27

AJ24
AF22
AG19

DMI_RXN0

V27

DMI_RXP0

V26

DMI_TXN0

U29

DMI_TXP0

U28

DMI_RXN1

Y27

DMI_RXP1

Y26

DMI_TXN1

W29

DMI_TXP1

W28

DMI_RXN2

AB26

DMI_RXP2

AB25

DMI_TXN2

AA29

DMI_TXP2

AA28

DMI_RXN3

AD27

DMI_RXP3

AD26

DMI_TXN3

AC29

DMI_TXP3

AC28

CLK_PCIE_ICH#

T26

CLK_PCIE_ICH

T25
Y23

Y24
G3

G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

Within 500 mils

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

S4_STATE#
PM_PWROK

ICH_LOW_BAT#
PWRBTN_O UT#

R233 10K_0402_5%

EC_RMRST#
CK_PWRGD

M_PWROK
PM_SLP_M#
CL_CLK0

CL_DATA0

CL_VREF0_ICH
CL_VREF1_ICH

WL_OFF#

R24510K_0402_5%

12

R396
100K_0402_5%

DMI_IRCOMP
USB20_N0

USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USBRBIAS

Compal Secret Data

Deciphered Date

1 2

@

R251 22.6_0402_1%

+3VALW

12

12

R217

R216

2.2K_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1

ICH_RI#
SUS_STAT#

T26PAD

XDP_DBRESET#
PM_BMBUSY#
EC_LID_OUT#
H_STP_PCI#

R_STP_CPU#

12

CLKRUN# DPRSLPVR
ICH_PCIE_ WAKE#

SIRQ

SIRQ30

THERM_SCI#
VGATE

VGATE15,37

SST_CTL

T29PAD

OCP#4

SB_SPKR24

OCP#

EC_SMI#
EC_SCI#

T31PAD

CLKSATAREQ#

IDE_RESET#
SB_SPKR
MCH_ICH_SYNC#

12

R246 1K_0 402_5%@

+3VALW

R250

@

10K_0402_5%

USB_OC#027
USB_OC#227

GPIO18
GPIO20
GPIO22
GPIO27

GPIO38
GPIO39

1 2

AG21

AG12
AG22

AG18

AG10

AG13

C2720.1U_0402_16V4Z

12

C2730.1U_0402_16V4Z

12

T40PAD
T41PAD
T42PAD

T43PAD

U7C

AJ26

SMBCLK

AD19

SMBDATA
LINKALERT#

AC17

SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#

AD15

SYS_RESET#
BMBUSY#/GPIO0
SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15
STP_CPU#/GPIO25

AH11

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ

AC13

THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8

AC19

GPIO12

AG8

TACH0/GPIO17

AH12

GPIO18

AE11

GPIO20
SCLOCK/GPIO22

AH25

QRT_STATE0/GPIO27

AD16

QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39

AD10

SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

SPICLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

USB_OC#0
USB_OC#1USB_OC#8
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9

Security Clas sification

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

T45 PAD
T46 PAD
T47 PAD
T48 PAD

CLK_14M_ICH 15
CLK_48M_ICH 15

T27 P AD

SLP_S3# 30
SLP_S4# 30
SLP_S5# 30

T28 P AD

PM_PWROK 7,30

R398 100K_0402_5%@

PWRBTN_O UT# 30

1 2

1 2

100_0402_5%

CK_PWRGD 15
M_PWROK 7 ,30

T30 P AD

CL_CLK0 7

CL_DATA0 7

CL_RST# 7

WL_OFF# 22

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1 7

DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_PCIE_ICH# 15
CLK_PCIE_ICH 15

R249 24. 9_0402_1%

1 2

USB20_N0 27
USB20_P0 27
USB20_N1 27
USB20_P1 27
USB20_N2 27
USB20_P2 27

USB20_N4 27

USB20_P4 27

USB20_N6 17

USB20_P6 17

1 2

2

DPRSLPVR 7,37

1 2

EC_RSMRST#

R234

+3VALW

Within 500 mils

2

+1.5VS

To USB/B.
To USB/B.
To MB.

R422
10K_0402_5%

1 2

EC_RSMRST# 30

1

C270

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C271

2

To Card Reader/B.
To WEBCAM.

Custom

Date: Sheet of

1

Place closely pin AG9

CLK_14M_ICH

12

R220

10_0402_5%@

1

C269

4.7P_0402_50V8C@

2

R428

EC_RMRST#

1 2

0_0402_5%

R238 3.2 4K_0402_1%

1 2

+3VS

12

R240

453_0402_1%

R243 3.24K_0402_1%

1 2

12

Title

Size Document Number Rev

LA-3981P

+3VALW

R247
453_0402_1%

Compal Electronics, Inc.

ICH8(3/4)_PM,USB,GPIO

ALW_PWRGD 34

20 42Monday, October 22, 2007

1

0.3

5

+RTCVCC

C274

1004_Change R252 from 0603 to 0805 package.

D D

+5VS +3VS

12

R254

100_0402_5%

C284

1U_0603_10V4Z

12

R255

C C

10_0402_5%

+1.5VS

B B

0.1U_0402_16V4Z

A A

MBV2012301YZF_0805

1 2

+1.5VS

21

D11

CH751H-40PT_SOD323-2

20 mils

ICH_V5REF_RUN

1

2

+3VALW+5VALW

21

D12

CH751H-40PT_SOD323-2

ICH_V5REF_SUS

1

C291

0.1U_0402_16V4Z

2

R256

1 2

CHB1608U301_0603

+1.5VS

0.1U_0402_16V4Z

+3VS

1

C307

2

R252

20 mils

1

C296

2

1U_0603_10V4Z

1

C304

2

R257 CHB1608U301_0603

1 2

+1.5VS

5

C278

220U_6.3V_M

C297

C308

40 mils

1

+

2

1

2

+1.5VS

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

1

1

2

2

0.1U_0402_16V4Z

1

C279

2

10U_0805_10V4Z

ICH_VCCSATAPLL

10U_0805_10V4Z

C305

1

C309

2

2.2U_0805_16V4Z

20 mils

C275

0.1U_0402_16V4Z

10U_0805_10V4Z

1

C280

2

+1.5VS

1U_0603_10V4Z

+1.5VS

1U_0603_10V4Z

1

2

T36
T37

ICH_VCCGLANPLL

1 2

+1.5VS

CHB1608U301_0603

4.7U_0805_10V4Z

+3VS

R2590_0402_5%@

1

C445

1U_0603_10V4Z

2

ICH_V5REF_RUN

ICH_V5REF_SUS

ICH_VCC1_5

1

C281

2

2.2U_0805_16V4Z

VCC1_5_A=1120mA

1

C298

2

VCC1_5_A=1120mA

1

C300

2

VCC1_5_A=1120mA

VCC1_5_A=1120mA

+1.5VS

VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2

R258

@

ICH_VCCGLAN1_5

1

C310

@

1mA

2

ICH_VCCGLAN3_3

1 2

50mA

6mA

3mA

770mA

10mA

12mA

27mA
74mA

AD25

A16

T7

G4

AA25
AA26
AA27
AB27
AB28
AB29

D28
D29
E25
E26
E27
F24
F25

G24

H23
H24
J23
J24
K24
K25
L23
L24

L25
M24
M25

N23

N24

N25

P24

P25

R24

R25

R26

R27

T23

T24

T27

T28

T29

U24

U25

V23

V24

V25
W25

Y25

AJ6
AE7

AF7
AG7
AH7

AJ7
AC1

AC2
AC3
AC4
AC5

AC10

AC9
AA5

AA6
G12

G17

H7

AC7
AD7

D1

F1
L6

L7
M6
M7

W23

F17

G18

F19

G20

A24
A26

A27
B26
B27
B28

B25

4

U7F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

4

CORE

VCCA3GP ATXARX

VCCP_COREVCCPSUSVCCPUSB

IDE

PCI

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCDMIPLL

VCC_DMI[1]
VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

3

+VCCP

1170mA

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

VCC3_3=310mA

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20
AC16
J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

G22
A22
F20

G21

0.1U_0402_16V4Z

1

1

C276

C277 0.1U_0402_16V4Z

2

2

ICH_VCCDMIPLL

C282

0.01U_0402_16V7K

26mA
40mA

14mA

VCC3_3=310mA
VCC3_3=310mA

0.1U_0402_16V4Z

VCC3_3=310mA

+3VS

+3VS

VCC3_3=310mA

0.1U_0402_16V4Z

1

C292

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C293

2

24mA
4mA

VCCSUS1_5_ICH_1
VCCSUS1_5_ICH_2

0.1U_0402_16V4Z

VCCCL1_05_ICH

1U_0603_10V4Z

12mA

0.1U_0402_16V4Z

T32

T33
T34
T35

1

2

+3VALW

VCCSUS3_3=141mA

1

C306

4.7U_0805_10V4Z

2

T38

1

+3VS

C311

2

@

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R253 CHB1608U301_0603

1 2

+1.25VS

+3VALW

+1.5VS

+3VS

1

C289

2

1

C299

2

+VCCP

4.7U_0805_10V4Z

(DMI)

+3VS

Compal Secret Data

Deciphered Date

1

1

C283

2

2

10U_0805_10V4Z

10U_0805_10V4Z

C285

1

2

0.1U_0402_16V4Z

+3VS

(SATA)

1

C290

2

+3VS

1

1

C294

C295

2

2

0.1U_0402_16V4Z

1

C301

2

+3VALW

VCCSUS3_3=141mA

0.1U_0402_16V4Z

1

C303

C302

2

2007/03/26 2006/03/10

3

0.1U_0402_16V4Z

C286

1

1

2

2

2

0.1U_0402_16V4Z

C287

C288

1

2

2

U7E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

VSS[006]

AB24

VSS[007]

AC11

VSS[008]

AC14

VSS[009]

AC25

VSS[010]

AC26

VSS[011]

AC27

VSS[012]

AD17

VSS[013]

AD20

VSS[014]

AD28

VSS[015]

AD29

VSS[016]

AD3

VSS[017]

AD4

VSS[018]

AD6

VSS[019]

AE1

VSS[020]

AE12

VSS[021]

AE2

VSS[022]

AE22

VSS[023]

AD1

VSS[024]

AE25

VSS[025]

AE5

VSS[026]

AE6

VSS[027]

AE9

VSS[028]

AF14

VSS[029]

AF16

VSS[030]

AF18

VSS[031]

AF3

VSS[032]

AF4

VSS[033]

AG5

VSS[034]

AG6

VSS[035]

AH10

VSS[036]

AH13

VSS[037]

AH16

VSS[038]

AH19

VSS[039]

AH2

VSS[040]

AF28

VSS[041]

AH22

VSS[042]

AH24

VSS[043]

AH26

VSS[044]

AH3

VSS[045]

AH4

VSS[046]

AH8

VSS[047]

AJ5

VSS[048]

B11

VSS[049]

B14

VSS[050]

B17

VSS[051]

B2

VSS[052]

B20

VSS[053]

B22

VSS[054]

B8

VSS[055]

C24

VSS[056]

C26

VSS[057]

C27

VSS[058]

C6

VSS[059]

D12

VSS[060]

D15

VSS[061]

D18

VSS[062]

D2

VSS[063]

D4

VSS[064]

E21

VSS[065]

E24

VSS[066]

E4

VSS[067]

E9

VSS[068]

F15

VSS[069]

E23

VSS[070]

F28

VSS[071]

F29

VSS[072]

F7

VSS[073]

G1

VSS[074]

E2

VSS[075]

G10

VSS[076]

G13

VSS[077]

G19

VSS[078]

G23

VSS[079]

G25

VSS[080]

G26

VSS[081]

G27

VSS[082]

H25

VSS[083]

H28

VSS[084]

H29

VSS[085]

H3

VSS[086]

H6

VSS[087]

J1

VSS[088]

J25

VSS[089]

J26

VSS[090]

J27

VSS[091]

J4

VSS[092]

J5

VSS[093]

K23

VSS[094]

K28

VSS[095]

K29

VSS[096]

K3

VSS[097]

K6

VSS[098]

ICH8M REV 1.0

Compal Electronics, Inc.

Title

ICH8(4/4)_POWER&GND

Size Document Number Rev

Custom

LA-3981P

Date: Sheet of

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

1

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

21 42Monday, October 22, 2007

1

0.3

A

B

C

D

E

F

G

+5VS

H

Placea ca ps. near ODD CONN.

HDD Connector CD-ROM Connector

IDE_HDD[0..15] 19

+5VS

1 1

C317

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

2

Pleace near HD CONN (JP23)

+3VS +3VS_HDD

R2630_0805_5%@

12

0.1U_0402_16V4Z

1

C323

@

2

1000P_0402_50V7K

Pleace near HD CONN

2 2

C318

1

2

C324

@

1

C319

2

0.1U_0402_16V4Z

1

C325

@

2

1U_0603_10V4Z

1

C320

2

0.1U_0402_16V4Z

1

+

C322

@

2

330U_V_2.5VK_R9

DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA
SUYIN_127043FR022G204ZL_22P_NR

JP9

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

23

GND

24

GND

CONN@

SUYIN_127043FR022G204ZL_NR

0.01U_0402_16V7K

SATA_RXN0

SATA_RXP0

0.01U_0402_16V7K

Near CONN side.

+3VS_HDD

+5VS

SATA_TXP0
SATA_TXN0

SATA_RXN0_C

C316

12

SATA_RXP0_C

C321

12

SATA_TXP0 19
SATA_TXN0 19

SATA_RXN0_C 19
SATA_RXP0_C 19

IDE_RESET#20

PLT_RST#7,18

+5VS

R260 0_0402_5%@

R261 33_0402_5%

IDE_HDIOW#19

IDE_HIORDY19

IDE_HIRQ19
IDE_HDA119
IDE_HDA019

IDE_HDCS1#19

R264 10K_0402_5%

+5VS

1 2
1 2

12

IDE_HDD7
IDE_HDD6
IDE_HDD5
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0

IDE_HDIOW#
IDE_HIORDY

IDE_HIRQ
IDE_HDA1
IDE_HDA0
IDE_HDCS1#
IDE_ACT#

SEC_CSEL

12

R265
470_0402_5%

JP10

1

2

1

2

3

4

3

4

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49
G53G

SUYIN_800194MR050S102ZU

CONN@

DC030001P00 WAFER OCTEK CDR-50JD1 50P P0.822P SATA
OCTEK_CDR-50JD1_50P

IDE_HDD8

6

6

IDE_HDD9

8

8

IDE_HDD10

10

10

IDE_HDD11

12

12

IDE_HDD12

14

14

IDE_HDD13

16

16

IDE_HDD14

18

18

IDE_HDD15

20

20

IDE_HDREQ

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

54

IDE_HDREQ 19

IDE_HDIOR#

IDE_HDIOR# 19

IDE_HDACK#

IDE_HDACK# 19

PDIAG#

R262 100K_0402_5%

1 2

IDE_HDA2
IDE_HDCS3#

IDE_HDA2 19

IDE_HDCS3# 19

+5VS

0.1U_0402_16V4Z

C312

1

2

+5VS

10U_0805_10V4Z

1U_0603_10V4Z

1

1

C313

2

1

C314

C315
10U_0805_10V4Z

2

2

Mini-Express Card---WLAN

+3VS_MINI +1.5VS_MINI

C326

1

0.01U_0402_16V7K

2

3 3

ICH_PCIE_WAKE#20

MINI_CLKREQ#15

CLK_PCIE_MCARD#15

CLK_PCIE_MCARD15

CLK_DEBUG_PORT_L15,29

PCIE_RXN120
PCIE_RXP120

PCIE_TXN120
PCIE_TXP120

4 4

Mini Card STANDOFF

H19

H20

HOLEA

HOLEA

1

1

A

EC029000100 MINICARD_STANDOFF_8

B

C

C327

0.1U_0402_16V4Z

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

PLT_RST#

PCIE_RXP1

PCIE_TXN1
PCIE_TXP1

1

2

4.7U_0805_10V4Z

ICH_PCIE_WAKE#

1 2

R266 0_0402_5%

1 2

R272 0_0402_5% DEBUG@

R273 0_0402_5%

1 2
1 2

R274 0_0402_5%

1

C328

2

MINI_CLKREQ#_MC

PCIE_C_RXN1PCIE_RXN1
PCIE_C_RXP1

SP01000P700 S H-CONN ACES 88914-5204 52P P0.8

D

1

2

JP11

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

C330

0.1U_0402_16V4Z

+1.5VS_MINI

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

C329

0.01U_0402_16V7K

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

FOX_AS0B22 6-S40N-7F~D

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DR AWING IS TH E PROPRIETARY PR OPERTY OF COMPAL ELECTRO NICS, IN C. AND CO NTAINS CON FIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE C OMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER T HIS SHEET NOR THE INFOR MATION IT C ONTAINS
MAY BE USED BY O R DISCLO SED TO ANY THI RD PARTY WITH OUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, IN C.

1

2

1

C331

4.7U_0805_10V4Z

2

+3VS_MINI

FBMA-L11-201209-102LMA10T

1 2

L13 FBMA-L11-201209-102LMA10T

R267 0_0402_5% DEBUG@

1 2

R268 0_0402_5% DEBUG@

1 2

R269 0_0402_5% DEBUG@

1 2

R270 0_0402_5% DEBUG@

1 2

R271 0_0402_5% DEBUG@

1 2

WL_D_OFF#
PLT_RST#

WL_LED#

2007/03/26 2007/08/29

Compal Secret Data

E

L12

1 2

C332

0.1U_0402_16V4Z@

+3VALW

ICH_SMBCLK 15,20
ICH_SMBDATA 15,20

WL_LED# 28

Deciphered Date

+3VALW

+3VS

1

2

+1.5VS

D29

2 1

CH751H-40PT_SOD323-2

LPC_FRAME# 19,29,30

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

F

LPC_AD[0..3] 19,29,30

+3VS

12

R411
100K_0402_5%

WL_LED#

Title

Size Document Number Rev

Date: Sheet

G

WL_OFF#WL_D_OFF#

WL_OFF# 20

Compal Electronics, Inc.

HDD/ODD/Mini Card CONN.

LA-3981P

22 42Monday, October 22, 2007

H

0.3

of

5

4

3

2

1

Cloase to JP12.

L21

MDO0-

1

1

4

4

WCM-2012-900T_4P

L22

MDO1+

1

D D

PCI_AD[0..31]18

C C

PCI_CBE#018
PCI_CBE#118
PCI_CBE#218
PCI_CBE#318

PCI_AD17

PCI_PAR18

PCI_FRAME#18

PCI_IRDY#18

PCI_TRDY#18

PCI_DEVSEL#18

PCI_STOP#18
PCI_PERR#18

PCI_SERR#18,30
PCI_REQ0#18

PCI_GNT0#18

B B

A A

PCI_PIRQ#18

PCI_PME#18,30

CLK_PCI_LAN15

CLK_PCI_LAN

12

R292

10_0402_5%

1

C356

10P_0402_50V8J

2

PCI_RST#18,29,30

5

PCI_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

LAN_IDSEL

1 2

R285 100_0402_5%

PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#

PCI_PERR#
PCI_SERR#

PCI_REQ0#
PCI_GNT0#

PCI_PIRQ#
PCI_PME#
PCI_RST#
CLK_PCI_LAN

1 2

R289
10K_0402_5%

U8

104

AD0

103

AD1

102

AD2

98

AD3

97

AD4

96

AD5

95

AD6

93

AD7

90

AD8

89

AD9

87

AD10

86

AD11

85

AD12

83

AD13

82

AD14

79

AD15

59

AD16

58

AD17

57

AD18

55

AD19

53

AD20

50

AD21

49

AD22

47

AD23

43

AD24

42

AD25

40

AD26

39

AD27

37

AD28

36

AD29

34

AD30

33

AD31

92

C/BE#0

77

C/BE#1

60

C/BE#2

44

C/BE#3

46

IDSEL

76

PAR

61

FRAME#

63

IRDY#

67

TRDY#

68

DEVSEL#

69

STOP#

70

PERR#

75

SERR#

30

REQ#

29

GNT#

25

INTA#

31

PME#

27

RST#

28

CLK

65

CLKRUN#

4

GND/VSS

17

GND/VSS

128

GND/VSS

21

GND/VSSPST

38

GND/VSSPST

51

GND/VSSPST

66

GND/VSSPST

81

GND/VSSPST

91

GND/VSSPST

101

GND/VSSPST

119

GND/VSSPST

35

GND

52

GND

80

GND

100

GND

RTL8100CL_LQFP128

EEDO

AUX/EEDI

EESK
EECS

LED0
LED1
LED2

NC/LED3

TXD+/MDI0+

TXD-/MDI0-

RXIN+/MDI1+

RXIN-/MDI1-

NC/MDI2+

NC/MDI2-

NC/MDI3+

NC/MDI3-

X1
X2

LWAKE

ISOLATE#

RTSET

NC/SMBCLK

NC/SMBDATA

NC/M66EN
NC/AVDDH

NC/HV

PCI I/F

NC/HSDAC+

NC/HG
NC/LG2
NC/LV2

NC/VSS
NC/VSS

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

LAN I/F

NC/GND

CTRL25

RTT3/CRTL18

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

VDD33

AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL

NC/AVDDL

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18

Power

AVDD25/HSDAC-

108
109
111
106

117
115
114
113

1
2
5
6

14
15
18
19

121
122

105
23
127
72
74

88
10

120
11

123
124
126

9
13

22
48
62
73
112
118

8
125
26

41
56
71
84
94
107

3
7
20
16

32
54
78
99

24
45
64
110
116

12

4

R276

3.6K_0402_5%

1 2

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

ACTIVITY#_R ACTIVITY#

1 2

R278 0_0 603_5%

1 2

R279 0_0 603_5%

TXD+/MDI0+
TXD-/MDI0­RXIN+/MDI1+
RXIN-/MDI1-

LAN_X1
LAN_X2

R281 1K_0402_5%

1 2

R282 15K_0402_5%

1 2

R283 5.6K _0603_1%

1 2

Q10

CTRL25

1

1

C343

0.1U_0402_16V4Z

2

1

C349

0.1U_0402_16V4Z

2

1

C352

0.1U_0402_16V4Z

2

V_12P

1

C359

0.1U_0402_16V4Z

2

U9

4

DO

3

DI

2

SK

1

CS

AT93C46-1 0SU-2.7_SO8

+3VALW

C340 1U_0603_10V4Z

1 2

2SB1188T100R_SC62-3

2 3

C342 4.7U_0805_10V4Z

1 2

1

2

1

2

1

2

R293
0_0402_5%

1 2

+3VA_LAN

5

GND

6

NC

7

NC

8

VCC

LINK_100#LI NK_100#_R

C336 27P_0402_50V8J

1 2

Y3
25MHZ_20P_1BG25000CK1A

C337 27P_0402_50V8J

1 2

1 2

+3VS

V2.5_LAN

1

C344

0.1U_0402_16V4Z

C350

0.1U_0402_16V4Z

C353

0.1U_0402_16V4Z

C345

0.1U_0402_16V4Z

2

1

C351

0.1U_0402_16V4Z

2

1

C354

0.1U_0402_16V4Z

2

V2.5_LAN

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

MDO1-

4

4

WCM-2012-900T_4P

1

C333 0.1U_0402_16V4Z

+3VALW

2

1 2

C334 680P_0402_50V7K

1 2

C335 680P_0402_50V7K

TXD+/MDI0+ MDO0+
TXD-/MDI0-

C339

0.1U_0402_16V4Z

1 2

RXIN+/MDI1+

RXIN-/MDI1-

1

C346

0.1U_0402_16V4Z

2

1

C355

0.1U_0402_16V4Z

2

3

R_MDO0-

2

2

R_MDO0+MDO0+

3

3

R_MDO1+

2

2

R_MDO1-

3

3

For EMI,
locate close
to LAN chip

U10

TD-8TX-

7

TD+

TX+

6

CT

CT

3

CT

CT

2

RD-

RX-

1

RD+

RX+

NS0013_16P

1

C347

0.1U_0402_16V4Z

2

V2.5_LAN

2007/03/26 2007/08/29

Compal Secret Data

PACDN042Y3R_SOT23-3

PACDN042Y3R_SOT23-3

9

MDO0-

10

MCT0

11

MCT1

14

MDO1+

15

MDO1-

16

+3VA_LAN

R288

0_0603_5%

Deciphered Date

+3VALW

ACTIVE#
LINK#

12

+3VALW

R275
300_0603_5%

ACTIVITY# ACTIVE#

1 2

R277
300_0603_5%

LINK_100# LINK#

1 2

2

3

D27

@

1

2

3

D28

@

1

R280
75_0402_5%

R284
75_0402_5%

close to chip

TXD+/MDI0+

TXD-/MDI0-

close to magnetic

RXIN+/MDI1+

RXIN-/MDI1-

Footprint can not match part number.

2

+3VALW

12

12

C357

220P_1808_3KV

JP12

11

R286

49.9_0402_1%

R287

49.9_0402_1%

R290

49.9_0402_1%

R291

49.9_0402_1%

Yellow LED+

12

Yellow LED-

8

RX2-

7

RX2+

R_MDO1-

6

RX1-

5

TX2-

4

TX2+

R_MDO1+

3

RX1+

R_MDO0-

2

TX1-

R_MDO0+

1

TX1+

10

Green LED-

9

Green LED+

TIP
RING

RJ45_GND

2

1

RJ45 / LED

13

RJ11_1

14

RJ11_2

JM34F2*-N5125-7F
JM34F2A-M5125-7F

C338

12

1000P_1206_2KV7K

C341

0.01U_0402_16V7K

12

12

12

C348

0.01U_0402_16V7K

12

12

12

SP020008Y00 S W-CONN ACES 88266-02001 2P P1.25
ACES_88266-02001_2P

JP13

RING

1

1

TIP

2

2

2

C358

3

G1

4

G2

1

ACES_88266-02001

220P_1808_3KV

CONN@

Title

Size Document Number Rev

Date: Sheet of

15

SGND1

16

SGND2

RJ11

JM34F2-M5125-7FCONN@

RJ11

Compal Electronics, Inc.

LAN-8100CL

LA-3981P

23 42Monday, October 22, 2007

1

0.3

A

In order for the modem wake on ring feature to function,
the CODEC must be powered by a rail that is not
removed when the system is in standby.

10U_0805_10V4Z

1

2

DIB_P25

DIB_N25

+3VDD_CODEC

1

1

2

2

C366

C365

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VDD_CODEC

1

2

C367

0.1U_0402_16V4Z

ACZ_RST#
ACZ_BITCLK

R299 33_0402_5%

1 2

R301 0_0 402_5%

1 2
1 2

R305 0_0 402_5%

C373

MONO_INRMONO_IN1

1 2

0.01U_0603_16V7K

T39

C446

10U_0805_10V4Z

DIBP_C
DIBN_C

EAPD

R294

ACZ_RST#19,30

ACZ_SYNC19
ACZ_SDIN019
ACZ_SDOUT19

R302

1 2

620_0402_5%

R306

143_0402_1%

R311 10K_ 0402_5%@

1 2
1 2

R42110K_0402_5%@

12

C364

12

+3VS

1 1

@

47_0402_5%

@

33P_0402_50V8K

ACZ_BITCLK19

SB_SPKR20

2 2

MBV2012301YZF_0805

ACZ_BITCLK

12

R300

1

C374

2

SB_SPKR

0927_Modify PC Beep circuit.

3 3

4 4

B

AUDIO CODEC

1

1

1

2

2

C363

0.1U_0402_16V4Z

9

44

4

3

U21

VDD_IO

DVDD_44

DVDD_1-8

11

10

43
42

12

48

45
46
47

DVDD_3-3

RESET#

6

BIT_CLK
SYNC

8

SDATA_IN

5

SDATA_OUT

DIB_P
DIB_N

PC_BEEP

S/PDIF

GPIO2
GPIO1
EAPD/GPIO0

1

DMIC_CLOCK

2

DMIC_1/2

DVSS_41

DVSS_7

7

41

25

DIGITAL A NALOG

C379

0.1U_0402_16V4Z

1 2

C380

0.1U_0402_16V4Z

1 2

C381

0.1U_0402_16V4Z

1 2

C382

0_0402_5%

1 2

C383

0.1U_0402_16V4Z

1 2

R312
0_1206_5%

1 2

0_1206_5%

1 2

C368

0.1U_0402_16V4Z

26

40

36

AVEE

PORTA_L

AVDD_26

AVDD_40

PORTA_R
MICBIASB

MIC_L
MIC_R

MICBIASC

PORTC_L

PORTC_R

PORTD_L

PORTD_R

PORTB_L
PORTB_R

MONO
STEREO_L
STEREO_R

SENSEA

VREF_FILT

FLY_P

FLY_N

RESERVED_22
RESERVED_23
RESERVED_32
RESERVED_33

AVSS_38

AVSS_25

CX20561-12Z_LQFP48_7X7

38

R313

2

1U_0603_10V4Z

For Layout:

Place decoupling caps near the
power pins of SmartAMC
device.

+3VAMP_CODEC

MBV2012301YZF_0805

1

1

2

2

C370

C369

10U_0805_10V4Z

0.1U_0402_16V4Z

HP_OUTL

34

HP_OUTR

35
19

+MICBIASB

MIC_INL

20

MIC_INR

21
18

+MICBIASC

MIC_EXTL

16

MIC_EXTR

17

27
28

14
15

29

LINE_OUTL

30

LINE_OUTR

31

SENSE

13

VC_REFA

24

VREF_HI

39

VREF_LO

37
22

23
32
33

1

C450

2

GNDA 26

C

R295

12

1

1

2

2

C448

C447

10U_0805_10V4Z

0.1U_0402_16V4Z

HP_OUTL 26
HP_OUTR 26

C371 2.2U_0805_10V6K

1 2

C372 2.2U_0805_10V6K

1 2

C375 2.2U_0805_10V6K

1 2

C376 2.2U_0805_10V6K

1 2

LINE_OUTL 26
LINE_OUTR 26

1 2

C377 1U_0603_10V4Z

1

C451
1U_0603_10V4Z

2

+VDDA_CODEC

R423

1 2

0_0805_5%

@

R296

4.7K_0402_5%

1 2

R309 5.1 K_0402_1%

1 2

R310 5.1 K_0402_1%

1 2

R337 20K_ 0402_1%

VC_REFA

C449

0.1U_0402_16V4Z

D

E

CODEC POWER

1

C361

0.1U_0402_16V4Z

2

MIC

ON

OFF

ON

OFF

(3.33V)
250mA

EQ

Disable
Disable

Enable

+5VALW

W=40Mil

1 2

C360 0.1U_0402_16V4Z

SUSP#30,31,33,35,36

+3VS

1 2

R429

1K_0402_5%

1

C452
10U_0805_10V4Z

2

R303

@

2.2K_0402_5%

HP_DET# 26

EXTMIC_DET# 26

1

1

2

2

C378

10U_0805_10V4Z

HP_DET#

+VDDA_CODEC

0925_Add LPF to reduce INT. MIC noise.

+MICBIASC

12

12

R304

2.2K_0402_5%

MIC_IN_R 26

MIC_EXT_L 26
MIC_EXT_R 26

+3VAMP_CODEC

MIC_DET

0(LOW)
0(LOW)

0(LOW)

NC

0(LOW)

NC NC

NC

U11

1

VIN

2

GND
SHDN#3BP

APE8805A-33Y5P_SOT23-5

0.1U_0402_16V4Z

LINEOUT

OFF
OFF

ON
ON Enable

5

OUT

4

C362

PORT-A
<Earphone OUT>

ON
ON

OFF
OFF

+VDDA_CODEC

1

2

GNDAGND

A

B

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/03/10

C

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

AMOM_codec

Size Document Number Rev

Custom

LA-3981P

Date: Sheet of

24 42Monday, October 22, 2007

E

0.3

5

4

3

2

1

MU1

AVdd

AGND_LSD

AGND_LSD

DIBN

PWR+

MC3

0.1uF

DIBP

DVdd

12

16

15

2

cap_0402_01uf

14

1

CX20548

TEST

DIBN

PWR

AVDD

DIBP

DVDD

MC2

0.1uF

cap_0402_01uf

AGND_LSD

RAC1

4

RAC

TAC1

5

TAC

EIC

11

EIC

R810 and C810 must be placed near pin 6 (RXI)
and there should be no vias on the(RXI)net.

RXI

6

RXI

10

EIO

EIF

9

EIF

TXO

8

TXO

TXF

7

TXF

13

GPIO

VC

EP

3

17

VC_LSD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERT Y OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMATION. T HIS SHEET MAY NO T BE TRAN SFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D
DEPARTMENT EXCEPT AS AU TH ORI ZED BY CO MPA L ELE CTR ONI CS, INC. NEI THE R THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRIT TEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

D D

DIB_P24

C C

B B

DIB_N24

MC12

GND

MJ4@

2
1

MJ5@

1
2

GND

DIBN_HS
DIBP_HS

150pF

CAP_0402_150PF

MC13
150pF

CAP_0402_150PF

GND

MT1

2 3

1

MODEM-SMAR

4

MC6
47P_0402_50V8J

CAP_0402_47PF

MC5

0.1uF

cap_0402_01uf

MC4

0.1uF

cap_0402_01uf

Revision History

Description

Initial Release

0

No changes to schematic. PCB updated to -003.

1

Updated footprints and corrected via spacing errors.

A A

Changed MC8 and MC9 pads. No schematic changes.

2

PCB updated to -005.

3

Added MR11 and MR12. PCB updated to -007.

4

Added MR13. PCB updated to -009.

4.01

AVL update only.

5

DateREV

April 26, 2005

August 18, 2005

November 3, 2005

November 18, 2005

January 3, 2006

April 20, 2006

4

RAC1_RING

MR3 6.81M

MR1 6.81M

res_0805_681m

MC11 0 .1uF

MR2

237K

cap_0402_01uf

AGND_LSD

RX1_1

MR13 100_0402_5%

MMBD3004S

MMBD3004S

TAC1_TIP TIP_1

MC1 0.047uF

100.0V

RES_0402_100

2007/03/26 2007/07/26

5335R13-005

MBR1

AGND_LSD

142

@

MBR2

5335R13-005

MQ2
MMBTA42

MR4
110

5%

Compal Secret Data

Deciphered Date

MFB2

3

ML1

Optional

MFB1

MC10 0 .01uF

cap_0603_001uf

BRIDGE_CC

MQ1

MMBTA42

QBASE

MR8
56

5%
RES_0603_56@

AGND_LSD

2

MC8

AGND_LSD

MR9
280

RES_1206_280

MQ3

MMBTA42

MR11

3.01

res_0402_301

MR7

9.1

res_1206_91

RING_1

2

MRV1

MC9

MC7

470 pF470 pF

Omit

@

Note: MC8 and MC9 can be optionally
populated here or behind the RJ-11
connector.

GND

MR5

MR6

280

280

RES_1206_280

RES_1206_280

BRIDGE_CC2

MQ4
MMBTA42

MR12

3.01

res_0402_301

Title

AMOM-CX20548

Size Document Number R ev

Date: Sheet of

1

MJ2

@
2

1

MJ1

@
2

1

MJ3

@

MR10
280

RES_1206_280

Compal Electronics, Inc.

LA-3981P

1

0.3

25 42Monday, October 22, 2007

A

1 1

C391 0.047U_0603_16V7K

1 2

C393 0.047U_0603_16V7K

LINE_OUTR24

LINE_OUTL24

2 2

3 3

1 2

C396 0.047U_0603_16V7K

1 2

EC_MUTE#30

C395 0.047U_0603_16V7K

LINE_C_OUTR

1 2

LINE_C_OUTL

EC_MUTE#

7

17

9

5

19

B

U13

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

10U_0805_10V4Z

15

6

16

VDD

PVDD1

PVDD2

GND41GND311GND213GND1

GND5

20

21

L24 MBC1608121YZF_0603

SPKR+

1 2

L25 MBC1608121YZF_0603

SPKR-

1 2

L26 MBC1608121YZF_0603

SPKL+

1 2

L27 MBC1608121YZF_0603

SPKL-

1 2

HP_OUTR24

HP_OUTL24

C

+5VS+5VAMP

0.1U_0402_16V4Z

1

C385

C384

2

2

GAIN0

3

GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

P3017THF D0 TSSOP 20P

L_SPKR+

18

L_SPKR-

14

L_SPKL+

4

L_SPKL-

8

12

NC

10

2

1

R_SPKR+

R_SPKR-

R_SPKL+

R_SPKL-

HP_OUTR OUT_R
HP_OUTL

R314
0_1206_5%

1 2

1

2

0.1U_0402_16V4Z

1

C386

2

L16 MBC1608121YZF_0603

1 2

L17 MBC1608121YZF_0603

1 2

L18 MBC1608121YZF_0603

1 2

L19 MBC1608121YZF_0603

1 2

Keep 10 mil width

C397

0.47U_0603_10V7K

1 2

110_0402_1%

1 2

R418

110_0402_1%

SPKR+

SPKR-

SPKL+

SPKL-

MIC_EXT_R24
MIC_EXT_L24

R417

100K_0402_5%

100K_0402_5%

MIC_EXT_R
MIC_EXT_L

3

1

SM05_SOT23

@

OUT_L

@

2

D31

16 dB

12

12

1 2
1 2

3

1

SM05_SOT23

12

12

2

D30

@

R325 MBC1608121YZF_0603

1 2
1 2

R326 MBC1608121YZF_0603

R315

R318

R424 100_0402_5%
R425 100_0402_5%

EXTMIC_DET# HP_DET#

D

SP02000D000 S W-CONN ACES 85204-04001 4P P1.25

+5VS

R316

100K_0402_5%

@

R319
100K_0402_5%

R321 MBC1608121YZF_0603

R322 MBC1608121YZF_0603

1 2
1 2

HP_DET#24

C401470P_0402_50V7K

12

12

C404470P_0402_50V7K

R_SPKL+
R_SPKL­R_SPKR+
R_SPKR-

1

1

C387

@

47P_0402_50V8J

AGND

MIC_IN_R24

EXTMIC_DET#24

C398470P_0402_50V7K

12

12

C399470P_0402_50V7K

HP_DET#

C388

2

2

@

47P_0402_50V8J

C394 47P_0402_50V8J@

12

R320 0_0603_5%

1 2

1 2

MBC1608121YZF_0603

EXTMIC_DET#

MICEXT_R
MICEXT_L

PR

PL

C389

@

L20

3

2

3

@

1

SM05_SOT23

47P_0402_50V8J

1

SM05_SOT23

D14

E

SPEAKER

JP15

4

4

3

3

2

2

1

1

E&T_3801-04

1

C390

2

@

47P_0402_50V8J

AGND

2

D13

@

HeadPhone Out/Line Out

6
5

4
3
2

1

CONN@

1

2

MIC INT In-R

JP28

MICIN_R

1

1

2

2

3

G1

4

G2

ACES_85204-02001

CONN@

MIC EXT In

CONN@

SUYIN_010030FR006G105ZR

6
5

4
3
2

1

JP16

CONN@

SUYIN_010030FR006G105ZR

JP17

0302_Change Audio Jack.

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAIN S CONFIDENTIA L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATI ON IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRONIC S, INC.

2007/03/26 2007/08/29

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

AMP & Audio Jack

Size Document Number Rev

D

Date: Sheet

LA-3981P

26 42Mo nday, October 22, 2007

E

0.3

of

5

D D

220U_6.3V_M

C C

B B

C406

0.1U_0402_16V4Z

+USB_VCCA

1

1

1

+

C407

C408
1000P_0402_50V7K

2

2

2

4

USB Port

+5VALW

SYSON# USB_OC#2

USB20_N220
USB20_P220

U14

1

GND

2

IN

3

IN

4

EN#

RT9711PS_SO8

PSOT24C_SOT23-3

8

OUT

7

OUT

6

OUT

5

FLG

2

3

D15

@

1

3

+USB_VCCA

USB_OC#2 20

JP19

1

1

2

2

3

3

4

4

5

GND

6

GND

7

GND

8

GND

SUYIN_020133MB004S580ZL-C

CONN@

DC233000U00 CONN SUYIN 020173MR004S558ZL 4P USB
SUYIN_020173MR004S558ZL_4P

2

JP29

USB20_P420

USB20_N420

+5VALW

+5VS

USB20_N020

USB20_P020

USB20_N120
USB20_P120
USB_OC#020

SYSON#31,35

1

1

3

3

5

5

7

7

9

9

11

11

+5VALW

SYSON#

SP02000DX00 S W-CONN ACES 87213-1000G 10P P1.0
ACES_87213-1000G_10P

GND13GND14GND15GND16GND17GND

JP18

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

CONN@

2

2

4

4

6

6

8

8

10

10

12

12

ACES_88020-12101

18

CONN@

+3VS

1

A A

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/07/26

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

USB CONN.

Size Document Number Rev

2

Date: Sheet of

LA-3981P

27 42Monday, October 22, 2007

1

0.3

5

1005_Disconnect ON/OFFBTN# and ON/OFFBTN_LED# from U22.

D D

WL_BTN#

+3VS

NUM_LED#

4

CH4

5

Vp

6

CH3

CM1293-04SO_SOT23-6

U22

1

CH1

2

Vn

3

CH2

WL_LED#

LID_SW#

Power ON/OFF

+3VALW

C C

D17

1

DAN202U_SC70

Q18
DTC124EK_SC59

+3VALW

12

2
3

R332

4.7K_0402_5%

ON/OFFBTN#

EC_ON

EC_ON30

R330

4.7K_0402_5%

1 2

ON/OFF
51ON#

1

O

G3I

2

+3VALW

1

2

C409

1000P_0402_50V7K

4

CM1293-04SO_SOT23-6

4

CH4

5

Vp

6

CH3

U23

ON/OFF 30
51ON# 34

3

M/BtoS/B

+3VALW

+3VS

JP20

1

1

2

1

CH1

2

Vn

3

CH2

NUM_LED#29,30
WL_BTN#30

ON/OFFBTN_LED#29,30

LID_SW#30

ON/OFFBTN#
WL_BTN#

ON/OFFBTN_LED#

WL_LED#

LID_SW#

SP01000H400 S H-CONN ACES 85201-1005N 10P P1.0
ACES_85201-1005N_10P

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

CONN@

M/B to SB(Caps Lock LED)

+3VS

JP21

1

1

CAPS_LED#29,30

SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P

2

2

3

G1

4

G2

ACES_85204-02001

CONN@

2

POWER LED(Left 1)

ON/OFFBTN_LED#

LTST-C191TBKT-5A_BLUE_0603

Battery Charge LED(Left 2)

BAT_LED#30

SATA_LED#19

0927_Change R329, R331, R333 (75 ohm), R335 (33 ohm) to 27 ohm.

LTST-C191TBKT-5A_BLUE_0603

HDD LED(Left 3)

LTST-C191TBKT-5A_BLUE_0603

Wireless ON/OFF LED(Left 4)

R334

330_0402_5%

AMBER BLUE

LTST-C195TBKFKT_BLUE/ORG

On (WL_ON#=L)-> Blue
Off (WL_ON#=H)-> Amber

WL_LED#22

D21

WL_LED#

1

BLUE

D16

21

BLUE

D18

21

BLUE

D20

21

+3VS

12

12

R335
27_0402_5%

2

4

Orange

Blue

1

3

13

D

Q19

2

G

2N7002_SOT23-3

S

13

D

Q20

2

G

2N7002_SOT23-3

S

R329

1 2

27_0402_5%

R331

1 2

27_0402_5%

R333

1 2

27_0402_5%

10K_0402_5%

WL_LED#_LIGHT

+3VALW

+3VALW

+3VS

R336

+3VS

12

B B

+3VS

TouchPAD ON/OFF LED

12

12

R338

33_0402_5%

+3VS

12

R341
10K_0402_5%

2N7002_SOT23-3

TP_LED#_LIGHT

A A

5

R339
330_0402_5%

2

4

AMBERBLUE

D23

LTST-C195TBKFKT_BLUE/ORG

Blue

Orange

1

3

Q21

13

D

2

G

On (TP_LED#=L)-> Blue

S

Off (TP_LED#=H)-> Amber

13

D

TP_LED#

Q22

2

G

2N7002_SOT23-3

S

TP_LED# 30

D21, D25, D23 Footprint can not match part number.

TP ON/OFF

+5V

R340

10K_0402_5%

1 2

TP_BTN#

1
2

6

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3
4

SN100000F00 S TACT SW SMT1-05-A SPST HCH H1.5 4P
SW_SMT1-05-A_4P

4

SW1

SMT1-05-A_4P

5

T/P Board

+5V

TP_BTN# 30

SP01000H300 S H-CONN ACES 85201-0405N 4P P1.0
ACES_85201-0405N_4P

2007/03/26 2006/07/26

3

JP22

1
2
3

4
G1
G2

ACES_85201-0405N

CONN@

Compal Secret Data

1
2
3
4
5
6

100P_0402_50V8J

Deciphered Date

1

C412

@

2

C413

@

0.1U_0402_16V4Z

1

1

@

2

2

TP_DATA
TP_CLK

TP_DATA 30
TP_CLK 30

C414
100P_0402_50V8J

2

2

3

D24
PACDN042Y3R_SOT23-3

1

SYSON30,31,35

Title

LED/SW

Size Document Number Rev

Date: Sheet of

+5VALW +5V

SI2301BDS-T1-E3_SOT23-3

S

12

R384

10K_0402_5%

13

D

SYSON

2

G

S

Compal Electronics, Inc.

LA-3981P

1

Q33

D

13

G

2

Q34
2N7002_SOT23-3

28 42Monday, October 22, 2007

0.3

1

C415

0.1U_0402_16V4Z

2

U16

8
7

SMB_EC_CK130,38
SMB_EC_DA130,38

6
5

AT24C16AN- 10SI-2.7_SO8

1

A0

VCC

2

A1

WP

3

SCL

A2

4

SDA

GND

SPI ROM

+3VALW

20mils

1

C416

0.1U_0402_16V4Z

FSEL#30
SPI_CLK30

2

1 2

R345 0_0 402_5%

1 2

R346 0_0 402_5%

FWR# FRD#

1 2

R347 0_0 402_5%

U17

8

VCC

3

HOLD#

W

7

HOLD

SPI_FSEL#

1

S

SPI_CLK_R

6

C

5

D

WIESON G6179 8P SPI@

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P

&U17

SST25LF080B_SO8-200mil

VSS

Q

+3VALW+3VALW

4

2

12

R342
100K_0402_5%

12

R343
100K_0402_5%

SPI_SOSPI_FWR#

1 2

R348 0_0 402_5%

LPC Debug Port

B+

JP23

1

Ground

CLK_DEBUG_PORT_L15,22

LPC_FRAME#19,22,30

PCI_RST#18,23,30

LPC_AD019,22,30
LPC_AD119,22,30
LPC_AD219,22,30
LPC_AD319,22,30

ON/OFFBTNLED#
CAPSLED#
NUMLED#

VCC1PWRGD
SPI_CLK_JP52
SPI_CS#_JP52
SPI_SI_JP52

R349 0_0402_5%@

1 2

R350 0_0402_5%@

1 2

R351 0_0402_5%@

1 2

R352 0_0402_5%@

1 2

R353 0_0402_5%@

1 2

1 2

R222 0_0402_5%@

1 2

R356 0_0402_5%@

1 2

R357 0_ 0402_5%@

1 2

R399 0_ 0402_5%@

SPI_SO_JP52
SPI_HOLD#_0

ON/OFFBTNLED#

SPI_CLK_JP52

SPI_CS#_JP52

SPI_SI_JP52

SPI_HOLD#_0

SPI_SO_JP52

CAPSLED#

NUMLED#

VCC1PWRGD

FRD# 30FWR#30

Connect pin3 & 23
together and pin 24
to GND in 6/29.

SPI_CLK

+3VALW

ON/OFFBTN_LED#28,30

1 2

3.3K_0402_5%

CAPS_LED#28,30

NUM_LED#28,30

VCC1_PWRGD30

FSEL#

FWR#

R410

HOLD#

FRD#

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM_LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

@

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/03/26 2006/07/26

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

BIOS ROM

Size Document Number Rev

Date: Sheet of

LA-3981P

29 42Monday, October 22, 2007

0.3

+3VALW_EC

0.1U_0402_16V4Z

1

C418

2

+3VS +5VALW

12

R363

12

12

R366

4.7K_0402_5%

1

C419

2

1000P_0402_50V7K

12

R364

4.7K_0402_5%

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

1

2

0.1U_0402_16V4Z

4.7K_0402_5%

4.7K_0402_5%

C417

R365

EC DEBUG port

JP26

@

1

1

2

2

3

3

4

4

ACES_85205-0400

FOR LPC SIO DEBUG PORT

JP24

@

1

1

2

2

3

3

4

4

5

5

6

6

LPC_AD0

7

7

LPC_AD1

8

8

LPC_AD2

9

9

LPC_AD3

10

10

LPC_FRAME#

11

11

LPC_DRQ#0

12

12

PCI_RST#

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_85201-2005

URX
UTX

+5VS

CLK_LPC_DEBUG

SIRQ

+5VALW

+3VS

CLK_14M_DEBUG 15

LPC_DRQ#0 19

0.1U_0402_16V4Z

1

C420

2

@

15P_0402_50V8J

+3VALW

SUSP#

12

R402
10K_0402_5%

@

10K_0402_5%

CLK_LPC_DEBUG 15

1000P_0402_50V7K

1

C421

2

R358

@

C424

1 2

1 2

33_0402_5%

CLK_PCI_EC15

R359

47K_0402_5%

C425

1 2

0.1U_0402_16V4Z

+3VALW +3VS

12

R403
10K_0402_5%

LID_SW# WL_BTN#

PCI_SERR#18,23

R383

12

GATEA2019
KB_RST#19

LPC_FRAME#19,22,29

LPC_AD319,22,29
LPC_AD219,22,29
LPC_AD119,22,29
LPC_AD019,22,29

PCI_RST#18,23,29

12

EC_SCI#20

12

J1
JOPEN

12

R404
10K_0402_5%

SMB_EC_CK129,38
SMB_EC_DA129,38
SMB_EC_CK24
SMB_EC_DA24

SLP_S3#20
SLP_S5#20
EC_SMI#20

LID_SW#28

SUSP#24,31,33,35,36

PWRBTN_O UT#20

PCI_PME#18,23

TP_BTN#28

PCI_SERR#

15P_0402_50V8J

3
2

ON/OFF28

NUM_LED#28,29

C426

1 2

4

OUT

NC

1

IN

NC

32.768KHZ_12.5P_1TJS125DJ2A073

Y4

1 2

15P_0402_50V8J
C427

Board ID
DB : 4
SI :
PV :

+3VALW

R382

12

0_0805_5%

U18

GATEA20

1

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

R368

CRY2

20M_0402_5%@

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

+3VALW_EC

12

+EC_AVCC

Int. K/B
Matrix

L14
0_0603_5%

KB_RST#
SIRQ

SIRQ20

LPC_LFRAME#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

CLK_PCI_EC
PCI_RST#
ECRST#
EC_SCI#

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
SUSP#
PWRBTN_O UT#
PCI_PME#

TP_BTN#

UTX

URX

ON/OFF
NUM_LED#

12

CRY1

+EC_AVCC

+3VALW_EC

67

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

PWM Output

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

SM Bus

GPIO

GND

GND

GND

11

24

35

94

1 2

C428

0.1U_0402_16V4Z

Security Clas sification

Issued Date

THIS SHEET OF EN GINE ERI NG D RAW ING IS THE PR OPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T I NFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

VR_ON/XCLK32K/GPIO57

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

GPO

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

GPI

AGND

GND

GND

KB926QFB1_LQFP128_14X14

69

113

ECAGND

1 2

AD3/GPIO3B

AD4/GPIO42

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

SYSON/GPIO56

AC_IN/GPIO59

EC_ON/GPXO05

ENBKL/GPXID2

L15

INV_PWM

21

FAN_PWM

23
26

ACOFF

27

63
64
65
66
75
76

DAC_BRIG

68
70

IREF

71
72

EC_MUTE#

83

ACZ_RST#

84

AIR_AC

85

TP_LED#

86

TP_CLK

87

TP_DATA

88

97

R360 4.7K_0402_5%

98
99

WL_BTN#

109

FRD#

119

FWR#

120

SPI_CLK

126

FSEL#

128

SPICS#

73

VCC1_PWRGD

74

FSTCHG

89
90

CAPS_LED#

91

BAT_LED#

92

ON/OFFBTN_LED#

93

SYSON

95

VR_ON

121

ACIN

127

EC_RSMRST#

100

R397 0_0402_5%

1 2

101

EC_ON

102
103

PM_PWROK

104

BKOFF#

105

M_PWROK

106
107

GPXO10

108

GPXO11

SLP_S4#

110
112
114

GPXID3

THERM_SCI#

115

GPXID4

116

GPXID5

117

GPXID6

118

GPXID7

124

V18R

1

2

0_0603_5%

2007/03/26 2006/07/26

Compal Secret Data

BATT_TEMP
BATT_OVP
ADP_IN
M/B_ID

CLK_ENABLE

C@

C438

0.1U_0402_16V4Z

INV_PWM 17
FAN_PWM 4

ACOFF 33

BATT_TEMP 38
BATT_OVP 33
ADP_I 33

DAC_BRIG 17
IREF 33

12

WL_BTN# 28

FRD# 29
FWR# 29
SPI_CLK 29
FSEL# 29

VCC1_PWRGD 29

FSTCHG 33
CAPS_LED# 28,29

BAT_LED# 28
ON/OFFBTN_LED# 28,29
SYSON 28,31,35
VR_ON 37
ACIN 33

R393 10K _0402_5%

EC_RSMRST# 20

PM_PWROK 7,20
BKOFF# 17
M_PWROK 7, 2 0

SLP_S4# 20

THERM_SCI# 20

Deciphered Date

1 2

C423 0.01U_0402_16V7K

EC_MUTE# 26
ACZ_RST# 19,24

TP_LED# 28
TP_CLK 28
TP_DATA 28

CLK_ENABLE 15

12

EC_ON 28
WEBCAM_ON/OFF# 17

ECAGND

EC_LID_OUT# 20

AIR_AC 33,38

MV :

M/B_ID

0.1U_0402_16V4Z

VCC 3.3V+/-5%
Ra 100K+/-5%
Board ID Rb V

0

00V0V0V

1

8.2K+/-5%

2

18K+/-5%

3

33K+/-5%

4

56K+/-5%

5

100K+/-5%

6

200K+/-5%

7

NC

ACIN

1

C440
100P_0402_50V8J

2

KSO17

1

1

KSO16

2

2

KSO15

3

3

KSO10

4

4

KSO11

5

5

KSO14

6

6

KSO13

7

7

KSO12

8

8

KSO3

9

9

KSO6

10

10

KSO8

11

11

KSO7

12

12

KSO4

13

13

KSO2

14

14

KSI0

15

15

KSO1

16

16

KSO5

17

17

KSI3

18

18

KSI2

19

19

KSO0

20

20

KSI5

21

21

KSI4

22

22

KSO9

23

23

KSI6

24

24

KSI7

25

25

KSI1

26

26

ACES_85201-26051

Title

Size Document Number Rev

Date: Sheet of

AD_BID

0.216V

0.436V

0.712V

1.036V

1.453V

1.935V

2.500V

JP25

27

G1

28

G2

CONN@

Compal Electronics, Inc.

EC KB926/KB conn

LA-3981P

+3VALW_EC

1

C422

2

min V typ

AD_BIDVAD_BID

0.250V

0.503V

0.819V

1.185V

1.650V

2.200V

3.300V

TP_CLK
TP_DATA

For EMI

KSO14
KSO11

2

KSO10

3

KSO15

4 5

100P_1206_8P4C_50V8

KSO6
KSO3

2

KSO12

3

KSO13

4 5

100P_1206_8P4C_50V8

KSO2
KSO4

2

KSO7

3

KSO8

4 5

100P_1206_8P4C_50V8

KSI3
KSO5

2

KSO1

3

KSI0

4 5

100P_1206_8P4C_50V8

KSI4
KSI5

2

KSO0

3

KSI2

4 5

100P_1206_8P4C_50V8

KSO17
KSO16

2

KSI1

3

KSI7

4 5

100P_1206_8P4C_50V8

30 42Monday, October 22, 2007

12

Ra

R354
100K_0402_5%

12

Rb

R355
56K_0402_5%

12

R36110K _0402_5%

12

R36210K _0402_5%

CP1

CP2

CP3

CP4

CP5

CP6

0.289V

0.538V

0.875V

1.264V

1.759V

2.341V

3.300V

+5V

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

81
7
6

max

0.3

A

B

C

D

E

1 1

2 2

3 3

4 4

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

+5VS+5VALW +3VS+3VALW

U19

1

8

S

D

2

7

S

D

3

6

1

C429

2

10U_0805_10V4Z

S

D

4

5

D

AO4422_SO8

SYSON#27,35 SUSP35

G

RUNON

0.1U_0402_16V4Z

SYSON#

SYSON

1

1

C431

C432
10U_0805_10V4Z

2

2

+5VALW

12

R371
100K_0402_5%

13

D

Q24

2

G

2N7002_SOT23-3

S

Discharge circuit

R373
470_0402_5%

Q27
2N7002_SOT23-3

+1.8V

12

13

D

2

G

S

B

+5VS +3VS

12

470_0402_5%

13

D

SUSP SUSP SYSON# SUSP SUSP SUSP SUSP

2

G

S

A

R374

Q26
2N7002_SOT23-3

12

13

D

2

G

S

R375
470_0402_5%

Q28
2N7002_SOT23-3

+1.5VS

12

13

D

2

G

S

330K_0402_5%

SUSP

R376
470_0402_5%

Q29
2N7002_SOT23-3

B+

12

R369

13

D

2

G

S

SUSP#24,30,33,35,36SYSON28,30,35

+1.25VS +VCCP +0.9V

12

13

D

2

G

S

8

D

7

D

6

1

D

C430

5

D

AO4422_SO8

2

10U_0805_10V4Z

RUNON

12

Q23
2N7002_SOT23-3

R377
470_0402_5%

Q30
2N7002_SOT23-3

1

2

SUSP

SUSP#

2

G

12

13

D

2

G

S

Security Clas sification

Issued Date

THIS SHEET OF ENG INEE RIN G DR AWIN G IS T HE PRO PRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRE T INFO RMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COM PAL ELECTRON ICS, INC. NE ITHER THIS SHE ET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

U20

10U_0805_10V4Z

1

S

2

S

3

S

4

1

G

R370
470_0402_5%

C435

0.01U_0402_16V7K

+5VALW

12

R372
100K_0402_5%

13

D

S

R378
470_0402_5%

Q31
2N7002_SOT23-3

C

1

C433

C434

2

2

0.1U_0402_16V4Z

Q25
2N7002_SOT23-3

12

R379
470_0402_5%

13

D

Q32

2

G

2N7002_SOT23-3

S

2007/03/26 2006/07/26

Compal Secret Data

Deciphered Date

FM7

1

1

H24
HOLEA

FM9

FM8

1

H25
HOLEA

FM10

1

1

H26
HOLEC

1

1

For Card reader/B stand off.

D

C436

1 2

0.1U_0402_16V4Z

C437

+VCCP +1.5VS

H28
HOLEA

1

H1

H2

HOLEA

HOLEA

1

1

H11

H27

HOLEA

HOLEA

1

1

FM1

1

CF1

1

Title

Size Document Number Rev

Date: Sheet of

1 2

0.1U_0402_16V4Z

H29
HOLEA

1

H5

H6

H3

HOLEA

HOLEA

HOLEA

1

1

1

H16

H12

H15

HOLEC

HOLEA

HOLEC

1

1

1

FM2

1

1

FM4

1

CF3

CF2

1

1

Compal Electronics, Inc.

DC/DC Interface

LA-3981P

+VCCP+VCC_CORE

H9

H8

H7

HOLEA

HOLEA

HOLEA

1

1

H21

H18

H17

HOLEC

HOLEC

HOLEC

1

1

FM5

FM6

1

1

CF4

CF6

CF5

1

1

1

31 42Monday, October 22, 2007

E

H10
HOLEA

1

1

H23
HOLEC

1

1

CF7

CF8

1

0.3

A

1 1

2 2

B

C

D

VIN

PL1

PC1

12

SMB3025500YA_2P

1 2

12

PC2
1000P_0402_50V7K

12

12

PC4

PC3

1000P_0402_50V7K

100P_0402_50V8J

PCN1

1

1

2

2

3

3

4

4

5

5

ACES_88334-057N

ADPIN

100P_0402_50V8J

+3VALW

3 3

PQ38
TP0610K-T1-E3_SOT23

2

AC_LED 33

1 3

PR157

1 2

100_0402_5%

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAIN S CONFIDENTIA L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATI ON IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

<Issued_Date> <Deciphered_Date>

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Custom

Date: Sheet

DC CONN

LA-3981P

D

32 42Mo nday, October 22, 2007

of

A

1
2
36

4

PC6

PQ8
RHU002N06_SOT323-3

12

PR22
10K_0402_1%

3.2V

12

12

RLZ4.3B_LL34

P2

12

0.22U_0603_16V7K

1 2

PR146

1 2

1K_0402_5%

PR29
10K_0402_5%

PQ2

FDS6675BZ_SO8

1
2
3 6

12

PR4
200K_0402_5%

PR8
150K_0402_5%

IREF 30

PACIN

PR35
10K_0402_5%

1 2

4

MB39A126

12

PC15

0.01U_0402_25V7K

ACIN 3 0

PACIN 3 4

VIN

PR3

47K_0402_5%

1 1

2 2

12

PC26

0.047U_0402_16V7K

3 3

4 4

FSTCHG30

47K_0402_1%

1 2

VIN

12

PR23

2.15K_0402_1%

1 2

12

PR28

PR6

2

G

RHU002N06_SOT323-3

100K_0603_1%

PR27

10K_0603_0.1%

PC28

22P_0402_25V8K

13

D

S

PACIN

ACOFF#

12

+3VALW

2

G

PC5

1 2

47P_0402_50V8J

2

PQ6

1 2

3K_0402_5%

1 2

1SS355_SOD323-2

P2

12

8

3

P

+

2

-

G

4

1 2

49.9K_0402_1%

4

5

12

PR33

47K_0402_1%

13

D

PQ13
RHU002N06_SOT323-3

S

2

13

PQ5

DTC115EUA_SC70-3

PR11

PD5

PR18

1 2

681K_0402_1%

PR160
47_1206_5%

12

PC24

0.1U_0603_25V7K

PU2A

1

O

LM393DG_SO8

PR30

REF

CATHODE

ANODE

LMV431ACM5X_SOT23-5

2

G

12

1 3

P2

PU3

NC
NC

CS

13

D

PQ12
RHU002N06_SOT323-3

S

PQ1

FDS6675BZ_SO8

8
7

5

PQ4

DTA144EUA_SC70-3

13

D

2

G

S

PD4

1.24VREF

3
2
1

VIN

BATT_OVP30

8
7

5

PR12
10K_0402_1%

1 2

12

PR15

10K_0402_1%

1 2

PR21

150K_0402_1%

1

ADP_I30

12

PR16

12

PC17

0

B

PC11

0.22U_0603_16V7K

PC12
4700P_0402_25V7K

1 2

VREF

28.7K_0603_1%~D

MB39A126

0.22U_0603_16V7K

12

PR24

100K_0402_1%

+5VALW

12

8

3

P

+

2

-

G

4

PU4A
LM358ADT_SO8

PR19
1K_0402_1%

1 2

12

PC29

0.01U_0402_25V7K

1 2

PC22

BATT

PR9

10K_0402_5%

PR14
100K_0402_1%

PC18
2200P_0402_50V7K

1 2

0.1U_0402_10V7K

12

PR31

340K_0402_1%

12

PR32

499K_0402_1%

12

PR34

105K_0402_1%

P4

12

12

12

@RHU002N06_SOT323-3

PR7

1 2

0.02_2512_1%

PU1
MB39A126PFV-ER_SSOP24

1

-INC2

ADP_I_A

2

OUTC2

3

+INE2

4

-INE2

5

ACOK

6

VREF

7

ACIN

8

-INE1

9

+INE1

PR25
10K_0402_1%

12

10

OUTC1

11

SEL

12

-INC1

PR168

0_0402_5%

CV=12.6V (6/12 CELLS LI-ION)
CC=3.08A (6/12 CELLS LI-ION)

+3VALW

D

PQ37

12

S

PC30

0.01U_0402_25V7K

+INC2

GND

CS

VCC

OUT

VH

XACOK

RT

-INE3

FB123

CTL

+INC1

PR158

@100K_0402_5%

1 2

13

2

G

B+

24

23

22

21

20

19

18

17

16

15

14

13

+3VALW

PL2
SMB3025500YA_2P

1 2

PC16

0.1U_0603_25V7K

1 2

PR20
47K_0402_1%

1 2

PR26
33K_0402_1%

MB39A126

1 2

PC25
10P_0402_50V8J

PR159

@100K_0402_5%

1 2

MAINPWON34

CHG_B+

12

CS

1 2

C

12

PR13

0_0402_5%

PC13

0.22U_0603_16V7K

1 2

PC14

0.1U_0603_25V7K

1 2

PC23

1500P_0402_50V7K

1 2

BATT_DET38

RHU002N06_SOT323-3

D

PQ3
FDS6675BZ_SO8

8

1

7

2
3 6

5

4

CHG_B+

12

12

12

PC9

PC7

PC8

PC10

AC_LED32

4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0603_25V7K
2200P_0402_50V7K

16

243

PQ10

FDS4435BZ_SO8

578

PL3

16UH_SIL1045R-160_4.1A_30%

1 2

12

PD1

EC31QS04

PD2

FSTCHG

1 2

12

RB751V-40_SOD323-2
PD3

PR1

1 2

RB751V-40_SOD323-2

100K_0402_1%

PC27
47P_0402_50V8J

1 2

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

13

D

PQ39

2

G

S

SUSP# 24,3 0,31,35,36

7

PR167
47K_0402_1%

1 2

+5VALW

8

P

0

G

4

1000P_0402_50V7K

+3VLP

PACIN

RHU002N06_SOT323-3

PU4B
LM358ADT_SO8

5

+

6

-

PC132

ACOFF#

PR10
100K_0402_5%

2

G

PQ9

PR17

1 2

0.02_1206_1%

12

12

2

G

13

D

S

PR163

15K_0402_1%

1 2

150K_0402_1%

12

PR162
150K_0402_1%

13

D

S

1 2

PR164

PC19

BATT

PR5

1 2

VIN

47K_0402_5%

PR2
10K_0402_5%

1 2

13

PQ11
DTC115EUA_SC70-3

PQ7

@RHU002N06_SOT323-3

ACOFF 30

2

BATT

12

12

12

PC20

PC21

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M

+5VS

12

CPU

PH1

10K_TH11-3H103FT_0603_1%

+5VALW

12

PR161

12

2.55K_0402_1%

PC133

0.22U_0603_10V7K

AIR_AC30,38

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERT Y OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, IN C. NEITHE R THIS SHEET NOR THE INFORMATIO N IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PR IOR WRIT TEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number R ev

Custom

Date: Sheet

Monday, October 22, 2007

D

Charger

of

4233

A

B

C

D

E

PR46

@499K_0402_1%

PR154
100K_0402_5%

1 2

PC32

0.1U_0603_50V4Z

1 2

B++

12

PR42
0_0402_5%

1 2

PR47

0_0402_5%

1 2

ALW_PW RGD 20

PQ26
TP0610K-T1-E3_SOT23

1 3

PC36

2

2200P_0402_50V7K

12

PC37

DH_3.3V_B

4.7U_1206_25V6K

PR156

100K_0402_5%

1 2

578

3 6

578

241

3 6

241

+3VLP

PQ16
AO4468_SO8

PQ36
AO4468_SO8

12

PL6

10U_LF919AS-100M-P3_4.5A_20%

+3VALWP

PR54

1

1 2

+

@3.57K_0402_1%

PC43
220U_6.3VM_R15

2

PR58

1 2

0_0402_5%

PC31

B++

12

47K_0402_5%

12

VL

PC42

0.1U_0603_25V7K

0.1U_0603_50V4Z

578

PQ15
AO4468_SO8

3 6

241

578

PQ35
AO4468_SO8

3 6

241

PR55

499K_0603_1%

1 2

DH_5V_B

1 2

2VREF_1999

MAINPWON

12

12

PC46

0.047U_0603_16V7K

PR39

0_0402_5%

1 2

PR49

0_0402_5%

PR50

1 2

@0_0402_5%

1 2

PR52

@10K_0402_5%

2VREF_1999

MAINPWON 33

PQ17

13

D

RHU002N06_SOT323-3

S

1 2

2

G

PR41
0_0402_5%

1 2

BST_5V
DH_5V
LX_5V

DL_5V

PR56

300K_0402_5%

2

3

1

VL

1

PC40

2

4.7U_0805_10V4Z
PU5

14

BST5

16

DH5

15

LX5

19

DL5

21

OUT5

9

FB5

1

N.C.

6

SHDN#

4

ON5

3

ON3

12

SKIP#

8

REF

12

PC44

0.22U_0603_10V7K

VL

12

PR59
100K_0402_5%

13

D

2

G

PQ18

S

RHU002N06_SOT323-3

BST_3.3V_BBST_5V_B

PD6
CHP202UPT_SOT323-3

B++

12

0.1U_0603_50V4Z

PC38

18

20

13

V+

TON

LD05

GND

LDO3

23

25

1

PC45

2

4.7U_0805_10V4Z

PACIN 33

VL

PR40

1 2

47_0402_5%

12

PC39

1U_0805_16V7K

17

5

VCC

ILIM3

11

ILIM5

28

BST3

26

DH3

24

DL3

27

LX3

22

OUT3

7

FB3

2

PGOOD

PRO#

MAX8734AEEI+_QSOP28

10

+3VLP

PR57
0_0402_5%

1 2

13

D

S

RHU002N06_SOT323-3

12

PC35

0.1U_0603_16V7K

2VREF_1999

PR43
0_0402_5%

1 2

PR45

1 2

@499K_0402_1%

BST_3.3V
DH_3.3V
DL_3.3V2VREF_1999
LX_3.3V

2

G

PQ19

0_0402_5%

PR44

1 2

1 2

PL4

FBM-L11-322513-151LMAT_1210

B+

1 1

2 2

3 3

B++

12

12

PC33

2200P_0402_50V7K

10U_LF919AS-100M-P3_4.5A_20%

+5VALWP

PC41

1

2

220U_6.3VM_R15

12

PC34

10U_1206_25V6M

12

PL5

PR48

1 2

@10.2K_0402_1%

+

PR51

PR53

0_0402_5%

1 2

51ON#28

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAIN S CONFIDENTIA L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMATI ON IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRONIC S, INC.

<Issued_Date> <Deciphered_Date>

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

D

Date: Sheet

3.3VALWP / 5VALWP

Monday, October 22, 2007

of

E

4234

5

PL7

FBMA-L11-322513-151LMA50T_1210

B+

12

D D

PC47
680P_0402_50V7K

SYSON28,30,31

C C

B B

1 2

+5VALWP

1 2

+3VALWP

1 2

+1.8VP

1 2

+1.05V_VCCP

1 2

+1.5VSP

1 2

A A

+0.9VP

12

1 2

PR64

0_0402_5%

PJP1

PAD-OPEN 4x4m
PJP3

PAD-OPEN 4x4m
PJP5

PAD-OPEN 4x4m
PJP6

PAD-OPEN 4x4m
PJP7

PAD-OPEN 4x4m
PJP8

PAD-OPEN 3x3m

5

1.8V_B+

12

12

PC48

PC49

2200P_0402_50V7K

+5VALW

(3A,120mils ,Via NO.= 6)

+3VALW

(7A,280mils ,Via NO.= 14)

+1.8V

(6A,240mils ,Via NO.=12)

+VCCP

(6A,240mils ,Via NO.=12)

+1.5VS

(2A,80mils ,Via NO.= 4)

+0.9V

10U_1206_25V6M

@2200P_0402_25V7K

PC57

1U_0603_10V6K

4

12

12

1M_0402_5%

PR61

10_0402_5%

1000P_0402_50V7K

12

PC55

+1.25VSP

+3VLP +3VL

4

PR62

PC54

12

PR66

100K_0402_5%

1
2
3
4

1 2

2 1

+5VALW

12

PD7

1SS355_SOD323-2

12

1 2

BOOT_1.8V

16

PU6

TON

VOUT
VCCA
FB
PGD

NC5VSSA

TP

17

PJP2

PAD-OPEN 3x3m

PJP4

PAD-OPEN 2x2m

PR65

1 2

0_0402_5%

14

15

13

NC

BST

12

DH

EN/PSV

11

LX

10

ILIM

9

VDDP

PGND7DL

SC411MLTRT_MLPQ16_4X4

6

8

PR70

1 2

27K_0603_0.1%

1 2

PC60
33P_0402_50V8J

12

PR71
10K_0603_0.1%

(500mA,40mils ,Via NO.= 1)(4.5A,180mils ,Via NO.= 9)

+1.25VS

(100mA,20mils ,Via NO.= 1)

LX_1.8V

PR69

1 2

18.2K_0402_1%

BOOT1_1.8V

12

PC59
1U_0603_10V6K

1005_Add PR169 to separate V_DDR_MCH_REF from PU8.

V_DDR_MCH_REF7,13,14

3

1 2

PC56

0.1U_0402_16V7K

UG_1.8V

LG_1.8V

578

578

3 6

PQ21
AO4468_SO8

3 6

241

PQ22
FDS6690AS_NL_SO8

241

2

1UH_MPLC0730L1R0_10.6A_20%

1 2

12

PR68
@4.7_1206_5%

12

PC58

@680P_0603_50V7K

1 2

PR147

@0_0402_5%

SUSP#24,30,31 ,33,36

+1.8V

12

12

PC64

@10U_0805_10V4Z

PQ20

2

G

12

PC68
@0.1U_0402_16V7K

Compal Secret Data

13

D

S

Deciphered Date

12

PR72

1K_0402_1%

12

PR67
1K_0402_1%

2

PC63

10U_0805_10V4Z

PR169

1 2

@0_0603_5%

SYSON#27,31

SUSP31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERT Y OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRO NICS, INC.

3

1 2

PR73

@0_0402_5%

RHU002N06_SOT323-3

1 2

PR60

0_0402_5%

<Issued_Date> <Deciphered_Date>

PL8

1 2

PR148

0_0402_5%

PC127

@0.01U_0402_16V7K

2
3
4

12

12

PC67
10U_1206_6.3V7K

0.1U_0402_16V7K

PC66

PU13

7

POK

8

EN

12

APL5913-KAC-TRL_SO8

PU8

VIN1VCNTL
GND
VREF
VOUT

G2992F1U_SO8

+0.9VP

1

+1.8VP

1

12

12

+

PC51

PC52

PC50

2

220U_6.3VM_R15

0.1U_0402_16V7K

0.1U_0402_16V7K

+5VALW

12

PC126
1U_0603_6.3V6M

6

5

VIN

9

VIN

VCNTL

3

VOUT

4

VOUT

2

FB

GND

1

PR149

33.2K_0402_1%

PR150

59K_0402_1%

6
5

NC

7

NC

8

NC

9

TP

Title

Size Document Number R ev

Date: Sheet

+1.5VS

12

PC129
10U_1206_6.3V6M

+1.25VSP

12

PC130
22U_1206_6.3V6M

12

12

PC128
47P_0402_50V8J

12

+5VALW

12

PC65
1U_0603_16V6K

Compal Electronics, Inc.

1.8VP/0.9VSP/2.5VSP

LA-3981P

1

of

35 42Monday, October 22, 2007

0.3

5

PL9

FBMA-L11 -322513-151LMA50T_1210

1 2

B+

12

12

PC72

4.7U_1206_25V6K

1

+

PC75

1 2

2

PC71

@2200P_0402_50V7K

PL14

3.3UH_SIQB74B-3R3PF_5.9A_20%

12

PC76

4.7U_0805_6.3V6K

SUSP#24,30,31,33,35

PQ23

1

G2

D2

2

D2

D1/S2/K

3

G1

D1/S2/K

4

D1/S2/K

S1/A

SP8K10S FD5 2N SOP8

8
7
6
5

@1000P_0402_50V7K

D D

+1.5VSP

C C

220U_6.3VM_R15

B B

UG1_1.5V

PR87

0_0402_5%

PR79
0_0402_5%

1 2

PR83

PC77

0_0402_5%

12

1 2

0.1U_0603_25V7K

12

12

PC79

4

LG_1.5V

73.2K_0402_1%

1 2

PR80

1 2

0_0402_5%

BST_1.5V

UG_1.5V

LX_1.5V

1U_0603_10V6K

3

B+++

PR77

PR74

PR75

75K_0402_1%

1 2

0_0402_5%

PU9

25

P PAD

7

PGOOD2

8

EN2

9

VBST2

10

DR VH2

11

LL2

12

DR VL2

PR85

16.5K_0402_1%

1 2

12

3.3_0402_5%

PC80

PR76

29.4K_0402_1%

75K_0402_1%

1 2

1 2

PR78

1 2

1

6

4

2

5

3

VO1

VO2

GND

VFB1

VFB2

TONSEL

24

PGOOD1

23

EN1

22

VBST1

UG_1.05V

21

DR VH1

20

LL1

19

DR VL1

TRIP117V5FILT

V5IN16TRIP2

PGND1

PGND2

TPS51124RGER_QFN24_4x4

15

14

18

13

12

PR86

18.2K_0402_1%

12

PR88

+5VALWP

12

PC81

4.7U_0805_10V6K

PR81

0_0402_5%

BST_1.05V

LX_1.05V

LG_1.05V

12

PC131

1 2

@0.1U_0603_16V7K

VCCP_POK

PR82

0_0402_5%

1 2

PR84

0_0402_5%

1 2

1 2

0_0402_5%

12

PC82
@1000P_0402_50V7K

UG1_1.05V

PC78

1 2

0.1U_0603_25V7K

PR89

SUSP#

578

578

3 6

241

3 6

241

PQ24
AO4468_SO8

2.2UH_PCMC063T-2R2MN_8A_20%

PQ25

FDS6690AS_NL_SO8

PL10

1 2

4.7U_0805_6.3V6K

PC74

2

+1.05V_VCCP

1

12

+

2

1

12

12

PC69

PC70

10U_1206_25V6M

@2200P_0402_50V7K

PC73

220U_6.3VM_R15

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERT Y OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE T RANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRO NICS, INC.

3

Compal Secret Data

2006/11/23 2007/11/23

Deciphered Date

2

Compal Electronics, Inc.

Title

1.2V_VP/1.5VSP/1.05VP

Size Document Number R ev

Date: Sheet

LA-3981P

of

36 42Monday, October 22, 2007

1

0.3

5

4

3

2

1

+5VS

12

PR94

D D

10_0402_5%

12

PR95

13K_0402_5%

@470KB_0402_5%_ERTJ0EV474J

PH4

12

CPU_VID05
CPU_VID15
CPU_VID25
CPU_VID35
CPU_VID45
CPU_VID55

C C

VGATE15,20
CLK_EN#

VR_ON30

B B

CPU_VID65

DPRSLPVR7,20
H_DPRSTP#5,7,19

H_PSI#5

+3VS

1 2

PR123 0_0402_5%

1 2

PR122 0_0402_5%

1 2

PR125

0_0402_5%

H_PROCHOT#4

PR119

1.91K_0402_1%

1 2

POUT

12

PR98 0_0402_5%
PR100 0_0402_5%
PR97 0_0402_5%
PR102 0_0402_5%
PR104 0_0402_5%
PR103 0_0402_5%
PR106 0_0402_5%

1 2

PR110 499_0402_1%

1 2

PR112 0_0402_5%

1 2

PR111 0_0402_5%

12

PR117
2K_0402_1%

PR126
@10K_0402_5%

1 2

PR128 @0_0402_5%

1 2

PR129 10K_0402_5%

PC111

0.1U_0402_16V7K

1 2

12
12
12
12
12
12
12

12

PR108 88.7K_0402_1%

1 2

PC99 470P_0402_50V8J

1 2

PC100 0.22U_0603_16V7K

1 2

VCC

19

31
32
33
34
35
36
37

11
39
40

38

PC97

1U_0603_16V6K

PU12

Vcc

6

THRM
D0
D1
D2
D3
D4
D5
D6

7

TIME

9

CCV
REF
DPRSLPVR
DPRSTP

3

PSI

2

PWRGD

1

CLKEN
SHDN

5

VRHOT

4

POUT

MAX8770GTL+_TQFN40

VSSSENSE5

2.2U_0603_6.3V6K

VDD
TON

BST1

DH1

PGND1

GND
CSP1
CSN1

DH2
BST2

PGND2

CSP2
CSN2

GNDS

PC90

LX1
DL1

CCI

LX2
DL2

FB

41

1 2

25
8
30
29
28
26
27
18
17
16
12
10
21
20
22
24
23
14
15
13

TP

PC105

PR127

100_0402_5%

VSSSENSE

CSN2_CPU

12

1000P_0402_50V7K

BST1_CPU

DH11_CPU
LX1_CPU

DL1_CPU

CSP1_CPU
CSN1_CPU
FB1_CPU
CC1_CPU
DH2_CPU
BST2_CPU
LX2_CPU
DL2_CPU

CSP2_CPU

1 2

12

12

PR96

200K_0402_5%

PR99 0_0402_5%

PC91

0.01U_0402_25V7K

BSTM1 CPU

12

PC98

1 2

1 2

PR114 0_0402_5%

BSTM2 CPU

1 2

PC109

0.22U_0603_16V7K

0.22U_0603_16V7K

PR101 2.2_0603_5%

1 2

1 2

PR124

20K_0402_1%

PR130 2.2_0603_5%

1 2

PQ28

FDS6676AS_SO8

PR115 @3K_0603_1%

PR118 3.65K_0402_1%

1 2

NTC

PR120
@3K_0603_1%

5

4

1 2

1 2

5

PQ31

4

FDS6676AS_SO8

A A

THIS SHEET OF E NGINE ERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFI DENTIAL
AND TRADE SEC RET I NFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMP AL ELECTRONICS, IN C. NEITHER THIS SH EET NOR THE INFO RMATION IT CONTAI NS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WIT HOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

5

DL1_CPU

4

1 2

PR121

@3K_0603_1%

DL2_CPU

CPU_B+

PQ27
SI7840DP-T1-E3_SO8

3 5

241

D8D7D6D

PQ29

S1S2S3G

FDS6676AS_SO8

1 2

PC106

470P_0402_50V8J

3 5

241

5

D8D7D6D

S1S2S3G

4

2

12

12

4.7_1206_5%

PR107

12

PC101

680P_0603_50V7K

PC103 @0.022U_0402_16V7K

PR116 100_0402_5%

12

PC104
4700P_0402_25V7K

12

PC107

PQ30

10U_1206_25V6M

SI7840DP-T1-E3_SO8

12

4.7_1206_5%

PR131

PQ32

12

FDS6676AS_SO8

PC112

680P_0603_50V7K

PL11

1

12

PC95

PC92

100U_25V_M

10U_1206_25V6M

1 2

1 2

PR109

0.22U_0603_16V7K

12

PC93

10U_1206_25V6M

PL12

1 2

10KB_0603_5%_ERTJ1VR103J

1 2

PC102

+

2

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR105

2.1K_0603_1%

1 2

PD11

3.48K_0402_1%

B340A_SMA2

1 2

FBMA-L18-453215-900LMA90T_1812

12

PC94

2200P_0402_50V7K

NTC

PH2

12

+VCC_CORE

VCCSENSE

1 2

CPU_B+

12

12

PC108

PC110

2200P_0402_50V7K

10U_1206_25V6M

12

PR132

2.1K_0603_1%

1 2

PD12

B340A_SMA2

Title

Size Document Number R ev

Date: Sheet

PL13

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

NTC

PH3

1 2

PR133

3.48K_0402_1%

1 2

10KB_0603_5%_ERTJ1VR103J

1 2

PC113 0.22U_0603_16V7K

Compal Electronics, Inc.

+CPU_CORE

Custom

1

1

+

2

+VCC_CORE

37 42Monday, October 22, 2007

PC134

100U_25V_M

of

B+

12

PC96

1000P_0402_50V7K

VCCSENSE 5

0.3

A

B

C

D

12

PC123

0.01U_0402_50V4Z

BATT

PCN2

1 1

TYCO_C-1746706_6P

2 2

BATT+

6

EC_SMD

5

SMD

EC_SMC

4

SMC

3

RES

2

TS

1

GND

12

12

PR138

100_0402_5%

PR139
100_0402_5%

3
2

12

PR153
1K_0402_5%

BATT_DET 33

@1K_0402_5%

PR152

6.49K_0402_1%

1 2

PR151

12

PD8 @SM05_SOT23

1

+3VL

SMB_EC_DA1
SMB_EC_CK1

2

3

1

PD9
@SM24.TC_SOT23-3

BATT_TEMP 30

12

PC122
1000P_0402_50V7K

SMB_EC_DA1 29,30
SMB_EC_CK1 29,30

VINVIN

3 3

PC124

0.047U_0402_16V7K

12

PR165

133K_0402_1%

8

PU2B

5

1.24VREF

12

PR144

12

10K_0603_0.1%

P

+

7

O

6

-

G

LM393DG_SO8

4

PD10

PR141
10K_0402_1%

1 2

12

RLZ4.3B_LL34

12

PR166
10K_0402_5%

AIR_AC

AIR_AC 30,33

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC . AND CONTAIN S CONFIDENTIA L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRONIC S, INC.

B

<Issued_Date> <Deciphered_Date>

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

LA-3981P

BATTERY CONN

D

3842Monday, October 22, 2007

of

5

4

3

2

Version change list (P.I.R. List) Power section Page 1 of 1

1

D D

Item Reason for change PG# Modify List Date Phase

1

1009_PL8 change to 1uH.

2
3
4
5
6

C C

7
8
9
10
11
12
13
14

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DR AWING IS TH E PROPRIETARY PR OPERTY OF COMPAL ELECTRO NICS, IN C. AND CO NTAINS CON FIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE C OMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER T HIS SHEET NOR THE INFOR MATION IT C ONTAINS

5

4

MAY BE USED BY O R DISCLO SED TO ANY THI RD PARTY WITH OUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, IN C.

3

2006/02/28 2007/02/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Changed-List H istory-1

Size Document Number Rev

2

Date: Sheet

LA-3981P

1

0.3

of

39 42Monday, October 22, 2007

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

D D

1
2
3
4
5
6
7

8

9

10
11
12
13
14

C C

15
16
17
18

19

20
21
22
23
24 DB --> SI
25 DB --> SI
26 DB --> SI
27 DB --> SI
28 DB --> SI

B B

29 DB --> SI

Change item Page PhaseItem Date

Change C262 and C263 from 15pF to 12pF 19 7/16
Reserved R245 and Add R422 20 7/16
Add D29 prevent leakage issue 22 7/16
Reserved diode D30 D31 for ESD 26 7/16
Reserved R423 for coat down plan 24 7/24
Remove Q12~Q17,R323 R324 R327 R328 R417 R418 26 7/30
Change EXT MIC port B to port C 24 7/31

Same as IBL80 MV BOM

DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI

DB --> SI

DB --> SI

DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI
DB --> SI

DB --> SI

DB --> SI
DB --> SI
DB --> SI
DB --> SI

A A

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DR AWING IS TH E PROPRIETARY PR OPERTY OF COMPAL ELECTRO NICS, IN C. AND CO NTAINS CON FIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE C OMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER T HIS SHEET NOR THE INFOR MATION IT C ONTAINS

5

4

MAY BE USED BY O R DISCLO SED TO ANY THI RD PARTY WITH OUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, IN C.

3

2007/03/26 2007/02/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

HW Changed-Li s t History-1

Size Document Number Rev

2

Date: Sheet

LA-3981P

1

0.3

of

40 42Monday, October 22, 2007

5

4

Version Change List ( P. I. R. List ) for HW Circuit

3

2

1

D D

C C

1
2
3

4
5
6

For support Intel Penryn CPU.

7

For ESD request.

8

For EMI request.

9

Change C391, C393, C395, C396 from 0.47uF to 0.047uF.

10

Add R417 and R418 to fine-tune Vp-p.

11

For ESD request.

12
13
14
15
16
17
18
19
20

Change item Page PhaseItem Date

Change R296 R337 R value 2 4 Follow conexant new design rule 8/6
Add R424 R425 100ohm on MIC_EXT_R and MIC_EXT_L 26 Follow conexant new design rule 8/6
Change PIRQ from F to A 18

Connect PCI_SERR# to EC GPIO pin. 18

20Modify PC BEEP circuit. 8/31
04
28
26
26
26
20

Choose R419 then control PIRQ A
Connect PCI_SERR# to EC GPIO pin.

Modify PC BEEP circuit.
Reserve R426 and R427 for support Intel Penryn CPU.
Add U22 and U23 for ESD request.
Add L24~L27

Change C391, C393, C395, C396 from 0.47uF to 0.047uF.

Add R417 and R418 to fine-tune Vp-p.
Add U22 and U23 for ESD request.

8/14
8/31

9/3
9/3
9/5
9/7
9/7
9/7

SI --> PV
SI --> PV
SI --> PV

SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV

SI --> PV

21
22
23
24

25
26
27
28

B B

29
30
31 SI --> PV
32
33
34
35
36
37
38

SI --> PV
SI --> PV
SI --> PV
SI --> PV

SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV

SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV
SI --> PV

A A

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DR AWING IS TH E PROPRIETARY PR OPERTY OF COMPAL ELECTRO NICS, IN C. AND CO NTAINS CON FIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE C OMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER T HIS SHEET NOR THE INFOR MATION IT C ONTAINS

5

4

MAY BE USED BY O R DISCLO SED TO ANY THI RD PARTY WITH OUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, IN C.

3

2007/03/26 2007/02/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

HW Changed-Li s t History-1

Size Document Number Rev

2

Date: Sheet

LA-3981P

1

0.3

of

41 42Monday, October 22, 2007

5

4

3

2

1

Version Change List ( P. I. R. List ) for HW Circuit

Item Change item Page PhaseDate

1

Solve Vref miss when entry S3 mode.

2

D D

Solve wave ripple on CRT and TV.

3

Solve RTC timing too exceed. Change C262 and C263 from 12pF to 15pF.

4

Reduce INT.MIC noise.

5

Solve S3 resume fail when use Micron DDR module. 35 Add PR169 to separate V_DDR_MCH_REF from PU8. 10/05 PV --> MV

6

Solve pop noise when entry or resume from S3. 24 Modify PC Beep (C373, R302, R306) circuit. 9/27
7
8
9
10

Solve can not power on when stuff U22. Disconnect ON/OFFBTN# and ON/OFFBTN_LED# from U22.28 10/05
11

13 Change R64, R79, R81 from 0 ohm to 1uH/400mA inductor.10 10/22Solve acoustic noise issue.

C C

B B

7 Stuff R43 and R46.

10 Change C439 from 0.47uF to 4.7uF. 9/25
18 9/25
24 Add LPF (R429 and C452). 9/25

Change R34/R35 from 20 ohm to 30 ohm.Solve EMI fail for Memory module. 7 9/27
Change R329, R331, R333, R335 from 33 ohm to 27 ohm.28Fine-tune LED brightness. 9/27
Change R252 package from 0603 to 0805.ICH 1.5V power rail 700mA current requirement. 21 10/04

Change L2, L3, L4 to FBMA-L10-201209-121LMT_0805.For EMI request. 16 10/19
Change CLRP1 and CLRP2 type like the same as PJP4.To avoid too easy to open solder for CLRP2. 15 10/1912

9/25

PV --> MV
PV --> MV
PV --> MV
PV --> MV

PV --> MV
PV --> MV
PV --> MV
PV --> MV
PV --> MV
PV --> MV
PV --> MV
PV --> MV

A A

Security Classification

Issued Date

THIS SHEET OF ENGIN EERING DR AWING IS TH E PROPRIETARY PR OPERTY OF COMPAL ELECTRO NICS, IN C. AND CO NTAINS CON FIDENTI AL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE C OMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONI CS, INC. NEITHER T HIS SHEET NOR THE INFOR MATION IT C ONTAINS

5

4

MAY BE USED BY O R DISCLO SED TO ANY THI RD PARTY WITH OUT PRIOR WRITTEN C ONSENT OF C OMPAL ELECTR ONICS, IN C.

3

2007/03/26 2007/02/28

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

HW Changed-Li s t History-1

Size Document Number Rev

2

Date: Sheet

LA-3981P

1

0.3

of

42 42Monday, October 22, 2007