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The manual printing date and part number indicate its current edition. The printing
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Second Edition: May 2002
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This chapter provides detailed system specifications for the HP Workstation x2100:
•Introduces the system’s internal and external features
•Lists the system’s specifications and characteristic data
•Provides a summary of the available documentation
Chapter 1
13
Page 14
System Overview
Workstation Description
Workstation Description
The HP Workstation x2100 is based on the ATX form factor.Thefollowing table provides
an overview of the system.
System BoardDimensions: 12 in. X 9.6 in. in an Extended-ATX (E-ATX) package
ProcessorIntel Pentium 4 processor
FeatureDescription
Socket 423
Cache Memory
(integratedin processor
package)
Internal Processor
Clock Speed
ChipsetIntel I850 chipset, including Memory Controller Hub (MCH) Host Bridge,
Super I/O ChipNS 87364
Basic I/O System
(BIOS)
•Level 1: 16KB code, 16KB data
•Level 2: 256KB
1.7GHz, 1.9GHz, 2.2 GHz and higher speeds with a quad-pumped
100MHz Front Side Bus
Input/Output Controller Hub (ICH) for I/O subsystem
Based on Phoenix core, including:
•4 megabits of flash memory
•Support for PCI 2.2 specification
•Support for RIMM memory modules
Firmware - BIOSFlash EEPROM: Intel’s firmware hub concept
HP MaxiLife UtilityHardware-monitoring utility that monitors system components via the
SMBus and an LCD status panel
Operating SystemAll models come preloaded with a Windows OS.
Main MemoryTwo pairs of RIMM sockets, supporting two or four PC800 RDRAM
memory modules
Each pair of memory sockets must contain identical memory modules
(identical in size, speed, and type). That is, sockets A1 and B1 must
contain identical modules, and sockets A2 and B2 must contain identical
modules (or continuity modules).
14
If only twoRDRAM modules are installed, use the socketsmarked A1 and
B1. The other two sockets (A2 and B2) must contain continuity modules.
Models are supplied with non-ECC RDRAM modules.
Both ECC and non-ECC modules are available.
The HP PC Accessories Web site, at
•Two front-access, third-height 3 1/2-inch drives (one for the floppy
disk drive and one free) (1-inch height)
•Three front-access, half-height, 5 1/4-inch drives (1-inch height); you
can use an adapter tray (available as an accessory) to install two 3
1/2-inch hard disk drives in one of the 5 1/4-inch shelves.
•Two internal 3 1/2-inch hard disk drives (1-inch height)
SCSI ControllerAdaptec Ultra 160 SCSI PCI card (optional).
IDE ControllerAll models include an integrated Ultra ATA-100 controller that supports
as many as four IDE devices.
Graphics Controllers
•nVIDIA Quadro2 MXR with TwinView or nVIDIA Quadro Pro
nVIDIA Quadro2 Ex
ATI FireGL 8800
•Matrox Millennium G450-DualmonitorAGP graphics controller with
16MB SGRAM graphics memory (maximum configuration)
•ATI FireGL2 or GL4 3D Graphics Card
Accessory Card SlotsOne AGP Pro Universal 4X 32-bit slot supporting:
•1.5V AGP cards (£25W)
•1.5V AGP Pro Cards (£50W)
The system doesn’t support high-power (i.e., greater than 50W) AGP Pro
and 3.3V AGP cards.
Five 32-bit 33MHz Peripheral Component Interconnect (PCI) slots,
supporting all bridges and multifunction PCI devices. All five PCI slots
comply with PCI Specification 2.2.
•PCI slot 5 contains a LAN interface board.
•PCI slot 4 is for a SCSI interface board (some models only).
LAN CardLan is now integrated onto the system board. All x2100 models come with
an HP 10/100BT PCI Ethernet Adapter LAN card supporting Wake-On
LAN 9WOL) and PCI Specification 2.2.
Optical DrivesModels include one or two of the following IDE drives: CD-ROM, CD-RW,
or DVD-ROM.
Chapter 1
AudioCrystalClear CS4299 Audio Codec 97 version 2.1 is integrated on the
system board.
15
Page 16
System Overview
Workstation Description
FeatureDescription
System Board
Connectors
Rear Connectors
(color coded)
•One flexible disk drive connector
•Two ATA-100 IDE connectors (for as many as four IDE devices)
•One CD-IN audio connector
•Internal speaker connector
•WOL connector
•Battery socket
•Status panel connector
•Main power supply connector and ATX 12V power connector
•Auxiliary power connector (MT models only)
•Main chassis fan connector
•Processor fan connector
•PCI card fan connector
•Chassis intrusion connector
•Thermal sensor connector
•Keyboard/Mouse
— HP enhanced keyboard with mini-DIN connector
— HP enhanced scrolling mouse with mini-DIN connector
•25-pin parallel
— Mode: Centronics or bidirectional modes (ECP/EPP)
— Parallel port: 1 (378h, IRQ 7), 2 (278h, IRQ 5), or Off
•9-pin serial (two, buffered)
— Standard: Two UART 16550 buffered serial ports
(both RS-232-C).
— Serial Ports A and B: 2F8h (IRQ 3), 2E8h (IRQ 3),
3F8h (IRQ 4), 3E8h (IRQ 4), or Off
(if one port uses 2xxh, the other port must use 3xxh).
•Dual USB connectors
•Audio
— LINE IN jack (3.5mm)
— LINE OUT jack (3.5mm)
— MIC IN jack (3.5mm)
16
Chapter 1
Page 17
Internal And External Components
Figure 1-1 and Figure 1-2 show the front and rear views of the HP Workstation x2100.
Figure 1-1Front and Side Views
Power Supply
Main Fan
Spare mounting rails:
- Wide green rails for
5.25-inch devices (for
example, Zip drive)
- Narrow green rails for
3.5-inch devices
- Blue rails for 3.5-inch
hard disk drives
System Overview
Internal And External Components
Front access
shelves:
- three 5 1/4-inch
drive shelves (can
be used for optical
drives or a 3
1/2-inch tray kit–
available as
accessory)
- two 3 1/2-inch
shelves, including
a 1.44MB floppy
disk drive
Secondary Hard Disk
Drive Shelf
Primary Hard Disk
Drive Shelf
Figure 1-2Rear View
Line Out (headphone) connector
Line In connector
Microphone connector
Keyboard
connector
Serial port A
Serial port B
Dual USB connectors
MaxiLife
Status Panel
HP MasterKey
Lock
Mouse
connector
Parallel port
Chapter 1
Display connector
17
Page 18
System Overview
Internal Features
Internal Features
The core architecture of the HP Workstation x2100 consists of:
•Memory Controller Hub (MCH)
•Input/Output Controller Hub (ICH)
•Host bus
The HP Workstation x2100 supports a Pentium 4 processor. For information about this
processor, see page 58.
For information about...Refer to...
System board componentsChapter 2
HP BIOS routinesChapter 3
Tests and error messages including Power On Self Test
(POST) routines
Graphics, network and SCSI devices, and mass storage
devices
Accessories Installation and Parts ReplacementChapter 6
Use or configuration problemsChapter 7
Troubleshooting and RecoveryChapter 7
Contacting supportChapter 7
Chapter 4
Chapter 5
18
Chapter 1
Page 19
Front Panel
The HP Workstation x2100’s front panel has the following features:
•Liquid Crystal Display (LCD). For information about LCD error messages and
available menus, see page 77.
•On/Off LED. The LED displays four states:
— Blank: Indicates that the computer is turned off.
— Green: Indicates that the computer is turned on and running correctly.
— Red (fixed or flashing): Indicates a preboot or a POST error that is preventing
the system from booting.
— Amber: Displayed during system reset, system lock.
•Hard disk drive activity LED. Activated during POST and during hard disk drive
access.
Figure 1-3Front Panel
System Overview
Front Panel
Reset
Button
Hard Disk
Activity Light
LCD Control
Buttons
Power On/Off
Button
Chapter 1
19
Page 20
System Overview
Specifications And Characteristics
Specifications And Characteristics
Physical Characteristics
System Processing Unit
Weight: (Standard
configuration as shipped,
excluding keyboard and
display)
Dimensions47.0cm max. (D) X 21.0cm (W) X 49.0cm (H)
Footprint0.09 square meters (1.06 square feet)
Electrical Specifications
14.4 kilograms (31.68 pounds)
(18.50 inches X 8.26 inches X 19.29 inches)
Maximum
Peak
ParameterTotal Rating
Input voltage
(Switch select)
Input current
(max)
Input frequency50 to 60 Hz—————
Available power492 W—100W for PCI slots and AGP Pro slot
Max current at
+12 V
Max current at
-12 V
Max current at
+3.3V
b
Vddq
Max current at
+5V
Max current at
-5V
Max current at
+5V stdby
combined with
3.3V stdby
100-127
V VAC
5.5 A2.5 A—————
15 A15 A0.5 A1 A4.2 A5.2 A
0.8 A—0.1 A———
28 A—7.6 A6 A7.6 A13.6 A
———2 A
30 A—5 A2 A
0.0 A—————
2 A—1.875 A total on 3.3V stdby
200-250
V VAC
(15
secs.)
——— ——
per PCI
Slots
32-bit
33MHz
Maximum for AGP Slot
Standard
Connector
ExtensionTotal
a
20
a. The system can draw a maximum of 50W from the AGP Pro slot. The standard part
of the AGP Pro connector supplies 25W (max.), plus 25W from the connector
extension (25W + 25W = 50W). For information about the AGP Pro Universal slot,
see page 33.
b. Only for I/O buffers.
Chapter 1
Page 21
System Overview
Specifications And Characteristics
If an overload triggers the power supply’s overload protection, all power is immediately
cut. To reset the power supply unit:
1. Disconnect the power cord.
2. Determine what caused the overload, and fix the problem.
3. Reconnect the power cord, and reboot the workstation.
If an overload occurs twice, then there is an undetected short circuit somewhere.
When you use the front panel's power button to turn off the workstation, power
consumption falls below the low power consumption (refer to the table on page 21), but
doesn't reach zero. This on/off feature extends the power supply's lifetime. To reach zero
power consumption in “off” mode, either unplug the workstation or use a power block
with a switch.
Power Consumption And Cooling
The power consumption and acoustics listed in the following table are valid for a
standard configuration as shipped (one processor, 256MB of memory, 492 W power
supply, one hard disk drive, graphics card, LAN card).
All information in this section is based on primary power consumptions.
Power consumption (approximate
values)
•Typical operating mode
•Suspend mode (Windows 2000
models only)
230V/50Hz and 115V/60Hz
70W
<4W
a. 1W = 3.4121Btu/h
Additional Component
•Processor
50W
- 170.6Btu/h
•SCSI harddisk drive with I/O
access
23W
- 78.4Btu/h
•SCSI hard disk without I/O
access (idle)
•PCI card
16W
10W to
36W
- 54.5Btu/h
- 64.1Btu/h to
122.8Btu/h
- 238.8Btu/h
- 13.6Btu/h
a
Chapter 1
21
Page 22
System Overview
Specifications And Characteristics
Environmental Specifications
Environmental Specifications (System Processing Unit with Hard Disk)
Operating Temperature+10 ˚C to +35 ˚C (+40 ˚F to +95 ˚F).
Storage Temperature-40 ˚C to +70˚C (-40 ˚F to +158 ˚F).
Over-Temperature Shutdown+50˚C (+122˚F)
Operating Humidity
Storage Humidity8% to 85% (relative).1
Acoustic noise emission(asdefined in ISO
7779):
•Operating
•Operating with hard disk access
15% to 80% (relative).
Sound Power
LwA <= 40.5dB
LwA <= 41.4dB
a
Sound Pressure
LpA <= 25.7dB
LpA <= 26.5dB
•Operating with floppy disk access
Operating Altitude10,000ft (3100m) max
Storage Altitude15,000ft (4600m) max
LwA <= 43.2dB
LpA <= 30.0dB
a. noncondensing conditions.
Operating temperature and humidity ranges may vary depending on the installed mass
storage devices. High humidity levels can cause improper disk operation. Low humidity
levels can aggravate static electricity problems and cause excessive wear of the disk
surface.
22
Chapter 1
Page 23
System Overview
Power Saving And Ergonometry
Power Saving And Ergonometry
Depending on the operating system, the following power-management types are
available:
•No sleeping state: Windows NT 4.0 (Full On and Off).
•ACPI: Windows 2000 or XP (Full On, Standby, Hibernate, Off).
Windows
2000/XP
Full On
A
SuspendNot Supported by
P
M
OffSupported
Standby (S1
or S3)
A
C
P
I
Hibernate
(S4)
Off (S5)Supported
Not Supported
by Windows 2000
Supported
(implemented as
S3, Suspend to
RAM)
Supported
Windows NT 4.0
Supported
Windows NT 4.0
APM
only
Operating
System
Power Saving And Ergonometry For APM Systems
Full On
ProcessorNormal speedHaltedHalted
DisplayOnBlanked, <5W (typ)Blanked, <5W (typ)
Hard disk driveNormal speedHaltedHalted
Suspend
a
Off
Chapter 1
Power
consumption
Resume eventsKeyboard, network
Resume delayA few secondsBoot delay
Supports up to
320W
<40W (230V, 50Hz)
<21W (115V, 60Hz)
(RWU), modem, USB
(plugged inbut turned
off) <5W (average)
Power button or RPO
a. Not supported by Windows NT 4.0.
Power Saving Modes And Resume Events For ACPI Systems
Full On
(S0)
ProcessorNormal
speed
DisplayOnBlankedOffOffOff
Suspend (S1)Suspend to
RAM (S3)
HaltedOffOffOff
Suspend to
Disk (S4)
Off (S5)
23
Page 24
System Overview
Power Saving And Ergonometry
Full On
(S0)
Hard Disk
Drive
Active Power
Planes
Power
Consumption
Resume EventsPower button,
Resume DelayInstantaneousInstantaneousBIOS boot
Normal
speed
VCC
VCCAux
Supports
up to 492W
Suspend (S1)Suspend to
RAM (S3)
HaltedOffOffOff
VCC
VCCAux
<40W<10W<10W<10W
LAN, Modem,
USB, Scheduler
Memory
VCCAux
Power button,
LAN, Modem,
Scheduler
Suspend to
Disk (S4)
VCCAuxVCCAux
Power button,
LAN, Modem,
Scheduler
delay
Soft Power Down
When you shut down the operating system, the environment is cleared, and the
computer is powered off. The Soft Power Down utility is available with Windows NT.
Off (S5)
Power
button
Regular
boot delay
24
Chapter 1
Page 25
System Overview
Documentation
Documentation
The following table lists the documentation available for the HP Workstation x2100.
Only selected publications are in hard-copy format. Most are available as PDF files from
the HP Web site.
Title
HP Workstation x2100
Getting Started Guide
HP Workstation x21000
Technical Reference And
Troubleshooting Guide
Available at
HP Web site
PDF fileA8030-90001
PDF fileNo
Hard-copy?
Access HP World Wide Web Site
Additional online support documentation, BIOS upgrades, and drivers are available
from HP’s Web site at http://www.hp.com/go/workstationsupport.
After accessing the site, select HP Workstation x2100.
Chapter 1
25
Page 26
System Overview
Documentation
Where To Find The Information
The table below summarizes information provided in the HP Workstation x2100
documentation set.
Figure 2-3 shows the position of the accessory board slots on the system board.
Figure 2-3Accessory Board Slots
One 1.5V AGP slot
System Board
Accessory Board Slots
PCI Slot 1
Five 32-bit 33
MHz PCI slots
Accelerated Graphics Port Slot
The HP Workstation x2100 has one Accelerated Graphics Port (AGP) graphics slot.
Figure 2-4AGP Slot
The AGP Pro 1.5V slot provides graphics performance for high-end graphics cards,
combining AGP 4X bandwidth (data transfer rates as fast as 1056MB/sec) with the
ability to accept high-end graphics cards drawing up that draw as much as 110W of
power.
PCI Slot 2
PCI Slot 3
PCI Slot 4
PCI Slot 5
Chapter 2
Toaccommodate AGP Pro cards, the AGP PRO slot connector is wider than the standard
AGP 4X connector. To meet the increased power requirements of AGP Pro graphics
cards, additional pins are present at both ends of the connector.
An AGP Pro card may draw power either from the existing part of the AGP Pro
connector, the extended part, or a combination of the two. In all cases, the maximum
power that an AGP Pro card may draw is limited to 110W in the workstation models.
Power on the existing part of the connector is delivered on 5.0V and 3.3V rails. Power on
the extension is delivered on the 12V and 3.3V rails.
You can use either standard AGP graphics cards or AGP Pro graphics cards that draw
less than 50W of power. (Below 25W, you can use a standard AGP connector.) Power is
provided through 3.3V, 5V, or 12V power rails.
33
Page 34
System Board
Accessory Board Slots
NOTEAGP Pro graphics cards that draw more than 50W and AGP 3.3V graphics cards cannot
be used in the workstation’s AGP slot.
The AGP Pro 1.5V slot is backward compatible with both AGP 1x and 2.x modes (using
1.5V signalling) and AGP 4x mode (where 1.5V signalling is necessary).
For information about the AGP interface and bus, see page 41.
Peripheral Component Interconnect Slots
The system board contains five 32-bit, 33MHz Component Interconnect (PCI)
connectors.
Figure 2-5PCI Slots
The PCI slots accept 3.3V and 5V PCI 32-bit 33MHz cards, and Universal PCI cards
(which are 3.3V or 5V compatible). Refer to the table on page 34 for the different PCI
board installations.
The maximum supported power consumption per slot is 25W, either from the 5V or the
3.3V supply. The power consumption must comply with the electrical specifications of the
PCI 2.2 specification. Total power consumption for the PCI slots must not exceed 60W.
The power consumption of each PCI board is automatically reported to the system
through the two presence-detect pins on each PCI slot. These pins code the following
cases:
•No accessory board in the PCI slot
•7W maximum PCI board in the PCI slot
•15W maximum PCI board in the PCI slot
•25 maximum PCI board in the PCI slot
The following table shows the various PCI board installations for the different PCI slots:
PCI Card
3.3V and 5VUniversal (3.3V or 5V compatible)
PCI Slot32-bit/
33MHz
Slots 1, 2, 3, 4, and 5
5V, 32-bit/33MHz
yes
64-bit/
33MHz
a
yes
32-bit/
33MHz or 66MHz
yesyesyes
64-bit/
33MHz or 66MHz
yes
b
34
a. You can install a 64-bit card in a 32-bit slot. However, this card will only
operate in 32-bit mode.
Chapter 2
Page 35
System Board
Accessory Board Slots
b. You can install a 66Mhz card in a 33MHz slot. However, this card will only
operate in 33MHz mode.
The system board and BIOS support the PCI 2.2 specification. This specification
supports PCI-to-PCI bridges and multifunction PCI devices, and each of the five PCI
slots have master capabilities.
The PCI slots are connected to the ICH2 PCI 32-bit 33MHz bus.
Chapter 2
35
Page 36
System Board
System Board Switches
System Board Switches
There Are 10 System Board Switches Used For Configuration. You Should Not Modify
The Settings Of Reserved Switches 1 - 5; Modification Of These Switches Can Lead To
System Failure.
Switch
1-4OFFReserved. Do not change default settings.
5ONReserved. Do not change default setting.
6ONEnables keyboard power-on.
7OFFEnables normal modes.
8OFFRetains CMOS memory.
9OFFEnables User and System Administrator
10OFFChassis type
Default
Position
Use
OFF disables this option.
ON enables the BIOS recovery mode at next
boot.
ON clears CMOS memory at next boot.
passwords.
ON clears the passwords at next boot.
OFF = desktop, ON= minitower
36
Chapter 2
Page 37
ICH2
System Board
System Chipset
System Chipset
The Intel I850 chipset is a high-integration chipset designed for graphics/multimedia PC
platforms and is comprised of the following:
MCH
•The 82850 MCH is a bridge between the:
— System bus
— Dual Rambus bus (main memory)
— AGP 4x (graphic) bus
— Hub link 8-bit
For detailed information about the MCH chip feature, see page 38.
•The 82801BA ICH2 is a bridge between the 32-bit, 33MHz PCI bus and the SMBus.
Additionally, the ICH2 supports the:
— integrated IDE controller (Ultra ATA/100)
— enhanced DMA controller
— USB controller
— interrupt controller
— Low Pin Count (LPC) interface
— FWH interface
— Integrated LAN
— ACPI Power Management Logic
— AC’97 2.1 Compliant Link
— Alert-On-LAN (AOL) and Real Time Clock (RTC)
— CMOS
For detailed information about the ICH2, see page 44.
•The 82802AB FWH stores system BIOS and SCSI BIOS (i.e., the nonvolatile
memory component). In addition, the FWH contains an Intel Random Number
Generator (RNG). The RNG provides random numbers to enable fundamental
security building blocks for stronger encryption, digital signing, and security
protocols for the workstation. For detailed information about the FWH, see page 56.
Chapter 2
37
Page 38
System Board
Memory Controller Hub (82850)
Memory Controller Hub (82850)
The MCH host bridge/controller is contained in a 615-pin Organic Land Grid Array
(OLGA) package and is the bridge between the system bus, Dual Rambus bus (main
memory), AGP 4x (graphic), and Hub Link 8-bit.
Figure 2-6 shows an example of the system block diagram using the MCH.
Figure2-6System Block Diagram using MCH
Address (36)
Control
Data (64)
1.5V
AGP
PRO
connector
Socket 423
AGP 4x Bus
133MHz (1 GB
MB/s data transfer
rate)
Intel Pentium IV
Processor
I850 Memory
Controller Hub (MCH)
82850
AGP
Inter-
face
I/O Controller Hub2
(ICH2) 82801BA
Memory
Controller
HUB LINK 8
(266MB/sdata
transfer rate)
100MHz two-way system bus
(Data Busruns at4 x 100MHz,
3.2GB/s transfer rate)
Dual Rambus
3.2GB/s at400MHz
data transfer rate
Four onboard
RIMM sockets
supporting
RDRAM
memory
38
Chapter 2
Page 39
System Board
Memory Controller Hub (82850)
The following table shows the features that the MCH host bridge/controller offers.
FeatureFeature
•Processor/system bus:
— Supports Pentium IV processor at
100MHz systembus frequency (400MHz
data bus)
— Provides an eight-deep In-Order Queue
that supports as many as eight
outstanding transaction requests on the
system bus
— Desktop optimized AGTL+ bus driver
technology with integrated AGTL +
termination resistors
— Support for 32-bit system bus address
•Memory Controller
Direct Rambus:
•Accelerated Graphics Port (AGP) interface:
— Single 1.5V AGP Pro connector
— AGP 2.0 compliant, including AGP 4x
data transfers and 2x/4x Fast Write
protocol
— AGP 1.5V connector support with 1.5V
signalling only
— AGP PIPE# or SBA initiated accesses to
DRAM is not snooped
— AGP FRAME initiated accesses to
DRAM are snooped
(snooper identifies that data is coherent
in cache memory)
— Hierarchical PCI configuration
mechanism
— Delayed transaction support for
AGP-to-DRAM reads that cannot be
serviced immediately
•As many as 64 Direct Rambus devices
•Dual Direct Rambus Channels operating in
lock-step (both channels must be populated
with a memory module).
Supporting 300MHz or 400MHz
•RDRAM 128Mbit and 256Mbit devices
•Minimum upgrade incrementof32MB using
128Mbit DRAM technology
•Hub Link 8-bit interface to ICH2:
— High-speed interconnect between the
MCH and ICH2 (266MB/sec)
•Dual-channel maximum memory array size
is:
— 1GB using 128Mbit DRAM technology
— 2GB using 256Mbit DRAM technology
•As many as eight simultaneous open pages:
— 1KB page size support for 128Mbit and
256Mbit RDRAM devices
— 2KB page size support for 256Mbit
RDRAM devices
Chapter 2
39
Page 40
System Board
Memory Controller Hub (82850)
FeatureFeature
•Power management:
— SMRAM space remapping to A0000h -
BFFFFh (128KB).
— Extended SMRAM space above 256MB,
additional 128KB, 256KB, 512KB, 1MB
TSEG from top of memory, cacheable
(cacheability controlled by processor)
•Arbitration:
— Distributed arbitration model for
concurrency support
— Concurrent operations of system, hub
interface, AGP, and memory buses
supported through a dedicated
arbitration and data-buffering logic
— ACPI 1.0 compliant power management
— APM 1.2 compliant power management
The MCH provides the processor interface, memory interface, AGP interface and hub
interface in an Intel 850 chipset platform. The MCH supports two channels of Direct
RDRAM operating in lock-step. It also supports 4x AGP data transfers and 2x/4x AGP
fast writes. The primary host interface enhancements include:
•Source synchronous double pumped address
•Source synchronous quad pumped data
•System bus interrupt delivery
The MCH supports a 64B cache line size. One processor is supported at a system bus
frequency of 100 MHz (400 MHz Data Bus). It supports 32-bit host addresses, letting the
processor address the entire 4GB space of the MCH’s memory address space. The MCH
also provides an eight-deep In-Order Queue that supports as many as eight outstanding
pipelined address requests on the host bus.
Host-initiated I/O signals are subtractively decoded to the hub interface. Host-initiated
memory cycles are positively decoded to AGP or RDRAM and are again subtractively
decoded to the hub interface.
AGP semantic memory accesses initiated from AGP to DRAM are not snooped on the
host bus. Memory accesses initiated from AGP using PCI semantics and accesses from
the hub interface to DRAM are snooped on the system bus. Memory access whose
addresses lie within the AGP aperture are translated using the AGP address translation
table, regardless of the originating interface.
Accelerated Graphics Port (AGP) Bus Interface
A controller for the AGP Pro 1.5V slot is integrated in the MCH. The AGP interface
supports 1x/2x/4x AGP signaling and 2x/4x fast writes. AGP semantic cycles to the
DRAM are not snooped on the host bus. PCI semantic cycles to DRAM are snooped on
the host bus. The MCH supports PIPE# or SBA{7.0} AGP address mechanisms, but not
both simultaneously. Either the PIPE# or the SBA{7.0] mechanism must be selected
during system initialization. Both upstream and downstream addressing is limited to
40
Chapter 2
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System Board
Memory Controller Hub (82850)
32-bit for AGP and AGP/PCI transactions. The MCH contains a 32-deep AGP Requests
queue. High priority accesses are supported. All accesses from the AGP interface that
fall within the graphic aperture address range pass through an address translation
mechanism with a fully associative 20 entry TLB. Accesses between AGP and the hub
interface are limited to memory writes originating from the hub interface for the AGP
bus.
The AGP interface is clocked from a dedicated 66 MHz clock (661N). The
AGP-to-host/core interface is asynchronous. The AGP buffers operate only in 1.5V mode.
They are not 3.3V safe.
Hub Interface
The 8-bit hub interface connects the MCH to the ICH2. Most communications between
the MCH and the ICH2 occur over this interface. The hub interface runs at 66 MHz/266
MB/s.
The hub interface’s supported traffic types include: hub interface-to -AGP memory
writes, hub interface-to-DRAM, processor-to-hub interface, messaging (MSI interrupt
messages, power management state change, MI, SCI, and SERR error indication). It is
assumed that the hub interface is always connected to an ICH2.
RDRAM Interface
The MCH directly supports two channels of Direct RDRAM memory operating in
lock-step using RSL technology. These channels run at 300 MHz and 400MHz and
support 128 Mb and 256 Mb technology RDRAM Direct devices. These 128 Mb and 256
Mb RDRAMs use page sizes of 1 Kb, while 256 Mb devices may also be configured to use
2 Kb pages. A maximum of 64 RDRAM devices are supported on the paired channels
without external logic (128Mbit technology implies 1GB maximum in 32MB increments,
whereas 256Mbit technology implies 2GB maximum in 64MB increments).
The MCH also provides optional ECC error checking for RDRAM data integrity. During
DRAM writes, ECC is generated on a QWord(64-bit)basis.DuringDRAMreads,andthe
read of the data that underlies partial writes, the MCH supports detection of single-bit
and multiple-bit errors, and will correct single-bit errors when correction is enabled.
RDRAM Thermal Management
The relatively high power dissipation needs of RDRAM necessitate a MCH mechanism
capable of putting a number of memory devices into a power-saving mode to keep an
inadequately cooled system from overheating. RDRAM devices may be in one of three
power-management states: active, standby or “nap.” The MCH implements the RDRAM
nap mode.
Two queues are used in the MCH to control power consumption: the A queue contains
references to device pairs that are currently in the active mode while the B queue
contains references to devices that are in the standby mode. This means that all devices
that are in neither queue are in standby or napping. The A queue can hold from 1 to 8
device pairs, while the B queue can be configured to contain between 1 and 16 device
pairs. This allows power consumption to be tuned.
Chapter 2
The MCH also implements a mode in which all devices are turned on and it is assumed
that the system will provide adequate cooling. This means that all devices that are in
neither queue A or B are in standby mode. One fail-safe mechanism is supported that
41
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System Board
Memory Controller Hub (82850)
protects the RDRAM devices from thermal overload. This mechanism polls the thermal
indicator bits in the RDRAM devices themselves. When the mechanism is activated, the
MCH immediately exits the “all devices on” mode and reverts to whatever queue mode
has been programmed by system software.
Dual Rambus Bus
The Dual Rambus bus is comprised of 16 x 2 bits of data information, and eight bits of
Error Correcting Code (ECC). The bus is connected to the RIMM memory slots and to
the MCH chip so that the system supports two Dual Rambus channels (A and B).
Both channels run at 300MHz or 400MHz, supporting as many as 32 Rambus devices
per channel. The maximum available data bandwidth is 3.2GB/s at 400MHz.
The configuration of both primary rambus channels must be symmetrical. The memory
configuration on channel A must be identical to the memory configuration on channel B.
This means that you must install the memory in identical pairs.
RIMM Memory Slots
The HP Workstation x2100 has four RIMM memory sockets for installing two or four
RDRAM memory modules:
•RIMM A1
•RIMM A2
•RIMM B1
•RIMM B2
Figure 2-7RIMM Memory Slots
Each pair of memory sockets must contain identical memory modules (identical in size,
speed, and type). That is, sockets A1 and B1 must contain identical modules, and sockets
A2 and B2 must contain identical modules (or continuity modules).
If you install only two RDRAM modules, use the sockets marked A1 and B1. The other
two sockets (A2 and B2) must contain continuity modules.
Each RIMM socket is connected to the SMBus.
Read/Write Buffers
42
The MCH defines a data-buffering scheme to support the required level of concurrent
operations and provide adequate sustained bandwidth between the DRAM subsystem
and all other system interfaces (CPU, AGP, and PCI).
Chapter 2
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System Board
Memory Controller Hub (82850)
System Clocking
The MCH has the following clock input pins:
•Differential BCLK0/BCLK1 for the host interface
•66 MHz clock input for the AGP and hub interface
•Differential CTM/CTM# and CFM/CFM# for each of the two RAC’s.
Clock synthesizer chip(s) are responsible for generating the system host clocks, AGP and
hub interface clocks, PCI clocks and RDRAM clocks. The MCH provides two pairs of
feedback signals to the Direct Rambus Clock Generator (DRCG) chips to keep the host
and RDRAM clocks aligned. The host speed is 100 MHz. The RDRAM speed is 300 MHz
or 400 MHz. The MCH does not require any relationship between the BCLK host clock
and the 66 MHz clock generated for AGP and hub interfaces; they are totally
asynchronous from each other. The AGP and hub interfaces run at a constant 66 MHz
base frequency. The hub interface runs at 4x. AGP transfers may be 1x/2x/4x.
Chapter 2
43
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System Board
Input/output Controller Hub 2 (82801BA)
Input/output Controller Hub 2 (82801BA)
The ICH2 is encapsulated in a 360-pin Enhanced Ball Grid Array (EBGA) package and
resides on the system board just underneath the AGP connector.It provides the interface
between the PCI bridge (PCI 2.2 compliant with support for 32-bit 33MHz PCI
operations),
PCI-to-Low Pin Count (LPC) bridge, IDE controller, USB controller, SMBus controller,
and Audio Codec’97 controller.
You’ll find more detail about the ICH2 functions and capabilities later in this section.
Figure 2-8 shows an example of the system block diagram using the ICH2.
•Timers based on 82C54:
— System timer, refresh request, speaker
tone output
•System timer, refresh request, speaker tone
output
•System TCO reduction circuits:
— Timers to generate SMI# and reset upon
— Timers to detect improper processor
reset
— Integrated processor frequency strap
logic
•SMBus
— Host interface allows processor to
communicate via SMBus
— Compatible with two-wire I2C bus
•GPIO:
— TTL, Open-Drain, Inversion
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System Board
Input/output Controller Hub 2 (82801BA)
•FWH interface•3.3V operation with 5V tolerant buffers for
•241 BGA package•Alert-On-LAN (AOL) support
ICH2 Features
ICH2 Architecture
The ICH2 interface architecture ensures that the I/O subsystems, both PCI and the
integrated I/O features (for example, IDE, AC’97, and USB), receive adequate
bandwidths.
By placing the I/O bridge directly on the ICH2 interface, and no longer on the PCI bus,
the ICH2 architecture ensures that the I/O functions obtain the bandwidth necessary for
peak performance.
ICH2 PCI Bus Interface
FeatureFeature
IDE and PCI signals
The ICH2 PCI provides the interface to a PCI bus interface operating at 33MHz. This
interface implementation is compliant with PCI 2.2 specification, supporting as many as
five external PCI masters in addition to the ICH2 requests. The PCI bus can reach a
data transfer rate of 133MB/sec. The maximum PCI burst transfer can be between
256 bytes and 4KB. It also supports advanced snooping for PCI master bursting, and
provides a prefetch mechanism dedicated for IDE read.
For a list of ICH2 interrupts, see the table on page 60.
SMBus Controller
The System Management (SM) bus is a two-wire serial bus that runs at a maximum of
100kKHz. The SMBus host interface allows the processor to communicate with SMBus
slaves and an SMBus slave interface that allows external masters to activate
power-management events. The bus connects to sensor devices that monitor some of the
hardware functions of the system board, both during system boot and run-time.
For a description of the devices on the SMBus, see page 49. For information about the
MaxiLife ASIC, see page 51.
Low Pin Count Interface
The ICH2 implements the LPC interface 1.0 specification.
Enhanced USB Controller
The USB controller provides enhanced support for the Universal Host Controller
Interface (UHCI). This includes support that allows legacy software to use a USB-based
keyboard and mouse. The USB supports four stacked connectors on the back panel.
These ports are built into the ICH2, as standard USB ports.
46
The ICH2 is USB 1.1 compliant.
Chapter 2
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System Board
Input/output Controller Hub 2 (82801BA)
USB works only if you’ve enabled the USB interface within the HP Setup program.
Currently, only Microsoft Windows 95 SR2.1, Windows 98, and Windows 2000 provide
USB support.
AC’97 Controller
The AC’97 controller is a single-chip CS4299 audio controller that provides full audio
features for the HP Workstation x2100.
For information about the CS4299 audio solution, see page 48.
IDE Controller
The IDE controller is implemented as part of the ICH2 chip and has PCI-Master
capability. Two independent ATA/100 IDE channels are provided with two connectors
per channel. You can connect two IDE devices (one master and one slave) per channel. To
guarantee data transfer integrity, you must use Ultra-ATA cables for Ultra-ATA modes
(Ultra-ATA/33, Ultra-ATA/66, and Ultra-ATA/100).
The PIO IDE transfers as fast as 14MB/sec, and the system supports Bus Master IDE
transfer rates of as fast as 66MB/sec. The IDE controller integrates 16 x 32-bit buffers
for optimal transfers.
You can mix a fast and a slow device (for example, a hard disk and a CD-ROM) on the
same channel without affecting the performance of the faster device. The BIOS
automatically determines the fastest configuration that each device supports.
DMA Controller
The seven-channel DMA controller incorporates the functionality of two 82C37 DMA
controllers. Channels zero to three are for 8-bit count-by-byte transfers, whereas
channels five to seven are for 16-bit count-by-word transfers. (For allocated DMA
channel allocations, see the table on page 74.) You can program any two of the seven
DMA channels to support fast Type-F transfers.
The ICH2 DMA controller supports the LPC DMA. The LPC interface supports Single,
Demand, Verify, and Incremental modes. Channels zero to three are 8-bit, whereas
channels five to seven are 16-bit. Channel four is reserved as a generic bus master
request.
Interrupt Controller
The interrupt controller is equivalent in function to the two 82C59 interrupt controllers.
The two interrupt controllers are cascaded so that 14 external and 2 internal interrupts
are possible. In addition, the ICH2 supports a serial interrupt scheme and also
implements the I/O APIC controller. The table on page 60 shows how the master and
slave controllers are connected.
Timer/Counter Block
Chapter 2
The timer/counter block contains three counters that are equivalent in function to those
found in one 82C54 programmable interval counter/timer. These three counters provide
the system timer function and speaker tone. The 14.318MHz oscillator input provides
the clock source for these three counters.
47
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System Board
Input/output Controller Hub 2 (82801BA)
Advanced Programmable Interrupt Controller
You can use the APIC, which is incorporated in the ICH2, in either single-processor or
multiprocessor systems, whereas the standard interrupt controller supports only
single-processor systems.
Real Time Clock
The RTC is 146818A-compatible, with 256 bytes of CMOS. The RTC performs two key
functions:
•Keeps track of the time
•Stores system data
The RTC operates on a 32.768KHz crystal and a separate 3V lithium battery that
provides up to seven years of protection for an unplugged system. The RTC also supports
two lockable memory ranges. By setting bits in the configuration space, you can lock two
8-byte ranges to read and write accesses. This procedure prevents unauthorized reading
of passwords or other security information. Another feature is a date alarm that allows
for a schedule wake-up event as much as 30 days in advance.
Enhanced Power Management
The ICH2’s power-management functions include enhanced clock control, local and
global monitoring support for 14 individual devices, and various low-power (suspend)
states. A hardware-based thermal management circuit permits software-independent
entry points for low-power states.
The ICH2 includes full support for the Advanced Configuration and Power Interface
(ACPI) specifications.
Crystal CS4299 Integrated PCI Audio
Based on the earlier crystal audio controller, the CS4299 extends these features to
include, among many other enhancements, PC’98 and PC’99 compliancy for multimedia
desktops that require high-quality audio.
Features of the CS4299 include:
•AC’97 2.1 compatibility
•Industry-leading mixed-signal technology
•20-bit stereo digital-to-analog converter and 18-bit analog-to-digital converter
•High-quality pseudo-differential CD input
•Mono microphone input
•Analog line-level stereo inputs for LINE IN
•Stereo line-level output
48
•Compliance with Microsoft’s PC’98 and PC’99 audio performance requirements
Chapter 2
Page 49
The CS4299 introduces a new architecture that is different from the one used with the
CS4280-CS4297 pair.
Figure 2-9CS4280-CS4297 and CS4299 Architecture
Previous
Architecture
North
Bridge
PCI Slots
South
Bridge
PCI Bus
System Board
Input/output Controller Hub 2 (82801BA)
New
Architecture
North
Bridge
South
Bridge
CS4280 digital
controller
Audio controller link
CS4297
Audio controller link
CS4299
Devices On The SMBus
The SMBus is a subset of the I2C bus. It is a two-wired serial bus that runs at a
maximum speed of 100KHz. The SMBus monitors some of the system board’s hardware
functions (for example, voltage levels, temperature, fan speed, memory presence, and
type), both at system boot and during normal run-time. The SMBus controller,located in
the ICH2, controls the SMBus.
The following devices are connected to the SMBus:
•LCD status panel
•One serial EEPROM MaxiLife (also includes backup values of CMOS settings)
•PCI slot 5 ready for Alert-On LAN (AOL) from a hardware level
•ICH2 SMBus master controller 100KHz maximum
•MaxiLife for hardware management, bus master controller
Chapter 2
•One LM75 thermal sensor on the system board
•One ADM1024 hardware-monitoring sensor
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System Board
Input/output Controller Hub 2 (82801BA)
•RIMM serial EEPROM
Figure 2-10Devices on the SMBus
Intel Pentium IV
Processor
with L2 cache memory
I850 Memory
Controller Hub
(MCH)
82840-QP
HUB LINK 8
(233MB/s data
transfer rate)
I/O Controller Hub
I/O Controller Hub
(ICH2) 82801BA
(ICH2) 82801AA
IDE
Controller
4 x USB
Controller
PCI bridge
CS audio
codec
(CS4299)
System Bus
DMA
Controller
SMBus
Controller
MaxiLife
Fans
Monitor-
Serial
EEPROM
SMBus
ing Chip
LCD
Status
Panel
ICH2 SMBus Master Controller
The ICH2 provides a processor-to-SMBus controller. All access performed to the SMBus
occurs through the ICH2 SMBus interface. Typically, the processor has access to all the
devices connected to the SMBus.
50
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System Board
Input/output Controller Hub 2 (82801BA)
RIMM Sockets
Each RIMM socket is connected to the SMBus. The 168-pin RIMM modules include a
256-byte I2C serial EEPROM. The first 128 bytes contain general information, including
the DRAM chips’ manufacturer’s name, RIMM speed rating, RIMM type, and so on. You
can use the second 128 bytes of the serial EEPROM to store data online.
AS98127F
The AS98127 chip is a hardware-monitoring sensor dedicated to the processor
temperature. This chip uses the thermal diodes integrated into each processor cartridge
and makes the temperature information available through the SMBus. It also monitors
processor power supply voltages.
Serial EEPROM
This is the nonvolatile memory that holds the default values for the CMOS memory (in
the event of battery failure).When you install a new system board, the serial EEPROM
will have a blank serial number field. The BIOS automatically detects this, and the
system prompts you for the serial number printed on the identification label on the back
of the workstation.
The computer uses 16KB of serial EEPROM implemented within two chips. Serial
EEPROM is ROM in which the application of appropriate electrical signals can return
one byte at a time to its unprogrammed state. In effect, you can make serial EEPROM
behave like very slow, nonvolatile RAM. It is used for storing the tattoo string, the serial
number, and the parameter settings for the Setup program as well as MaxiLife
firmware.
LM75 Temperature Sensor
The LM75 temperature sensor and alarm reside on the system board. The sensor
measures the temperature in various areas of the system board. The system uses this
information to regulate fans.
HP MaxiLife Hardware-monitoring Chip
MaxiLife is a hardware-monitoring chip on the system board. Its functions include:
•Other miscellaneous functions (such as special OK/FAIL symbols based on a smiling
face)
Figure 2-11HP MaxiLife Hardware-Monitoring Chip
Chapter 2
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System Board
Input/output Controller Hub 2 (82801BA)
The integrated microprocessor includes the following:
•Synopsys cell based on Dallas “8052” equivalent
•2KB boot ROM
•256 bytes of data RAM
•I2C cell
•Analog-to-Digital (ADC) with five entries
•Additional glue logic for interrupt control, fan regulation, and a status panel control
MaxiLife downloads its code in 96 milliseconds from an I2C serial EEPROM. The total
firmware (MaxiLife 8051-code, running in RAM) size is 14KB. As it exceeds the 2KB
program RAM space, a paging mechanism swaps code as necessary, based on a 512-byte
buffer. The first 2KB pages of firmware code is crucial because it controls the initial
power on/reset to boot the system. This initial page is checked with a null-checksum test
and the presence of MaxiLife markers (located just below the 2KB limit).
MaxiLife is not accessible in I/O space or memory space of the system platform, but only
through the SMBus (which is a subset of the I2C bus), via the ICH2. Its I2C cell may
operate either in slave or master mode, switched by firmware, or automatically in the
event of Arbitration loss.
As a monitoring chip, MaxiLife reports critical errors at start-up, and is therefore
powered by Vstandby (3.3V) power. For MaxiLife to work, the workstation must be
connected to a grounded outlet. This enables the workstation’s hardware-monitoring
chip to be active, even if the system has been powered off.
Test Sequence And Error Messages
For detailed information about the different test sequences and error messages, see
“MaxiLife Test Sequence And Error Messages” on page 78.
52
Chapter 2
Page 53
MaxiLife Architecture
The MaxiLife chip continuously monitors temperature and voltage sensors located in
critical regions on the system board. This chip receives data about the various system
components via a dedicated I2C bus, which is a reliable communications bus to control
the integrated circuit boards.
Figure 2-12MaxiLife Architecture
System Board
Input/output Controller Hub 2 (82801BA)
LCD Status Panel
Serial
EEPROM
Memory
Speed up/slow
down
HP MaxiLife
AGPset
System Fans
I2C Bus
Temperature
Sensor
Hardwaremonitoring
Voltage Sensor
Memory
ASIC
NOTEMaxiLife is powered by VSTBY. Therefore, MaxiLife is functional as soon as the power
cord is plugged in.
Chapter 2
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System Board
Input/output Controller Hub 2 (82801BA)
Devices On The LPC Bus
Figure 2-13 illustrates the devices connected to the LPC bus.
Figure 2-13Devices on the LPC Bus
Keyboard,
mouse,
and floppy
Super
I/O
NS 87364
LPC / FWH Link
Intel Pentium IV
Processor
I850 Memory
Controller
Hub (MCH)
82840-QP
HUB LINK 8
I/O Controller Hub
I/O Controller Hub
(ICH2) 82801BA
(ICH) 82801AA
IDE
Controller
4 x USB
Controller
DMA
Controller
PCI bridge
CS audio
(CS4299)
Controller
System Bus
codec
SMBus
Paralleland
serial ports
The Super I/O Controller
The Super I/O chip (NS 87364) provides control for two FDD devices, two serial ports,
one bidirectional multimode parallel port, and a keyboard and mouse controller.
Serial/Parallel Communications Ports
The 9-pin serial ports (whose pin layouts are depicted on page 114) support RS-232-C
and are buffered by 16550A UARTs, with 16-byte FIFOs. You can program them as
COM1, COM2, COM3, COM4, or you can disable them.
The 25-pin parallel port (also depicted on page 115) is Centronics compatible, supporting
IEEE 1284. You can program the port as LPT1, LPT2, or you can disable it. It can
operate in the following modes:
FirmWare
Hardware
(FWH) 82802
Super I/O
DeviceIndexData
2Eh2Fh
54
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System Board
Input/output Controller Hub 2 (82801BA)
•Standard mode (PC/XT, PC/AT, and PS/2 compatible).
•Bidirectional mode (PC/XT, PC/AT, and PS/2 compatible).
The integrated floppy disk controller (FDC) supports any combination of two of the
following: tape drives, 3.5-inch flexible disk drives, 5.25-inch flexible disk drives. It is
software- and register-compatible with the 82077AA, and IBM-compatible. It has an A
and B drive-swapping capability and a non-burst DMA option.
Keyboard And Mouse Controller
The computer has an 8042-based keyboard and mouse controller. See page 113 for
connector pin layouts.
Chapter 2
55
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System Board
FirmWare Hub (82802AB)
FirmWare Hub (82802AB)
The FWH (also known as flash memory) is connected to the LPC bus. It contains 4Mbit
(512KB) of flash memory.
The hardware features of the FWH include:
•Random Number Generator (RNG)
•Five General Purpose Inputs (GPI)
•Register-based block locking
•Hardware-based locking
An integrated combination of logic features and nonvolatile memory:
•Enables better protection for the storage and update of system code and data.
•Adds flexibility through additional GPIs.
•Allows for quicker introduction of security/manageability features.
The following table outlines the available FWH features
•FWH interface mode:
— Five signal communication interface supporting
x8 reads and writes
— Register-basedread and write protection foreach
code/data storage blocks
— Five additional GPIs for system design and
flexibility
— A hardware RNG
— Integrated Command User Interface (CUI) for
requesting access to locking, programming, and
erasing options. Also handles requests for data
residing in status, ID, and block lock registers.
— Operates with 33MHz PCI clock and 3.3V I/O
•A/A Mux Interface/Mode, supporting:
•Two configurable interfaces:
— FWH interface for system operation
— Address/Address Multiplexed (A/A Mux)
interface
•4Mbits of flash memory for system code/data
nonvolatile storage:
— Symmetrically blocked, 64KB memory
sections
— Automated byte program and block erase
through an integrated Write State
Machine (WSM)
•Power supply specifications:
56
— 11-pin multiplexed address and 8-pin data I/O
interface
— Fast on-board or out-of-system programming
— Vcc: 3.3V +/- 0.3V
— Vpp: 3.3V and 12V for fast programming,
80ns
Chapter 2
Page 57
FeatureFeature
System Board
FirmWare Hub (82802AB)
•Industry standard packages:
— 40L TSOP or 32L PLCC
The FWH includes two hardware interfaces:
•FWH interface
•A/A Mux interface
The Interface Configuration (IC) pin on the FWH provides the control between these
interfaces. You must select the interface mode prior to power-up or before return from
reset (RST# or INIT# low to high transition).
The FWH interface works with the ICH2 during system operation, while the A/A Mux
interface is designed as a programming interface for component preprogramming.
An internal CUI serves as the control center between the FWH and A/A Mux interfaces,
and internal operation of the nonvolatile memory. A valid command sequence written to
the CUI initiates device automation. An internal WSM automatically executes the
algorithms and timings necessary for block erase and program operations.
•Case temperature operating range
Chapter 2
57
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System Board
System Bus
System Bus
The system bus of the Pentium IV processor is implemented in the Gunning Transceiver
Logic (GTL)+ technology. This technology features open-drain signal drivers that are
pulled up through resistors at bus extremities to the operating voltage of the processor
core. These resistors also act as bus terminators and are integrated in the processor and
in the 82850 MCH.
Figure 2-14The System Bus
Address (32)
Control
Data (64)
1.5V
AGP
Pro
Connector
Socket 423
AGP 4x Bus
(133MHz
(1GB/sec data
transfer rate)
Intel Pentium IV
Processor
850
Memory
Controller Hub
(MCH)
82850
HUB LINK 8
(266MB/s
data transfer
rate)
I/O Controller Hub
(ICH) 82801AA
Dual Rambus channel
3.2GB/s at
400MHz data
transfer rate)
100MHz two-way system bus (data busruns at
4 x 100MHz, 3.2GB/s
transfer rate)
4 onboard RIMM
sockets
supporting
RDRAM memory
The supported operating frequency of the GTL+ bus for the Pentium IV is 100MHz. The
width of the data bus is 64 bits, whereas the width of the address is 32 bits. Data bus
transfers occur at four times the system bus, at 400MHz. Along with the operating
frequencies, the processor voltage is set automatically.
58
The control signals of the system bus allow the implementation of a “split -transaction”
bus protocol. This allows the Pentium IV processor to send its request (for example, for
the contents of a given memory address) and release the bus, rather than waiting for the
result. Therefore, processor can accept another request. The MCH, as the target device,
then requests the bus again when it is ready to respond, and sends the requested data
packet. As many as four transactions can be outstanding at any given time.
Intel Pentium IV Processor
The Pentium IV processor has several features that enhance performance:
•Data bus frequency of 400MHz
Chapter 2
Page 59
System Board
System Bus
•Dual independent bus architecture, which combines a dedicated 64-bit Level 2 cache
bus (supporting 256KB), plus a 64-bit system bus that enables multiple
simultaneous transactions
•MMX2 technology, which gives higher performance for media
communications, and 3D applications
•Dynamic execution to speed up software performance
•Internet Streaming SIMD Extensions 2 (SSE2) for enhanced floating point and 3D
application performance
•Uses multiple low-power states, such as AutoHALT, Stop-Grant, Sleep, and Deep
Sleep to conserve power during idle times
The Pentium IV processor is packaged in a pin grid array (PGA) that fits into a PGA423
socket (423-pin Zero Insertion Force—ZIF—socket).
Processor Clock
The 100MHz system bus clock is provided by a PLL. The processor core clock is derived
from the system bus by applying a ratio. This ratio is fixed in the processor. The
processor then applies this ratio to the system bus clock to generate its CPU core
frequency.
Bus Frequencies
The system board contains a 14.318MHz crystal oscillator. This frequency is multiplied
to 133MHz by a phase-locked loop. An internal clock multiplier within the processor
further scales this number.
The bus frequency and the processor voltage are set automatically.
Voltage Regulation Module (VRM)
One VRM is integrated on the system board, complying with VRM specification 9.0. The
system supports high-current and low-voltage processors.
The processor requires a dedicated power voltage to supply the CPU core and Level 2
cache. The processor codes through Voltage Identification (VID) pins with a required
voltage level of 1.30V to 2.05V. The VID set is decoded by the VRM on the system board
that in return supplies the required power voltage to the processor. Note, however, that
voltage may vary from one processor model to another.
Cache Memory
The Pentium IV integrates the following cache memories on the same die as the
processor cache:
•A trace instruction and Level 1 data cache. The trace cache is 4-way set associative.
•A 256KB Level 2 cache. The Level 2 cache is 8-way associative.
Chapter 2
Intel sets the amount of cache memory at the time of manufacture. You can’t change the
value.
59
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System Board
Assigned Device Interrupts
Assigned Device Interrupts
I/o Controller Hub Interrupts
Device
AC’97 audio
controller
USB controller
AGP slot
PCI 32-bit slot #1
PCI 32-bit slot #2
PCI 32-bit slot #5
(LAN card)
Reference
Name
CS42804
————A———
J34—016AB——
J371
J380
J425
PCI 64-bit Hub Interrupts
Device
Ultra-Wide SCSI U160
controller
Reference
Name
AIC-78922(P64H) 925— — — — — — — — A
REQ/
GNT
(ICH2)
(ICH2)
(ICH2)
(ICH2)
REQ/G
IDSEL
ID
AD[xx]
521—A——
622CDAB
824ABCD
1127BCDA
NT
ID
Chip-set Interrupt Connection
INTAINTBINTCINTD
IDSEL
AD[xx]
Interrupt Requests (IRQ)
012 3 456 78
60
PCI 32-bit slot #3
PCI 32-bit slot #4
J391 (P64H) 420— — — — A B C D —
J400 (P64H) 723A B C D — — — — —
Interrupt Controllers
The system has an interrupt controller that is equivalent in function to that of two
82C59 interrupt controllers. The following table shows how the interrupts are connected
to the APIC controller. The IRQs are numbered sequentially, starting with the master
controller, and followed by the slave (both of 82C59 type).
Chapter 2
Page 61
System Board
Assigned Device Interrupts
Although you can use the Setup program to change some of the settings, the following
address map isn’t completely BIOS dependent but is determined partly by the operating
system. Note that some of the interrupts are allocated dynamically.
APIC ControllerInterrupt Signalling on
Interrupt Source
of deviceInput
INTA - PCI slot 3 (32/33)P64HIRQ0BT_INTAPIC bus
INTB - PCI slot 3 (32/33)P64HIRQ1BT_INTAPIC bus
INTC - PCI slot 3 (32/33)P64HIRQ2BT_INTAPIC bus
INTD - PCI slot 3 (32/33)P64HIRQ3BT_INTAPIC bus
INTA - PCI slot 4 (32/33)P64HIRQ4BT_INTAPIC bus
INTB - PCI slot 4 (32/33)P64HIRQ5BT_INTAPIC bus
INTC - PCI slot 4 (32/33)P64HIRQ6BT_INTAPIC bus
INTD - PCI slot 4 (32/33)P64HIRQ7BT_INTAPIC bus
INTA - onboard SCSI controllerP64HIRQ8BT_INTAPIC bus
AGP - INTA,PCI Slot 1 - INTC,PCI
Device on Primary IDE ChannelICH2IRQ14INTAPIC bus
Device on Secondary IDE ChannelICH2IRQ15INTAPIC bus
Serial Interrupt from Super I/OICH2SERIRQINTAPIC bus
ICH2INTAINTAPIC bus
ICH2INTBINTAPIC bus
ICH2INTCINTAPIC bus
ICH2INTDINTAPIC bus
(PIC
mode)
a
(APIC
modes)
a. In PIC mode, the interrupts signaled to the P64H are chained as INTC to the ICH2.
Three major interrupt modes are available:
•PIC mode: This mode uses only legacy interrupt controllers, so only one processor
can be supported. Because this system has dual-processor capability, Windows NT
doesn’t choose this mode as the default. However, during Windows NT installation,
you can select this mode.
•Virtual wire mode: This mode is implemented with APIC controllers in the ICH2
and P64H and used during boot time. The virtual wire mode allows the transition to
the symmetric I/O mode. In the virtual wire mode, only one processor executes
instructions.
•Symmetric I/O mode: This mode is implemented with APIC controllers in the
ICH2 and P64H and allows for multiple processor operations.
NOTEIn PIC mode and virtual wire mode, PCI interrupts are routed to the INT line. In
symmetric I/O mode, PCI interrupts are routed to the I/O APIC controllers and
forwarded over an APIC bus to the processors.
Chapter 2
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System Board
Assigned Device Interrupts
PCI IRQ Lines
PCI devices generate IRQs using up to four PCI IRQ lines (INTA#, INTB#, INTC#, and
INTD#).
PCI interrupts can be shared; several devices can use the same interrupt. However,
optimal system performance is reached when minimizing the sharing of interrupts.
Refer to page 60 for a table of the PCI device interrupts.
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3System BIOS
Chapter 3
63
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System BIOS
Overview
Overview
This chapter summarizes the HP Workstation x2100’s Setup program and BIOS.
Chapter 4, “Tests And Error Messages,” describes the POST routines.
The BIOS is based on the core Phoenix BIOS, which includes 4Mbits of flash memory,
support for PCI Specification 2.2, suspend to RAM, and RIMM or DIMM memory
modules.
The BIOS includes a boot ROM for the 3COM 3C905C and HP LAN cards.
The system ROM contains the Power-On Self-Test (POST) routines and the BIOS: the
system BIOS, video BIOS, and low-option ROM. This chapter (and Chapter 4) gives an
overview of the following:
•Menu-driven Setup with context-sensitive help.
•The address space, with details of the interrupts used.
•POST routines, which are a sequence of tests the computer performs to ensure that
the system is functioning correctly. See Chapter 4 for information.
The system BIOS is identified by the version number IY.WM, where:
•IY is a two-letter code indicating that it is for the x2100.
•W is a one-digit code indicating the HP entity.
•JG.W1.01US is the major BIOS version.
An example of a released version would look similar to the following: JG.W1.01US.
See page 70 for the procedure for updating the system ROM firmware.
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Using The HP Setup program
Torun the Setup program, press F2 while the initial HP logo displays, immediately after
restarting the workstation.
Alternatively, press Esc to view the summary configuration screen. By default, this
screen displays for 15 seconds, but pressing any key stops this delay.
The band at the top of the Setup screen offers the following menus: Main, Advanced,
Security, Boot, Power, and Exit. Use the left and right arrow keys to select these menus.
The following screens are examples of a BIOS configuration.
Main Screen
The Main Screen shows a list of fields. To change a value press F7 or F8.
PhoenixBIOS Setup Utility
MainAdvancedSecurityBootPowerExit
Item-Specific Help
BIOS Version:IC.11.02.
PnP OS[No]
Reset Configuration Data:[No]
System BIOS
Overview
System Time:[14:42:33]
System Date:[02/08/2000]
Key Click:[Disabled]
Keyboard auto-repeat rate speed: [21.8 per Second]
Delay before auto-repeat:[0.50
The Advanced Screen doesn’t have the same structure as the Main Screen and Power
Screen. Instead of presenting a list of fields, it offers a list of submenus.
Advanced users use the Advanced Screen to carry out special system configurations.
>>Large Disk Access Method[NT/DOS]
>>Integrated IDE Controller[Both Enabled]
66
IDE Primary Master Device
Advanced
IDE Primary Master Device (HD 2564)Item-Specific Help
Type
Multisector transfer
LBA Mode Control
32 bit I/O
Transfer Mode
ULTRA DMA Mode
Chapter 3
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Integrated USB Interface
Advanced
Integrated USB InterfaceItem-Specific Help
USB Controller[Auto]
Legacy Keyboard Emulation[Disabled]
Integrated I/O Ports
Advanced
Integrated I/O PortsItem-Specific Help
Parallel Port[Auto]
Parallel Port Mode[ECP]
Serial Port A[Auto]
Serial Port B[Auto]
Integrated Audio Device
System BIOS
Overview
Advanced
Integrated Audio DeviceItem-Specific Help
Integrated Audio[Enabled]
AGP Configuration (Video)
Advanced
AGP Configuration (Video)Item-Specific Help
Graphic Aperture[64MB]
PCI Device, Slot #1
Advanced
PCI Device, Slot 1
Option ROM Scan[Auto]
Bus Master[Disabled]
Bus Latency Timer[0040h]
a. PCI Slot #x have the same options as above. PCI Device, Slot 1 is only
an example.
a
Item-Specific Help
Chapter 3
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System BIOS
Overview
Integrated LAN
Advanced
Integrated LANItem-Specific Help
Integrated Network:[Enabled]
Option ROM Scan[Enabled]
Bus Master[Disabled]
Bus Latency Timer[0020h]
Security Screen
Submenus let you change the characteristics and values of the:
•systems administrator password
•user password
•power-on password
•boot device security
•hardware protection
MainAdvancedSecurityBootPowerExit
Item-Specific Help
Administrator PasswordClear.
Set Administrator Password [Enter]
Clear Both Passwords[Enter]
User PasswordClear
Set User Password[Enter]
Power-on Password[Disabled]
Start from Floppy[Enabled]
Start from CD-ROM[Enabled]
Start from HDD[Enabled]
>>Hardware Protection
Hardware Protection
Write on Floppy
Disks
Secured Setup
Configuration
Hard Disk Boot Sector[Unlocked]
Security
Hardware Protection
[Unlocked]
[No]
Item-Specific
Help
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System BIOS
Overview
Boot Screen
This screen lets you select the order of the devices in which you want the BIOS to
attempt to boot the operating system:
•Hard disk drives
•Removable devices
The operating system assigns drive letters to these devices in the order that you specify.
During POST, if the BIOS unsuccessfully boots from one device, it attempts to boot from
the next device on the Boot Device Priority list until it finds an operating system.
MainAdvancedSecurityBoot PowerExit
Item-Specific Help
Quickboot Mode[Enabled]
Display Option ROM Messages [Enabled]
>Boot Device Priority
Power Screen
This screen lets you set the Standby Delay and Suspend Delay modes. Standby mode
slows down the processor, whereas Suspend mode saves energy. These options are
available only with Windows 95 RTM. For other operating systems (for example,
Windows 95 SR 2.5, Windows 98, and Windows 2000), use the control panel for similar
options.
Modem Ring enables or disables the system’s ability to return to full speed after an
Interrupt Request (IRQ) is generated. Network Interface enables or disables the
system’s ability to return to full speed after the network interface receives a specific
command.
You can download the latest system BIOS (standard flash operation) from HP’s Web site
at www.hp.com/go/workstationsupport. After accessing the site, select HP x2100
Workstation
Instructions for updating the BIOS accompany the downloaded BIOS files and a BIOS
flash utility (flash.txt).
The BIOS update not only flashes the BIOS but also updates MaxiLife. Figure 3-1 shows
how the system BIOS flash operates.
Figure 3-1System BIOS Flash Process
.
Boot
from
floppy
disk
CAUTIONDon’t turn off the computer until the system BIOS update procedure has completed,
successfully or not; otherwise, irrecoverable damage to the ROM might occur.
Flash
BIOS
Reboot
Workstation
(press a key)
Flash
MaxiLife
Workstation
powers off
automaticall
Workstation
powers on
automaticall
Workstation
Boots
Restoring BIOS Default Settings
BIOS and configuration issues may cause suspected hardware errors. If the BIOS
settings are wrong, perform the following steps to restore the BIOS to its default setting:
1. ToaccesstheSetupprogram,press F2 while the initial HP logo displays immediately
after restarting the workstation.
2. Press F9 to load the default settings from the Setup program.
70
3. In the main menu, set the Reset Configuration Data to Yes.
Take note of the system setup before you make any modifications to the BIOS.
If You Forget The Administrator Password
1. Turn off the workstation, disconnect the power cord and all cables, then remove the
cover.
2. Set switch 9 on the system board switch block to ON.
3. Replace the power cord, and restart the workstation.
4. When the Passwords have been cleared message appears, turn off the
workstation.
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System BIOS
Updating The System BIOS
5. Remove the power cord, and reset switch 9 back to OFF.
6. Replace the workstation’s cover, turn on the workstation, and let it complete its
startup routine.
7. After POST completes, press F2 when prompted to use the Setup program.
8. Set the administrator and new user passwords.
9. To save the new password and exit Setup, press Esc or select Exit Menu.
Clearing The CMOS
1. Turn off the workstation, disconnect the power cord and all cables, then remove the
cover.
2. Set the system board switch 8 to ON.
3. Replace the cover, and reconnect the power cord and video cable.
4. Reboot the workstation. A message similar to the following
will appear:
“Configuration has been cleared, set switch Clear to the ON positionbefore rebooting.”
5. Turn off the workstation, disconnect the power cord and video cable, and remove the
cover.
6. Set the system board switch 8 to OFF.
7. Replace the cover, and reconnect the power cord and data cables.
8. Turn on the workstation. Press F2 to run Setup, then press F9. The system
automatically downloads and saves the CMOS default values.
9. To save the configuration and exit Setup, press Esc .
Recovering The BIOS (Crisis Mode)
If the BIOS is corrupted and you can’t use the standard flash, use the BIOS Recovery
Mode (exceptional BIOS recovery operation) to restore the BIOS.
1. Obtain a bootable DOS floppy disk.
2. Copy the BIOS files onto the floppy disk. For information about how to download the
system BIOS, see page 70.
3. Create (or edit) the autoexec.bat file, which should contain the following line of text:
“phlash /c /mode=3 /s IY.W1.XX.FUL”
(Rename the BIOS filename with the filename on the floppy disk.)
4. Turn off the workstation, disconnect the power cord, and remove the cover.
5. Set switch 7 to ON.
Chapter 3
6. Insert the floppy disk into the floppy disk drive.
7. Reconnect the power cord, and turn on the workstation.
8. The workstation boots from the floppy disk, then flashes the BIOS. During the flash
process, the screen remains blank. When you hear one long beep, the recovery
process is finished.
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System BIOS
Updating The System BIOS
9. Turn off the workstation. Remove the floppy disk from the drive.
Remove the power cord.
10. Set switch 7 back to OFF.
11. Replace the cover, reconnect the power cord, then reboot the
workstation.
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System BIOS
BIOS Addresses
BIOS Addresses
This section provides a summary of the main features of the HP system BIOS. This is
software that provides an interface between the computer hardware and the operating
system. For the procedure to update the system ROM firmware, see page 70.
System Memory Map
Reserved memory that accessory boards use must reside in the area from C8000h to
EFFFFh.
0000 0000 - 0000 03FFReal-mode IDT
0000 0400 - 0000 04FFBIOS data area
0000 0500 - 0009 FC00Used by operating system
0009 FC00 - 0009 FFFFExtended BIOS data area
000A_0000 - 000B_FFFFVideoRAMor SMRAM (not visible unless
in SMM)
000C 0000 - 000C 7FFFVideo ROM (VGA ROM)
000C 8000 - 000F FFFFAdapter ROM, RAM, memory-mapped
registers, BIOS
000E 0000-000F FFFF128KB BIOS (Flash/Shadow)
0001 0000-000F FFFFMemory (1MB to 16MB)
0010 0000-001F FFFFMemory (16MB to 32MB)
0020 0000-003F FFFFMemory (32MB to 64MB)
0040 0000-007F FFFFMemory (64MB to 128MB)
0080 0000-7FFF FFFFMemory (128MB to 2GB)
FECO 0000I/O APIC
FEEO 0000Local APIC (each CPU)
FFF8 0000-FFFF FFFF512KB BIOS (Flash)
HP I/O Port Map (I/O Addresses Used By The System, if
configured)
You access peripheral devices, accessory devices, and system controllers through the
system I/O space, which isn’t located in system memory space. The 64KB of addressable
I/O space comprises 8-bit and 16-bit registers (called I/O ports) located in the various
Chapter 3
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System BIOS
BIOS Addresses
system components. When you install an accessory board, ensure that the selected I/O
address space is in the free area of the space reserved for accessory boards (100h to
3FFh).
0378 - 037FLPT1
03B0 - 03DFVGA
03E8 - 03EFCOM3
03F0 - 03F5Floppy disk drive controller
03F6IDE primary channel
03F7Floppy disk drive controller
03F8 - 03FFCOM1
04D0 - 04D1Interrupt edge/level control
0778 - 077FLPT1 ECP
0CF8 - 0CFFPCI configuration space
C000 -Power management I/O space and ACPI registers
C100 - C10FSMBus I/O space
Function
drive)
74
DMA Channel Controllers
The system permits only I/O-to-memory and memory-to-I/O transfers. The hardware
configuration doesn’t allow I/O-to-I/O or memory-to-memory transfers.
The system controller supports seven DMA channels, each with a page register that
extends the channel’s addressing range to 16MB.
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System BIOS
BIOS Addresses
The following table shows how the system allocates DMA channels.
DMA controller
ChannelFunction
DMA 0Free
DMA 1Free if not used for parallel port in Setup
DMA 2Floppy disk drive controller
DMA 3Free if not used for parallel port in Setup
DMA 4Used to cascade DMA channels 0-3
DMA 5Free
DMA 6Free
DMA 7Free
Interrupt Controllers
The system’s interrupt controller is equivalent in function to two 82C59 interrupt
controllers. The following table shows how the interrupts are connected to the APIC
controller. The IRQs are numbered sequentially, starting with the master controller and
followed by the slave (both of 82C59 type).
I/O APIC InputIRQIRQ Description
INTIN0ICH
INTIN1IRQ1Super I/O keyboard controller
INTIN2IRQ0ICH system timer
INTIN3IRQ3Super I/O - Used by serial port if enabled
INTIN4IRQ4Super I/O - Used by serial port if enabled
INTIN5IRQ5Free if not used for parallel port or audio
INTIN6IRQ6Super I/O - floppy disk controller
INTIN7IRQ7Super I/O - LPT1
INTIN8IRQ8ICH - RTC
INTIN9IRQ9Available for PCI devices
INTIN10IRQ10Available for PCI devices
INTIN11IRQ11Available for PCI devices
INTIN12IRQ12Super I/O - mouse
INTIN13IRQ13Coprocessor
INTIN14IRQ14ICH - Integrated IDE Controller (primary)
INTIN15IRQ15ICH - Integrated IDE Controller (secondary)
INTIN16PCINTA
INTIN17PCINTB
•PIC mode: This mode uses only legacy interrupt controllers, so the system can
support only one processor. You can select this mode when you install Windows NT.
•Virtual wire mode: This mode, which is implemented using the 82C59 interrupt
and the I/O APIC controller, is used during boot time. The virtual wire mode allows
the transition to the symmetric I/O mode. In the virtual wire mode, only one
processor executes operations.
•Symmetric I/O mode: This mode is implemented using the I/O APIC controller and
allows for multiple processor operations.
NOTEIn PIC mode and virtual wire mode, PCI interrupts are routed to the INT line. In
symmetric I/O mode, PCI interrupts are routed to the I/O APIC controllers and
forwarded over an APIC bus to the processors.
PCI IRQ Lines
PCI devices generate IRQs using up to four PCI IRQ lines (INTA#, INTB#, INTC#, and
INTD#).
PCI interrupts can be shared; several devices can use the same interrupt. However,
optimal system performance is reached when minimizing the sharing of interrupts.
Refer to page 60 for a table of the PCI device interrupts.
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4Tests And Error Messages
This chapter describes:
•MaxiLife firmware test sequences and error messages
•Preboot diagnostics error codes
•Power-On Self-Test (POST) routines, which the computer’s ROM BIOS contains
•Error messages and suggestions for corrective action
Chapter 4
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Tests And Error Messages
MaxiLife Test Sequence And Error Messages
MaxiLife Test Sequence And Error Messages
When you turn on the workstation, the system initiates the normal startup sequence,
which consists of the following steps:
•Basic preboot diagnostics
•BIOS launch
•POST phase
•Operating system boot phase
If the system detects any errors during the startup sequence, MaxiLife won’t necessarily
freeze the system. However, some critical hardware errors are fatal to the system and
prevent the system from starting. (For example, CPU socket and power supply
malfunctions can prevent the system from working.)
The system detects non-crucial errors both during preboot diagnostics and POST, in
which the BIOS boot process returns an error code. The system detects some errors only
during POST sequence; these errors produce the same process.
Finally, while the workstation is working, the system can report fan and temperature
controls. (For example, the system can report a fan error if a fan cable is disconnected.)
This type of error disappears as soon as you fix the problem (for example, reconnect the
fan cable).
The next sections describe the different diagnostics.
Basic Pre-boot Diagnostics
The first diagnostic, called basic preboot diagnostics, runs to check the presence of the
processors or terminators, power supply, hardware monitoring, and thermal sensors. If
you have a power cord connected to the workstation, the basic preboot diagnostics are
activated.
The preboot diagnostic tests run in order of priority, according to their importance to
computer functions.
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On the HP Workstation x2100, the first detected error displays a message on the LCD
status panel. If an error occurs, one of the following screens displays.
Figure 4-1Possible Error Messages
Presence of processor
Tests And Error Messages
MaxiLife Test Sequence And Error Messages
Control of some voltages:
12V, 3.3V, 1.8V, 2.5V, -5V
ERROR
CPU Socket
Missing or incorrectly installed
processor
Figure 4-2 shows how the preboot diagnostics work when an error occurs.
Figure 4-2Preboot Diagnostics Error
Vcc State (5V)
MaxiLife
Firmware
Hardware
Monitoring
LCD Status
Panel
ERROR
CPU Socket
ERROR
Power Supply
If a power supply error occurs, a
cause could reside in the power
supply cabling or circuits
CPU or Terminator
Voltage 12V, 3.3V, 1.8V, 2.5V
Voltage CPU1
I2C Bus
Temperature
Sensors
An error has been detected when
checking the processor. The
displayed error message could
indicate a missing or incorrectly
connected processor.
System
Memory
Table 4-1
Chapter 4
The following table shows the test sequence carried out, the type of error message, and
the action to take.
TestError CodeBeep CodesAction to Take
Presence a processorCPU socket1Check that the processor and
correctly installed
Control of some voltages: 12V,
3.3V, 1.8V, 2.5V
Check the hardware monitoringNo HW monitoringSystem board problem
Check thermal sensorTherm. sensor 90System board problem
Check thermal sensorTherm. sensor 92System board problem
Power supply2Check the power supply cable
and connectors, and processor
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Tests And Error Messages
MaxiLife Test Sequence And Error Messages
Pre-boot Diagnostics Error Codes
When a failure occurs prior to the operating system loading, the workstation beeps three
times, then begins a series of beeps. These beeps identify the part that needs
troubleshooting or replacement.
Number of beepsProblem
1Absent or incorrectly connected processor
2Power supply is in protected mode
3Memory modules not present, incompatible, or not functioning
4Video controller failure
5PnP/PCI initialization failure
6Corrupted BIOS; you need to activate crisis-recovery procedure
7System board failure
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POST Sequence And POST Error
In this phase, MaxiLife waits for any error messages that the BIOS may issue. If such an
error occurs, an error code appears on the monitor screen.
On the HP Workstation x2100, a screen similar to Figure 4-3 displays. The error code
that appears on the LCD status panel is the same as the one that appears on the monitor
screen. If the POST issues several error codes, only the last one is visible on the LCD
status panel.
Figure 4-3POST Sequence and POST Error
ERROR
Keyboard Test
Figure 4-4 and Figure 4-5 show the different BIOS-generated errors.
Tests And Error Messages
POST Sequence And POST Error
Figure 4-4BIOS-generated Errors
“BIOS” ERROR
BIOS
“read system
memory”
Figure 4-5BIOS-generated Errors
“BIOS”-Generated Errors
BIOS
Video
Slots
Table 4-2
“No Video”
MaxiLife
“Spy System
Memory”
System
Memory
MaxiLife
Beep Codes
A time-out of three seconds
occurs before the message
appears on the LCD status
panel and video display
ERROR
BIOS Check sum
LCD Status Panel
ERROR
No Video
LCD Status Panel
Chapter 4
TestError CodeBeep CodesAction to Take
Incompatible memory modulesMem miscompare3Check that the memory
modules are of the same speed
and type
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Tests And Error Messages
POST Sequence And POST Error
Table 4-2 (Continued)
TestError CodeBeep CodesAction to Take
Presence ofcontinuity modules
in the RIMM sockets
Compatibility speed rating of
installed RDRAM modules
Compatibility of installed
RDRAM modules
Presence of memory modulesNo RIMM3Check that the memory
Availability of video controller
is checked by the BIOS. If an
error is detected, and it isn’t a
fatal error, the BIOS continues
its execution normally.
RIMM continuity3Check that the RDRAM
continuity modules are
installed
RIMM speed3Check that the installed
RDRAM modules have the
same speed ratings
RIMM devices3The 32-device limit per
RDRAM has been exceeded
modules are correctly installed
No video4Check that the video controller
is correctly installed
Note: No error is detected if a
monitor isn’t connected to an
installed video controller. This
isn’t a fatal error, and the
BIOS continues its normal
execution.
Operating System Boot Phase
If no error message appears at this stage of the system startup, the operating system
launches. The LCD status panel displays the system platform and a smiling icon.
Run-time Errors
During the normal usage of the workstation (and at boot), MaxiLife continually monitors
vital system parameters. These include: temperature errors, fan malfunctions, power
voltage drops and CPU problems.
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Table 4-3
Tests And Error Messages
POST Sequence And POST Error
TestError CodeAction to Take
During normal usage,
HP MaxiLife continually
checks vital system
parameters. If an error
occurs, a message
appears on the LCD
panel.
System FANSystem or chassis fan, fan cable
PCI FANPCI fan, fan cable
CPU 1 FANCPU fan, fan cable
CPU ThrottleProcessor frequency has been lowered to
prevent over temp errors
CPU ShutdownProcessor has undergone an internal error
(IERR) or the processor temperaturehasrisen
too quickly for CPU Throttle to be effective.
PCI temperatureAmbient or PCI temperature > 64˚C
Disk temperatureDisk temperature > 58˚C, or sensor unplugged
PSU 12 V errorPower supply unit failed. Try the following:
Power CPU error
PSU 3V3 error
•Replace the power supply unit with a
known working one
•If theproblem persists, replacethe system
PSU 2V5 error
PSU 1V8 error
PSU -5V error
board
Chapter 4
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Tests And Error Messages
Main Menu
Main Menu
The main menu appears when you press any of the LCD buttons. (You can access the
MaxiLife LCD status panel even when the workstation is powered off.) The main menu
consists of three submenus:
•System Info
•Boot Steps
•Boot Report
system info
Obtains information from the BIOS and the system’s serial EEPROM. This information
includes:
•Product name
•BIOS version
•Serial number
•Speed of processor
•Size of memory for each socket
Figure 4-6 shows how the System Info obtains its information.
Figure 4-6System Information
System Info
strings in
EEPROM
BIOS
DMI
Table
Write
MaxiLife
HP x2100
InfoServices
LCD Status Panel
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Boot Steps
Shows the POST codes during system startup. The BIOS provides the POST code, which
appears on the LCD panel as soon as it is available. If the system stops during startup,
the last successful boot-step POST code appears on the LCD. When you select Boot
Steps, the POST step appears on the LCD status panel during the subsequent boot
processes.
To ensure that MaxiLife is ready to display the first POST codes as soon as possible, the
preboot diagnostics aren’t executed when the system is booted with the Boot Steps
option selected. Figure 4-7 shows how Boot Steps obtains its information from the BIOS,
then displays a POST error if necessary.
Figure 4-7Boot Steps
Tests And Error Messages
Main Menu
System Info
Boot Steps
NextOk
This is a toggle
item, which is
indicatedwith a
check mark
“Write
POST
Code”
MaxiLife
BIOS
“Write
POST
ERROR”
HP x2100
Post Code 24
Error
Post Code XX
Boot Report
Runs a set of diagnostics that assess the system’s components. Results of the tests
appear on the LCD status panel, one after another, when you press the LCD
buttons.
Components are tested in sequence when the you press the Next button. When all
components have been checked, a diagnostic screen appears. Depending on the result of
the diagnostics, the screen could indicate either Diagnostics Done OK or FAIL.
At the end of the test, you can exit the diagnostic mode by pressing theLCD button.
For more information about MaxiLife, refer to Chapter 7 “troubleshooting your hp
workstation x2100.”
Chapter 4
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Tests And Error Messages
Order In Which POSTs Occur
Order In Which POSTs Occur
The POST executes each time the system is powered on or a reset is performed. The
POST process verifies the basic functionality of the system components and initializes
certain system parameters.
The POST starts by displaying a graphic screen of the HP PC Workstation’s logo when
you restart the system. If you want to view the POST details, press Esc to access the HP
Summary Screen.
If the POST detects an error, the screen switches to text mode and a detailed error
message appears on a View System Errors screen. On this screen, the error message
utility (EMU) not only displays the error diagnosis but suggests corrective action. (Refer
to page 93 for a brief summary.)
On the HP Workstation x2100, the LCD status panel displays either a message, a POST
code number (refer to Table 4-4), or an EMU code.
Devices such as memory and newly installed hard disks are configured automatically.
You don’t need to confirm the change.
During the POST, the system copies BIOS and other ROM data into high-speed shadow
RAM. The shadow RAM is addressed at the same physical location as the original ROM
in a manner that is completely transparent to applications. Therefore, shadow RAM
appears to behave as very fast ROM. This technique provides faster access to the system
BIOS firmware.
Table 4-4 lists the POST checkpoint codes and their associated beeps. See page 81 for
more details about preboot diagnostics error codes.
Table 4-4POST Checkpoint Codes
Checkpoint
Code
02hVerify real mode
03hDisable Non-Maskable Interrupt (NMI)
04hGet CPU type
06hInitialize system hardware
08hInitialize chipset with initial POST values
09hSet IN POST flagPOST Start
0AhInitialize CPU registersCPU Regist. Init
0BhEnable CPU cache
POST Routine Description
MaxiLife LCD
Display Message
Beep
Codes
86
0ChInitialize caches to initial POST values
0EhInitialize I/O componentI/O Init.
0FhInitialize the local bus IDEIDE Init.
10hInitialize power management
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Table 4-4POST Checkpoint Codes (Continued)
Tests And Error Messages
Order In Which POSTs Occur
Checkpoint
Code
11hLoad alternate registers with initial POST
values
12hRestore CPU control word during warm boot
13hInitialize PCI bus mastering devicesPCI Mast. Init.
14hInitialize keyboard controller
16hBIOS ROM checksumBIOS Check sum
17hInitialize cache before memory autosize
18h8254 timer initialization
1Ah8237 DMA controller initialization
1ChReset programmable interrupt controller
20hTest DRAM refreshRAM Refresh Test
22hTest 8742 keyboard controllerKeyb. Ctrl. Test
24hSet ES segment register to 4GB
26hEnable A20 line
28hAutosize DRAMMemory Detection3
POST Routine Description
MaxiLife LCD
Display Message
Beep
Codes
29hInitialize POST memory manager
2AhClear 512KB base RAM
2Ch
2EhRAM failure on data bits xxxx1 of low byte of
2FhEnable cache before system BIOS shadow
30hRAM failure on data bits xxxx1 of high byte
32hTest CPU bus-clock frequency
33hInitialize POST dispatch manager
36hWarm start shut down
38hShadow system BIOS ROMShadow BIOS ROM
3AhAutosize cache
3ChAdvanced configuration of chipset registers
3DhLoad alternate registers with CMOS values
42hInitialize interrupt vectors
RAM failure on address line
memory bus
of memory bus
a
RAM Add. Failure
RAM Data Low
RAM Data High
Chapter 4
45hPOST device initialization
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Tests And Error Messages
Order In Which POSTs Occur
Table 4-4POST Checkpoint Codes (Continued)
Checkpoint
Code
46hCheck ROM copyright notice
48hCheck video configuration against CMOS
49hInitialize PCI bus and devicesPCI Detection5
4AhInitialize all video adapters in systemVideo Detection4
4BhDisplay QuietBoot screen (optional)
4ChShadow video BIOS ROM
4EhDisplay BIOS copyright notice
50hDisplay CPU type and speed
51hInitialize EISA board
52hTest keyboardKeyboard Test
54hSet key click if enabled
56hEnable keyboard
58hTest for unexpected interruptsUnexpect. STOP
59hInitialize POST display service
POST Routine Description
MaxiLife LCD
Display Message
Beep
Codes
5AhDisplay prompt press F2 to enter Setup
5BhDisable CPU cache
5ChTest RAM between 512KB and 640KBBase Memory Test
60hTest extended memoryExt. Memory Data
62hTest extended memory address linesExt. Memory Add.
64hJump to UserPatch1
66hConfigure advanced cache registers
67hInitialize multiprocessor APIC
68hEnable external and CPU caches
69hSetup System Management Mode (SMM)
area
6AhDisplay external Level 2 cache size
6ChDisplay shadow-area message
6EhDisplay possible high address for UMB
recovery
70hDisplay error messages
72hCheck for configuration errors
88
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Table 4-4POST Checkpoint Codes (Continued)
Tests And Error Messages
Order In Which POSTs Occur
Checkpoint
Code
76hCheck for keyboard errorsKeyboard Test
7ChSet up hardware interrupt vectors
7EhInitialize coprocessor if present
80hDisable onboard super I/O ports and IRQs
81hLate POST device initialization
82hDetect and install external RS 232 ports
83hConfigure non-MCD IDE controllers
84hDetect and install external parallel ports
85hInitialize PC-compatible PnP ISA devices
86hRe-initialize onboard I/O ports
87hConfigure system board configurable devices
(optional)
88hInitialize BIOS data area
89hEnable Non-Maskable Interrupts (NMIs)
8AhInitialize extended BIOS data area
POST Routine Description
MaxiLife LCD
Display Message
Beep
Codes
8BhTest and initialize PS/2Mouse PS2 Test
8ChInitialize floppy controller
8FhDetermine number of ATA drives (optional)
90hInitialize hard disk controllersDisc Ctrl. Init.
91hInitialize local-bus hard disk controllersDisc Bus Init.
92hJump to UsersPatch2Maxilife Test
93hBuild MPTABLE for multiprocessor boards
95hInstall CD-ROM for bootCDROM Ctr. Init.
96hClear huge ES segment register
97hFix multiprocessor table
98hSearch for option ROMsOpt. Rom Detect.
99hCheck for SMART drive
9AhShadow option ROMs
9ChSet up power management
9DhInitialize security engine (optional)
9EhEnable hardware interrupts
Chapter 4
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Tests And Error Messages
Order In Which POSTs Occur
Table 4-4POST Checkpoint Codes (Continued)
Checkpoint
Code
9FhDetermine number of ATA and SCSI drivesCheck ATA / SCSI
A0hSet time of day
A2hCheck key lock
A4hInitialize typematic rate
A8hErase F2 prompt
AAhScan for F2 key stroke
AChEnter SETUPBIOS SETUP
AEhClear Boot flag
B0hCheck for errors...Checking...
B2hPOST done - prepare to boot operating
system
B5HTerminate QuietBoot (optional)
B6hCheck password (optional)Check Password
B7hACPI tables initializedACPI Init.
B8hClear global descriptor table
POST Routine Description
MaxiLife LCD
Display Message
Beep
Codes
B9hPrepare bootPrepare Boot...
BAhInitialize DMI parametersDMI Tables Init.
BBhInitialize PnP Option ROMsPNP Opt. ROM Init
BChClear parity checkers
BDhDisplay MultiBoot menu
BEhClear screen (optional)
BFhCheck virus and backup reminders
C0hTry to boot with INT 19
C1hInitialize POST Error Manager (PEM)
C2hInitialize error logging
C3hInitialize error display function
C4hInitialize system error handling
C5hPnPnd dual CMOS (optional)
C6hInitialize notebook docking (optional)
C7hInitialize notebook docking late
C8hForce check (optional)
E0hInitialize the chipset
E1hInitialize the bridge
E2hInitialize the CPU
E3hInitialize system timer
E4hInitialize system I/O
E5hCheck force recovery boot
E6hChecksum BIOS ROM
E7hGo to BIOS
E8hSet huge segment
E9hInitialize multiprocessor
EAhInitialize OEM special code
POST Routine Description
MaxiLife LCD
Display Message
Beep
Codes
EBhInitialize PIC and DMA
EChInitialize memory type
EDhInitialize memory size
EEhShadow boot block
EFhSystem memory test
F0hInitialize interrupt vectors
F1hInitialize run time clock
F2hInitialize video
F3hInitialize system management mode
F4hOutput one beep before boot
F5hBoot to mini DOS
F6hClear huge segment
F7hBoot to full DOS
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Tests And Error Messages
Order In Which POSTs Occur
a. If the BIOS detects error 2C, 2E, or 30 (base 512KB RAM error), it displays an
additional word-bitmap (xxxx) indicating the address line or bits that failed. For
example:
2C 0002 means line 1 (bit one set) has failed.
2E 1020 means data bits 12 and 5 (bits 12 and 5 set) have failed in the lower 16
bits.
The BIOS also sends the bitmap to the port-80 LED display. It first displays the
checkpoint code, followed by a delay, the high-order byte, another delay, then the
low-order byte of the error. It repeats this sequence continuously.
92
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Tests And Error Messages
Error Message Summary
Error Message Summary
In the event an error generates in POST during the boot process, the Error Setup
Manager gives access to one or more detected errors. Each EMU error displays as a
four-digit code with an associated text message on the monitor screen and/or the
MaxiLife LCD panel.
You can get further details by pressing Enter. A detailed description of the reason for the
failure and how to solve the problem displays. The following examples give the different
types of error categories.
Category #1:If the error is only a warning (such as, key stuck), the POST should
prompt:
WARNING
00100Keyboard Error
a
a. After a time-out period of five seconds without any intervention, the
system resumes to boot.
Category #2:If the error is serious, the POST should prompt:
00xxThe BIOS has detected a serious problem that prevents your PC from
booting
Press Enter to view more information about error messages.
Code #Cause/SymptomShort message (US)
0000hAny POST error that isn’t listed belowSystem error
0010hCMOS Checksum error (if no serial EEPROM)Incorrect CMOS Checksum
0011hDate and time (CMOS backed up from SE2P)Date and time lost
0012hPC configuration lost (both SE2P and CMOS lost)Incorrect PC configuration
0020hAny POST error regarding an AT option ROMOption ROM error
0040hSerial number corrupted (bad checksum or null #)Invalid PC serial number
Chapter 4
0041Product flag not initialized or badInvalid internal product type
0060hRPO initialization failureRemote power on error
0100hKeyboard stuck keyKeyboard error
0101hKeyboard self-test failureKeyboard error
0102hKeyboard controller I/O access failureKeyboard error
0103hKeyboard not connectedKeyboard error
0300hFloppy A: self-test failureFlexible disk drive A error
0301hFloppy B: self-test failureFlexible disk drive B error
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Tests And Error Messages
Error Message Summary
Code #Cause/SymptomShort message (US)
0310hFloppy A: not detected (but configured in CMOS)Flexible disk drive error
0311hFloppy B: not detected (but configured in CMOS)Flexible disk drive error
0306hGeneral failure on floppy controllerFlexible disk drive error
0400hCD-ROM test failureCD-ROM error
0401hCD-ROM not detected (but configured in CMOS)CD-ROM error
0500hGeneral failure on HDD onboard primary ctrlIDE device error
0501hGeneral failure on HDD onboard secondary ctrlIDE device error
0510hHDD # 0 self-test errorIDE device # 0 error
0520hHDD # 0 not detected (but configured in CMOS)IDE device # 0 error
0521hHDD # 1 not detected (but configured in CMOS)IDE device # 1 error
0522hHDD # 2 not detected (but configured in CMOS)IDE device # 2 error
0523hHDD # 3 not detected (but configured in CMOS)IDE device # 3 error
0530hFound a drive on slave connector only (primary)IDE device error
0531hFound a drive on slave connector only (secondary)IDE device error
0600hFound less video memory than configured in
CMOS
0700hFound less DRAM memory than at previous bootSystem memory error
0711hDefective SIMM (module 1, bank 1)System memory error
0800hFound lower cache size than configuredSystem cache error
0801hCache self-test failureSystem cache error
0A00hPlug and Play (PnP) video auto-setting failure
(DDC hang)
Video memory error
DDC video error
The following table summarizes the most significant problems that can be reported.
MessageExplanation or Suggestions for Corrective Action
Operating system not found
•Check whether the disk, HDD, FDD, or CD-ROM drive is
connected.
•If it is connected, check that it is detected by POST.
•Check that your boot device is enabled on the Setup Security
menu.
94
•If the problem persists, check that the boot device contains the
operating system.
Missing operating systemIf you have configured HDD user parameters, check that they are
correct. Otherwise, use HDD type “Auto” parameters.
Chapter 4
Page 95
Tests And Error Messages
Error Message Summary
MessageExplanation or Suggestions for Corrective Action
Resource allocation conflict
-PCI device 0079 on system
board
Video PnP interrupted or
failed; re-enable in Setup and
try again
System CMOS checksum bad
- run Setup
No message, system “hangs”Check that the main memory modules are correctly set in their
OtherAn error message may display and the computer may hang for 20
Clear CMOS.
You may have powered your computer off/on too quickly and the
computer turned off video PnP as a protection.
CMOS contents have changed between two power-on sessions. Run
Setup for configuration.
sockets.
seconds, then beep. The POST is probably checking for a mass
storage device, which it can’t find, and the computer is in time-out
mode. After time-out, run Setup to check the configuration.
Chapter 4
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Tests And Error Messages
Error Message Summary
96
Chapter 4
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5Hardware Components
This chapter describes:
•Graphics cards and PCI cards
•Mass storage devices
•Connectors and sockets
•The rear panel
Chapter 5
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Hardware Components
Graphics Cards
Graphics Cards
HP Workstation x2100 models provide installation and factory support for certain
Matrox, nVIDIA and ATI graphics cards. HP-supported drivers for these cards can be
found on the http://www.hp.com/go/workstationsupport web page. For all other product
information (specifications, features, etc.), visit the individual manufacturer’s web page:
•Matrox Millennium G450 (for HP-supported drivers, see
http://www.hp.com/go/workstationsupport; for product information, see
http://www.matrox.com/mga/home.htm)
•nVIDIA Quadro2 MXR and Quadro Pro (for HP-supported drivers, see
http://www.hp.com/go/workstationsupport; for product information, see
http://www.nvidia.com/Products.nsf)
•nVIDIA Quadro2 Ex (for HP-supported drivers, see
http://www.hp.com/go/workstationsupport; for product information, see
http://www.nvidia.com/Products.nsf)
•ATI FireGL2 and FireGL4(for HP-supported drivers, see
http://www.hp.com/go/workstationsupport; for product information, see
http://www.ati.com)
•ATI FireGL 8800 (for HP-supported drivers, see
http://www.hp.com/go/workstationsupport; for product information, see
http://www.ati.com)
Selecting A Monitor For Your Workstation
The table below provides a list of display resolutions and frequencies for the graphics
cards supported by your workstation. Using these resolutions and frequencies you will
be able to select the appropriate monitor for your graphics card. Note that frequencies of
85Hz and higher provide ergonomic flicker-free viewing.
If the monitor you select is DDC-2B or DDC-2B+ compliant, the graphics card will
automatically limit itself to those resolutions and frequencies supported by that monitor.
In this case, you do not need to use Table 5-1 to select your monitor.
Table 5-1Graphics Cards, Resolutions and Display Frequencies
a. 1 Only common resolutions are listed. Other intermediate resolutions are possible.
b. The 120Hz frequency is supported only in Stereo mode.
c. The maximum frequency may not be available at all color depths.
b
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Hardware Components
PCI Cards
PCI Cards
HP 10/100 TX PCI LAN Interface
The 10/100 TX LAN Interface is a 32-bit PCI 2.2 card that supports 10Mbits per second
(10Base-T) and 100Mbits per second (100 TX) transfer speeds, and both half and full
duplex operation.
HP 10/100 TX PCI LAN Interface Features
FeatureDescription
RJ45 connectorConnection to Ethernet 10/100 TX autonegotiation
BootROMProtocols:
•PxE 2.0
•On-board socket support up to 128Kb
Remote Power On
(RPO)
Remote Wake Up
(RWU)
Power Management
Manageability
Diagnostic
Full remote power on using Magic Packet for Microsoft
Windows NT 4.0 in APM mode.
Enable and Wake Up from Suspend state using Magic
Packet and Pattern Matching for Microsoft Win2000 in
ACPI mode.
This feature enables a host computer to remotely (over
the network) poweroncomputers and wake computers up
from energy-saving sleep mode. To enable these features,
use the Setup program to configure the BIOS.
•OnNow 1.0
•Advanced Power Management 1.2
•PCI Power Management 1.1
•WfM 2.0 compliant, ACPI
•Desktop Management Interface (DMI) 2.0 dynamic
driver
•DMI 2.0 SNMP mapper
•PXE 2.0 Flashable BootROM (optional on socket)
•Mac address DOS report tool
•User Diag for DOS
100
Chapter 5
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