HP 14-Q070NR Schematics

5

www.schematic-x.blogspot.com

4

3

2

1

01

A23 SHB ULT SYSTEM BLOCK DIAGRAM

D D

USB2.0 (Rserve)

Memory Down

Channel A 1Rx16

Channel B 1Rx16

SATA SSD 16GB/32GB

ICT

USB 2.0 Port

Push-Push

C C

socket

CON.

Card Reader Realtek RTS5141

NGFFWWANSIM Slot

ICTICT

MINI CARD WLAN+BT

Dual Channel DDR3L 1333/1600 MHZ

NGFF

USB2.0

I/O Board Conn.

USB2.0

PCIECLOCK-2

SATA0

USB2.0 x3

PCIE-3

USB2.0

Haswell ULT 15W

MCP 1168pins

IMC

SATA

DC+GT2

40 mm X 24 mm

Integrated PCH

CLK

CI-E x1

P

USB2.0

ICT

SB3.0/2.0

U

USB3.0/2.0

I2C

eDP

Realtek

eDP to LVDS

LVDS

RTD2132R

USB2.0

DMIC

DDI1

I2C

Ambit Light Sensor Intersil ISL29023

HDMI Conn.

USB3 Port MB side

Touch Panel conn

LVDS CONN.

CCD(Camera) DMIC

LVDS CONN.

Combo HP / MIC

B B

A A

Speaker

5

Int. MIC

Realtek ALC283

AUDIO CODEC RTD3

PP3300_RTC

TPM Infineon SLB9655TT1.2

F4.32

4

Azalia

RTC

Thermal IC

I

HDA

LPC

P2~P13

X'TAL 32.768KHz X'TAL 24MHz

Keyboard

K/B controlled recover/reset IC

Silego SLG4N059 SLG4K4137

3

SPI

I2C

ICT

EC

TI TM4E1G31H6ZRBI

Google Debug conn

SPI ROM/8MB

Touch pad

X'TAL

32.768KHz

Fan Driver

(PWM Type)

2

BQ24738

Batery Charger

TPS51225

PP3300_DSW/PP5000

NCP81101

+VCCIN

AOZ1237

PP1050_PCH_SUS

TPS51216

PP1350

APW8824

PP1500_PCH_TS

C

Date:

Thermal Protection Discharger

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Block Diagram

Tuesday, August 20, 2013

1

Sheet :

ICT

of

1 42

Rev.Size

1A

5

4

3

2

1

02

D D

Haswell ULT (DISPLAY,eDP)

U42A

INT_HDMITX2N[18] INT_HDMITX2P[18] INT_HDMITX1N[18] INT_HDMITX1P[18] INT_HDMITX0N[18]

HDMI

INT_HDMITX0P[18]

INT_HDMICLK-[18] INT_HDMICLK+[18]

DP

C C

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

U42I

HSW_ULT_DDR3L

1 OF 19

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP DP_UTIL

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2

EDPDDI

EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

I

EDP_TXN0 [16] EDP_TXP0 [16] EDP_TXN1 [16] EDP_TXP1 [16]

EDP_TXN2 [16] EDP_TXP2 [16] EDP_TXN3 [16] EDP_TXP3 [16]

EDP_AUXN [16] EDP_AUXP [16]

R149 24.9/F_4

R561 *0/J_4 R562 *0/J_4

DP_UTIL [16]

eDP Panel

PCH_BL_PWM

+VCCIOA_OUT

eDP_RCOMP Trace length < 100 mils Trace width = 20 mils Trace spacing = 25 mils

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

C

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

HDMI_DDCCLK_SW [18] HDMI_DDCDATA_SW [18]

INT_HDMI_HPD [18] EDP_HPD [16]

R806 100K/J_4

+VCCIOA_OUT[5]

PP3300_PCH[7,8,9,10,11,13,20,25,29]

PCH_GPIO77 PCH_GPIO78 PCH_GPIO79 PCH_GPIO80 SIM_DET TOUCH_INT_L_DX ALS_INT_L TRACKPAD_INT_DX GPIO55

DDPB/C_CTRLDATA has an iPD 20K, When PU at rising edge of

PCH_PWROK, the DDI port will be detected

+VCCIOA_OUT PP3300_PCH

R160 10K/J_4 R635 10K/J_4 R623 10K/J_4 R617 10K/J_4 R6433 10K/J_4 R599 10K/J_4 R607 10K/J_4 R602 10K/J_4 R6541 10K/J_4

PP3300_PCH

+3V

B8 A9

C6

U6

P4 N4 N2

AD4

U7

L1

L3 R5

L4

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

+3V +3V +3V +3V +3V

eDP SIDEBAND

+3V +3V +3V +3V +3V_S5

PCIE

9 OF 19

DISPLAY

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

TP46

PCH_GPIO77 PCH_GPIO78 PCH_GPIO79 PCH_GPIO80

PCH_BL_PWM PCH_BL_EN PCH_EDP_VDD_EN

PCI_PME#

GPIO55 SIM_DET TOUCH_INT_L_DX ALS_INT_L TRACKPAD_INT_DX

PCH_BL_PWM[16,26] PCH_BL_EN[16,26]

PCH_EDP_VDD_EN[16,26]

SIM_DET[22] TOUCH_INT_L_DX[20] ALS_INT_L[22] TRACKPAD_INT_DX[25]

Haswell C-1 2c BGA 1.6GHz ULV 15W 2+2 i5-4200U QS for proto/AJ0QEVEVT01

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 1/5 (DDI/eDP)

Date:

Tuesday, August 20, 2013

5

4

3

2

Tuesday, August 20, 2013

Sheet :

1

T

of

2 42

Rev.Size

1A

5

4

3

2

1

Haswell ULT (DDR3L) Haswell Processor (DDR3L)

U42C

M_A_DQ<0>[14] M_A_DQ<1>[14] M_A_DQ<2>[14] M_A_DQ<3>[14] M_A_DQ<4>[14] M_A_DQ<5>[14] M_A_DQ<6>[14] M_A_DQ<7>[14]

D D

C C

M_A_DQ<8>[14] M_A_DQ<9>[14] M_A_DQ<10>[14] M_A_DQ<11>[14] M_A_DQ<12>[14] M_A_DQ<13>[14] M_A_DQ<14>[14] M_A_DQ<15>[14] M_A_DQ<16>[14] M_A_DQ<17>[14] M_A_DQ<18>[14] M_A_DQ<19>[14] M_A_DQ<20>[14] M_A_DQ<21>[14] M_A_DQ<22>[14] M_A_DQ<23>[14] M_A_DQ<24>[14] M_A_DQ<25>[14] M_A_DQ<26>[14] M_A_DQ<27>[14] M_A_DQ<28>[14] M_A_DQ<29>[14] M_A_DQ<30>[14] M_A_DQ<31>[14] M_A_DQ<32>[14] M_A_DQ<33>[14] M_A_DQ<34>[14] M_A_DQ<35>[14] M_A_DQ<36>[14] M_A_DQ<37>[14] M_A_DQ<38>[14] M_A_DQ<39>[14] M_A_DQ<40>[14] M_A_DQ<41>[14] M_A_DQ<42>[14] M_A_DQ<43>[14] M_A_DQ<44>[14] M_A_DQ<45>[14] M_A_DQ<46>[14] M_A_DQ<47>[14] M_A_DQ<48>[14] M_A_DQ<49>[14] M_A_DQ<50>[14] M_A_DQ<51>[14] M_A_DQ<52>[14] M_A_DQ<53>[14] M_A_DQ<54>[14] M_A_DQ<55>[14] M_A_DQ<56>[14] M_A_DQ<57>[14] M_A_DQ<58>[14] M_A_DQ<59>[14] M_A_DQ<60>[14] M_A_DQ<61>[14] M_A_DQ<62>[14] M_A_DQ<63>[14]

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57

AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54

AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

HSW_ULT_DDR3L

DDR CHANNEL A

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1 SA_CKE0

SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS SA_BA0

SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32 AY34

AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

TP62 TP60

+VREF_CA_CPU +VREFDQ_SA_M3 +VREFDQ_SB_M3

M_A_DIM0_CK_DDR0_DN [14]

M_A_DIM0_CK_DDR0_DP [14]

M_A_DIM0_CKE0 [14]

M_A_DIM0_CS0_N [14]

M_A_RAS_N [14] M_A_WE_N [14] M_A_CAS_N [14]

M_A_BS0 [14] M_A_BS1 [14] M_A_BS2 [14]

M_A_A<0> [14] M_A_A<1> [14] M_A_A<2> [14] M_A_A<3> [14] M_A_A<4> [14] M_A_A<5> [14] M_A_A<6> [14] M_A_A<7> [14] M_A_A<8> [14] M_A_A<9> [14] M_A_A<10> [14] M_A_A<11> [14] M_A_A<12> [14] M_A_A<13> [14] M_A_A<14> [14] M_A_A<15> [14]

M_A_DQS_DN<0> [14] M_A_DQS_DN<1> [14] M_A_DQS_DN<2> [14] M_A_DQS_DN<3> [14] M_A_DQS_DN<4> [14] M_A_DQS_DN<5> [14] M_A_DQS_DN<6> [14] M_A_DQS_DN<7> [14]

M_A_DQS_DP<0> [14] M_A_DQS_DP<1> [14] M_A_DQS_DP<2> [14] M_A_DQS_DP<3> [14] M_A_DQS_DP<4> [14] M_A_DQS_DP<5> [14] M_A_DQS_DP<6> [14] M_A_DQS_DP<7> [14]

U42D

M_B_DQ<0>[15] M_B_DQ<1>[15] M_B_DQ<2>[15] M_B_DQ<3>[15] M_B_DQ<4>[15] M_B_DQ<5>[15] M_B_DQ<6>[15] M_B_DQ<7>[15] M_B_DQ<8>[15] M_B_DQ<9>[15] M_B_DQ<10>[15] M_B_DQ<11>[15] M_B_DQ<12>[15] M_B_DQ<13>[15] M_B_DQ<14>[15] M_B_DQ<15>[15] M_B_DQ<16>[15] M_B_DQ<17>[15] M_B_DQ<18>[15] M_B_DQ<19>[15] M_B_DQ<20>[15] M_B_DQ<21>[15] M_B_DQ<22>[15] M_B_DQ<23>[15] M_B_DQ<24>[15] M_B_DQ<25>[15] M_B_DQ<26>[15] M_B_DQ<27>[15] M_B_DQ<28>[15] M_B_DQ<29>[15] M_B_DQ<30>[15] M_B_DQ<31>[15] M_B_DQ<32>[15] M_B_DQ<33>[15] M_B_DQ<34>[15] M_B_DQ<35>[15] M_B_DQ<36>[15] M_B_DQ<37>[15] M_B_DQ<38>[15] M_B_DQ<39>[15] M_B_DQ<40>[15] M_B_DQ<41>[15] M_B_DQ<42>[15] M_B_DQ<43>[15] M_B_DQ<44>[15] M_B_DQ<45>[15] M_B_DQ<46>[15] M_B_DQ<47>[15] M_B_DQ<48>[15] M_B_DQ<49>[15] M_B_DQ<50>[15] M_B_DQ<51>[15] M_B_DQ<52>[15] M_B_DQ<53>[15] M_B_DQ<54>[15] M_B_DQ<55>[15] M_B_DQ<56>[15] M_B_DQ<57>[15] M_B_DQ<58>[15] M_B_DQ<59>[15] M_B_DQ<60>[15] M_B_DQ<61>[15] M_B_DQ<62>[15] M_B_DQ<63>[15]

AY31

AW31

AY29

AW29

AV31 AU31 AV29 AU29 AY27

AW27

AY25

AW25

AV27 AU27 AV25 AU25 AM29 AK29

AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25

AL25 AY23

AW23

AY21

AW21

AV23 AU23 AV21 AU21 AY19

AW19

AY17

AW17

AV19 AU19 AV17 AU17 AR21 AR22

AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18

AL18 AK20 AM20 AR18 AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HSW_ULT_DDR3L

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS SB_BA0

SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32 AM35

AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

TP63 TP57

M_B_A<0> [15] M_B_A<1> [15] M_B_A<2> [15] M_B_A<3> [15] M_B_A<4> [15] M_B_A<5> [15] M_B_A<6> [15] M_B_A<7> [15] M_B_A<8> [15] M_B_A<9> [15] M_B_A<10> [15] M_B_A<11> [15] M_B_A<12> [15] M_B_A<13> [15] M_B_A<14> [15] M_B_A<15> [15]

M_B_DIM0_CK_DDR0_DN [15]

M_B_DIM0_CK_DDR0_DP [15]

M_B_DIM0_CKE0 [15]

M_B_DIM0_CS0_N [15]

M_B_RAS_N [15] M_B_WE_N [15] M_B_CAS_N [15]

M_B_BS0 [15] M_B_BS1 [15] M_B_BS2 [15]

M_B_DQS_DN<0> [15] M_B_DQS_DN<1> [15] M_B_DQS_DN<2> [15] M_B_DQS_DN<3> [15] M_B_DQS_DN<4> [15] M_B_DQS_DN<5> [15] M_B_DQS_DN<6> [15] M_B_DQS_DN<7> [15]

M_B_DQS_DP<0> [15] M_B_DQS_DP<1> [15] M_B_DQS_DP<2> [15] M_B_DQS_DP<3> [15] M_B_DQS_DP<4> [15] M_B_DQS_DP<5> [15] M_B_DQS_DP<6> [15] M_B_DQS_DP<7> [15]

03

3 OF 19

B B

A A

5

ICT IC

4

3

4 OF 19

2

T

+VREF_CA_CPU[14] +VREFDQ_SA_M3[14] +VREFDQ_SB_M3[15]

+VREF_CA_CPU +VREFDQ_SA_M3 +VREFDQ_SB_M3

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 2/5 (DDR3 I/F)

Date:

Tuesday, August 20, 2013

ICT

Rev.Size

1A

Sheet :

1

of

3 42

1A

5

4

3

2

1

04

D D

C C

DRAM COMP

H_PECI (50ohm) Route on microstrip only Spacing >18 mils Trace Length: 0.4~6.125 iches

H_PWRGOOD (50ohm) Trace Length: 1~11.25 inches

CPU_PLTRST# (50ohm) Trace Length: 10~17 inches

H_PROCHOT#[17,26,32]

CPU_PGOOD[26]

R683 200/F_4

R691 121/F_4

R686 100/F_4

TP79

H_PECI[26] XDP_PRDY# [13]

SM_RCOMP[0:2] Trace length < 500 mils Trace width = 12~15 mils Trace spacing = 20 mils

TP25

R605 56/J_4

R87 *0/J_4S

TP83

XDP PU/PD

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

Haswell ULT (SIDEBAND)

U42B

AU60 AV60 AU61 AV15 AV61

XDP_TDO_CPU

XDP_TCK0 XDP_TRST#

D61

PROC_DETECT

K61

CATERR

N62

PECI

K63

PROCHOT

C61

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

R141 51/J_4

R202 51/J_4 R690 *51/J_4

MISC

THERMAL

PWR

DDR3L

DSW

+1.05V_VCCST

PROC_DETECT CATERR# H_PECI

H_PROCHOT#_RH_PROCHOT#

H_PWRGOOD_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

DDR_PG_CTRL

HSW_ULT_DDR3L

JTAG

2 OF 19

PRDY

PREQ PROC_TCK PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

J62 K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_PRDY# XDP_PREQ# XDP_TCK0 XDP_TMS_CPU XDP_TRST# XDP_TDI_CPU XDP_TDO_CPU

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7CPU_DRAMRST#

XDP_PREQ# [13] XDP_TCK0 [8,13] XDP_TMS_CPU [13] XDP_TRST# [8,13] XDP_TDI_CPU [13] XDP_TDO_CPU [13]

XDP_BPM#0 [13]

XDP_BPM#1 [13]

TP82 TP80 TP23 TP81 TP27 TP24

TCK,TMS Trace Length < 9000mils

BPM#[0:7] Trace Length 1~6 inches Length match < 300 mils

B B

A A

5

PU/PD of CPU

H_PROCHOT#

H_PWRGOOD_R

+1.05V_VCCST

R614 62/J_4

R569 10K/J_4

DRAMRST

PP1350

12

R403 470/J_4

CPU DRAM

CPU_DRAMRST#

4

R404 *0/J_4S

12

*0.1u/10V/X5R_4

DDR3_DRAMRST# [14,15]

C459

3

+1.05V_VCCST[5,10] PP1350[5,14,15,30]

2

+1.05V_VCCST PP1350

Date:

+1.35V_SUS

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 3/5 (SideBand)

Friday, August 16, 2013

Rev.Size

1A

Sheet :

1

of

4 42

1A

5

4

3

2

1

05

D D

VCC Output Decoupling Recommendations

VDDQ Output Decoupling Recommendations

330uFx2 7343 22uFx11 10uFx10

PP1350

PP3300_DSW

VCCST PWRGD

C C

B B

A A

PP1050_PGOOD[13,26,31]

PCH_PWROK[7,26] SYS_PWROK[7,13,26]

R579 *0/J_4 R544 *0/J_4S R580 *0/J_4

0415 VCCST PWRGD

SVID

VR_SVID_DATA[32]

VR_SVID_ALERT#[32]

VR_SVID_CLK[32]

VCCST_PWRGD_EN VCCST_PWRGD_R

Layout note: need routing together and ALERT need between CLK and DATA.

Place PU resistor close to CPU

R625 *0/J_4S

+1.05V_VCCST

NC1VCC

2

A

ICT

GND3Y

74AUP1G07GW

Reserve

D46 *RB501V-40

G Path

+1.05V_VCCST

Place PU resistor close to CPU

R640 75/J_4

R630 43/J_4

C5667

R6554

0.1U/10V/X7R_4

54.9/F_4

R641 *0/J_4S

U38

21

R618 130/F_4

5

4

H_CPU_SVIDDAT

H_CPU_SVIDART#

H_CPU_SVIDCLK

CRB is via +1.05V PG

C584

0.1U/10V/X5R_4

R545 *0/J_4S

VCCST_PWRGD[13]

+1.05V_VCCST

C582 *0.1u/10V/X5R_4

R551 10K/J_4

VRON_CPU[32]

VCORE_PGOOD[10,32]

PWR_DEBUG[13]

+VCCIN

C225 22u/6.3V/X5R_8

VCC_SENSE[32]

+1.05V_VCCST

0415 VCCST_PWRGD need PP1050_RUN power good

+1.05V_VCCST

EC14 *1U/6.3V/X5R_4

Reserve for RF

BOT socket side 5 onTOP, 6 on BOT inside socket cavity

0805

5 onTOP, 5 on BOT inside socket cavity

0805

C5658

C5657

10u/6.3V/X5R_6

+1.35V_CPU 1.4A

C260

C261

10u/6.3V/X5R_6

R583 100/F_4

+VCCIN

R587 *0/J_4S

R566 *10K/J_4 R567 10K/J_4

R173 *0/J_4S R151 150/J_6

EC15 *470p/50V/X7R_4

C5656 10u/6.3V/X5R_6

C259 10u/6.3V/X5R_6

+VCCIN

300mA

+VCCIOA_OUT

300mA

R190 *0/J_8S

C5660

2.2u/6.3V/X7R_6

C224

2.2u/6.3V/X7R_6

+1.05V_VCCSTPP1050_PCH

+VCCIN

C5659

2.2u/6.3V/X7R_6

TP29 TP20

C256

2.2u/6.3V/X7R_6

TP28 TP41

TP42 TP514

TP43 TP47 TP50

TP30 TP31 TP26 TP85 TP32 TP49 TP51 TP36 TP39 TP37 TP54 TP35 TP34

C223 *4.7u/6.3V/X5R_6

ULT_RVSD_61 ULT_RVSD_62

ULT_RVSD_63 ULT_RVSD_64

VCC_SENSE_R ULT_RVSD_65 +VCCIO_OUT

ULT_RVSD_66 ULT_RVSD_67 ULT_RVSD_68

H_CPU_SVIDART# H_CPU_SVIDCLK H_CPU_SVIDDAT VCCST_PWRGD VRON_CPU VCORE_PGOOD

PWR_DEBUG_R ULT_RVSD_69

ULT_RVSD_70 ULT_RVSD_71 ULT_RVSD_72 ULT_RVSD_73 ULT_RVSD_74 ULT_RVSD_75 ULT_RVSD_76 ULT_RVSD_77 ULT_RVSD_78 ULT_RVSD_79 ULT_RVSD_80 ULT_RVSD_81

Haswell ULT (POWER)

HSW_ULT_DDR3L

HSW ULT POWER

12 OF 19

+VCCIOA_OUT +VCCIN +1.05V_VCCST PP1350 PP1050_PCH PP3300_DSW

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

AC58

AB23

AD23 AA23 AE59

AD60 AD59 AA59 AE60 AC59 AG58

AC22 AE22 AE23

AB57 AD57 AG57

L59 J58

F59 N58

E63 A59

E20

L62 N63 L63 B59 F60 C59

D63 H59 P62 P60 P61 N59 N61 T59

U59 V59

C24 C28 C32

U42L

RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

+VCCIOA_OUT[2] +VCCIN[32] +1.05V_VCCST[4,10] PP1350[4,14,15,30] PP1050_PCH[11,13,26,31] PP3300_DSW[7,8,10,11,13,20,21,24,25,26,28,29,33]

470uFx4 7343 22uFx8 22uFx11 10uFx11

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

ICT

TOP socket side 4 on TOP, 4 on BOT near socket edge

0805 0805

TOP, inside socket cavity

0805

BOT, inside socket cavity

+VCCIN 32A

C46 22u/6.3V/X5R_8

C190 22u/6.3V/X5R_8

C567 *22u/6.3V/X5R_8

C210 22u/6.3V/X5R_8

C167 22u/6.3V/X5R_8

C562 22u/6.3V/X5R_8

C204 22u/6.3V/X5R_8

C173 22u/6.3V/X5R_8

C71 22u/6.3V/X5R_8

C168 22u/6.3V/X5R_8

C73 22u/6.3V/X5R_8

C557 22u/6.3V/X5R_8

C45 22u/6.3V/X5R_8

C172 22u/6.3V/X5R_8

C74 22u/6.3V/X5R_8

+VCCIN

C228 22u/6.3V/X5R_8

C75 *22u/6.3V/X5R_8

C201 22u/6.3V/X5R_8

C202 22u/6.3V/X5R_8

C206 22u/6.3V/X5R_8

C169 22u/6.3V/X5R_8

C171 22u/6.3V/X5R_8

C165 22u/6.3V/X5R_8

C203 22u/6.3V/X5R_8

C170 22u/6.3V/X5R_8

C205 22u/6.3V/X5R_8

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 4/5 (POWER)

Date:

Tuesday, August 20, 2013

5

4

3

2

Tuesday, August 20, 2013

Sheet :

1

ICT

of

5 42

Rev.Size

1A

5

4

3

2

1

06

D D

CFG0[13] CFG1[13] CFG2[13] CFG3[13] CFG4[8,13] CFG5[13] CFG6[13] CFG7[13] CFG8[13]

CFG9[13] CFG10[13] CFG11[13] CFG12[13] CFG13[13] CFG14[13] CFG15[13]

NOA_STBN_0[13] NOA_STBN_1[13] NOA_STBP_0[13] NOA_STBP_1[13]

R177 49.9/F_4

C C

NOA_STBN_0 NOA_STBN_1 NOA_STBP_0 NOA_STBP_1

CFG_RCOMP

R572 8.2K/J_4

Processor Strapping

CFG0 EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKED

CFG1

PCH/ PCH LESS MODE SELECTION

CFG3

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

CFG 8 ALLOW THE USE OF NOA ON LOCKED UNITS

CFG9

B B

NO SVID PROTOCOL CAPABLE VR CONNECTED

(DEFAULT) NORMAL OPERATION; NO STALL

(DEFAULT) NORMAL OPERATION

DISABLED NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

DISABLED(DEFAULT); IN THIS CASE, NOA WILL BE DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS

VRS SUPPORTING SVID PROTOCOL ARE PRESENT

Haswell ULT (CFG,RSVD)

U42S

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

1 0

STALL

PCH-LESS MODE

ENABLED AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT

ENABLED; NOA WILL BE AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT

NO VR SUPPORTING SVID IS PRESENT. THE CHIP WILL NOT GENERATE (OR RESPOND TO) SVID ACTIVITY

HSW_ULT_DDR3L

RESERVED

19 OF 19

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD RSVD

RSVD

PROC_OPI_RCOMP

RSVD RSVD

AV63 AU63

C63 C62 B43

A51 B51

L60 N60 W23

Y22 AY15

OPI_COMP1

CFG0

CFG1

CFG3

CFG9

R700 49.9/F_4

R203 *1K/J_4

R184 *1K/J_4

R192 *1K/J_4

R171 *1K/J_4

R172 *1K/J_4

AV62 D58

P22

VSS

N21

VSS

P20 R20

CFG8

CFG10

E MODE BOOT

SAF

A A

5

4

POWER FEATURES ACTIVATED DURING RESET

POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED

3

CFG10

R183 *1K/J_4

2

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 5/5 (CFG/GND)

Date:

Friday, August 16, 2013

Rev.Size

1A

Sheet :

1

of

6 42

1A

5

4

3

2

1

07

D D

Haswell ULT PCH (PM)

SUSACK#_R

C617 *1U/6.3V/X5R_4

R547 *0/J_4S

R719 *0/J_4S R659 *0/J_4 R274 *0/J_4S R277 *0/J_4S

R653 *0/J_4S

R664 *0/J_4S

R662 *0/J_4

TP45

SUSACK#_RPCH_SUSPWRACK

SYS_RESET#

SYS_PWROK_R PCH_PWROK_R APWROK_RPCH_PWROK PCI_PLTRST#

PCH_RSMRST#

PCH_SUSPWRACK

PCH_PWRBTN# PCH_ACPRESENT PCH_BATLOW# PCH_SLP_S0#_R

PCH_SUSACK_L[26]

SYS_RESET#[13,17]

SYS_PWROK

SYS_PWROK[5,13,26]

PCH_RSMRST_L[13,26]

PCH_SUSWARN_L[26]

PCH_PWRBTN_L[26]

ACPRESENT[27]

PCH_SLP_S0_L[13,26]

R656 *0/J_4S

U42H

ICT

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

+3V_S5

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

+3V_S5 DSW DSW DSW +3V_S5 DSW

8 OF 19

+3V +3V_S5 +3V_S5 DSW

DSWVRMEN

DPWROK

DSW

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

DSW

SLP_S4

DSW

SLP_S3

DSW

SLP_A

DSW

SLP_SUS

DSW

SLP_LAN

AW7

DSWVREN

AV5

DPWROK_R

AJ5

PCIE_PCH_WAKE#

V5

CLKRUN#

AG4

PCH_SUS_STAT

AE6

PCH_SUSCLK

AP5

PCH_SLP_S5_L

AJ6

PCH_SLP_S4_L

AT4

PCH_SLP_S3_L

AL5

PCH_SLP_A_L

AP4

PCH_SLP_SUS_L

AJ7

PCH_SLP_LAN#

Deep Sx

R722 *0/J_4S

R813 *0/J_4S

R816 *0/J_4S

TP64 TP44

TP58

DSWVREN [8] PCH_DPWROK [26]

LPC_CLKRUN_L

PCH_SLP_S5_L [13,26,29,30]

PCH_SLP_S4_L [13] PCH_SLP_S3_L [13,26,29,30,31,33] PCH_SLP_A_L [13] PCH_SLP_SUS_L [26,29]

PCH_WAKE_L [26]

LPC_CLKRUN_L [26]

4/22 modify, default skip EC control

C C

PCH PM PU/PD

PP3300_PCH

CLKRUN# SYS_RESET#

PCH_RSMRST# SYS_PWROK DPWROK_R

PCH_SUSPWRACK

B B

PCH_ACPRESENT PCH_BATLOW# PCIE_PCH_WAKE# PCH_PWRBTN#

R176 8.2K/J_4 R644 10K/J_4

R6550 *1K/J_4 R707 10K/J_4 R565 *10K/J_4 R721 100K/F_4

PP3300_PCH_SUS

R696 10K/J_4

PP3300_DSW

R259 10K/J_4 R262 8.2K/J_4 R276 1K/J_4 R261 *10K/J_4

PLTRST# Buffer

PCH_PWROK[5,26]

PCI_PLTRST#

4/22 modify, default is bypass PLTRST#

PCH_PWROK PCH_PWROK_R

R354 10K/J_4

PP3300_PCH

C255 *0.1u/10V/X5R_4

2 1

U19

3 5

*TC7SH08FU

4

R353 *0/J_4S

R720 *0/J_4

No

n Deep Sx

R242 100K/J_4

PCI_PLTRST# PLTRST#

DPWROK_RPCH_RSMRST_L

PLTRST# [13,19,21,22,26]

R757 *0/J_4S

PP3300_PCH[2,8,9,10,11,13,20,25,29] PP3300_PCH_SUS[8,9,10,11,13,20,25,29] PP3300_DSW[5,8,10,11,13,20,21,24,25,26,28,29,33]

PP3300_PCH PP3300_PCH_SUS PP3300_DSW

check if need pull up to DEEP _SUS

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

PCH 1/6 (PM)

Date:

Tuesday, August 20, 2013

5

4

3

2

Tuesday, August 20, 2013

Sheet :

1

ICT

of

7 42

Rev.Size

1A

RTC Clock 32.768KHz (RTC)

RTC Circuitry (RTC)

PP3300_RTC

D D

HDA

PCH JTAG

C C

C624 12p/50V/C0G_4

C625 12p/50V/C0G_4

+3V_RTC Tr

PCH_AZ_CODEC_RST#[23]

PCH_AZ_CODEC_SDOUT[23]

PCH_AZ_CODEC_BITCLK[23]

PCH_AZ_CODEC_SYNC[23]

JTAG_TCK,JTAG_TMS

ace Length < 9000mils

Tr

XDP_TMS XDP_TDI PCH_JTAG_TDO PCH_JTAGX

XDP_TCK1

ace width = 20 mils

R373 *0/J _6S R708 1M/J_4

5

23

Y7

32.768KHZ

4 1

+3V_RTC

R703 33/J _4 R701 33/J _4 R698 33/J _4

C639 22p/50V/NPO_4

R726 33/J _4 C638 *10p/50V/COH_4

MP remove(Intel)

R200 51/J_4 R201 51/J_4 R216 *51/J_4 R650 *1K/J_4

R657 51/J_4

RTC_X1

R699 10M/J_4

RTC_X2

+3V_RTC Trace width = 30 mils

R754

20K/F_4

C671 1U/6.3V/X5R_4

R750

20K/F_4

C676

C670

1U/6.3V/X5R_4

PP1050_PCH_SUS

check if need c onnect to PCH_RTCRST_ R/PCH_SRTCRST_R

PCH_RTCRST_R

PCH_SRTCRST_R

HDA_RST#_R HDA_SDO_R HDA_BCLK_R

HDA_SYNC_R

+3V_RTC

PCH_AZ_CODEC_SDIN0[23]

R6407 *0/J_4 R6408 *0/J_4

R215 *0/J_4S

R652 *0/J_4S

PCH_SRTCRST[26] PCH_RTCRST[13,26]

4/22 modify, default skip EC control

RTCRST_L and SRTCRST_L please take out layout

XDP_TRST#[4,13]

XDP_TCK1[13] XDP_TDI[13] XDP_TDO[13] XDP_TMS[13]

XDP_TCK0[4,13]

ULT Strapping Table

Pin Name Strap description

GPIO81(SPKR)

HDA_SDO

INTVRMEN

GPIO66

GPIO86

GPIO15

B B

CFG4

DSWVREN

No reboot on TCO Timer expiration

Flash Descriptor Security Override / Intel ME Debug Mode

Integrated 1.05V VRM enable ALWAYS

Top-Block Swap override

Boot BIOS Strap Bit

TLS(Transport layer security)

DP presence strap

Deep Sx well on die VR enable

Sampled

PWROK

Configuration note

0 = Default enable (iPD 20K)

1 =Disable No-Reboot mode

0 = Default can program ME (iPD 20K)

1 =can't program ME

1=Should be always pull-up

0 = Default disable (iPD 20K)

1 = Enable TBS function

0 = Default SPI (iPD 20K)

1 =LPC

0 = Default enable w/o confidentiality(iPD 20K)

1 =Default enable with confidentiality

0 = Enable an external display

rt is connected to the eDP

po

1 =disable

1=Should be always pull-up

4

Haswell ULT PCH (RTC/HDA/SATA/SPI)

HSW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

R642 *1K /J_4

R702 *0/J _4

PCH_INTVRMEN

GPIO66[10]

R578 *1K /J_4

GPIO86[10]

R136 *1K/J_4

GPIO15[10]

R195 *8.2K /J_4

CFG4[6,13]

x86 stuff

CFG4

DSWVREN

GPIO66

GPIO86

GPIO15

5 OF 19

+3V +3V +3V +3V

SPKR

PCH_HDA_SDO [26]

R704 *330K /J_4

R577 *1K /J_4

R129 *1K /J_4

R189 *1K /J_4

R193 1K/J _4

R706 *330K /J_4

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SPKR [10,23]

RTC_X1 RTC_X2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST_R PCH_RTCRST_R

HDA_BCLK_R HDA_SYNC_R HDA_RST#_R

HDA_SDO_R

XDP_TCK1 XDP_TDI PCH_JTAG_TDO

PCH_JTAGX

U42E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

PP3300_PCH

+3V_RTC

PP3300_PCH

PP3300_PCH_SUS

DSWVREN[7]

+3V_RTC

HDA_SDO_R

R717 330K/ J_4

R718 330K/ J_4

3

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

RSVD RSVD

SATA_RCOMP

SATALED

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1

EC_SMI_L

U1

PCH_NMI_DBG_L

V6

EC_SCI_L

AC1

GPIO37

A12

SATA_IREF

L11 K10 C12

SATA_RCOMP

U3

SATA_LED#

SATA_RCOMP Impedance = 50 ohm Trace length < 500 mils Trace spacing = 15 mils

PCH dual I/O SPI ROM

4/23 modify for WP circuit

SPI_WP_ME

R573 *0/J_4S

R574 3.01K /F_4 R636 10K/J _4

PP3300_DSW

PCH_SPI_CS0#_R[17] PCH_SPI_CLK_R[17] PCH_SPI_SI_R[17]

PCH_SPI_SO_R[17]

PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO

SATA_RXN0_SSD [2 0] SATA_RXP0_SSD [20] SATA_TXN0_SSD [20] SATA_TXP0_SSD [20]

+V1.05S_ASATA3PLL

PP3300_PCH

R627 *0/J _6S R624 *0/J _6

near SPI ROM as possible

R146 33/J_4 R145 33/J_4 R153 33/J_4 R103 33/J_4

C162 *22p/50V/NPO_4

+3V_PCH_ME

C257 0.1U/10V/X5R_4

2 1

U21

3 5

TC7SH08FU

SPI_WP_ME SPI_HOLD_ME

1

2

Haswell ULT PCH(LPC,SPI,SMBUS,C-LINK,THERMAL)

LPC_LAD0[19,21,26] LPC_LAD1[19,21,26] LPC_LAD2[19,21,26] LPC_LAD3[19,21,26]

LPC_LFRAME#[19,21,26]

TP88

TP91 TP115

EC_SMI_L [26] PCH_NMI_DBG_L [26] EC_SCI_L [26]

W25Q64FVSSIG(SOIC) / AKE3EFP0N06----->8MB

D2 RB500V-40

R541 *0/J_4S R546 *0/J_4S R548 *0/J_4S R549 *0/J_4S

4

SPI_WP_ME_ROM

R658 10K/J_4

4/23 modify for WP circuit

near SPI ROM as possible

R552 *0/J_4S R553 *0/J_4S

Q472N7002K

3

2

SPI_WP_ME

AU14

AW12

AY12

AW11

AV12

AA3

PCH_SPI_CLK

Y7 Y4

PCH_SPI_CS1#

AC2 AA2

PCH_SPI_SI

AA4

PCH_SPI_SO

Y6

PCH_SPI_IO2

AF1

PCH_SPI_IO3

EC_SMI_L

EC_SCI_L

PCH_NMI_DBG_L

GPIO37

+3V_PCH_MEPP3300_PCH

R309 4.7K/J _4

U14

1

CE#

VDD

6

SCK

5

SI

2

SO

HOLD#

3

WP#

VSS

ROM-8M

GPIO_SPI_WP [17] SPI_HOLD#_BIOS [17]

PCH_SPI_WP_D [10]

PCH_SPI_WP_D co nnect to GPIO58 at GR B

SPI_WP_ME [24,26]

U42G

LAD0 LAD1 LAD2 LAD3 LFRAME

SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3

PP3300_PCH

R182 10K/J_4

R168 10K/J_4 R169 10K/J_4

R655 10K/J_4

+3V_PCH_ME

8

7

SPI_HOLD_ME

R147 100K/ J_4

4

TP523 TP524 TP525 TP526 TP527

5/6 add for ICT

To debug header

To PCH

From Screw/EC

HSW_ULT_DDR3L

LPC

+3V_PCH_ME

C147

0.1U/10V/X5R_4

TP528

+3V_S5 +3V_S5 +3V_S5

SMBUS

+3V_S5 +3V_S5 +3V

+3V_S5

SML1ALERT/PCHHOT/GPIO73

+3V_S5 +3V_S5

C-LINKSPI

SMBus

SMBALERT/GPIO11

SMBDATA

SML0ALERT/GPIO60

_S5

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

7 OF 19

PP3300_PCH_SUS

R680 10K/J_4 R697 10K/J_4 R689 10K/J_4

R285 2.2K/J_4 R284 2.2K/J_4 R663 2.2K/J_4 R661 2.2K/J_4

R278 2.2K/J _4 R290 2.2K/J _4

SMB_PCH_CLK_LVDS[16]

SMB_PCH_DAT_LVDS[16]

DX/LVDS Bridge

SMBCLK

SML0CLK

CL_CLK

CL_DATA

CL_RST

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

R279

2.2K/J_4

1

SMBALERT# SMB_PCH_CLK SMB_PCH_DAT SMB0ALERT# SMB_ME0_CLK SMB_ME0_DAT SMB1ALERT# SMB_ME1_CLK SMB_ME1_DAT

CL_CLKPCH_SPI_CS0# CL_DAT CL_RST#

SMB0ALERT# SMB1ALERT# SMBALERT#

SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SMB_ME1_CLK SMB_ME1_DAT

PP3300_DX

R280

2.2K/J_4

PP3300_DX[16,18,20,21,22,23,25,26,29] +V1.05S_ASATA3PLL[1 1]

PP3300_DSW[5,7,10,11,13,20,21,24,25,26,28,29,33] PP3300_RTC[11,22,23,25,26,27,28]

PP1050_PCH_SUS[11,13,31] PP3300_PCH[2,7,9,10,11,13,20,25,29] PP3300_PCH_SUS[7,9,10,11,13,20,25,29] +3V_PCH_ME[17]

Q68

1

4 3

2N7002DW

LVDS Bridge

TP87 TP86 TP89

SMB_PCH_CLK [13] SMB_PCH_DAT [13]

6

SMB_PCH_CLK

2

SMB_PCH_DAT

5

PCH_SUS/PCH

PP3300_DX +V1.05S_ASATA3PLL

PP3300_DSW PP3300_RTC

PP1050_PCH_SUS PP3300_PCH PP3300_PCH_SUS +3V_PCH_ME

08

PP3300_DX

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

PCH 2/6 (RTC/HDA/SATA/SPI)

Date:

Friday, August 16, 2013

5

4

3

2

Friday, August 16, 2013

Sheet :

1

of

8 42

Rev.Size

1A

5

4

3

2

1

09

Haswell ULT PCH (PCIE,USB3.0,USB2.0)

PCIE USB

+3V_S5 +3V_S5

HSW_ULT_DDR3L

11 OF 19

+3V_S5 +3V_S5

+3V_S5 +3V_S5 +3V_S5 +3V_S5

DSW

USB2N0

DSW

USB2P0

DSW

USB2N1

DSW

USB2P1

DSW

USB2N2

DSW

USB2P2

DSW

USB2N3

DSW

USB2P3

DSW

USB2N4

DSW

USB2P4

DSW

USB2N5

DSW

USB2P5

DSW

USB2N6

DSW

USB2P6

DSW

USB2N7

DSW

USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

ICT

RSVD RSVD

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USBCOMP

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USBP0- [24] USBP0+ [24]

USBP1- [24] USBP1+ [24]

USBP2- [16] USBP2+ [16]

USBP3- [19] USBP3+ [19]

USBP4- [22] USBP4+ [22]

USBP5- [20] USBP5+ [20]

USBP6- [22] USBP6+ [22]

USBP7- [22] USBP7+ [22]

USB3_RXN0 [24] USB3_RXP0 [24]

USB3_TXN0 [24] USB3_TXP0 [24]

USB3_RXN1 [24] USB3_RXP1 [24]

USB3_TXN1 [24] USB3_TXP1 [24]

R245 22.6/F_4

USB_OC0# [26]

USB_OC3# [26]

MB USB3.0_A MB USB3.0_B CCD BT LTE

Touch screen

CardReader

USB 2.0

MB USB3.0_A

MB USB3.0_B

USBCOMP Impedance = 50 ohm Trace length < 500 mils Trace spacing = 15 mils

MB U10/U11 DB

USB Overcurrent

PP3300_PCH_SUS

10

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

RP6

9 8 7 4

10K/J_10P8R

1 2 3

56

U42K

F10

PERN5_L0

E10

PERP5_L0

PCIE_RXN1 PCIE_RXP1

PCIE_TXN1 PCIE_TXP1

PCIE_TX3PCIE_TX3+

C23 C22

F8 E8

B23 A23

H10 G10

B21 C21

E6 F6

B22 A21

G11 F11

C29 B30

F13 G13

B29 A29

G17 F17

C30 C31

F15 G15

B31 A31

E15 E13 A27 B27

PETN5_L0 PETP5_L0

PERN5_L1 PERP5_L1

PETN5_L1 PETP5_L1

PERN5_L2 PERP5_L2

PETN5_L2 PETP5_L2

PERN5_L3 PERP5_L3

PETN5_L3 PETP5_L3

PERN3 PERP3

PETN3 PETP3

PERN4 PERP4

PETN4 PETP4

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

RSVD RSVD PCIE_RCOMP PCIE_IREF

D D

TP22 TP21

TP11 TP9

PCIE_RX3-_WLAN[19] PCIE_RX3+_WLAN[19]

WLAN

PCIE_TX3-_WLAN[19]

C C

PCIE_TX3+_WLAN[19]

+V1.05S_AUSB3PLL

C587 0.1U/10V/X7R_4 C586 0.1U/10V/X7R_4

R571 3.01K/F_4 R570 *0/J_4S

PCIE_RCOMP PCIE_IREF

Haswell ULT PCH (CLOCK)

U42F

CLK_PCIE_WLANN[19] CLK_PCIE_WLANP[19]

WLAN

B B

CLK_PCIE_REQ0# CLK_PCIE_REQ1# CLK_PCIE_REQ2# CLK_PCIE_REQ3# CLK_PCIE_REQ4# CLK_PCIE_REQ5#

A A

PCIE_CLKREQ_WLAN#[19]

PP3300_PCH

R637 10K/J_4 R645 10K/J_4 R654 10K/J_4 R612 10K/J_4 R608 10K/J_4

5

R639 *0/J_4S

TP75 TP73

CLK_PCIE_REQ2#

CLK_PCIE_REQ1# CLK_PCIE_N0

CLK_PCIE_P0 CLK_PCIE_REQ0#

CLK_PCIE_REQ3#

CLK_PCIE_REQ4#

CLK_PCIE_REQ5#

C43 C42

U2

B41 A41

Y5

C41

B42

AD1

B38

C37

N1

A39 B39

U5

B37 A37

T2

4

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23

HSW_ULT_DDR3L

+3V

CLOCK

SIGNALS

6 OF 19

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8

TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

ICLK_BIAS TESTLOW_C35

TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLK_PCH_PCI3 CLK_PCH_PCI4

3

XTAL24_IN

XTAL24_OUT

R558 1M/J_4

1 3

R557 3.01K/F_4

R25722/J_4 R25522/J_4 R653322/J_4

C590 12p/50V/C0G_4

Y6 24MHz

2 4

C591 12p/50V/C0G_4

+V1.05S_AXCK_LCPLL

PCLK_TPM [21] CLK_PCI_EC [26]

CLK_PCI_DEBUG [19] CLK_PCIE_XDPN [13] CLK_PCIE_XDPP [13]

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

2

+V1.05S_AUSB3PLL

PP3300_PCH_SUS PP3300_PCH

+V1.05S_AXCK_LCPLL

+V1.05S_AUSB3PLL[11]

PP3300_PCH_SUS[7,8,10,11,13,20,25,29] PP3300_PCH[2,7,8,10,11,13,20,25,29]

+V1.05S_AXCK_LCPLL[11]

C266

*18p/50V/C0G_4

R563 10K/J_4 R564 10K/J_4 R258 10K/J_4 R271 10K/J_4

PCLK_TPMCLK_PCI_EC

CLK_PCI_DEBUG

C268

*18p/50V/C0G_4R634 10K/J_4

C

Date:

C5651

*18p/50V/C0G_4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

PCH 3/6 (PCIE/USB/CLK)

Tuesday, August 20, 2013

1

Sheet :

of

9 42

Rev.Size

1A

5

4

3

2

1

10

+1.05V_VCCST

12

IMVP_PWRGD_3V

R709 49.9/F_4

PP3300_PCH

R807 10K/J_4

IMVP_PWRGD_3V [26]

+1.05V_VCCST

2

+1.05V_VCCST

R133 1K/J_4

1 3

Q19 MMBT3904-7-F

EC_RCIN_L [26]

IRQ_SERIRQ [21,26]

GPIO86 [8]

I2C0_SDA_GPIO4 [25] I2C0_SCL_GPIO5 [25] I2C1_SDA_GPIO6 [20,22] I2C1_SCL_GPIO7 [20,22]

GPIO66 [8]

3

Q18 FDV301N

1

R132 1K/J_4

2

CPU thermal trip

SYS_SHDN# [22,26,28,33]

strapping

TRACKPAD TOUCHSCREEN / ALS

strapping

4/23 modify, follow Intel suggestion to un-stuff for unused GPIO

GPIO27 : If not used then use

8.2-kΩ to 10-kΩ pull-down to GND.

PCH GPIO PU/PD

EC_RCIN_L IRQ_SERIRQ PCH_SSD_12_EN PCH_SSD_18_EN

PCH_GPIO76 ODD_PRSNT# TPM_LP_EN_L PP3300_SSD_IO_EN GPIO50 GPIO70 GPIO38 GPIO39

GPIO83 GPIO84 GPIO85 GPIO87 GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO0 GPIO1 GPIO2 GPIO3 GPIO64 GPIO65 GPIO67 GPIO68 GPIO69

I2C0_SDA_GPIO4 I2C0_SCL_GPIO5 I2C1_SDA_GPIO6 I2C1_SCL_GPIO7

WK_GPIO27

GPIO24 ODD_PRSNT# GPIO28 PP3300_SSD_EN

PP3300_CODEC_EN

GPIO56 PP3300_CCD_EN

R585 4.7K/J_4 R586 4.7K/J_4 R609 4.7K/J_4 R601 4.7K/J_4

R727 10K/J_4 R728 *10K/J_4

R6536 10K/J_4 R6537 10K/J_4 R6538 10K/J_4 R6539 10K/J_4 R6540 10K/J_4 R6542 10K/J_4 R6545 10K/J_4

R187 10K/J_4 R159 10K/J_4 R651 10K/J_4 R598 10K/J_4

R626 10K/J_4 R679 *10K/J_4 R643 10K/J_4 R649 10K/J_4 R648 10K/J_4 R121 10K/J_4 R611 10K/J_4 R665 10K/J_4

R206 *10K/J_4 R150 *10K/J_4 R207 *10K/J_4 R152 *10K/J_4 R208 *10K/J_4 R205 *10K/J_4 R597 *10K/J_4 R594 *10K/J_4 R209 *10K/J_4 R590 *10K/J_4 R588 *10K/J_4 R210 *10K/J_4 R589 *10K/J_4 R595 *10K/J_4 R592 *10K/J_4 R584 *10K/J_4 R134 *10K/J_4 R130 *10K/J_4 R128 *10K/J_4 R581 *10K/J_4

PP3300_DSW

PP3300_PCH_SUS

PP3300_PCH

GSPUARTI2C SDIO useless GPIO

U55

VCORE_PGOOD[5,32]

D D

2

NC1VCC

A

GND3Y

74AUP1G07GW

5

C767

0.1U/10V/X5R_4

4

Haswell ULT PCH (GPIO,CPU/MISC,NCTF)

+3V_S5 +3V_S5

+3V +3V +3V_S5 DSW +3V_S5 +3V_S5

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V +3V +3V

+3V_S5 +3V_S5 DSW +3V_S5 +3V_S5

+3V_S5 +3V_S5

+3V

HSW_ULT_DDR3L

GPIO

+3V

+3V +3V +3V +3V

4 3

1

DSW

10 OF 19

Q44

*2N7002DW

CPU/ MISC

+3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V

SERIAL IO

+3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V

5

2 6

PP3300_PCH_SUS

THRMTRIP

+3V

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92

UART0_RTS/GPIO93 UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST/GPIO2 UART1_CTS/GPIO3

I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

PP3300_WLAN_EN [19,26,29]

WLAN_WAKE_L_Q

PP3300_LTE_EN [26]

LTE_WAKE_L_Q

R250 10K/J_4 R256 10K/J_4

D60 V4 T4 AW15 AF20 AB21

R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2

THRMTRIP# EC_RCIN_L IRQ_SERIRQ

OPI_COMP2

GPIO83 GPIO84 GPIO85 GPIO86 GPIO87 GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO0 GPIO1 GPIO2 GPIO3 I2C0_SDA_GPIO4 I2C0_SCL_GPIO5 I2C1_SDA_GPIO6 I2C1_SCL_GPIO7 GPIO64 GPIO65 GPIO66 GPIO67 GPIO68 GPIO69

U42J

PCH_GPIO76 LTE_WAKE_L_Q

TP40 TP48

TP52

PP3300_CODEC_EN

TRACKPAD_INT_L PCH_SSD_12_EN

PCH_SSD_18_EN GPIO24 WK_GPIO27 GPIO28 ODD_PRSNT#

GPIO56 PP3300_CCD_EN PCH_SPI_WP_D LTE_DISABLE_L PP3300_SSD_EN RAM_ID2 TPM_LP_EN_L PP3300_SSD_IO_EN GPIO50 MODPHY_EN RAM_ID0 GPIO14 TOUCH_INT_L

RAM_ID1 WLAN_WAKE_L_Q DEVSLP0 GPIO70 GPIO38 GPIO39

TRACKPAD_INT_L[25]

4/22 modify

C C

LTE_DISABLE_L need PU to +3V_LTE

MODPHY_EN[11]

EC_IN_RW[25]

TOUCH_INT_L[20]

WLAN_DISABLE_L[19]

DEVSLP0 for internal SATA I/F.

B B

PP3300_PCH_SUSPP3300_PCH

GPIO15[8]

PCH_SPI_WP_D[8]

LTE_DISABLE_L[22]

R86 *0/J_4S

DEVSLP0[20]

SPKR[8,23]

I PathG Path

R90

R91

*0/J_4S

*0/J_4

R682 10K/J_4 R122 10K/J_4

PCH_SPI_WP_D GPIO14

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

WLAN_WAKE_L[19]

LTE_WAKE_L[22]

RAM ID

PP3300_PCH_SUSPP3300_DSW

G PathI Path

R89

R88

*0/J_4

*0/J_4S

R263 10K/J_4

A A

R681 10K/J_4

TRACKPAD_INT_L TOUCH_INT_L

5

4/22 modify

Micron 84G Hynix Elpida EDJ4216EFBG-GN-F

Hynix H5TC4G63AFR-PBA Elpida EDJ4216EFBG-GN-F

R693 *10K/J_4 R695 *10K/J_4 R688 *10K/J_4

Part Number Vender Total size (Bytes) MT41K256M16HA-125:E H5TC4G63AFR-PBA

MT41K256M16HA-125:E

4

RAM_ID0 RAM_ID1 RAM_ID2

4G 4G 4G 4G 4G

R692 *10K/J_4 R694 *10K/J_4 R687 *10K/J_4

Install Quantity Size/Chip (Bit)

PP3300_PCH_SUS

8 8 4 2GMicron 4 4

4G 4G 4G

2G

3

RAM_ID2/RAM_ID1/RAM_ID0

000 001 010 011 100 1012G

PP3300_PCH_SUS[7,8,9,11,13,20,25,29] +1.05V_VCCST[4,5]

PP3300_PCH[2,7,8,9,11,13,20,25,29]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

PCH 4/6 (GPIO/MISC)

Date:

Friday, August 16, 2013

2

Friday, August 16, 2013

PP3300_PCH_SUS +1.05V_VCCST

PP3300_PCH

1

Sheet :

of

10 42

Rev.Size

1A

5

4

3

2

1

PCH VCCHSIO Power

PP5000

U40

12

MODPHY_EN[10]

C607 0.1U/10V/X5R_4

12

C601 1U/6.3V/X5R_4

PP3300_PCH PP3300_DSW

R604 100K/J_4

PP1050_PCH_SUS

D D

C C

1

R228 *100K/J_4

R596 *0/J_4S

R230 *100K/J_4

SLG59M1470VTR

VDD D_012S_01 D_02_033S_02_03

ON

9

12

C608

0.047u/25V/X7R_4

PP1050_PCH

8

GND

7 5

check this foorpint

+V1.05DX_MODPHY

4/23 modify,Intel suggest 0 ohm

PP1050_PCH

PP3300_PCH

PP1500_PCH_TS

reserve

L39 *80/5A

R560 *0/J_8S R559 *0/J_8S

12

C602

0.1U/10V/X5R_4

+V1.05DX_MODPHY

R6548 *0/J_8S C248 *47u/6.3V/X5R_8 C619 *47u/6.3V/X5R_8 C218 1U/6.3V/X5R_4

R252 0/J_6 R260 *0/J_6 C234 0.1U/10V/X5R_4

Place close to ball

PP3300_PCH_SUS

Deep Sx Non Deep Sx

B B

0412 MOW-WW15 a 0.47uF cap between VccDSW3_3 and DcpSusByp current requirement cannot meet

A A

5

is required if the 1.9A inrush

PP3300_DSW

PP3300_PCH_SUS

PP1050_PCH

+V1.05DX_MODPHY

PP1050_PCH

L18 2.2uH/210mA_8

C88 22u/6.3V/X5R_8 C77 22u/6.3V/X5R_8 C595 1U/6.3V/X5R_4

L17 2.2uH/210mA_8

C89 22u/6.3V/X5R_8 C79 22u/6.3V/X5R_8 C596 1U/6.3V/X5R_4

+V1.05S_APLLOPI

+V3.3DX_1.5DX_1.8DX_AUDIO

C270 22u/6.3V/X5R_8

R254 *0/J_6S R253 *0/J_6

C238 1U/6.3V/X5R_4

PP3300_PCH

4

R165 *0/J_8S C174 22u/6.3V/X5R_8

R6546 *0/J_8S C197 *1U/6.3V/X5R_4

C579 47u/6.3V/X5R_8 C578 *47u/6.3V/X5R_8 C158 1U/6.3V/X5R_4

R6547 *0/J_8S

C68 47u/6.3V/X5R_8 C76 *47u/6.3V/X5R_8 C594 1U/6.3V/X5R_4

PP1050_PCH

PP3300_PCH_SUS

C577 *1U/6.3V/X5R_4 C163 1U/6.3V/X5R_4 C175 1U/6.3V/X5R_4

R179 *0/J_8S C181 *1U/6.3V/X5R_4

+V1.05S_AUSB3PLL

1.741A

41mA

Haswell ULT PCH (Power)

HSIO

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

HSW_ULT_DDR3L

OPI

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

AH11 AG10 AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

PP1050_PCH_SUS[8,13,31]

PP3300_RTC[8,22,23,25,26,27,28] PP1050_PCH[5,13,26,31]

+V1.05S_AUSB3PLL[9] +V1.05S_ASATA3PLL[8]

PP3300_PCH_SUS[7,8,9,10,13,20,25,29] PP3300_DSW[5,7,8,10,13,20,21,24,25,26,28,29,33] PP3300_PCH[2,7,8,9,10,13,20,25,29]

+V1.05S_AXCK_LCPLL[9]

PP5000[18,20,22,23,24,25,28,30,31,32,34]

+V3.3A_DSW_PRTCSUS

+VCCRTCEXT

+V3.3M_PSPI

PCH_VCC_1_1_20 PCH_VCC_1_1_21

+V1.05S_CORE_PCH

+PCH_VCCDSW +V1.05M_VCCASW

+1.05V_DCPSUS1

0.109A

+V1.5S_VCCATS

+V3.3S_VCCPTS

+V3.3S_VCCSDIO

+1.05V_DCPSUS4

+V1.05S_VCCUSBCORE

2

C208 0.1U/10V/X5R_4

18mA

3mA

1mA

+V1.05S_ASATA3PLL

1.838A

+V1.05S_AIDLE

42mA

57mA

C177 *10u/6.3V/X5R_6 C166 *1U/6.3V/X5R_4

C235 *1U/6.3V/X5R_4 C233 1U/6.3V/X5R_4

+1.05V_DCPSUS3

11mA

+1.05V_DCPSUS2

+VCCPDSW

+V3.3S_VCCPCORE

0.114A

41mA 17mA

+V1.05S_AXCK_DCB

0.2A

+V1.05S_AXCK_LCPLL

31mA

R6543 *0/J_6S

R6544 *0/J_6S

+V1.05S_SSCF100

C164 1U/6.3V/X5R_4

+V1.05S_SSCFF

C209 1U/6.3V/X5R_4

AA21

AH14

AH13

AH10

AE20 AE21

L10

B18 B11

Y20

W21

J13

AC9 AA9

W9

J18 K19 A20 J17 R21 T21 K18 M20 V21

K9

M9 N8

P9

V8

U42M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

63mA

3

R212 *0/J_6S R194 *0/J_6S

4/22 modify

C4 0.47u/25V/X7R_6

0.658A

C212 *1U/6.3V/X5R_4

R111 *0/J_6S R107 *0/J_6S C183 1U/6.3V/X5R_4

R158 *0/J_6S C194 1U/6.3V/X5R_4

R270 *0/J_8S C236 1U/6.3V/X5R_4

PP1050_PCH_SUS

PP3300_RTC PP1050_PCH

+V1.05S_AUSB3PLL +V1.05S_ASATA3PLL

PP3300_PCH_SUS PP3300_DSW PP3300_PCH

+V1.05S_AXCK_LCPLL PP5000

+V1.05M_VCCASW

R217 *0/J_8S C217 22u/6.3V/X5R_8 C221 1U/6.3V/X5R_4

R197 *0/J_6S C220 1U/6.3V/X5R_4

C642 1U/6.3V/X5R_4 C643 0.1U/10V/X5R_4 C231 0.1U/10V/X5R_4

R220 *0/J_6 R204 *0/J_6S C216 0.1U/10V/X5R_4

PP1050_PCH PP1050_PCH

+VCCPDSW

PP1500_PCH_TS PP3300_PCH

PP3300_PCH

PP1050_PCH

C

Date:

PP3300_PCH_SUS

PP3300_RTC

PP3300_DSW PP3300_PCH

7/12 modify for leakage

place near CPU

4/23 modify, change short PAD

R174 *short_8 C192 10u/6.3V/X5R_6 C213 1U/6.3V/X5R_4 C237 1U/6.3V/X5R_4

PP1050_PCH

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

PCH 5/6 (POWER)

Friday, August 16, 2013

1

Sheet :

11

PP1050_PCH

11 42

Rev.Size

1A

of

5

4

3

2

1

12

Haswell ULT (GND)

D D

HSW_ULT_DDR3L

U42N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

VSS

AC61

VSS

AD21

VSS

AD3

VSS

AD63

VSS

AE10

VSS

AE5

VSS

AE58

VSS

AF11

VSS

AF12

VSS

AF14

VSS

AF15

VSS

AF17

VSS

AF18

VSS

AG1

VSS

C C

B B

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

14 OF 19

AJ35

VSS

AJ39

VSS

AJ41

VSS

AJ43

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

AP22 AP23 AP26 AP29

AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

HSW_ULT_DDR3L

U42O

VSS VSS VSS VSS

AP3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AR5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AU1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

15 OF 19

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D5 D50 D51 D53 D54 D55 D57 D59 D62

D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22

G3

G5

G6

G8 H13

HSW_ULT_DDR3L

U42P

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

16 OF 19

VSS_SENSE

H17

VSS

H57

VSS

J10

VSS

J22

VSS

J59

VSS

J63

VSS

K1

VSS

K12

VSS

L13

VSS

L15

VSS

L17

VSS

L18

VSS

L20

VSS

L58

VSS

L61

VSS

L7

VSS

M22

VSS

N10

VSS

N3

VSS

P59

VSS

P63

VSS

R10

VSS

R22

VSS

R8

VSS

T1

VSS

T58

VSS

U20

VSS

U22

VSS

U61

VSS

U9

VSS

V10

VSS

V3

VSS

V7

VSS

W20

VSS

W22

VSS

Y10

VSS

Y59

VSS

Y63

VSS

V58

VSS

AH46

VSS

V23

VSS

E62

VSS_SENSE_R

AH16

VSS

U42R

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

R591 *0/J_4S

R593 100/F_4

HSW_ULT_DDR3L

18 OF 19

VSS_SENSE [32]

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

U42Q

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 TP_DC_TEST_AY60

TP97

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 TP_DC_TEST_B2

TP77

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

DC_TEST_C1_C2

A A

5

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

4

HSW_ULT_DDR3L

17 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

3

A3

DC_TEST_A3_B3

A4

TP_DC_TEST_A4

A60

TP_DC_TEST_A60

A61

DC_TEST_A61_B61

A62

TP_DC_TEST_A62

AV1

TP_DC_TEST_AV1

AW1

TP_DC_TEST_AW1

AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

TP_DC_TEST_AW63

TP76 TP74 TP78

TP95 TP94

TP96

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

PCH 6/6 (GND)

Date:

Friday, August 16, 2013

2

Friday, August 16, 2013

Sheet :

1

of

12 42

Rev.Size

1A

5

4

3

2

1

13

D D

CN32

XDP_PREQ#[4] XDP_PRDY#[4]

XDP_BPM#0[4] XDP_BPM#1[4]

SMB_PCH_DAT[8]

SMB_PCH_CLK[8]

XDP_TCK1[8] XDP_TCK0[4,8]

R745 *0/J_6

CFG0[6] CFG1[6]

CFG2[6] CFG3[6]

CFG4[6,8] CFG5[6]

CFG6[6] CFG7[6]

H_SYS_PWROK_XDP

R287 1K/J_4

PP3300_PCH_SUS

Close to R719 (8/13)

PCH_RSMRST_L[7,26]

PP1050_PGOOD[5,26,31]

PWR_DEBUG[5]

C5669

0.1U/10V/X5R_4

C C

SYS_PWROK[5,7,26]

R6564 1K/J_4

R286 *1K/J_4

R288 *0/J_4S

R766 *0/J_6

APS3

XDP_PREQ_N XDP_PRDY_N

CFG0 CFG1

CFG2 CFG3

CFG4 CFG5

CFG6 CFG7

VCCST_PWRGD_XDP PWR_BTN_L

H_SYS_PWROK_XDP

APS7APS1

31

*XDP_CONN_60P

APS

CN19

1

APS1 APS3

APS7

R767 *0/J_6 R765 *0/J_4 R742 *0/J_6 R764 *0/J_4 R763 *0/J_4 R762 *0/J_4 R744 *0/J_6

R761 *0/J_4 R760 *0/J_4 R759 *0/J_4 R758 *0/J_4

1

2

3

4

5

6

7

B B

10 11 12 13 14 15 16 17 18

*APS_CONN_18P

8

9

10 11 12 13 14 15 16 17 18

PP3300_PCH_SUS

PWR_BTN_L SYS_RESET#

PCH_SLP_S3_L [7,26,29,30,31,33] PCH_SLP_S5_L [7,26,29,30]

PCH_SLP_S4_L [7] PCH_SLP_A_L [7]

PCH_RTCRST [8,26] PWR_BTN_L [17,25,26] SYS_RESET# [7,17] PCH_SLP_S0_L [7,26] VCCST_PWRGD[5]

PP3300_DSW

31 323229 333328 343427 353526 363625 373724 383823 393922 404021 414120 424219 434318 444417 454516 464615 474714 484813 494912 505011 515110 52529 53538 54547 55556 56565 57574 58583 59592

ICT

60601

30

2

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

U56

NC1VCC

A

GND3Y

74AUP1G07GW

NOA_STBP_0 NOA_STBN_0

CFG8 CFG9

CFG10 CFG11

NOA_STBP_1 NOA_STBN_1

CFG12 CFG13

CFG14 CFG15

CK_XDP_P_R CK_XDP_N_R

XDP_RST_R_N XDP_DBRESET_N

XDP_TDO XDP_TRST_N XDP_TDI XDP_TMS

XDP_TDO[8]

XDP_TDI[8]

XDP_TMS[8]

PP1050_PCH

5

C768

0.1U/10V/X5R_4

4

NOA_STBP_0 [6] NOA_STBN_0 [6]

CFG8 [6] CFG9 [6]

CFG10 [6] CFG11 [6]

NOA_STBP_1 [6] NOA_STBN_1 [6]

CFG12 [6] CFG13 [6]

CFG14 [6] CFG15 [6]

R236 *0/J_4S R237 *0/J_4S

R238 1K/J_4 R239 *0/J_4S

R219 51/J_4

XDP_TDO

XDP_TDI

XDP_TMS

XDP_TRST_N

PP3300_PCH

R489

12

10K/J_4

PP3300_PCH

SYS_RESET#

C176

0.1U/10V/X5R_4

U15

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126

XDP_DBRESET_N

CLK_PCIE_XDPP [9] CLK_PCIE_XDPN [9]

PLTRST# [7,19,21,22,26]

PP1050_PCH_SUS

R240 1K/J_4

3

1B

6

2B

8

3B

11

4B

15

DPAD

7

GND

PP3300_DSW[5,7,8,10,11,20,21,24,25,26,28,29,33] PP3300_PCH_SUS[7,8,9,10,11,20,25,29] PP1050_PCH_SUS[8,11,31] PP1050_PCH[5,11,26,31] PP3300_PCH[2,7,8,9,10,11,20,25,29]

PP3300_PCH

C5668

0.1U/10V/X5R_4

XDP_TDO_CPU [4]

XDP_TDI_CPU [4]

XDP_TMS_CPU [4]

XDP_TRST# [4,8]

PP3300_DSW PP3300_PCH_SUS PP1050_PCH_SUS PP1050_PCH PP3300_PCH

PP1050_PCH_SUSPP1050_PCH_SUS

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

CPU/PCH XDP

Date:

Tuesday, August 20, 2013

5

4

3

2

Tuesday, August 20, 2013

Sheet :

1

of

13 42

Rev.Size

1A

HP 14-Q070NR Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual