HP 14-Q070NR Schematics

5

www.schematic-x.blogspot.com

4

3

2

1

01

A23 SHB ULT SYSTEM BLOCK DIAGRAM

D D

USB2.0 (Rserve)

Memory Down

Channel A 1Rx16

Channel B 1Rx16

SATA SSD 16GB/32GB

ICT

USB 2.0 Port

Push-Push

C C

socket

CON.

Card Reader Realtek RTS5141

NGFFWWANSIM Slot

ICTICT

MINI CARD WLAN+BT

Dual Channel DDR3L 1333/1600 MHZ

NGFF

USB2.0

I/O Board Conn.

USB2.0

PCIECLOCK-2

SATA0

USB2.0 x3

PCIE-3

USB2.0

Haswell ULT 15W

MCP 1168pins

IMC

SATA

DC+GT2

40 mm X 24 mm

Integrated PCH

CLK

CI-E x1

P

USB2.0

ICT

SB3.0/2.0

U

USB3.0/2.0

I2C

eDP

Realtek

eDP to LVDS

LVDS

RTD2132R

USB2.0

DMIC

DDI1

I2C

Ambit Light Sensor Intersil ISL29023

HDMI Conn.

USB3 Port MB side

Touch Panel conn

LVDS CONN.

CCD(Camera) DMIC

LVDS CONN.

Combo HP / MIC

B B

A A

Speaker

5

Int. MIC

Realtek ALC283

AUDIO CODEC RTD3

PP3300_RTC

TPM Infineon SLB9655TT1.2

F4.32

4

Azalia

RTC

Thermal IC

I

HDA

LPC

P2~P13

X'TAL 32.768KHz X'TAL 24MHz

Keyboard

K/B controlled recover/reset IC

Silego SLG4N059 SLG4K4137

3

SPI

I2C

ICT

EC

TI TM4E1G31H6ZRBI

Google Debug conn

SPI ROM/8MB

Touch pad

X'TAL

32.768KHz

Fan Driver

(PWM Type)

2

BQ24738

Batery Charger

TPS51225

PP3300_DSW/PP5000

NCP81101

+VCCIN

AOZ1237

PP1050_PCH_SUS

TPS51216

PP1350

APW8824

PP1500_PCH_TS

C

Date:

Thermal Protection Discharger

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Block Diagram

Tuesday, August 20, 2013

1

Sheet :

ICT

of

1 42

Rev.Size

1A

5

4

3

2

1

02

D D

Haswell ULT (DISPLAY,eDP)

U42A

INT_HDMITX2N[18] INT_HDMITX2P[18] INT_HDMITX1N[18] INT_HDMITX1P[18] INT_HDMITX0N[18]

HDMI

INT_HDMITX0P[18]

INT_HDMICLK-[18] INT_HDMICLK+[18]

DP

C C

C54

DDI1_TXN0

C55

DDI1_TXP0

B58

DDI1_TXN1

C58

DDI1_TXP1

B55

DDI1_TXN2

A55

DDI1_TXP2

A57

DDI1_TXN3

B57

DDI1_TXP3

C51

DDI2_TXN0

C50

DDI2_TXP0

C53

DDI2_TXN1

B54

DDI2_TXP1

C49

DDI2_TXN2

B50

DDI2_TXP2

A53

DDI2_TXN3

B53

DDI2_TXP3

U42I

HSW_ULT_DDR3L

1 OF 19

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP DP_UTIL

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2

EDPDDI

EDP_TXN3 EDP_TXP3

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

I

EDP_TXN0 [16] EDP_TXP0 [16] EDP_TXN1 [16] EDP_TXP1 [16]

EDP_TXN2 [16] EDP_TXP2 [16] EDP_TXN3 [16] EDP_TXP3 [16]

EDP_AUXN [16] EDP_AUXP [16]

R149 24.9/F_4

R561 *0/J_4 R562 *0/J_4

DP_UTIL [16]

eDP Panel

PCH_BL_PWM

+VCCIOA_OUT

eDP_RCOMP Trace length < 100 mils Trace width = 20 mils Trace spacing = 25 mils

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

DDPB_HPD DDPC_HPD

EDP_HPD

C

B9 C9 D9 D11

C5 B6 B5 A6

C8 A8 D6

HDMI_DDCCLK_SW [18] HDMI_DDCDATA_SW [18]

INT_HDMI_HPD [18] EDP_HPD [16]

R806 100K/J_4

+VCCIOA_OUT[5]

PP3300_PCH[7,8,9,10,11,13,20,25,29]

PCH_GPIO77 PCH_GPIO78 PCH_GPIO79 PCH_GPIO80 SIM_DET TOUCH_INT_L_DX ALS_INT_L TRACKPAD_INT_DX GPIO55

DDPB/C_CTRLDATA has an iPD 20K, When PU at rising edge of

PCH_PWROK, the DDI port will be detected

+VCCIOA_OUT PP3300_PCH

R160 10K/J_4 R635 10K/J_4 R623 10K/J_4 R617 10K/J_4 R6433 10K/J_4 R599 10K/J_4 R607 10K/J_4 R602 10K/J_4 R6541 10K/J_4

PP3300_PCH

+3V

B8 A9

C6

U6

P4 N4 N2

AD4

U7

L1

L3 R5

L4

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

+3V +3V +3V +3V +3V

eDP SIDEBAND

+3V +3V +3V +3V +3V_S5

PCIE

9 OF 19

DISPLAY

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

TP46

PCH_GPIO77 PCH_GPIO78 PCH_GPIO79 PCH_GPIO80

PCH_BL_PWM PCH_BL_EN PCH_EDP_VDD_EN

PCI_PME#

GPIO55 SIM_DET TOUCH_INT_L_DX ALS_INT_L TRACKPAD_INT_DX

PCH_BL_PWM[16,26] PCH_BL_EN[16,26]

PCH_EDP_VDD_EN[16,26]

SIM_DET[22] TOUCH_INT_L_DX[20] ALS_INT_L[22] TRACKPAD_INT_DX[25]

Haswell C-1 2c BGA 1.6GHz ULV 15W 2+2 i5-4200U QS for proto/AJ0QEVEVT01

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 1/5 (DDI/eDP)

Date:

Tuesday, August 20, 2013

5

4

3

2

Tuesday, August 20, 2013

Sheet :

1

T

of

2 42

Rev.Size

1A

5

4

3

2

1

Haswell ULT (DDR3L) Haswell Processor (DDR3L)

U42C

M_A_DQ<0>[14] M_A_DQ<1>[14] M_A_DQ<2>[14] M_A_DQ<3>[14] M_A_DQ<4>[14] M_A_DQ<5>[14] M_A_DQ<6>[14] M_A_DQ<7>[14]

D D

C C

M_A_DQ<8>[14] M_A_DQ<9>[14] M_A_DQ<10>[14] M_A_DQ<11>[14] M_A_DQ<12>[14] M_A_DQ<13>[14] M_A_DQ<14>[14] M_A_DQ<15>[14] M_A_DQ<16>[14] M_A_DQ<17>[14] M_A_DQ<18>[14] M_A_DQ<19>[14] M_A_DQ<20>[14] M_A_DQ<21>[14] M_A_DQ<22>[14] M_A_DQ<23>[14] M_A_DQ<24>[14] M_A_DQ<25>[14] M_A_DQ<26>[14] M_A_DQ<27>[14] M_A_DQ<28>[14] M_A_DQ<29>[14] M_A_DQ<30>[14] M_A_DQ<31>[14] M_A_DQ<32>[14] M_A_DQ<33>[14] M_A_DQ<34>[14] M_A_DQ<35>[14] M_A_DQ<36>[14] M_A_DQ<37>[14] M_A_DQ<38>[14] M_A_DQ<39>[14] M_A_DQ<40>[14] M_A_DQ<41>[14] M_A_DQ<42>[14] M_A_DQ<43>[14] M_A_DQ<44>[14] M_A_DQ<45>[14] M_A_DQ<46>[14] M_A_DQ<47>[14] M_A_DQ<48>[14] M_A_DQ<49>[14] M_A_DQ<50>[14] M_A_DQ<51>[14] M_A_DQ<52>[14] M_A_DQ<53>[14] M_A_DQ<54>[14] M_A_DQ<55>[14] M_A_DQ<56>[14] M_A_DQ<57>[14] M_A_DQ<58>[14] M_A_DQ<59>[14] M_A_DQ<60>[14] M_A_DQ<61>[14] M_A_DQ<62>[14] M_A_DQ<63>[14]

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57

AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54

AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

HSW_ULT_DDR3L

DDR CHANNEL A

SA_CLK#0

SA_CLK0

SA_CLK#1

SA_CLK1 SA_CKE0

SA_CKE1 SA_CKE2 SA_CKE3

SA_CS#0 SA_CS#1

SA_ODT0

SA_RAS

SA_WE

SA_CAS SA_BA0

SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32 AY34

AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49 AR51 AP51

TP62 TP60

+VREF_CA_CPU +VREFDQ_SA_M3 +VREFDQ_SB_M3

M_A_DIM0_CK_DDR0_DN [14]

M_A_DIM0_CK_DDR0_DP [14]

M_A_DIM0_CKE0 [14]

M_A_DIM0_CS0_N [14]

M_A_RAS_N [14] M_A_WE_N [14] M_A_CAS_N [14]

M_A_BS0 [14] M_A_BS1 [14] M_A_BS2 [14]

M_A_A<0> [14] M_A_A<1> [14] M_A_A<2> [14] M_A_A<3> [14] M_A_A<4> [14] M_A_A<5> [14] M_A_A<6> [14] M_A_A<7> [14] M_A_A<8> [14] M_A_A<9> [14] M_A_A<10> [14] M_A_A<11> [14] M_A_A<12> [14] M_A_A<13> [14] M_A_A<14> [14] M_A_A<15> [14]

M_A_DQS_DN<0> [14] M_A_DQS_DN<1> [14] M_A_DQS_DN<2> [14] M_A_DQS_DN<3> [14] M_A_DQS_DN<4> [14] M_A_DQS_DN<5> [14] M_A_DQS_DN<6> [14] M_A_DQS_DN<7> [14]

M_A_DQS_DP<0> [14] M_A_DQS_DP<1> [14] M_A_DQS_DP<2> [14] M_A_DQS_DP<3> [14] M_A_DQS_DP<4> [14] M_A_DQS_DP<5> [14] M_A_DQS_DP<6> [14] M_A_DQS_DP<7> [14]

U42D

M_B_DQ<0>[15] M_B_DQ<1>[15] M_B_DQ<2>[15] M_B_DQ<3>[15] M_B_DQ<4>[15] M_B_DQ<5>[15] M_B_DQ<6>[15] M_B_DQ<7>[15] M_B_DQ<8>[15] M_B_DQ<9>[15] M_B_DQ<10>[15] M_B_DQ<11>[15] M_B_DQ<12>[15] M_B_DQ<13>[15] M_B_DQ<14>[15] M_B_DQ<15>[15] M_B_DQ<16>[15] M_B_DQ<17>[15] M_B_DQ<18>[15] M_B_DQ<19>[15] M_B_DQ<20>[15] M_B_DQ<21>[15] M_B_DQ<22>[15] M_B_DQ<23>[15] M_B_DQ<24>[15] M_B_DQ<25>[15] M_B_DQ<26>[15] M_B_DQ<27>[15] M_B_DQ<28>[15] M_B_DQ<29>[15] M_B_DQ<30>[15] M_B_DQ<31>[15] M_B_DQ<32>[15] M_B_DQ<33>[15] M_B_DQ<34>[15] M_B_DQ<35>[15] M_B_DQ<36>[15] M_B_DQ<37>[15] M_B_DQ<38>[15] M_B_DQ<39>[15] M_B_DQ<40>[15] M_B_DQ<41>[15] M_B_DQ<42>[15] M_B_DQ<43>[15] M_B_DQ<44>[15] M_B_DQ<45>[15] M_B_DQ<46>[15] M_B_DQ<47>[15] M_B_DQ<48>[15] M_B_DQ<49>[15] M_B_DQ<50>[15] M_B_DQ<51>[15] M_B_DQ<52>[15] M_B_DQ<53>[15] M_B_DQ<54>[15] M_B_DQ<55>[15] M_B_DQ<56>[15] M_B_DQ<57>[15] M_B_DQ<58>[15] M_B_DQ<59>[15] M_B_DQ<60>[15] M_B_DQ<61>[15] M_B_DQ<62>[15] M_B_DQ<63>[15]

AY31

AW31

AY29

AW29

AV31 AU31 AV29 AU29 AY27

AW27

AY25

AW25

AV27 AU27 AV25 AU25 AM29 AK29

AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25

AL25 AY23

AW23

AY21

AW21

AV23 AU23 AV21 AU21 AY19

AW19

AY17

AW17

AV19 AU19 AV17 AU17 AR21 AR22

AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18

AL18 AK20 AM20 AR18 AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

HSW_ULT_DDR3L

DDR CHANNEL B

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3

SB_CS#0 SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS SB_BA0

SB_BA1 SB_BA2

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7

SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32 AM35

AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

TP63 TP57

M_B_A<0> [15] M_B_A<1> [15] M_B_A<2> [15] M_B_A<3> [15] M_B_A<4> [15] M_B_A<5> [15] M_B_A<6> [15] M_B_A<7> [15] M_B_A<8> [15] M_B_A<9> [15] M_B_A<10> [15] M_B_A<11> [15] M_B_A<12> [15] M_B_A<13> [15] M_B_A<14> [15] M_B_A<15> [15]

M_B_DIM0_CK_DDR0_DN [15]

M_B_DIM0_CK_DDR0_DP [15]

M_B_DIM0_CKE0 [15]

M_B_DIM0_CS0_N [15]

M_B_RAS_N [15] M_B_WE_N [15] M_B_CAS_N [15]

M_B_BS0 [15] M_B_BS1 [15] M_B_BS2 [15]

M_B_DQS_DN<0> [15] M_B_DQS_DN<1> [15] M_B_DQS_DN<2> [15] M_B_DQS_DN<3> [15] M_B_DQS_DN<4> [15] M_B_DQS_DN<5> [15] M_B_DQS_DN<6> [15] M_B_DQS_DN<7> [15]

M_B_DQS_DP<0> [15] M_B_DQS_DP<1> [15] M_B_DQS_DP<2> [15] M_B_DQS_DP<3> [15] M_B_DQS_DP<4> [15] M_B_DQS_DP<5> [15] M_B_DQS_DP<6> [15] M_B_DQS_DP<7> [15]

03

3 OF 19

B B

A A

5

ICT IC

4

3

4 OF 19

2

T

+VREF_CA_CPU[14] +VREFDQ_SA_M3[14] +VREFDQ_SB_M3[15]

+VREF_CA_CPU +VREFDQ_SA_M3 +VREFDQ_SB_M3

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 2/5 (DDR3 I/F)

Date:

Tuesday, August 20, 2013

ICT

Rev.Size

1A

Sheet :

1

of

3 42

1A

5

4

3

2

1

04

D D

C C

DRAM COMP

H_PECI (50ohm) Route on microstrip only Spacing >18 mils Trace Length: 0.4~6.125 iches

H_PWRGOOD (50ohm) Trace Length: 1~11.25 inches

CPU_PLTRST# (50ohm) Trace Length: 10~17 inches

H_PROCHOT#[17,26,32]

CPU_PGOOD[26]

R683 200/F_4

R691 121/F_4

R686 100/F_4

TP79

H_PECI[26] XDP_PRDY# [13]

SM_RCOMP[0:2] Trace length < 500 mils Trace width = 12~15 mils Trace spacing = 20 mils

TP25

R605 56/J_4

R87 *0/J_4S

TP83

XDP PU/PD

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

Haswell ULT (SIDEBAND)

U42B

AU60 AV60 AU61 AV15 AV61

XDP_TDO_CPU

XDP_TCK0 XDP_TRST#

D61

PROC_DETECT

K61

CATERR

N62

PECI

K63

PROCHOT

C61

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

R141 51/J_4

R202 51/J_4 R690 *51/J_4

MISC

THERMAL

PWR

DDR3L

DSW

+1.05V_VCCST

PROC_DETECT CATERR# H_PECI

H_PROCHOT#_RH_PROCHOT#

H_PWRGOOD_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

DDR_PG_CTRL

HSW_ULT_DDR3L

JTAG

2 OF 19

PRDY

PREQ PROC_TCK PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

J62 K62 E60 E61 E59 F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_PRDY# XDP_PREQ# XDP_TCK0 XDP_TMS_CPU XDP_TRST# XDP_TDI_CPU XDP_TDO_CPU

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7CPU_DRAMRST#

XDP_PREQ# [13] XDP_TCK0 [8,13] XDP_TMS_CPU [13] XDP_TRST# [8,13] XDP_TDI_CPU [13] XDP_TDO_CPU [13]

XDP_BPM#0 [13]

XDP_BPM#1 [13]

TP82 TP80 TP23 TP81 TP27 TP24

TCK,TMS Trace Length < 9000mils

BPM#[0:7] Trace Length 1~6 inches Length match < 300 mils

B B

A A

5

PU/PD of CPU

H_PROCHOT#

H_PWRGOOD_R

+1.05V_VCCST

R614 62/J_4

R569 10K/J_4

DRAMRST

PP1350

12

R403 470/J_4

CPU DRAM

CPU_DRAMRST#

4

R404 *0/J_4S

12

*0.1u/10V/X5R_4

DDR3_DRAMRST# [14,15]

C459

3

+1.05V_VCCST[5,10] PP1350[5,14,15,30]

2

+1.05V_VCCST PP1350

Date:

+1.35V_SUS

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 3/5 (SideBand)

Friday, August 16, 2013

Rev.Size

1A

Sheet :

1

of

4 42

1A

5

4

3

2

1

05

D D

VCC Output Decoupling Recommendations

VDDQ Output Decoupling Recommendations

330uFx2 7343 22uFx11 10uFx10

PP1350

PP3300_DSW

VCCST PWRGD

C C

B B

A A

PP1050_PGOOD[13,26,31]

PCH_PWROK[7,26] SYS_PWROK[7,13,26]

R579 *0/J_4 R544 *0/J_4S R580 *0/J_4

0415 VCCST PWRGD

SVID

VR_SVID_DATA[32]

VR_SVID_ALERT#[32]

VR_SVID_CLK[32]

VCCST_PWRGD_EN VCCST_PWRGD_R

Layout note: need routing together and ALERT need between CLK and DATA.

Place PU resistor close to CPU

R625 *0/J_4S

+1.05V_VCCST

NC1VCC

2

A

ICT

GND3Y

74AUP1G07GW

Reserve

D46 *RB501V-40

G Path

+1.05V_VCCST

Place PU resistor close to CPU

R640 75/J_4

R630 43/J_4

C5667

R6554

0.1U/10V/X7R_4

54.9/F_4

R641 *0/J_4S

U38

21

R618 130/F_4

5

4

H_CPU_SVIDDAT

H_CPU_SVIDART#

H_CPU_SVIDCLK

CRB is via +1.05V PG

C584

0.1U/10V/X5R_4

R545 *0/J_4S

VCCST_PWRGD[13]

+1.05V_VCCST

C582 *0.1u/10V/X5R_4

R551 10K/J_4

VRON_CPU[32]

VCORE_PGOOD[10,32]

PWR_DEBUG[13]

+VCCIN

C225 22u/6.3V/X5R_8

VCC_SENSE[32]

+1.05V_VCCST

0415 VCCST_PWRGD need PP1050_RUN power good

+1.05V_VCCST

EC14 *1U/6.3V/X5R_4

Reserve for RF

BOT socket side 5 onTOP, 6 on BOT inside socket cavity

0805

5 onTOP, 5 on BOT inside socket cavity

0805

C5658

C5657

10u/6.3V/X5R_6

+1.35V_CPU 1.4A

C260

C261

10u/6.3V/X5R_6

R583 100/F_4

+VCCIN

R587 *0/J_4S

R566 *10K/J_4 R567 10K/J_4

R173 *0/J_4S R151 150/J_6

EC15 *470p/50V/X7R_4

C5656 10u/6.3V/X5R_6

C259 10u/6.3V/X5R_6

+VCCIN

300mA

+VCCIOA_OUT

300mA

R190 *0/J_8S

C5660

2.2u/6.3V/X7R_6

C224

2.2u/6.3V/X7R_6

+1.05V_VCCSTPP1050_PCH

+VCCIN

C5659

2.2u/6.3V/X7R_6

TP29 TP20

C256

2.2u/6.3V/X7R_6

TP28 TP41

TP42 TP514

TP43 TP47 TP50

TP30 TP31 TP26 TP85 TP32 TP49 TP51 TP36 TP39 TP37 TP54 TP35 TP34

C223 *4.7u/6.3V/X5R_6

ULT_RVSD_61 ULT_RVSD_62

ULT_RVSD_63 ULT_RVSD_64

VCC_SENSE_R ULT_RVSD_65 +VCCIO_OUT

ULT_RVSD_66 ULT_RVSD_67 ULT_RVSD_68

H_CPU_SVIDART# H_CPU_SVIDCLK H_CPU_SVIDDAT VCCST_PWRGD VRON_CPU VCORE_PGOOD

PWR_DEBUG_R ULT_RVSD_69

ULT_RVSD_70 ULT_RVSD_71 ULT_RVSD_72 ULT_RVSD_73 ULT_RVSD_74 ULT_RVSD_75 ULT_RVSD_76 ULT_RVSD_77 ULT_RVSD_78 ULT_RVSD_79 ULT_RVSD_80 ULT_RVSD_81

Haswell ULT (POWER)

HSW_ULT_DDR3L

HSW ULT POWER

12 OF 19

+VCCIOA_OUT +VCCIN +1.05V_VCCST PP1350 PP1050_PCH PP3300_DSW

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

AC58

AB23

AD23 AA23 AE59

AD60 AD59 AA59 AE60 AC59 AG58

AC22 AE22 AE23

AB57 AD57 AG57

L59 J58

F59 N58

E63 A59

E20

L62 N63 L63 B59 F60 C59

D63 H59 P62 P60 P61 N59 N61 T59

U59 V59

C24 C28 C32

U42L

RSVD RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCC RSVD RSVD

VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD

VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCST VCCST VCCST

VCC VCC VCC VCC VCC VCC

+VCCIOA_OUT[2] +VCCIN[32] +1.05V_VCCST[4,10] PP1350[4,14,15,30] PP1050_PCH[11,13,26,31] PP3300_DSW[7,8,10,11,13,20,21,24,25,26,28,29,33]

470uFx4 7343 22uFx8 22uFx11 10uFx11

C36

VCC

C40

VCC

C44

VCC

C48

VCC

C52

VCC

C56

VCC

E23

VCC

E25

VCC

E27

VCC

E29

VCC

E31

VCC

E33

VCC

E35

VCC

E37

VCC

E39

VCC

E41

VCC

E43

VCC

E45

VCC

E47

VCC

E49

VCC

E51

VCC

E53

VCC

E55

VCC

E57

VCC

F24

VCC

F28

VCC

F32

VCC

F36

VCC

F40

VCC

F44

VCC

F48

VCC

F52

VCC

F56

VCC

G23

VCC

G25

VCC

G27

VCC

G29

VCC

G31

VCC

G33

VCC

G35

VCC

G37

VCC

G39

VCC

G41

VCC

G43

VCC

G45

VCC

G47

VCC

G49

VCC

G51

VCC

G53

VCC

G55

VCC

G57

VCC

H23

VCC

J23

VCC

K23

VCC

K57

VCC

L22

VCC

M23

VCC

M57

VCC

P57

VCC

U57

VCC

W57

VCC

ICT

TOP socket side 4 on TOP, 4 on BOT near socket edge

0805 0805

TOP, inside socket cavity

0805

BOT, inside socket cavity

+VCCIN 32A

C46 22u/6.3V/X5R_8

C190 22u/6.3V/X5R_8

C567 *22u/6.3V/X5R_8

C210 22u/6.3V/X5R_8

C167 22u/6.3V/X5R_8

C562 22u/6.3V/X5R_8

C204 22u/6.3V/X5R_8

C173 22u/6.3V/X5R_8

C71 22u/6.3V/X5R_8

C168 22u/6.3V/X5R_8

C73 22u/6.3V/X5R_8

C557 22u/6.3V/X5R_8

C45 22u/6.3V/X5R_8

C172 22u/6.3V/X5R_8

C74 22u/6.3V/X5R_8

+VCCIN

C228 22u/6.3V/X5R_8

C75 *22u/6.3V/X5R_8

C201 22u/6.3V/X5R_8

C202 22u/6.3V/X5R_8

C206 22u/6.3V/X5R_8

C169 22u/6.3V/X5R_8

C171 22u/6.3V/X5R_8

C165 22u/6.3V/X5R_8

C203 22u/6.3V/X5R_8

C170 22u/6.3V/X5R_8

C205 22u/6.3V/X5R_8

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 4/5 (POWER)

Date:

Tuesday, August 20, 2013

5

4

3

2

Tuesday, August 20, 2013

Sheet :

1

ICT

of

5 42

Rev.Size

1A

5

4

3

2

1

06

D D

CFG0[13] CFG1[13] CFG2[13] CFG3[13] CFG4[8,13] CFG5[13] CFG6[13] CFG7[13] CFG8[13]

CFG9[13] CFG10[13] CFG11[13] CFG12[13] CFG13[13] CFG14[13] CFG15[13]

NOA_STBN_0[13] NOA_STBN_1[13] NOA_STBP_0[13] NOA_STBP_1[13]

R177 49.9/F_4

C C

NOA_STBN_0 NOA_STBN_1 NOA_STBP_0 NOA_STBP_1

CFG_RCOMP

R572 8.2K/J_4

Processor Strapping

CFG0 EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKED

CFG1

PCH/ PCH LESS MODE SELECTION

CFG3

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

CFG 8 ALLOW THE USE OF NOA ON LOCKED UNITS

CFG9

B B

NO SVID PROTOCOL CAPABLE VR CONNECTED

(DEFAULT) NORMAL OPERATION; NO STALL

(DEFAULT) NORMAL OPERATION

DISABLED NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

DISABLED(DEFAULT); IN THIS CASE, NOA WILL BE DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS

VRS SUPPORTING SVID PROTOCOL ARE PRESENT

Haswell ULT (CFG,RSVD)

U42S

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

1 0

STALL

PCH-LESS MODE

ENABLED AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE EMBEDDED DISPLAY PORT

ENABLED; NOA WILL BE AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT

NO VR SUPPORTING SVID IS PRESENT. THE CHIP WILL NOT GENERATE (OR RESPOND TO) SVID ACTIVITY

HSW_ULT_DDR3L

RESERVED

19 OF 19

RSVD_TP RSVD_TP

RSVD

RSVD_TP RSVD_TP

RSVD_TP

RSVD RSVD

RSVD

PROC_OPI_RCOMP

RSVD RSVD

AV63 AU63

C63 C62 B43

A51 B51

L60 N60 W23

Y22 AY15

OPI_COMP1

CFG0

CFG1

CFG3

CFG9

R700 49.9/F_4

R203 *1K/J_4

R184 *1K/J_4

R192 *1K/J_4

R171 *1K/J_4

R172 *1K/J_4

AV62 D58

P22

VSS

N21

VSS

P20 R20

CFG8

CFG10

E MODE BOOT

SAF

A A

5

4

POWER FEATURES ACTIVATED DURING RESET

POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED

3

CFG10

R183 *1K/J_4

2

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Haswell 5/5 (CFG/GND)

Date:

Friday, August 16, 2013

Rev.Size

1A

Sheet :

1

of

6 42

1A

5

4

3

2

1

07

D D

Haswell ULT PCH (PM)

SUSACK#_R

C617 *1U/6.3V/X5R_4

R547 *0/J_4S

R719 *0/J_4S R659 *0/J_4 R274 *0/J_4S R277 *0/J_4S

R653 *0/J_4S

R664 *0/J_4S

R662 *0/J_4

TP45

SUSACK#_RPCH_SUSPWRACK

SYS_RESET#

SYS_PWROK_R PCH_PWROK_R APWROK_RPCH_PWROK PCI_PLTRST#

PCH_RSMRST#

PCH_SUSPWRACK

PCH_PWRBTN# PCH_ACPRESENT PCH_BATLOW# PCH_SLP_S0#_R

PCH_SUSACK_L[26]

SYS_RESET#[13,17]

SYS_PWROK

SYS_PWROK[5,13,26]

PCH_RSMRST_L[13,26]

PCH_SUSWARN_L[26]

PCH_PWRBTN_L[26]

ACPRESENT[27]

PCH_SLP_S0_L[13,26]

R656 *0/J_4S

U42H

ICT

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

+3V_S5

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPWRDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

HSW_ULT_DDR3L

SYSTEM POWER MANAGEMENT

+3V_S5 DSW DSW DSW +3V_S5 DSW

8 OF 19

+3V +3V_S5 +3V_S5 DSW

DSWVRMEN

DPWROK

DSW

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

DSW

SLP_S4

DSW

SLP_S3

DSW

SLP_A

DSW

SLP_SUS

DSW

SLP_LAN

AW7

DSWVREN

AV5

DPWROK_R

AJ5

PCIE_PCH_WAKE#

V5

CLKRUN#

AG4

PCH_SUS_STAT

AE6

PCH_SUSCLK

AP5

PCH_SLP_S5_L

AJ6

PCH_SLP_S4_L

AT4

PCH_SLP_S3_L

AL5

PCH_SLP_A_L

AP4

PCH_SLP_SUS_L

AJ7

PCH_SLP_LAN#

Deep Sx

R722 *0/J_4S

R813 *0/J_4S

R816 *0/J_4S

TP64 TP44

TP58

DSWVREN [8] PCH_DPWROK [26]

LPC_CLKRUN_L

PCH_SLP_S5_L [13,26,29,30]

PCH_SLP_S4_L [13] PCH_SLP_S3_L [13,26,29,30,31,33] PCH_SLP_A_L [13] PCH_SLP_SUS_L [26,29]

PCH_WAKE_L [26]

LPC_CLKRUN_L [26]

4/22 modify, default skip EC control

C C

PCH PM PU/PD

PP3300_PCH

CLKRUN# SYS_RESET#

PCH_RSMRST# SYS_PWROK DPWROK_R

PCH_SUSPWRACK

B B

PCH_ACPRESENT PCH_BATLOW# PCIE_PCH_WAKE# PCH_PWRBTN#

R176 8.2K/J_4 R644 10K/J_4

R6550 *1K/J_4 R707 10K/J_4 R565 *10K/J_4 R721 100K/F_4

PP3300_PCH_SUS

R696 10K/J_4

PP3300_DSW

R259 10K/J_4 R262 8.2K/J_4 R276 1K/J_4 R261 *10K/J_4

PLTRST# Buffer

PCH_PWROK[5,26]

PCI_PLTRST#

4/22 modify, default is bypass PLTRST#

PCH_PWROK PCH_PWROK_R

R354 10K/J_4

PP3300_PCH

C255 *0.1u/10V/X5R_4

2 1

U19

3 5

*TC7SH08FU

4

R353 *0/J_4S

R720 *0/J_4

No

n Deep Sx

R242 100K/J_4

PCI_PLTRST# PLTRST#

DPWROK_RPCH_RSMRST_L

PLTRST# [13,19,21,22,26]

R757 *0/J_4S

PP3300_PCH[2,8,9,10,11,13,20,25,29] PP3300_PCH_SUS[8,9,10,11,13,20,25,29] PP3300_DSW[5,8,10,11,13,20,21,24,25,26,28,29,33]

PP3300_PCH PP3300_PCH_SUS PP3300_DSW

check if need pull up to DEEP _SUS

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

PCH 1/6 (PM)

Date:

Tuesday, August 20, 2013

5

4

3

2

Tuesday, August 20, 2013

Sheet :

1

ICT

of

7 42

Rev.Size

1A

RTC Clock 32.768KHz (RTC)

RTC Circuitry (RTC)

PP3300_RTC

D D

HDA

PCH JTAG

C C

C624 12p/50V/C0G_4

C625 12p/50V/C0G_4

+3V_RTC Tr

PCH_AZ_CODEC_RST#[23]

PCH_AZ_CODEC_SDOUT[23]

PCH_AZ_CODEC_BITCLK[23]

PCH_AZ_CODEC_SYNC[23]

JTAG_TCK,JTAG_TMS

ace Length < 9000mils

Tr

XDP_TMS XDP_TDI PCH_JTAG_TDO PCH_JTAGX

XDP_TCK1

ace width = 20 mils

R373 *0/J _6S R708 1M/J_4

5

23

Y7

32.768KHZ

4 1

+3V_RTC

R703 33/J _4 R701 33/J _4 R698 33/J _4

C639 22p/50V/NPO_4

R726 33/J _4 C638 *10p/50V/COH_4

MP remove(Intel)

R200 51/J_4 R201 51/J_4 R216 *51/J_4 R650 *1K/J_4

R657 51/J_4

RTC_X1

R699 10M/J_4

RTC_X2

+3V_RTC Trace width = 30 mils

R754

20K/F_4

C671 1U/6.3V/X5R_4

R750

20K/F_4

C676

C670

1U/6.3V/X5R_4

PP1050_PCH_SUS

check if need c onnect to PCH_RTCRST_ R/PCH_SRTCRST_R

PCH_RTCRST_R

PCH_SRTCRST_R

HDA_RST#_R HDA_SDO_R HDA_BCLK_R

HDA_SYNC_R

+3V_RTC

PCH_AZ_CODEC_SDIN0[23]

R6407 *0/J_4 R6408 *0/J_4

R215 *0/J_4S

R652 *0/J_4S

PCH_SRTCRST[26] PCH_RTCRST[13,26]

4/22 modify, default skip EC control

RTCRST_L and SRTCRST_L please take out layout

XDP_TRST#[4,13]

XDP_TCK1[13] XDP_TDI[13] XDP_TDO[13] XDP_TMS[13]

XDP_TCK0[4,13]

ULT Strapping Table

Pin Name Strap description

GPIO81(SPKR)

HDA_SDO

INTVRMEN

GPIO66

GPIO86

GPIO15

B B

CFG4

DSWVREN

No reboot on TCO Timer expiration

Flash Descriptor Security Override / Intel ME Debug Mode

Integrated 1.05V VRM enable ALWAYS

Top-Block Swap override

Boot BIOS Strap Bit

TLS(Transport layer security)

DP presence strap

Deep Sx well on die VR enable

Sampled

PWROK

Configuration note

0 = Default enable (iPD 20K)

1 =Disable No-Reboot mode

0 = Default can program ME (iPD 20K)

1 =can't program ME

1=Should be always pull-up

0 = Default disable (iPD 20K)

1 = Enable TBS function

0 = Default SPI (iPD 20K)

1 =LPC

0 = Default enable w/o confidentiality(iPD 20K)

1 =Default enable with confidentiality

0 = Enable an external display

rt is connected to the eDP

po

1 =disable

1=Should be always pull-up

4

Haswell ULT PCH (RTC/HDA/SATA/SPI)

HSW_ULT_DDR3L

RTC

AUDIO SATA

JTAG

R642 *1K /J_4

R702 *0/J _4

PCH_INTVRMEN

GPIO66[10]

R578 *1K /J_4

GPIO86[10]

R136 *1K/J_4

GPIO15[10]

R195 *8.2K /J_4

CFG4[6,13]

x86 stuff

CFG4

DSWVREN

GPIO66

GPIO86

GPIO15

5 OF 19

+3V +3V +3V +3V

SPKR

PCH_HDA_SDO [26]

R704 *330K /J_4

R577 *1K /J_4

R129 *1K /J_4

R189 *1K /J_4

R193 1K/J _4

R706 *330K /J_4

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0

SPKR [10,23]

RTC_X1 RTC_X2 SM_INTRUDER# PCH_INTVRMEN PCH_SRTCRST_R PCH_RTCRST_R

HDA_BCLK_R HDA_SYNC_R HDA_RST#_R

HDA_SDO_R

XDP_TCK1 XDP_TDI PCH_JTAG_TDO

PCH_JTAGX

U42E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

PP3300_PCH

+3V_RTC

PP3300_PCH

PP3300_PCH_SUS

DSWVREN[7]

+3V_RTC

HDA_SDO_R

R717 330K/ J_4

R718 330K/ J_4

3

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

SATA_IREF

RSVD RSVD

SATA_RCOMP

SATALED

J5 H5 B15 A15

J8 H8 A17 B17

J6 H6 B14 C15

F5 E5 C17 D17

V1

EC_SMI_L

U1

PCH_NMI_DBG_L

V6

EC_SCI_L

AC1

GPIO37

A12

SATA_IREF

L11 K10 C12

SATA_RCOMP

U3

SATA_LED#

SATA_RCOMP Impedance = 50 ohm Trace length < 500 mils Trace spacing = 15 mils

PCH dual I/O SPI ROM

4/23 modify for WP circuit

SPI_WP_ME

R573 *0/J_4S

R574 3.01K /F_4 R636 10K/J _4

PP3300_DSW

PCH_SPI_CS0#_R[17] PCH_SPI_CLK_R[17] PCH_SPI_SI_R[17]

PCH_SPI_SO_R[17]

PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO

SATA_RXN0_SSD [2 0] SATA_RXP0_SSD [20] SATA_TXN0_SSD [20] SATA_TXP0_SSD [20]

+V1.05S_ASATA3PLL

PP3300_PCH

R627 *0/J _6S R624 *0/J _6

near SPI ROM as possible

R146 33/J_4 R145 33/J_4 R153 33/J_4 R103 33/J_4

C162 *22p/50V/NPO_4

+3V_PCH_ME

C257 0.1U/10V/X5R_4

2 1

U21

3 5

TC7SH08FU

SPI_WP_ME SPI_HOLD_ME

1

2

Haswell ULT PCH(LPC,SPI,SMBUS,C-LINK,THERMAL)

LPC_LAD0[19,21,26] LPC_LAD1[19,21,26] LPC_LAD2[19,21,26] LPC_LAD3[19,21,26]

LPC_LFRAME#[19,21,26]

TP88

TP91 TP115

EC_SMI_L [26] PCH_NMI_DBG_L [26] EC_SCI_L [26]

W25Q64FVSSIG(SOIC) / AKE3EFP0N06----->8MB

D2 RB500V-40

R541 *0/J_4S R546 *0/J_4S R548 *0/J_4S R549 *0/J_4S

4

SPI_WP_ME_ROM

R658 10K/J_4

4/23 modify for WP circuit

near SPI ROM as possible

R552 *0/J_4S R553 *0/J_4S

Q472N7002K

3

2

SPI_WP_ME

AU14

AW12

AY12

AW11

AV12

AA3

PCH_SPI_CLK

Y7 Y4

PCH_SPI_CS1#

AC2 AA2

PCH_SPI_SI

AA4

PCH_SPI_SO

Y6

PCH_SPI_IO2

AF1

PCH_SPI_IO3

EC_SMI_L

EC_SCI_L

PCH_NMI_DBG_L

GPIO37

+3V_PCH_MEPP3300_PCH

R309 4.7K/J _4

U14

1

CE#

VDD

6

SCK

5

SI

2

SO

HOLD#

3

WP#

VSS

ROM-8M

GPIO_SPI_WP [17] SPI_HOLD#_BIOS [17]

PCH_SPI_WP_D [10]

PCH_SPI_WP_D co nnect to GPIO58 at GR B

SPI_WP_ME [24,26]

U42G

LAD0 LAD1 LAD2 LAD3 LFRAME

SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3

PP3300_PCH

R182 10K/J_4

R168 10K/J_4 R169 10K/J_4

R655 10K/J_4

+3V_PCH_ME

8

7

SPI_HOLD_ME

R147 100K/ J_4

4

TP523 TP524 TP525 TP526 TP527

5/6 add for ICT

To debug header

To PCH

From Screw/EC

HSW_ULT_DDR3L

LPC

+3V_PCH_ME

C147

0.1U/10V/X5R_4

TP528

+3V_S5 +3V_S5 +3V_S5

SMBUS

+3V_S5 +3V_S5 +3V

+3V_S5

SML1ALERT/PCHHOT/GPIO73

+3V_S5 +3V_S5

C-LINKSPI

SMBus

SMBALERT/GPIO11

SMBDATA

SML0ALERT/GPIO60

_S5

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

7 OF 19

PP3300_PCH_SUS

R680 10K/J_4 R697 10K/J_4 R689 10K/J_4

R285 2.2K/J_4 R284 2.2K/J_4 R663 2.2K/J_4 R661 2.2K/J_4

R278 2.2K/J _4 R290 2.2K/J _4

SMB_PCH_CLK_LVDS[16]

SMB_PCH_DAT_LVDS[16]

DX/LVDS Bridge

SMBCLK

SML0CLK

CL_CLK

CL_DATA

CL_RST

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

AF2 AD2 AF4

R279

2.2K/J_4

1

SMBALERT# SMB_PCH_CLK SMB_PCH_DAT SMB0ALERT# SMB_ME0_CLK SMB_ME0_DAT SMB1ALERT# SMB_ME1_CLK SMB_ME1_DAT

CL_CLKPCH_SPI_CS0# CL_DAT CL_RST#

SMB0ALERT# SMB1ALERT# SMBALERT#

SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SMB_ME1_CLK SMB_ME1_DAT

PP3300_DX

R280

2.2K/J_4

PP3300_DX[16,18,20,21,22,23,25,26,29] +V1.05S_ASATA3PLL[1 1]

PP3300_DSW[5,7,10,11,13,20,21,24,25,26,28,29,33] PP3300_RTC[11,22,23,25,26,27,28]

PP1050_PCH_SUS[11,13,31] PP3300_PCH[2,7,9,10,11,13,20,25,29] PP3300_PCH_SUS[7,9,10,11,13,20,25,29] +3V_PCH_ME[17]

Q68

1

4 3

2N7002DW

LVDS Bridge

TP87 TP86 TP89

SMB_PCH_CLK [13] SMB_PCH_DAT [13]

6

SMB_PCH_CLK

2

SMB_PCH_DAT

5

PCH_SUS/PCH

PP3300_DX +V1.05S_ASATA3PLL

PP3300_DSW PP3300_RTC

PP1050_PCH_SUS PP3300_PCH PP3300_PCH_SUS +3V_PCH_ME

08

PP3300_DX

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

PCH 2/6 (RTC/HDA/SATA/SPI)

Date:

Friday, August 16, 2013

5

4

3

2

Friday, August 16, 2013

Sheet :

1

of

8 42

Rev.Size

1A

5

4

3

2

1

09

Haswell ULT PCH (PCIE,USB3.0,USB2.0)

PCIE USB

+3V_S5 +3V_S5

HSW_ULT_DDR3L

11 OF 19

+3V_S5 +3V_S5

+3V_S5 +3V_S5 +3V_S5 +3V_S5

DSW

USB2N0

DSW

USB2P0

DSW

USB2N1

DSW

USB2P1

DSW

USB2N2

DSW

USB2P2

DSW

USB2N3

DSW

USB2P3

DSW

USB2N4

DSW

USB2P4

DSW

USB2N5

DSW

USB2P5

DSW

USB2N6

DSW

USB2P6

DSW

USB2N7

DSW

USB2P7

USB3RN1 USB3RP1

USB3TN1 USB3TP1

USB3RN2 USB3RP2

USB3TN2 USB3TP2

USBRBIAS

OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

ICT

RSVD RSVD

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11 AN10 AM10

AL3 AT1 AH2 AV3

USBCOMP

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

USBP0- [24] USBP0+ [24]

USBP1- [24] USBP1+ [24]

USBP2- [16] USBP2+ [16]

USBP3- [19] USBP3+ [19]

USBP4- [22] USBP4+ [22]

USBP5- [20] USBP5+ [20]

USBP6- [22] USBP6+ [22]

USBP7- [22] USBP7+ [22]

USB3_RXN0 [24] USB3_RXP0 [24]

USB3_TXN0 [24] USB3_TXP0 [24]

USB3_RXN1 [24] USB3_RXP1 [24]

USB3_TXN1 [24] USB3_TXP1 [24]

R245 22.6/F_4

USB_OC0# [26]

USB_OC3# [26]

MB USB3.0_A MB USB3.0_B CCD BT LTE

Touch screen

CardReader

USB 2.0

MB USB3.0_A

MB USB3.0_B

USBCOMP Impedance = 50 ohm Trace length < 500 mils Trace spacing = 15 mils

MB U10/U11 DB

USB Overcurrent

PP3300_PCH_SUS

10

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

RP6

9 8 7 4

10K/J_10P8R

1 2 3

56

U42K

F10

PERN5_L0

E10

PERP5_L0

PCIE_RXN1 PCIE_RXP1

PCIE_TXN1 PCIE_TXP1

PCIE_TX3PCIE_TX3+

C23 C22

F8 E8

B23 A23

H10 G10

B21 C21

E6 F6

B22 A21

G11 F11

C29 B30

F13 G13

B29 A29

G17 F17

C30 C31

F15 G15

B31 A31

E15 E13 A27 B27

PETN5_L0 PETP5_L0

PERN5_L1 PERP5_L1

PETN5_L1 PETP5_L1

PERN5_L2 PERP5_L2

PETN5_L2 PETP5_L2

PERN5_L3 PERP5_L3

PETN5_L3 PETP5_L3

PERN3 PERP3

PETN3 PETP3

PERN4 PERP4

PETN4 PETP4

PERN1/USB3RN3 PERP1/USB3RP3

PETN1/USB3TN3 PETP1/USB3TP3

PERN2/USB3RN4 PERP2/USB3RP4

PETN2/USB3TN4 PETP2/USB3TP4

RSVD RSVD PCIE_RCOMP PCIE_IREF

D D

TP22 TP21

TP11 TP9

PCIE_RX3-_WLAN[19] PCIE_RX3+_WLAN[19]

WLAN

PCIE_TX3-_WLAN[19]

C C

PCIE_TX3+_WLAN[19]

+V1.05S_AUSB3PLL

C587 0.1U/10V/X7R_4 C586 0.1U/10V/X7R_4

R571 3.01K/F_4 R570 *0/J_4S

PCIE_RCOMP PCIE_IREF

Haswell ULT PCH (CLOCK)

U42F

CLK_PCIE_WLANN[19] CLK_PCIE_WLANP[19]

WLAN

B B

CLK_PCIE_REQ0# CLK_PCIE_REQ1# CLK_PCIE_REQ2# CLK_PCIE_REQ3# CLK_PCIE_REQ4# CLK_PCIE_REQ5#

A A

PCIE_CLKREQ_WLAN#[19]

PP3300_PCH

R637 10K/J_4 R645 10K/J_4 R654 10K/J_4 R612 10K/J_4 R608 10K/J_4

5

R639 *0/J_4S

TP75 TP73

CLK_PCIE_REQ2#

CLK_PCIE_REQ1# CLK_PCIE_N0

CLK_PCIE_P0 CLK_PCIE_REQ0#

CLK_PCIE_REQ3#

CLK_PCIE_REQ4#

CLK_PCIE_REQ5#

C43 C42

U2

B41 A41

Y5

C41

B42

AD1

B38

C37

N1

A39 B39

U5

B37 A37

T2

4

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23

HSW_ULT_DDR3L

+3V

CLOCK

SIGNALS

6 OF 19

XTAL24_IN

XTAL24_OUT

RSVD RSVD

DIFFCLK_BIASREF

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8

TESTLOW_AL8

CLKOUT_LPC_0 CLKOUT_LPC_1

CLKOUT_ITPXDP

CLKOUT_ITPXDP_P

A25 B25

K21 M21 C26

C35 C34 AK8 AL8

AN15 AP15

B35 A35

ICLK_BIAS TESTLOW_C35

TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

CLK_PCH_PCI3 CLK_PCH_PCI4

3

XTAL24_IN

XTAL24_OUT

R558 1M/J_4

1 3

R557 3.01K/F_4

R25722/J_4 R25522/J_4 R653322/J_4

C590 12p/50V/C0G_4

Y6 24MHz

2 4

C591 12p/50V/C0G_4

+V1.05S_AXCK_LCPLL

PCLK_TPM [21] CLK_PCI_EC [26]

CLK_PCI_DEBUG [19] CLK_PCIE_XDPN [13] CLK_PCIE_XDPP [13]

TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8

2

+V1.05S_AUSB3PLL

PP3300_PCH_SUS PP3300_PCH

+V1.05S_AXCK_LCPLL

+V1.05S_AUSB3PLL[11]

PP3300_PCH_SUS[7,8,10,11,13,20,25,29] PP3300_PCH[2,7,8,10,11,13,20,25,29]

+V1.05S_AXCK_LCPLL[11]

C266

*18p/50V/C0G_4

R563 10K/J_4 R564 10K/J_4 R258 10K/J_4 R271 10K/J_4

PCLK_TPMCLK_PCI_EC

CLK_PCI_DEBUG

C268

*18p/50V/C0G_4R634 10K/J_4

C

Date:

C5651

*18p/50V/C0G_4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

PCH 3/6 (PCIE/USB/CLK)

Tuesday, August 20, 2013

1

Sheet :

of

9 42

Rev.Size

1A

5

4

3

2

1

10

+1.05V_VCCST

12

IMVP_PWRGD_3V

R709 49.9/F_4

PP3300_PCH

R807 10K/J_4

IMVP_PWRGD_3V [26]

+1.05V_VCCST

2

+1.05V_VCCST

R133 1K/J_4

1 3

Q19 MMBT3904-7-F

EC_RCIN_L [26]

IRQ_SERIRQ [21,26]

GPIO86 [8]

I2C0_SDA_GPIO4 [25] I2C0_SCL_GPIO5 [25] I2C1_SDA_GPIO6 [20,22] I2C1_SCL_GPIO7 [20,22]

GPIO66 [8]

3

Q18 FDV301N

1

R132 1K/J_4

2

CPU thermal trip

SYS_SHDN# [22,26,28,33]

strapping

TRACKPAD TOUCHSCREEN / ALS

strapping

4/23 modify, follow Intel suggestion to un-stuff for unused GPIO

GPIO27 : If not used then use

8.2-kΩ to 10-kΩ pull-down to GND.

PCH GPIO PU/PD

EC_RCIN_L IRQ_SERIRQ PCH_SSD_12_EN PCH_SSD_18_EN

PCH_GPIO76 ODD_PRSNT# TPM_LP_EN_L PP3300_SSD_IO_EN GPIO50 GPIO70 GPIO38 GPIO39

GPIO83 GPIO84 GPIO85 GPIO87 GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO0 GPIO1 GPIO2 GPIO3 GPIO64 GPIO65 GPIO67 GPIO68 GPIO69

I2C0_SDA_GPIO4 I2C0_SCL_GPIO5 I2C1_SDA_GPIO6 I2C1_SCL_GPIO7

WK_GPIO27

GPIO24 ODD_PRSNT# GPIO28 PP3300_SSD_EN

PP3300_CODEC_EN

GPIO56 PP3300_CCD_EN

R585 4.7K/J_4 R586 4.7K/J_4 R609 4.7K/J_4 R601 4.7K/J_4

R727 10K/J_4 R728 *10K/J_4

R6536 10K/J_4 R6537 10K/J_4 R6538 10K/J_4 R6539 10K/J_4 R6540 10K/J_4 R6542 10K/J_4 R6545 10K/J_4

R187 10K/J_4 R159 10K/J_4 R651 10K/J_4 R598 10K/J_4

R626 10K/J_4 R679 *10K/J_4 R643 10K/J_4 R649 10K/J_4 R648 10K/J_4 R121 10K/J_4 R611 10K/J_4 R665 10K/J_4

R206 *10K/J_4 R150 *10K/J_4 R207 *10K/J_4 R152 *10K/J_4 R208 *10K/J_4 R205 *10K/J_4 R597 *10K/J_4 R594 *10K/J_4 R209 *10K/J_4 R590 *10K/J_4 R588 *10K/J_4 R210 *10K/J_4 R589 *10K/J_4 R595 *10K/J_4 R592 *10K/J_4 R584 *10K/J_4 R134 *10K/J_4 R130 *10K/J_4 R128 *10K/J_4 R581 *10K/J_4

PP3300_DSW

PP3300_PCH_SUS

PP3300_PCH

GSPUARTI2C SDIO useless GPIO

U55

VCORE_PGOOD[5,32]

D D

2

NC1VCC

A

GND3Y

74AUP1G07GW

5

C767

0.1U/10V/X5R_4

4

Haswell ULT PCH (GPIO,CPU/MISC,NCTF)

+3V_S5 +3V_S5

+3V +3V +3V_S5 DSW +3V_S5 +3V_S5

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V +3V +3V

+3V_S5 +3V_S5 DSW +3V_S5 +3V_S5

+3V_S5 +3V_S5

+3V

HSW_ULT_DDR3L

GPIO

+3V

+3V +3V +3V +3V

4 3

1

DSW

10 OF 19

Q44

*2N7002DW

CPU/ MISC

+3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V

SERIAL IO

+3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V +3V

5

2 6

PP3300_PCH_SUS

THRMTRIP

+3V

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92

UART0_RTS/GPIO93 UART0_CTS/GPIO94

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST/GPIO2 UART1_CTS/GPIO3

I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

PP3300_WLAN_EN [19,26,29]

WLAN_WAKE_L_Q

PP3300_LTE_EN [26]

LTE_WAKE_L_Q

R250 10K/J_4 R256 10K/J_4

D60 V4 T4 AW15 AF20 AB21

R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2

THRMTRIP# EC_RCIN_L IRQ_SERIRQ

OPI_COMP2

GPIO83 GPIO84 GPIO85 GPIO86 GPIO87 GPIO88 GPIO89 GPIO90 GPIO91 GPIO92 GPIO93 GPIO94 GPIO0 GPIO1 GPIO2 GPIO3 I2C0_SDA_GPIO4 I2C0_SCL_GPIO5 I2C1_SDA_GPIO6 I2C1_SCL_GPIO7 GPIO64 GPIO65 GPIO66 GPIO67 GPIO68 GPIO69

U42J

PCH_GPIO76 LTE_WAKE_L_Q

TP40 TP48

TP52

PP3300_CODEC_EN

TRACKPAD_INT_L PCH_SSD_12_EN

PCH_SSD_18_EN GPIO24 WK_GPIO27 GPIO28 ODD_PRSNT#

GPIO56 PP3300_CCD_EN PCH_SPI_WP_D LTE_DISABLE_L PP3300_SSD_EN RAM_ID2 TPM_LP_EN_L PP3300_SSD_IO_EN GPIO50 MODPHY_EN RAM_ID0 GPIO14 TOUCH_INT_L

RAM_ID1 WLAN_WAKE_L_Q DEVSLP0 GPIO70 GPIO38 GPIO39

TRACKPAD_INT_L[25]

4/22 modify

C C

LTE_DISABLE_L need PU to +3V_LTE

MODPHY_EN[11]

EC_IN_RW[25]

TOUCH_INT_L[20]

WLAN_DISABLE_L[19]

DEVSLP0 for internal SATA I/F.

B B

PP3300_PCH_SUSPP3300_PCH

GPIO15[8]

PCH_SPI_WP_D[8]

LTE_DISABLE_L[22]

R86 *0/J_4S

DEVSLP0[20]

SPKR[8,23]

I PathG Path

R90

R91

*0/J_4S

*0/J_4

R682 10K/J_4 R122 10K/J_4

PCH_SPI_WP_D GPIO14

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

WLAN_WAKE_L[19]

LTE_WAKE_L[22]

RAM ID

PP3300_PCH_SUSPP3300_DSW

G PathI Path

R89

R88

*0/J_4

*0/J_4S

R263 10K/J_4

A A

R681 10K/J_4

TRACKPAD_INT_L TOUCH_INT_L

5

4/22 modify

Micron 84G Hynix Elpida EDJ4216EFBG-GN-F

Hynix H5TC4G63AFR-PBA Elpida EDJ4216EFBG-GN-F

R693 *10K/J_4 R695 *10K/J_4 R688 *10K/J_4

Part Number Vender Total size (Bytes) MT41K256M16HA-125:E H5TC4G63AFR-PBA

MT41K256M16HA-125:E

4

RAM_ID0 RAM_ID1 RAM_ID2

4G 4G 4G 4G 4G

R692 *10K/J_4 R694 *10K/J_4 R687 *10K/J_4

Install Quantity Size/Chip (Bit)

PP3300_PCH_SUS

8 8 4 2GMicron 4 4

4G 4G 4G

2G

3

RAM_ID2/RAM_ID1/RAM_ID0

000 001 010 011 100 1012G

PP3300_PCH_SUS[7,8,9,11,13,20,25,29] +1.05V_VCCST[4,5]

PP3300_PCH[2,7,8,9,11,13,20,25,29]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

PCH 4/6 (GPIO/MISC)

Date:

Friday, August 16, 2013

2

Friday, August 16, 2013

PP3300_PCH_SUS +1.05V_VCCST

PP3300_PCH

1

Sheet :

of

10 42

Rev.Size

1A

5

4

3

2

1

PCH VCCHSIO Power

PP5000

U40

12

MODPHY_EN[10]

C607 0.1U/10V/X5R_4

12

C601 1U/6.3V/X5R_4

PP3300_PCH PP3300_DSW

R604 100K/J_4

PP1050_PCH_SUS

D D

C C

1

R228 *100K/J_4

R596 *0/J_4S

R230 *100K/J_4

SLG59M1470VTR

VDD D_012S_01 D_02_033S_02_03

ON

9

12

C608

0.047u/25V/X7R_4

PP1050_PCH

8

GND

7 5

check this foorpint

+V1.05DX_MODPHY

4/23 modify,Intel suggest 0 ohm

PP1050_PCH

PP3300_PCH

PP1500_PCH_TS

reserve

L39 *80/5A

R560 *0/J_8S R559 *0/J_8S

12

C602

0.1U/10V/X5R_4

+V1.05DX_MODPHY

R6548 *0/J_8S C248 *47u/6.3V/X5R_8 C619 *47u/6.3V/X5R_8 C218 1U/6.3V/X5R_4

R252 0/J_6 R260 *0/J_6 C234 0.1U/10V/X5R_4

Place close to ball

PP3300_PCH_SUS

Deep Sx Non Deep Sx

B B

0412 MOW-WW15 a 0.47uF cap between VccDSW3_3 and DcpSusByp current requirement cannot meet

A A

5

is required if the 1.9A inrush

PP3300_DSW

PP3300_PCH_SUS

PP1050_PCH

+V1.05DX_MODPHY

PP1050_PCH

L18 2.2uH/210mA_8

C88 22u/6.3V/X5R_8 C77 22u/6.3V/X5R_8 C595 1U/6.3V/X5R_4

L17 2.2uH/210mA_8

C89 22u/6.3V/X5R_8 C79 22u/6.3V/X5R_8 C596 1U/6.3V/X5R_4

+V1.05S_APLLOPI

+V3.3DX_1.5DX_1.8DX_AUDIO

C270 22u/6.3V/X5R_8

R254 *0/J_6S R253 *0/J_6

C238 1U/6.3V/X5R_4

PP3300_PCH

4

R165 *0/J_8S C174 22u/6.3V/X5R_8

R6546 *0/J_8S C197 *1U/6.3V/X5R_4

C579 47u/6.3V/X5R_8 C578 *47u/6.3V/X5R_8 C158 1U/6.3V/X5R_4

R6547 *0/J_8S

C68 47u/6.3V/X5R_8 C76 *47u/6.3V/X5R_8 C594 1U/6.3V/X5R_4

PP1050_PCH

PP3300_PCH_SUS

C577 *1U/6.3V/X5R_4 C163 1U/6.3V/X5R_4 C175 1U/6.3V/X5R_4

R179 *0/J_8S C181 *1U/6.3V/X5R_4

+V1.05S_AUSB3PLL

1.741A

41mA

Haswell ULT PCH (Power)

HSIO

USB3

HDA

VRM

GPIO/LPC

LPT LP POWER

HSW_ULT_DDR3L

OPI

13 OF 19

RTC

SPI

CORE

THERMAL SENSOR

SERIAL IO

SUS OSCILLATOR

USB2

VCCSUS3_3

VCCRTC DCPRTC

VCCSPI

VCCASW VCCASW

VCC1_05 VCC1_05 VCC1_05 VCC1_05

VCC1_05 DCPSUSBYP DCPSUSBYP

VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

VCCSDIO VCCSDIO

DCPSUS4

RSVD VCC1_05 VCC1_05

AH11 AG10 AE7

Y8

AG14 AG13

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

J15 K14 K16

U8 T9

AB8

AC20 AG16 AG17

PP1050_PCH_SUS[8,13,31]

PP3300_RTC[8,22,23,25,26,27,28] PP1050_PCH[5,13,26,31]

+V1.05S_AUSB3PLL[9] +V1.05S_ASATA3PLL[8]

PP3300_PCH_SUS[7,8,9,10,13,20,25,29] PP3300_DSW[5,7,8,10,13,20,21,24,25,26,28,29,33] PP3300_PCH[2,7,8,9,10,13,20,25,29]

+V1.05S_AXCK_LCPLL[9]

PP5000[18,20,22,23,24,25,28,30,31,32,34]

+V3.3A_DSW_PRTCSUS

+VCCRTCEXT

+V3.3M_PSPI

PCH_VCC_1_1_20 PCH_VCC_1_1_21

+V1.05S_CORE_PCH

+PCH_VCCDSW +V1.05M_VCCASW

+1.05V_DCPSUS1

0.109A

+V1.5S_VCCATS

+V3.3S_VCCPTS

+V3.3S_VCCSDIO

+1.05V_DCPSUS4

+V1.05S_VCCUSBCORE

2

C208 0.1U/10V/X5R_4

18mA

3mA

1mA

+V1.05S_ASATA3PLL

1.838A

+V1.05S_AIDLE

42mA

57mA

C177 *10u/6.3V/X5R_6 C166 *1U/6.3V/X5R_4

C235 *1U/6.3V/X5R_4 C233 1U/6.3V/X5R_4

+1.05V_DCPSUS3

11mA

+1.05V_DCPSUS2

+VCCPDSW

+V3.3S_VCCPCORE

0.114A

41mA 17mA

+V1.05S_AXCK_DCB

0.2A

+V1.05S_AXCK_LCPLL

31mA

R6543 *0/J_6S

R6544 *0/J_6S

+V1.05S_SSCF100

C164 1U/6.3V/X5R_4

+V1.05S_SSCFF

C209 1U/6.3V/X5R_4

AA21

AH14

AH13

AH10

AE20 AE21

L10

B18 B11

Y20

W21

J13

AC9 AA9

W9

J18 K19 A20 J17 R21 T21 K18 M20 V21

K9

M9 N8

P9

V8

U42M

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

RSVD VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3

63mA

3

R212 *0/J_6S R194 *0/J_6S

4/22 modify

C4 0.47u/25V/X7R_6

0.658A

C212 *1U/6.3V/X5R_4

R111 *0/J_6S R107 *0/J_6S C183 1U/6.3V/X5R_4

R158 *0/J_6S C194 1U/6.3V/X5R_4

R270 *0/J_8S C236 1U/6.3V/X5R_4

PP1050_PCH_SUS

PP3300_RTC PP1050_PCH

+V1.05S_AUSB3PLL +V1.05S_ASATA3PLL

PP3300_PCH_SUS PP3300_DSW PP3300_PCH

+V1.05S_AXCK_LCPLL PP5000

+V1.05M_VCCASW

R217 *0/J_8S C217 22u/6.3V/X5R_8 C221 1U/6.3V/X5R_4

R197 *0/J_6S C220 1U/6.3V/X5R_4

C642 1U/6.3V/X5R_4 C643 0.1U/10V/X5R_4 C231 0.1U/10V/X5R_4

R220 *0/J_6 R204 *0/J_6S C216 0.1U/10V/X5R_4

PP1050_PCH PP1050_PCH

+VCCPDSW

PP1500_PCH_TS PP3300_PCH

PP3300_PCH

PP1050_PCH

C

Date:

PP3300_PCH_SUS

PP3300_RTC

PP3300_DSW PP3300_PCH

7/12 modify for leakage

place near CPU

4/23 modify, change short PAD

R174 *short_8 C192 10u/6.3V/X5R_6 C213 1U/6.3V/X5R_4 C237 1U/6.3V/X5R_4

PP1050_PCH

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

PCH 5/6 (POWER)

Friday, August 16, 2013

1

Sheet :

11

PP1050_PCH

11 42

Rev.Size

1A

of

5

4

3

2

1

12

Haswell ULT (GND)

D D

HSW_ULT_DDR3L

U42N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

VSS

AC61

VSS

AD21

VSS

AD3

VSS

AD63

VSS

AE10

VSS

AE5

VSS

AE58

VSS

AF11

VSS

AF12

VSS

AF14

VSS

AF15

VSS

AF17

VSS

AF18

VSS

AG1

VSS

C C

B B

AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

14 OF 19

AJ35

VSS

AJ39

VSS

AJ41

VSS

AJ43

VSS

AJ45

VSS

AJ47

VSS

AJ50

VSS

AJ52

VSS

AJ54

VSS

AJ56

VSS

AJ58

VSS

AJ60

VSS

AJ63

VSS

AK23

VSS

AK3

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL20

VSS

AL22

VSS

AL23

VSS

AL26

VSS

AL29

VSS

AL31

VSS

AL33

VSS

AL36

VSS

AL39

VSS

AL40

VSS

AL45

VSS

AL46

VSS

AL51

VSS

AL52

VSS

AL54

VSS

AL57

VSS

AL60

VSS

AL61

VSS

AM1

VSS

AM17

VSS

AM23

VSS

AM31

VSS

AM52

VSS

AN17

VSS

AN23

VSS

AN31

VSS

AN32

VSS

AN35

VSS

AN36

VSS

AN39

VSS

AN40

VSS

AN42

VSS

AN43

VSS

AN45

VSS

AN46

VSS

AN48

VSS

AN49

VSS

AN51

VSS

AN52

VSS

AN60

VSS

AN63

VSS

AN7

VSS

AP10

VSS

AP17

VSS

AP20

VSS

AP22 AP23 AP26 AP29

AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

HSW_ULT_DDR3L

U42O

VSS VSS VSS VSS

AP3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AR5

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AU1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

15 OF 19

AV59

VSS

AV8

VSS

AW16

VSS

AW24

VSS

AW33

VSS

AW35

VSS

AW37

VSS

AW4

VSS

AW40

VSS

AW42

VSS

AW44

VSS

AW47

VSS

AW50

VSS

AW51

VSS

AW59

VSS

AW60

VSS

AY11

VSS

AY16

VSS

AY18

VSS

AY22

VSS

AY24

VSS

AY26

VSS

AY30

VSS

AY33

VSS

AY4

VSS

AY51

VSS

AY53

VSS

AY57

VSS

AY59

VSS

AY6

VSS

B20

VSS

B24

VSS

B26

VSS

B28

VSS

B32

VSS

B36

VSS

B4

VSS

B40

VSS

B44

VSS

B48

VSS

B52

VSS

B56

VSS

B60

VSS

C11

VSS

C14

VSS

C18

VSS

C20

VSS

C25

VSS

C27

VSS

C38

VSS

C39

VSS

C57

VSS

D12

VSS

D14

VSS

D18

VSS

D2

VSS

D21

VSS

D23

VSS

D25

VSS

D26

VSS

D27

VSS

D29

VSS

D30

VSS

D31

VSS

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D5 D50 D51 D53 D54 D55 D57 D59 D62

D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22

G3

G5

G6

G8 H13

HSW_ULT_DDR3L

U42P

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

16 OF 19

VSS_SENSE

H17

VSS

H57

VSS

J10

VSS

J22

VSS

J59

VSS

J63

VSS

K1

VSS

K12

VSS

L13

VSS

L15

VSS

L17

VSS

L18

VSS

L20

VSS

L58

VSS

L61

VSS

L7

VSS

M22

VSS

N10

VSS

N3

VSS

P59

VSS

P63

VSS

R10

VSS

R22

VSS

R8

VSS

T1

VSS

T58

VSS

U20

VSS

U22

VSS

U61

VSS

U9

VSS

V10

VSS

V3

VSS

V7

VSS

W20

VSS

W22

VSS

Y10

VSS

Y59

VSS

Y63

VSS

V58

VSS

AH46

VSS

V23

VSS

E62

VSS_SENSE_R

AH16

VSS

U42R

AT2

RSVD

AU44

RSVD

AV44

RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

R591 *0/J_4S

R593 100/F_4

HSW_ULT_DDR3L

18 OF 19

VSS_SENSE [32]

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

U42Q

DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 TP_DC_TEST_AY60

TP97

DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 TP_DC_TEST_B2

TP77

DC_TEST_A3_B3 DC_TEST_A61_B61 DC_TEST_B62_B63

DC_TEST_C1_C2

A A

5

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

4

HSW_ULT_DDR3L

17 OF 19

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

3

A3

DC_TEST_A3_B3

A4

TP_DC_TEST_A4

A60

TP_DC_TEST_A60

A61

DC_TEST_A61_B61

A62

TP_DC_TEST_A62

AV1

TP_DC_TEST_AV1

AW1

TP_DC_TEST_AW1

AW2

DC_TEST_AY2_AW2

AW3

DC_TEST_AY3_AW3

AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

TP_DC_TEST_AW63

TP76 TP74 TP78

TP95 TP94

TP96

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

PCH 6/6 (GND)

Date:

Friday, August 16, 2013

2

Friday, August 16, 2013

Sheet :

1

of

12 42

Rev.Size

1A

5

4

3

2

1

13

D D

CN32

XDP_PREQ#[4] XDP_PRDY#[4]

XDP_BPM#0[4] XDP_BPM#1[4]

SMB_PCH_DAT[8]

SMB_PCH_CLK[8]

XDP_TCK1[8] XDP_TCK0[4,8]

R745 *0/J_6

CFG0[6] CFG1[6]

CFG2[6] CFG3[6]

CFG4[6,8] CFG5[6]

CFG6[6] CFG7[6]

H_SYS_PWROK_XDP

R287 1K/J_4

PP3300_PCH_SUS

Close to R719 (8/13)

PCH_RSMRST_L[7,26]

PP1050_PGOOD[5,26,31]

PWR_DEBUG[5]

C5669

0.1U/10V/X5R_4

C C

SYS_PWROK[5,7,26]

R6564 1K/J_4

R286 *1K/J_4

R288 *0/J_4S

R766 *0/J_6

APS3

XDP_PREQ_N XDP_PRDY_N

CFG0 CFG1

CFG2 CFG3

CFG4 CFG5

CFG6 CFG7

VCCST_PWRGD_XDP PWR_BTN_L

H_SYS_PWROK_XDP

APS7APS1

31

*XDP_CONN_60P

APS

CN19

1

APS1 APS3

APS7

R767 *0/J_6 R765 *0/J_4 R742 *0/J_6 R764 *0/J_4 R763 *0/J_4 R762 *0/J_4 R744 *0/J_6

R761 *0/J_4 R760 *0/J_4 R759 *0/J_4 R758 *0/J_4

1

2

3

4

5

6

7

B B

10 11 12 13 14 15 16 17 18

*APS_CONN_18P

8

9

10 11 12 13 14 15 16 17 18

PP3300_PCH_SUS

PWR_BTN_L SYS_RESET#

PCH_SLP_S3_L [7,26,29,30,31,33] PCH_SLP_S5_L [7,26,29,30]

PCH_SLP_S4_L [7] PCH_SLP_A_L [7]

PCH_RTCRST [8,26] PWR_BTN_L [17,25,26] SYS_RESET# [7,17] PCH_SLP_S0_L [7,26] VCCST_PWRGD[5]

PP3300_DSW

31 323229 333328 343427 353526 363625 373724 383823 393922 404021 414120 424219 434318 444417 454516 464615 474714 484813 494912 505011 515110 52529 53538 54547 55556 56565 57574 58583 59592

ICT

60601

30

2

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

U56

NC1VCC

A

GND3Y

74AUP1G07GW

NOA_STBP_0 NOA_STBN_0

CFG8 CFG9

CFG10 CFG11

NOA_STBP_1 NOA_STBN_1

CFG12 CFG13

CFG14 CFG15

CK_XDP_P_R CK_XDP_N_R

XDP_RST_R_N XDP_DBRESET_N

XDP_TDO XDP_TRST_N XDP_TDI XDP_TMS

XDP_TDO[8]

XDP_TDI[8]

XDP_TMS[8]

PP1050_PCH

5

C768

0.1U/10V/X5R_4

4

NOA_STBP_0 [6] NOA_STBN_0 [6]

CFG8 [6] CFG9 [6]

CFG10 [6] CFG11 [6]

NOA_STBP_1 [6] NOA_STBN_1 [6]

CFG12 [6] CFG13 [6]

CFG14 [6] CFG15 [6]

R236 *0/J_4S R237 *0/J_4S

R238 1K/J_4 R239 *0/J_4S

R219 51/J_4

XDP_TDO

XDP_TDI

XDP_TMS

XDP_TRST_N

PP3300_PCH

R489

12

10K/J_4

PP3300_PCH

SYS_RESET#

C176

0.1U/10V/X5R_4

U15

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

74CBTLV3126

XDP_DBRESET_N

CLK_PCIE_XDPP [9] CLK_PCIE_XDPN [9]

PLTRST# [7,19,21,22,26]

PP1050_PCH_SUS

R240 1K/J_4

3

1B

6

2B

8

3B

11

4B

15

DPAD

7

GND

PP3300_DSW[5,7,8,10,11,20,21,24,25,26,28,29,33] PP3300_PCH_SUS[7,8,9,10,11,20,25,29] PP1050_PCH_SUS[8,11,31] PP1050_PCH[5,11,26,31] PP3300_PCH[2,7,8,9,10,11,20,25,29]

PP3300_PCH

C5668

0.1U/10V/X5R_4

XDP_TDO_CPU [4]

XDP_TDI_CPU [4]

XDP_TMS_CPU [4]

XDP_TRST# [4,8]

PP3300_DSW PP3300_PCH_SUS PP1050_PCH_SUS PP1050_PCH PP3300_PCH

PP1050_PCH_SUSPP1050_PCH_SUS

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

CPU/PCH XDP

Date:

Tuesday, August 20, 2013

5

4

3

2

Tuesday, August 20, 2013

Sheet :

1

of

13 42

Rev.Size

1A

1

<DDR>

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM +SMDDR_VREF_DQ0

M_A_A<0>[3] M_A_A<1>[3] M_A_A<2>[3] M_A_A<3>[3] M_A_A<4>[3] M_A_A<5>[3] M_A_A<6>[3] M_A_A<7>[3] M_A_A<8>[3]

A A

M_A_DIM0_CK_DDR0_DP[3] M_A_DIM0_CK_DDR0_DN[3]

B B

ndor

DDR3_DRAMRST#[4,15]

P/NVe

M_A_A<9>[3] M_A_A<10>[3] M_A_A<11>[3] M_A_A<12>[3] M_A_A<13>[3] M_A_A<14>[3] M_A_A<15>[3]

M_A_BS[2:0][3]

M_A_DIM0_CKE0[3]

M_A_DIM0_CS0_N[3]

M_A_RAS_N[3] M_A_CAS_N[3] M_A_WE_N[3]

M_A_DQS_DP<2>[3] M_A_DQS_DP<3>[3]

M_A_DQS_DN<2>[3] M_A_DQS_DN<3>[3]

M_A_BS0 M_A_BS1 M_A_BS2

M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DN M_A_DIM0_CKE0

M_A_ODT0 M_A_DIM0_CS0_N M_A_RAS_N M_A_CAS_N M_A_WE_N

DDR3_DRAMRST# DDR3_DRAMRST#

R402 240/F_4

1 2

M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15>

2

BYTE2_16-23

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9

VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

BYTE3_24-31

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M_A_DQ<16> [3] M_A_DQ<18> [3] M_A_DQ<21> [3] M_A_DQ<19> [3] M_A_DQ<17> [3] M_A_DQ<23> [3] M_A_DQ<20> [3] M_A_DQ<22> [3]

M_A_DQ<27> [3] M_A_DQ<24> [3] M_A_DQ<26> [3] M_A_DQ<28> [3] M_A_DQ<30> [3] M_A_DQ<29> [3] M_A_DQ<31> [3] M_A_DQ<25> [3]

PP1350 PP1350 PP1350 PP1350

M_A_DQS_DP<7>[3] M_A_DQS_DP<5>[3]

M_A_DQS_DN<7>[3] M_A_DQS_DN<5>[3] M_A_DQS_DN<6>[3]

U23

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL SDRAM DDR3

RAM

_DDR3L

Micron/MT41K256M16HA-125:E/AKD5JGSTL02 for proto board

3

M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DN

+SMDDR_VREF_DQ0

M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15>

M_A_BS0 M_A_BS1 M_A_BS2

M_A_DIM0_CKE0

M_A_ODT0

M_A_DIM0_CS0_N

M_A_RAS_N M_A_CAS_N M_A_WE_N

M_A_ZQ2M_A_ZQ1

R367 240/F_4

1 2

4

BYTE7_56-63

U24

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL SDRAM DDR3

RAM

_DDR3L

BYTE5_40-47 BYTE6_48-55

E3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1

VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1

VSSQ#D8

VSSQ#E2 VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

M_A_DQ<60> [3]

F7

M_A_DQ<58> [3]

F2

M_A_DQ<56> [3]

F8

M_A_DQ<62> [3]

H3

M_A_DQ<61> [3]

H8

M_A_DQ<63> [3]

G2

M_A_DQ<57> [3]

H7

M_A_DQ<59> [3]

D7

M_A_DQ<45> [3]

C3

M_A_DQ<42> [3]

C8

M_A_DQ<40> [3]

C2

M_A_DQ<46> [3]

A7

M_A_DQ<41> [3]

A2

M_A_DQ<47> [3]

B8

M_A_DQ<44> [3]

A3

M_A_DQ<43> [3]

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M_A_DQS_DP<0>[3] M_A_DQS_DP<1>[3]

M_A_DQS_DN<0>[3] M_A_DQS_DN<1>[3]

5

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0

M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15>

M_A_BS0 M_A_BS1 M_A_BS2

M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DN

M_A_DIM0_CKE0

M_A_ODT0 M_A_DIM0_CS0_N

M_A_RAS_N M_A_CAS_N M_A_WE_N

DDR3_DRAMRST#

M_A_ZQ3

R405 240/F_4

1 2

6

BYTE0_0-7

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSSQ#B1

VSSQ#B9 VSSQ#D1 VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

BYTE1_8-15

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M_A_DQ<2> [3] M_A_DQ<3> [3] M_A_DQ<6> [3] M_A_DQ<1> [3] M_A_DQ<7> [3] M_A_DQ<4> [3] M_A_DQ<5> [3] M_A_DQ<0> [3]

M_A_DQ<13> [3] M_A_DQ<10> [3]

M_A_DQ<8> [3]

M_A_DQ<14> [3]

M_A_DQ<9> [3] M_A_DQ<15> [3] M_A_DQ<12> [3] M_A_DQ<11> [3]

M_A_DQS_DP<4>[3] M_A_DQS_DP<6>[3]

M_A_DQS_DN<4>[3]

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0

M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DN

M_A_ODT0 M_A_DIM0_CS0_N

M_A_RAS_N M_A_CAS_N M_A_WE_N

DDR3_DRAMRST#

1 2

U25

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL SDRAM DDR3

RAM

_DDR3L

M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15>

M_A_BS0 M_A_BS1 M_A_BS2

M_A_DIM0_CKE0

M_A_ZQ4

R369 240/F_4

7

8

BYTE4_32-39

U26

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL SDRAM DDR3

RAM

_DDR3L

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9 VSSQ#D1 VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

E3

M_A_DQ<32> [3]

F7

M_A_DQ<38> [3]

F2

M_A_DQ<35> [3]

F8

M_A_DQ<36> [3]

H3

M_A_DQ<33> [3]

H8

M_A_DQ<37> [3]

G2

M_A_DQ<34> [3]

H7

M_A_DQ<39> [3]

D7

M_A_DQ<48> [3]

C3

M_A_DQ<53> [3]

C8

M_A_DQ<49> [3]

C2

M_A_DQ<52> [3]

A7

M_A_DQ<55> [3]

A2

M_A_DQ<51> [3]

B8

M_A_DQ<54> [3]

A3

M_A_DQ<50> [3]

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

14

Hynix

AKD5JGST400

Elpida

C C

DDR3L 1333Mhz 4 Gb

DDR3L 1600Mhz 4 GbAKD5JGST404

PP1350

Distributed around all DRAM devices (CHA and CHB)

C411

C463

C461 10u/6.3V/X5R_6

10u/6.3V/X5R_6

C350 10u/6.3V/X5R_6

Place these Caps near each X16 Memory Down

C362

C448 1U/6.3V/X5R_4

1U/6.3V/X5R_4

C452 1U/6.3V/X5R_4

C447 1U/6.3V/X5R_4

C666 10u/6.3V/X5R_6

C444 1U/6.3V/X5R_4

C699 10u/6.3V/X5R_6

C445 1U/6.3V/X5R_4

C462 10u/6.3V/X5R_6

C453 1U/6.3V/X5R_4

C712 1U/6.3V/X5R_4

C674 1U/6.3V/X5R_4

M_A_RAS_N M_A_CAS_N M_A_WE_N M_A_BS0 M_A_BS1 M_A_BS2 M_A_DIM0_CKE0 M_A_DIM0_CS0_N M_A_A<0> M_A_A<1> M_A_A<2> M_A_A<3> M_A_A<4> M_A_A<5> M_A_A<6> M_A_A<7> M_A_A<8> M_A_A<9> M_A_A<10> M_A_A<11> M_A_A<12> M_A_A<13> M_A_A<14> M_A_A<15>

R374 34.8/F_4 R768 34.8/F_4 R364 34.8/F_4 R776 34.8/F_4 R779 34.8/F_4 R375 34.8/F_4 R361 34.8/F_4 R370 34.8/F_4 R780 34.8/F_4 R784 34.8/F_4 R383 34.8/F_4 R783 34.8/F_4 R388 34.8/F_4 R397 34.8/F_4 R401 34.8/F_4 R399 34.8/F_4 R400 34.8/F_4 R379 34.8/F_4 R772 34.8/F_4 R384 34.8/F_4 R378 34.8/F_4 R398 34.8/F_4 R396 34.8/F_4 R371 34.8/F_4

M_A_ODT0

Modify in MV stage (8/14)

M_A_DIM0_CK_DDR0_DP M_A_DIM0_CK_DDR0_DN

R360 30/F_4

R769 26.1/F_4 R755 26.1/F_4

PP1350+DDR_VTT_RUN

+DDR_VTT_RUN

C358 1U/6.3V/X5R_4

C309 10u/6.3V/X5R_6

C375 1U/6.3V/X5R_4

+SMDDR_VREF_DIMM

+SMDDR_VREF_DQ0

C352 1U/6.3V/X5R_4

12

C437

0.047u/25V/X7R_4

1U/6.3V/X5R_4

12

C436

0.047u/25V/X7R_4

1U/6.3V/X5R_4

12

C434

0.047u/25V/X7R_4

12

C394

0.047u/25V/X7R_4

12

C703

0.047u/25V/X7R_4

C689

C363

Place these Caps near Memory Down CA & DQ pin

12

C720

0.047u/25V/X7R_4

12

C385

0.047u/25V/X7R_4

3

12

C387

0.047u/25V/X7R_4

12

C724

0.047u/25V/X7R_4

12

C400

0.047u/25V/X7R_4

12

C384

0.047u/25V/X7R_4

M1 solution

PP1350

R391

1.8K/F_4

R392

1.8K/F_4

Vref_CA

+SMDDR_VREF_DIMM

6

C438 470p/50V/X7R_4

+VREFDQ_SA_M3

R337 *0/J _6S

M3 solution

7

R6526 *0/J_6

R345 5/F_6

C347

0.022u/16V/X7R_4

1 2

R335

24.9/F_4

Custom

Date:

5

R6525 *0/J_6

R387 2.7 /F_6

C412

0.022u/16V/X7R_4

1 2

R381

24.9/F_4

PP1350_VREF PP1350_VREF

+VREF_CA_CPU

4

R382 *0/J _6S

M3 solution

M1 solution

PP1350

R347

1.8K/F_4

+SMDDR_VREF_DQ0

R349

1.8K/F_4

+VREF_CA_CPU[3] +VREFDQ_SA_M3[3] PP1350[4,5,15,30]

+DDR_VTT_RUN[15,30]

+SMDDR_VREF_DIMM[15]

PP1350_VREF[15,30]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

DDR3L MEMORY DOWNx16 A

Friday, August 16, 2013

Sheet :

8

Vref_DQ

C374 470p/50V/X7R_4

+VREF_CA_CPU +VREFDQ_SA_M3 PP1350

+DDR_VTT_RUN +SMDDR_VREF_DIMM

PP1350_VREF

of

14 42

Rev.Size

1A

C433 1U/6.3V/X5R_4

C687 1U/6.3V/X5R_4

C440 1U/6.3V/X5R_4

C377 1U/6.3V/X5R_4

1U/6.3V/X5R_4

C417 1U/6.3V/X5R_4

2

C379 1U/6.3V/X5R_4

+DDR_VTT_RUN

C690 1U/6.3V/X5R_4

D D

1

C413

5

<DDR>

U31

M_B_A<0> M_B_A<1> M_B_A<2> M_B_A<3> M_B_A<4> M_B_A<5> M_B_A<6> M_B_A<7> M_B_A<8> M_B_A<9> M_B_A<10> M_B_A<11> M_B_A<12> M_B_A<13> M_B_A<14> M_B_A<15>

M_B_BS0 M_B_BS1 M_B_BS2

M_B_ODT0

M_B_ZQ1

R487 240/F_4

M8

H1 N3

P7 P3 N2 P8 P2 R8 R2 T8 R3

L7 R7 N7 T3 T7

M7

M2

N8

M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

T2

L8

J1

L1

J9

L9

C742 10u/6.3V/X5R_6

C456 1U/6.3V/X5R_4

C504 1U/6.3V/X5R_4

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

BA0 BA1 BA2

CK CK CKE

VDDQ#A1

ODT CS

VDDQ#A8

RAS

VDDQ#C1

CAS

VDDQ#C9

WE

VDDQ#D2 VDDQ#E9

VDDQ#F1

DQSL

VDDQ#H2

DQSU

VDDQ#H9

DML DMU

DQSL DQSU

RESET ZQ

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2

NC#J1

VSSQ#E8

NC#L1

VSSQ#F9

NC#J9

VSSQ#G1 VSSQ#G9

NC#L9

100-BALL SDRAM DDR3

RAM

_DDR3L

Micron/MT41K256M16HA-125:E/AKD5JGSTL02 for proto board

10u/6.3V/X5R_6

C451 1U/6.3V/X5R_4

C505 1U/6.3V/X5R_4

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1

M_B_A<0>[3] M_B_A<1>[3] M_B_A<2>[3] M_B_A<3>[3] M_B_A<4>[3] M_B_A<5>[3] M_B_A<6>[3] M_B_A<7>[3] M_B_A<8>[3]

D D

M_B_DIM0_CK_DDR0_DP[3] M_B_DIM0_CK_DDR0_DN[3] M_B_DIM0_CKE0[3]

C C

DDR3_DRAMRST#[4,14]

M_B_A<9>[3] M_B_A<10>[3] M_B_A<11>[3] M_B_A<12>[3] M_B_A<13>[3] M_B_A<14>[3] M_B_A<15>[3]

M_B_BS[2:0][3]

M_B_DIM0_CK_DDR0_DP M_B_DIM0_CK_DDR0_DN M_B_DIM0_CKE0

M_B_DIM0_CS0_N[3] M_B_RAS_N[3] M_B_CAS_N[3] M_B_WE_N[3]

M_B_DQS_DP<2>[3] M_B_DQS_DP<1>[3]

M_B_DQS_DN<2>[3] M_B_DQS_DN<1>[3]

M_B_DIM0_CS0_N M_B_RAS_N M_B_CAS_N M_B_WE_N

DDR3_DRAMRST#

1 2

P/NVendor

Hynix

AKD5JGST400

Elpida

B B

DDR3L 1333Mhz 4 Gb

DDR3L 1600Mhz 4 GbAKD5JGST404

PP1350

C1001 10u/6.3V/X5R_6

C705 1U/6.3V/X5R_4

C503 1U/6.3V/X5R_4

C669 10u/6.3V/X5R_6

C454 1U/6.3V/X5R_4

C501 1U/6.3V/X5R_4

C1002 10u/6.3V/X5R_6

Place these Caps near each X16 Memory Down

C702 1U/6.3V/X5R_4

C502 1U/6.3V/X5R_4

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

C508 10u/6.3V/X5R_6

C342 1U/6.3V/X5R_4

C356 1U/6.3V/X5R_4

TE1_8-15

C716 1U/6.3V/X5R_4

C506 1U/6.3V/X5R_4

4

U35

M8

VREFCA

H1

VREFDQ

N3

M_B_A<0>

A0

P7

M_B_A<1>

A1

P3

M_B_A<2>

A2

N2

M_B_A<3>

A3

P8

M_B_A<4>

A4

P2

M_B_A<5>

A5

R8

M_B_A<6>

A6

R2

M_B_A<7>

A7

T8

M_B_A<8>

A8

R3

M_B_A<9>

A9

L7

M_B_A<10>

A10/AP

R7

M_B_A<11>

A11

N7

M_B_A<12>

A12/BC

T3

M_B_A<13>

A13

T7

M_B_A<14>

A14

M7

M_B_A<15>

A15

M2

M_B_BS0 M_B_BS1 M_B_BS2

M_B_ODT0

DDR3_DRAMRST# DDR3_DRAMRST#

M_B_ZQ2

R485 240/F_4

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL SDRAM DDR3

RAM

_DDR3L

M_B_DQS_DP<6>[3] M_B_DQS_DP<5>[3]

M_B_DQS_DN<6>[3] M_B_DQS_DN<5>[3]

C708 1U/6.3V/X5R_4

C519 1U/6.3V/X5R_4

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1

M_B_DIM0_CK_DDR0_DP M_B_DIM0_CK_DDR0_DN M_B_DIM0_CKE0

M_B_DIM0_CS0_N M_B_RAS_N M_B_CAS_N M_B_WE_N

1 2

M_B_DQ<23> [3] M_B_DQ<20> [3] M_B_DQ<18> [3] M_B_DQ<17> [3] M_B_DQ<22> [3] M_B_DQ<16> [3] M_B_DQ<19> [3] M_B_DQ<21> [3]

M_B_DQ<13> [3] M_B_DQ<10> [3]

M_B_DQ<8> [3]

M_B_DQ<14> [3]

M_B_DQ<9> [3] M_B_DQ<15> [3] M_B_DQ<12> [3] M_B_DQ<11> [3]

PP1350 PP1350 PP1350 PP1350

C658

1U/6.3V/X5R_4

C517

1U/6.3V/X5R_4

BYTE6_48-55 BYTE7_56-63BYTE2_16-23 BYTE3_24-31

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

A9

VSS#A9

B3

VSS#B3

E1

VSS#E1

G8

VSS#G8

J2

VSS#J2

J8

VSS#J8

M1

VSS#M1

M9

VSS#M9

P1

VSS#P1

P9

VSS#P9

T1

VSS#T1

T9

VSS#T9

B1

VSSQ#B1

B9

VSSQ#B9

D1

VSSQ#D1

D8

VSSQ#D8

E2

VSSQ#E2

E8

VSSQ#E8

F9

VSSQ#F9

G1

VSSQ#G1

G9

VSSQ#G9

3

M_B_DQ<53> [3] M_B_DQ<49> [3] M_B_DQ<50> [3] M_B_DQ<55> [3] M_B_DQ<48> [3] M_B_DQ<51> [3] M_B_DQ<54> [3] M_B_DQ<52> [3]

M_B_DQ<45> [3] M_B_DQ<42> [3] M_B_DQ<40> [3] M_B_DQ<46> [3] M_B_DQ<41> [3] M_B_DQ<47> [3] M_B_DQ<44> [3] M_B_DQ<43> [3]

M_B_DQS_DP<0>[3] M_B_DQS_DP<3>[3]

M_B_DQS_DN<0>[3] M_B_DQS_DN<3>[3]

2

BYTE0_0-7BY

U33

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1

M_B_DIM0_CK_DDR0_DP M_B_DIM0_CK_DDR0_DN M_B_DIM0_CKE0

M_B_DIM0_CS0_N M_B_RAS_N M_B_CAS_N M_B_WE_N

DDR3_DRAMRST#

1 2

M8

VREFCA

H1

VREFDQ

N3

M_B_A<0>

A0

P7

M_B_A<1>

A1

P3

M_B_A<2>

A2

N2

M_B_A<3>

A3

P8

M_B_A<4>

A4

P2

M_B_A<5>

A5

R8

M_B_A<6>

A6

R2

M_B_A<7>

A7

T8

M_B_A<8>

A8

R3

M_B_A<9>

A9

L7

M_B_A<10>

A10/AP

R7

M_B_A<11>

A11

N7

M_B_A<12>

A12/BC

T3

M_B_A<13>

A13

T7

M_B_A<14>

A14

M7

M_B_A<15>

A15

M2

M_B_BS0 M_B_BS1 M_B_BS2

M_B_ODT0 M_B_ODT0

M_B_ZQ3

R484 240/F_4

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL SDRAM DDR3

RAM

_DDR3L

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSSQ#B1

VSSQ#B9 VSSQ#D1 VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M_B_DQ<1> [3] M_B_DQ<3> [3] M_B_DQ<2> [3] M_B_DQ<7> [3] M_B_DQ<4> [3] M_B_DQ<5> [3] M_B_DQ<6> [3] M_B_DQ<0> [3]

M_B_DQ<30> [3] M_B_DQ<24> [3] M_B_DQ<26> [3] M_B_DQ<29> [3] M_B_DQ<31> [3] M_B_DQ<28> [3] M_B_DQ<27> [3] M_B_DQ<25> [3]

M_B_DQS_DP<4>[3] M_B_DQS_DP<7>[3]

M_B_DQS_DN<4>[3] M_B_DQS_DN<7>[3]

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1

M_B_A<0> M_B_A<1> M_B_A<2> M_B_A<3> M_B_A<4> M_B_A<5> M_B_A<6> M_B_A<7> M_B_A<8>

M_B_A<9> M_B_A<10> M_B_A<11> M_B_A<12> M_B_A<13> M_B_A<14> M_B_A<15>

M_B_BS0 M_B_BS1 M_B_BS2

M_B_DIM0_CK_DDR0_DP M_B_DIM0_CK_DDR0_DN

M_B_DIM0_CKE0

M_B_DIM0_CS0_N M_B_RAS_N M_B_CAS_N M_B_WE_N

M_B_ZQ4

R486 240/F_4

1 2

M_B_RAS_N M_B_CAS_N M_B_WE_N M_B_BS0 M_B_BS1 M_B_BS2 M_B_DIM0_CKE0 M_B_DIM0_CS0_N

M_B_A<0> M_B_A<1> M_B_A<2> M_B_A<3> M_B_A<4> M_B_A<5> M_B_A<6> M_B_A<7> M_B_A<8> M_B_A<9> M_B_A<10> M_B_A<11> M_B_A<12> M_B_A<13> M_B_A<14> M_B_A<15>

U32

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2

T8

R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

T2

L8

J1

L1

J9

L9

RAM

R467 34.8/F_4 R770 34.8/F_4 R448 34.8/F_4 R792 34.8/F_4 R795 34.8/F_4 R449 34.8/F_4 R469 34.8/F_4 R419 34.8/F_4 R787 34.8/F_4C709 R793 34.8/F_4 R465 34.8/F_4 R470 34.8/F_4 R1000 34.8/F_4 R437 34.8/F_4 R1002 34.8/F_4 R471 34.8/F_4 R450 34.8/F_4 R814 34.8/F_4 R775 34.8/F_4 R466 34.8/F_4 R464 34.8/F_4 R1003 34.8/F_4 R468 34.8/F_4 R1001 34.8/F_4

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

100-BALL SDRAM DDR3

_DDR3L

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9 VSSQ#D1 VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

BYTE4_32-39BYTE5_40-47

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M_B_DIM0_CK_DDR0_DP M_B_DIM0_CK_DDR0_DN

1

M_B_ODT0

M_B_DQ<36> [3] M_B_DQ<35> [3] M_B_DQ<32> [3] M_B_DQ<39> [3] M_B_DQ<37> [3] M_B_DQ<34> [3] M_B_DQ<33> [3] M_B_DQ<38> [3]

M_B_DQ<58> [3] M_B_DQ<61> [3] M_B_DQ<62> [3] M_B_DQ<60> [3] M_B_DQ<59> [3] M_B_DQ<56> [3] M_B_DQ<63> [3] M_B_DQ<57> [3]

R409 30/F_4

R756 26.1/F_4 R815 26.1/F_4

15

PP1350+DDR_VTT_RUN

+DDR_VTT_RUN

M1 solution

C513

C511

1U/6.3V/X5R_4

C744

C745

1U/6.3V/X5R_4

+DDR_VTT_RUN

C407

A A

1U/6.3V/X5R_4

C694 1U/6.3V/X5R_4

C697 1U/6.3V/X5R_4

5

C698 1U/6.3V/X5R_4

C510 1U/6.3V/X5R_4

C682 1U/6.3V/X5R_4

C382 1U/6.3V/X5R_4

C515 1U/6.3V/X5R_4

C530 1U/6.3V/X5R_4

C420 1U/6.3V/X5R_4

C512 1U/6.3V/X5R_4

C747 1U/6.3V/X5R_4

C310 10u/6.3V/X5R_6

+SMDDR_VREF_DIMM

+SMDDR_VREF_DQ1

C516 1U/6.3V/X5R_4

C678 1U/6.3V/X5R_4

12

C514 1U/6.3V/X5R_4

C743 1U/6.3V/X5R_4

C441

0.047u/25V/X7R_4

12

C402

0.047u/25V/X7R_4

C518 1U/6.3V/X5R_4

C717 1U/6.3V/X5R_4

12

C409

0.047u/25V/X7R_4

12

C469

0.047u/25V/X7R_4

Place these Caps near Memory Down CA & DQ pin

12

C426

0.047u/25V/X7R_4

12

C432

0.047u/25V/X7R_4

4

12

C739

0.047u/25V/X7R_4

C740

0.047u/25V/X7R_4

12

C446

0.047u/25V/X7R_4

PP1350_VREF

+VREFDQ_SB_M3

3

R338 *0/J _6S

solution

M3

2

R6527 *0/J_6

R474 5/F_6

C349

0.022u/16V/X7R_4

1 2

R336

24.9/F_4

PP1350

R348

1.8K/F_4

R473

1.8K/F_4

+VREF_CA_CPU[3,14] +VREFDQ_SB_M3[3] PP1350[4,5,14,30] PP3300_DX[8,16, 18,20,21,22,23,25,26,29] +DDR_VTT_RUN[14,30 ] +SMDDR_VREF_DIMM[14]

PP1350_VREF[14,30]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

DDR3L MEMORY DOWNx16 B

Date:

Friday, August 16, 2013

1

Vref_DQ

+SMDDR_VREF_DQ1

C376 470p/50V/X7R_4

+VREF_CA_CPU +VREFDQ_SB_M3 PP1350 PP3300_DX +DDR_VTT_RUN +SMDDR_VREF_DIMM

PP1350_VREF

Sheet :

of

15 42

Rev.Size

1A

1

2

3

4

5

6

7

8

16

PP3300_DX

7

WP

3

A2

2

A1

1

A0

R782 0/J_4 R781 0/J_4

LVDS

R6509 *1K/J_4

R246 *1K/J_4

R6488

100K/J_ 4

CCD

DMIC

Close to Pin8

LCD_VI N

C246

4.7u/25V/X 5R_8

Rc

R6104.7K/J_4 R6154.7K/J_4

Rd

C5640 22P/50V /NPO_4

USBP2+[9] USBP2-[9 ]

DMIC_CL K_L[23] DMIC_DA T_L[23]

C5649 *0.1U/10V/X7 R_4

C247 1000p/5 0V/X7R_4

I2C_SC L_LCD I2C_SD A_LCD

EDP_TX N0_R EDP_TX P0_R

EDP_TX N1[2] EDP_TX P1[2]

EDP_TX N2[2] EDP_TX P2[2]

EDP_TX N3[2] EDP_TX P3[2]

R6482 0/J_4 R6483 0/J_4 R735 0/J_4 R736 0/J_4

R737 0/J_4 R738 0/J_4

R6479 0/J_4 R6480 0/J_4

PP3300 _DX

EC_BL_ PWM_CONN

DLW21 HN900SQ2L_C /330mA/90ohm

C222

PP3300 _DX

Re

R6524 *100K/F _4

C647 *0.1U/10V/X7R_ 4 C648 *0.1U/10V/X7R_ 4

C649 *0.1U/10V/X7R_ 4 C651 *0.1U/10V/X7R_ 4

C652 *0.1U/10V/X7R_ 4 C654 *0.1U/10V/X7R_ 4

C659 *0.1U/10V/X7R_ 4 C660 *0.1U/10V/X7R_ 4

BLON_CO N

L36

443

1

2

C207

150p/50V/NPO_4

150p/50 V/NPO_4

EDP:Rb LVDS:Ra

EDP_HPD[2,1 6]

3

USBP2+_R

2

USBP2-_R

R180 600,0.3A R186 600,0.3A

VLED

C5641 1000p/5 0V/X7R_4

Ra

R6434 0/J_6

R6435 *0/J_6

Rb

DMIC_CL K DMIC_DA T

R233 *0/J_6S R234 *0/J_6S

LVDS_Y0 _N_R LVDS_Y0 _P_R LVDS_Y1 _N_R LVDS_Y1 _P_R

LVDS_Y2 _N_R LVDS_Y2 _P_R

EDP_TX N3_C EDP_TX P3_C

LVDS_C LK_N_R LVDS_C LK_P_R

LCDVCC

PP3300 _DX

LVDS_SPI_PWR

I2C_SC L_LCD I2C_SD A_LCD

C273 10p/50V /C0G_4

LCD_VIN

CN27

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

LVDS_C ONN_30P

50406-0 3071-001-30 p-r

C271 1000p/5 0V/X7R_4

LVDS_C LK_N_R LVDS_C LK_P_R

Close to CN27

32

35

34

33

31

DFWF3 0MR012

C357

4.7u/6.3V/X 5R_6

C5655 *10p/50V /C0G_4

C5654 *10p/50V /C0G_4

U8

8

VCC

5

R25 *0/J_4

A A

Mode Configure Table (Power On Latch)

MODE_CFG1(PIN31)

EDP_AUX/TX0

LVDS_SCL/SDA/Y0

2132

EDP_TX1/TX2

LVDS_Y1/Y2

2132

EDP_TX3

B B

DP_DVCC33

C20

0.1U/10V/X 5R_4

C C

DP_AVCC33

C12

0.1U/10V/X 5R_4

LVDS_CLK

2132

L35 TI1 60808U600

C301 10u/6.3V/X 5R_6

L31 HCB 1608KF_1.5 A_6

C300 10u/6.3V/X 5R_6

For EDP Only: stuff Resistor

For LVDS only stuff Cap

PP3300_DX

CONN

EDP_AUX N[2] EDP_AUX P[2]

Defasult ROM mode

SMB_PCH_ CLK_LVDS[8]

SMB_PCH_ DAT_LVDS[8]

EC_SMB1 _CLK[26]

EC_SMB1 _DATA[2 6]

PP3300_DX

R6478 *1M/F_4

EDP_TX P0[2] EDP_TX N0[2]

R6477 *1M/F _4

for bebug

R6499 0/J_4 R6500 0/J_4

R6522 *0/J_4 R6523 *0/J_4

EDP_HPD PD 100K at CPU side

R733 *0/J_4 R734 *0/J_4

R739 *0/J_4 R740 *0/J_4

EDP_HPD[2,1 6]

EDP_TX P0_R EDP_TX N0_R

use LDO mode at pin12 SWR_LX and DP_VCCK_V12 routing IN3

0

1

EDP_AUX N_R EDP_AUX P_R

MODE_CFG0(PIN30)

RO

M ONLY MODE

PP3300_DX

R83

4.7K/J_4

R84 *4.7K/J_4

C645 0.1U/10V/X7R_ 4 C646 0.1U/10V/X7R_ 4 C13 0.1U/10V /X5R_4

C637 0.1U/10V/X7R_ 4 C644 0.1U/10V/X7R_ 4 C14 0.1U/10V /X5R_4

R229 12K /F_4

C302 10u/6.3V/X 5R_6

close U1

10

EP MODEX

EEPROM MODE

PP3300_DX

R81 *4.7K/J_4

R82

4.7K/J_4

DAUXN DAUXP DP_AVC C33

DRX0P DRX0N DP_VCC K_V12 DP_REX T

R170*0/J_8S

EC_BL_ PWM[26]

PCH_BL_ PWM[2,26]

DP_UTIL[2]

DP_VCC K_V12 SWR_L X

C641

0.1U/10V/X 7R_4

1 2 3 4 5 6 7 8

DP_HPD_ R

U1

AUX_CH_N AUX_CH_P DP_V33 DP_GND LANE0_P LANE0_N DP_V12 DP_REXT

R778 1K /J_4

C21

0.1U/10V/X 5R_4

Backlight Control

DP_MODE _CFG0 DP_MODE _CFG1

32

33

DP_HPD

EPAD_GND

RTD2132R

CIICSCL9CIICSDA10SWR_VCCK/LDO_VCCK11SWR_VDD/LDO_VDD13PWMOUT14PANEL_VCC15PWM_IN

DP_DVC C33

C348 22u/6.3V/X 5R_8

R6494*0/J_4

R6495*0/J_4S

R6496*0/J_4

30

29

28

MIICSCL

MIICSDA

MODE_CFG131MODE_CFG0

SWR_LX/LDO_FB

12

2132_P WMIN_R

R6503 100K/J_ 4

I2C_SD A_LCD I2C_SC L_LCD

RTD2132S => R25, R20 RTD2132R => R28, R23

I2C_3V 3_SCL_LCD I2C_3V 3_SDA_LCD

DP_VCC K_V12

26

25

27

VCCK

TXO0-

TXO0+

24

TXO1-

23

TXO1+

22

TXO2-

21

TXO2+

20

TXOC-

19

TXOC+

18

PVCC

17

BL_EN

16

2132_P WMIN 2132_D ISP_ON

2132_D PST_PWM

dify in PV stage (7/15)

Mo

R20 *0/J_4

R28 *0/J_4 R23 *0/J_4

C15 0.1U/10V/X 5R_4

R6506*0/J_4

SCA_SD A_R SCA_SC L_R

For LVDS stuff Rc=4.7k. Rd=4.7k Re un-stuff

For EDp reserve Rc=100k,Re=100k ,Rd no stuff

EDP_AUX N_R

EDP_AUX P_R

LVDS_Y1 _N LVDS_Y1 _P LVDS_Y2 _N LVDS_Y2 _P

DP_DVC C33 2132_L VDS_BLON

R65730/J_4

R65740/J_4

PP3300 _DX

C5642 *0.1U/10V /X7R_4 C5643 *0.1U/10V /X7R_4

LVDS_Y0 _N LVDS_Y0 _P

LVDS_C LK_N LVDS_C LK_P

C640 0.1U/10V/X7R_4

2132_L VDS_BLON

2132_D PST_PWM

only for EDP reserve

SDA

6

SCL

4

GND

*SGT-M24C 64-WMN6TP

R65051K/F_4

EC_BL_ EN_CONN[34]

EC_BL_ EN_CONN BLON_CO N

R6489 0/J_4 R6563 1 K/J_4

close U1

D D

1

2

EC_BL_ EN[26]

PCH_BL_ EN[2,26]

2132_L VDS_BLON

R6438 *0/J_4

R6498 *0/J_4

3

R6439

100K/J_ 4

R6493 100K/F_ 4 C5639 22P/5 0V/NPO_4

D48

RB500V -40

4

LVDS Power

EC_EDP _VDD_EN[26 ]

PCH_EDP _VDD_EN[2,26]

5

2132_D ISP_ON

80 mile trace

R6508 *0/J_4 R6423 0/J_4

R6497 *0/J_4

R6507 *0/J_8

C22 1U/6.3V/X5 R_4

R6425

100K/J_ 4

PP3300 _DX

6

U6

5

IN

4

IN

3

ON/OFF

IC(5P) G5 243AT11U

LCDVCC

1

OUT

2

GND

L54

TI1608 08U600

C5617 10u/6.3 V/X5R_6 C5618 0.01U/2 5V/X7R_4 C5619 0.1U/10 V/X7R_4

7

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

D

LVDS/CAMERA/DMIC/RTD2132

Date:

Date: Sheet : of

Friday, August 16 , 2013

8

Sheet : of

16 42

Rev.Size

1A

5

4

3

2

1

17

D D

PIN7 OD PIN14 OD

Debug Port

PCH_SPI_CS0#_R[8] PCH_SPI_SI_R [8]

PCH_SPI_SO_R[8]

SPI_HOLD#_BIOS[8]

PCH_UART_TXD[26]

SD_CDZ[22] EC_JTAG_TCK[26] PWR_BTN_L [13,25,26] EC_JTAG_TMS[26] EC_JTAG_TDI [26]

EC_JTAG_TDO[26]

EC_UARTTX[26]

HDMI_MB_HP[18]

C C

B B

H_PROCHOT#[4,26,32]

PIN19 OD PIN22 OD PIN28 OD PIN30 OD PIN37 OD PIN38 OD

SPI_CS#_BIOS SPI_DI_BIOS SPI_DO_BIOS SPI_HOLD#_BIOS

PCH_UART_TXD

R568 *0/J_4S

EC_JTAG_TCK EC_JTAG_TMS EC_JTAG_TDI

EC_JTAG_TDO EC_JTAG_RTCK EC_JTAG_TCK

PP3300_EC

R6315*0/J_4S

R639310/J_4 R639210/J_4

PIN39 OD PIN41 OD PIN43 OD PIN44 OD PIN45 OD PIN46 OD PIN47 OD PIN48 OD

GPIO_SD_DECT

EC_UART_TXD

GPO_HPD GPIO_SPI_WP GPIO_PROC_HOT#

PIN49 OD PIN50 OD

CN4

112 334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950

*G-debug_CONN_50P

2

SPI_CLK_BIOS

4 6 8 10 12 14

GPIO_EC_RST#

16

PCH_UART_RXD

18 20 22

GPIO_PWR_BTN#

24 26 28 30

GPIO_REC_MODE_L

32

EC_UART_RXD

34 36 38 40 42 44 46 48 50

4/24 check debug port type

R6311 10/J_4

R6312 10/J_4

R582 *0/J_4S R575 10/J_4

R6316 *0/J_4S

PP3300_EC

+3V_PCH_ME[8] PP3300_EC[26,28,30,31]

+3V_PCH_ME

PP3300_EC

PCH_SPI_CLK_R [8]

EC_RST# [25,26]

PCH_UART_RXD [26]

SYS_RESET# [7,13]

RECOVERY_L [26]

EC_UARTRX [26]

GPIO_SPI_WP [8] LID_OPEN [22,26]

+3V_PCH_ME PP3300_EC

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Debug

Date:

Friday, August 16, 2013

5

4

3

2

Friday, August 16, 2013

Sheet :

1

of

17 42

Rev.Size

1A

5

4

3

2

1

18

Layout Notes: Place decoupling CAPs close to Connector

D D

C C

PP3300_DX PP3300_HDMI

INT_HDMITX2P[2]

INT_HDMITX2N[2]

INT_HDMITX1P[2]

INT_HDMITX1N[2]

INT_HDMITX0P[2]

INT_HDMITX0N[2]

INT_HDMICLK+[2]

INT_HDMICLK-[2]

R6413 *0/J_6S

C524 0.1U/10V/X7R_4

C525 0.1U/10V/X7R_4

C526 0.1U/10V/X7R_4

C527 0.1U/10V/X7R_4

C522 0.1U/10V/X7R_4

C523 0.1U/10V/X7R_4

C528 0.1U/10V/X7R_4

C529 0.1U/10V/X7R_4

PP3300_HDMI

R37 680/J_4

R44 680/J_4

R43 680/J_4

12

2

R62 *100K/F_4

R42 680/J_4

R41 680/J_4

12

Q8 2N7002K

R39 680/J_4

12

R38 680/J_4

3

1

HDMI DDC (HDM)

HDMI_DDCCLK_SW[2]

B B

HDMI_DDCDATA_SW[2]

R69 *0/J_4S

R513 *0/J_4S

HDMI_DDCCLK_COM

HDMI_DDCDATA_COM

PP5000

EMI (EMC)

R478 *100/F_4

R479 *100/F_4

R477 *100/F_4

R480 *100/F_4

R40 680/J_4

12

PP3300_HDMI

R6401

2.2K/J_4

2

1

PP3300_HDMI

R6402

2.2K/J_4

2

1

F1 FUSE1A6V_POLY

12

PP3300_HDMI

R6403 *0/J_4S

Q10 2N7002

3

R6404 *0/J_4S

Q51 2N7002

3

C521 *220p/50V/X7R_4

PP5000

D9 RB500V-40

R64

2.2K/J_4

D34 RB500V-40

R501

2.2K/J_4

D30 *14V/100p_4

HDMI_5V

HDMI connector (HDM) DFHS19FR079

new footprint not ready

INT_HDMITX2P_C INT_HDMITX2N_C

INT_HDMITX1P_C INT_HDMITX1N_C

INT_HDMITX0P_C INT_HDMITX0N_C

INT_HDMICLK+_C INT_HDMICLK-_C

HDMI_DDCCLK_MB HDMI_DDCDATA_MB

Follow CRB 1.0 change to

2.2K

Follow CRB 1.0 change to

2.2K

CN7

20

SHELL1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17

C27 *1000p/50V/X7R_4

C28 *1000p/50V/X7R_4

18 19

D2+

SHELL3 D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0CK+ CK Shield CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET

SHELL4

SHELL2

HDMI_CONN_19P

22

23 21

R6406

HDMI-detect (HDM)

INT_HDMI_HPD[2]

A A

5

4

1M/J_4

R6400 *0/J_4S

2

Q7 2N7002K

3

1

HDMI_MB_HP [17]

HDMI_MB_HP HP_DET_CN

12

R53 20K/F_4

3

12

RV5 *5V/0.2p_4

R45 *0/J_4S

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

HDMI

Date:

Friday, August 16, 2013

2

Friday, August 16, 2013

Sheet :

1

of

18 42

Rev.Size

1A

1

2

3

4

5

6

7

8

19

A A

MINI-CARD WLAN(MPC)

PP3300_WLAN_EN[10,26,29]

PCIE_TX3+_WLAN[9] PCIE_TX3-_WLAN[9]

PCIE_RX3+_WLAN[9] PCIE_RX3-_WLAN[9]

CLK_PCI_DEBUG[9]

CLK_PCIE_WLANP[9] CLK_PCIE_WLANN[9]

B B

WLAN_WAKE_L[10]

C C

TP101 TP100 TP99

PCIE_CLKREQ_WLAN#_Q

+WL_VDD

+3.3V: 1000mA +3.3Vaux:330mA +1.5V:500mA

R786 *0/J_4S

CLK_PCI_LPC_R CL_CLK1_WLAN

+WL_VDD

EC19 *10p/50V/COH_4

R313 4.7K/J_4

51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17

15 13 11

9 7 5 3 1

MINIPCI_CONN_52P

PCIE_CLKREQ_WLAN#_Q

H=5.2mm

CN18

Reserved Reserved Reserved Reserved GND +3.3Vaux +3.3Vaux GND GND PETp0 PETn0 GND GND PERp0 PERn0 GND UIM_C4 UIM_C8

GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE#

53

+WL_VDD

R317

4.7K/J_4

Q45 2N7002K

LED_WPAN# LED_WLAN#

LED_WWAN#

SMB_DATA

W_DISABLE#

UIM_RESET

UIM_DATA

UIM_PWR

GND54GND

3

+3.3V

GND

+1.5V

GND

USB_D+

USB_D-

GND

SMB_CLK

+1.5V

GND

+3.3Vaux

PERST#

GND

UIM_VPP

UIM_CLK

+1.5V

GND

+3.3V

2

52 50 48 46 44

WLAN#

42

WWAN#

40 38 36 34 32 30 28 26 24 22 20 18

16 14 12 10 8 6 4 2

PP3300_WLAN_EN

1

+WL_VDD +1.5V_MINI1_VDD

WLAN_CLK_SDATA WLAN_CLK_SCLK

+1.5V_MINI1_VDD +WL_VDD

W_DISABLE#

+1.5V_MINI1_VDD +WL_VDD

PCIE_CLKREQ_WLAN# [9]

TP98

+WL_VDD

R774 *4.7K/J_4

USBP3+ [9] USBP3- [9]

TP512 TP513

LPC_LAD0 [8,21,26] LPC_LAD1 [8,21,26] LPC_LAD2 [8,21,26] LPC_LAD3 [8,21,26]

LPC_LFRAME# [8,21,26]

R771 *0/J_4S R773 *0/J_4S

R777 *0/J_4

PLTRST# [7,13,21,22,26] WLAN_DISABLE_L [10]

WLAN_OFF_L [26]

PP3300_WLAN

PP1500_PCH_TS PP3300_WLAN

R749 *0/J_8S

500mA for +1.5V

C665

C675

0.1U/10V/X5R_4

10u/6.3V/X5R_6

+1.5V_MINI1_VDD

C668

C680

*0.1u/10V/X5R_4

*1000p/50V/X7R_4

LAYOUT NOTE:

SE TO CONNECTOR

CLO

PP1500_PCH_TS [11,23,33]

PP3300_WLAN [29]

+WL_VDD

C683 *0.1u/10V/X5R_4

R323 *0/J_8S

C653 *10u/6.3V/X5R_6

C650 *0.1u/10V/X5R_4

PP1500_PCH_TS

+WL_VDD

EC17 *1000p/50V/X7R_4

Reserve for RF

+1.5V_MINI1_VDD

EC18 *1000p/50V/X7R_4

D D

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

WIFI / BT

Date:

Friday, August 16, 2013

1

2

3

4

5

6

Friday, August 16, 2013

7

Sheet :

8

of

19 42

Rev.Size

1A

5

4

3

2

1

CN28

NGFF

1

PRESERVE

3

GND

D D

SATA_RXP0_SSD[8] SATA_RXN0_SSD[8]

SATA_TXN0_SSD[8] SATA_TXP0_SSD[8]

C C

C1005 0.01u/16V/X7R_4 C1003 0.01u/16V/X7R_4

C1006 0.01u/16V/X7R_4 C1004 0.01u/16V/X7R_4

SATA_RXP0_SSD_C SATA_RXN0_SSD_C

SATA_TXN0_SSD_C SATA_TXP0_SSD_C

5

N/A

7

N/A

9

N/A

11

N/A

13

Key

15

Key

17

Key

19

Key

21

WWAN/SSDIND_N

23

N/A

25

N/A

27

GND

29

N/A

31

N/A

33

GND

35

N/A

37

N/A

39

GND

41

SATA RX+

43

SATA RX-

45

GND

47

SATA TX-

49

SATA TX+

51

GND

53

REFCLKN

55

REFCLKP

57

GND

59

KEY

61

KEY

63

KEY

65

KEY

67

N/A

69

IFDET

71

GND

73

GND

75

GND

SSD_NGFF_CONN_75P

mipci-apci0020-p003h-75p-km

3.3Vaux

DAS#

Device sleep

MFG1 MFG2

SUSCLK

3.3Vaux

2

R6472 *0/J_6S

4 6

N/A

8

N/A

10 12

Key

14

Key

16

Key

18

Key

20

N/A

22

N/A

24

N/A

26

N/A

28

N/A

30

N/A

32

N/A

34

N/A

36

N/A

38 40

N/A

42

N/A

44

N/A

46

N/A

48

N/A

50

N/A

52

N/A

54

N/A

56 58 60

KEY

62

KEY

64

KEY

66

KEY

68 70 72 74

TP517

R6471 0/J_4

check power consumption

R6473 *0/J_8S

EC24

Reserve for RF

10u/6.3V/X5R_6

PP3300_DX

Added in MV stage (8/13)

EC21

EC20

470p/50V/X7R_4

10u/6.3V/X5R_6

R6575 10K/J_4

PP3300_DX

DEVSLP0 [10]

PP3300_DX

Reserve for RF

Power +3V for AUO TS

R6454 *0/J_6

PP5000

R817 *0/J_6

PP3300_DSW

R6557 *0/J_6

PP3300_PCH_SUS

double check

Touch screen connector

C5614 *1u/10V/X5R_4

TP_SHDN_L[25,26]

B B

R6516 *0/J_4

+VCC_TS

R6453 *100K/F_4

R6452 *0/J_6 U5

5

IN

4

IN

3

ON/OFF

*IC(5P) G5243AT11U

Close to CN22

1

OUT

2

GND

1

10

21

38

53

55 56 58

68

69

+VCC_TS

C5613 *1u/10V/X5R_4

Type

PRESENCE

DAS#

WWAN/SSDIND_N This pin connect to Ground

Device Sleep Signal

REFCLKN

REFCLKP no connect on SSD

MFG1

MFG2

SUSCLK

IFDET This pin connect to Ground

Description

This pin is grounded on the SSD. May be used by host to determine if slot is empty or populated

Device Activity Signal

If system didn't support DEVSLP, set DEVSLP Sleep Signal pin power high and keep (from power on), device will ignore. If system support DEVSLP, set DEVSLP Sleep Signal pin power low (from power on) device, device will support DEVSLP function. Device Sleep Signal H: SSD enter sleep model. Device Sleep Signal L: SSD exit sleep model.

no connect on SSD

Manufacturing pin. Use determined by vendor. Must be a noconnect on the host board

no connect on SSD

20

Q67 *2N7002DW

I2C1_SCL_GPIO7[10,22]

I2C1_SDA_GPIO6[10,22]

A A

5

4 3

1

R6517 *0/J_4

5

2

PP3300_PCH

6

USBP5-[9]

USBP5+[9]

Touch Panel interrupt

check this power status

TOUCH_INT_L[10]

TOUCH_INT_L_DX[2]

TOUCH_RST_L[26]

4

R6418

R6419

*4.7K/J_4

I2C1_SCL_GPIO7_R

I2C1_SDA_GPIO6_R

R6469 *0/J_4

L42 *MCM2012B900GBE

2

R6470 *0/J_4

1 43

D41 *TPL@RB500V-40

D40 *TPL@RB500V-40

R6551 *0/J_4

R6552 *0/J_4

USBP5-_C USBP5+_C

+VCC_TS +VCC_TS

2

3

Q28 *TPL@2N7002K

3

1

SOC3V3_RSTOUT_L

R243 *TPL@10K/J_4

TP_INT

C5615 *0.1U/10V/X7R_4

CN22

1 2 3 4 5 6

*Touch screen_CONN_6P

PP5000 [11,18,22,23,24,25,28,30,31,32,34] PP3300_PCH_SUS [7,8,9,10,11,13,25,29] PP3300_DX [8,16,18,21,22,23,25,26,29]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

SSD/TS /ALS

Date:

Friday, August 16, 2013

2

Friday, August 16, 2013

Sheet :

1

of

20 42

Rev.Size

1A

1

2

3

4

21

A A

B B

TPM (TPM)

TPM_VDD

0411 FAE : install R80 value is 4K7, and PIN7 wo an internal PD

TPM_VDD

12

R54 *20K/F_4

R266 *0/J_4S

R80 *4.7K/J_4

TPM_GPIO

TPM_PP

4 x100nF (place close to device VDD/GND pins)

TPM_VDD

C275

C277

0.1U/10V/X5R_4

U28

6

GPIO

2

NC2

7

PP

13

NC13

14

NC14

8

NC8

12

TPM SLB9655

NC12

3

NC3

1

NC1

GND[1]4GND[2]11GND[3]18GND[4]

SLB9655

25

VDD[4] VDD[3] VDD[2] VDD[1]

LCLK

LFRAME#

LAD3 LAD2 LAD1 LAD0

NC28

LRESET#[1] LRESET#[2]

SERIRQ

NC15

10 5 24 19

21 22

17 20 23 26

28 16

9 27

SERIRQ_R

15

C276

0.1U/10V/X5R_4

R6562 *0/J_4S R6558 *0/J_4S

R6559 *0/J_4S R6560 *0/J_4S R6561 *0/J_4S

TPM_RST_R

R295 *0/J_4S

R453 *0/J_4S

0411 FAE : a 0ohm between pin9 to LRESET signals

PP3300_DX

R411 *0/J_6S

C278

0.1U/10V/X5R_4

near pin 21 as possible

C487 *10p/50V/C0G_4

PCLK_TPM [9]

LPC_LFRAME# [8,19,26]

LPC_LAD3 [8,19,26] LPC_LAD2 [8,19,26] LPC_LAD1 [8,19,26] LPC_LAD0 [8,19,26]

PLTRST# [7,13,19,22,26]

IRQ_SERIRQ [10,26]

LED(UIF)

C C

PP3300_DSW

PWR LED

LED1

2 1

3P WHITE LED

C5630 *TVM0G5R5M261R_4

R1 360/J_4

PWR_LED#

PWR_LED# [26]

PP3300_DSW [5,7,8,10,11,13,20,24,25,26,28,29,33] PP3300_DX [8,16,18,20,22,23,25,26,29]

D D

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

TPM SLB9655 / LED

Date:

Friday, August 16, 2013

1

2

3

Friday, August 16, 2013

4

Sheet :

of

21 42

Rev.Size

1A

A

B

C

D

E

EC30 *1U/6.3V/X5R_4

EC31 *470p/50V/X7R_4

EC29 *47p/50V/NPO_4

PP5000PP3300_DX

EC27 *1U/6.3V/X5R_4

EC28 *470p/50V/X7R_4

22

Reserve for RFReserve for RF

4 4

Thermal CPU Sensor

U20

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

G781P8

ADDR=7H_0x4C

PP3300_DX

EC_SMB2_CLK[26] EC_SMB2_DATA[26]

FAN_ALERT#[26]

R6432 *0/J_4S

R225 *10K/J_4

Place oo PCB BOT Local Temp.

Thermal location sensor

1 2

+3V_THR

C498

0.1U/10V/X7R_4

3 3

R476

36.5K/F_4

1

5

SET

GND

2

R6530 150/F_4

3

SYS_SHDN-1#

VCC

OT

U5009

HYST

G708T1U

4

PP3300_DX

1

C200 0.1U/10V/X5R_4

VCC

2

DXP

3

DXN GND

PP3300_DX

5

R6531 *470K/J_4

R6532 *0/J_4S

C16 2200p/50V/X7R_4

Over Temperature Protecton

DEGREE

R476

70 36.5K

THM_DXP

THM_DXN

2

Q1 MMBT3904-7-F

1 3

Place oo PCB TOP Remote Temp.

SYS_SHDN# [10,26,28,33]

USBP7-[9]

USBP7+[9]

3G@MCM2012B900GBE/400mA/90ohm

USBP4+[9]

USBP4-[9]

USBP6+[9]

USBP6-[9]

L56

1

2

1

2

3

443

R99 *0/J_4S

R100 *0/J_4S

R101 *0/J_4S

R102 *0/J_4S

USBP7-_R USBP7+_R

USBP4+_R USBP4-_R

USBP6+_R USBP6-_R

PP5000PP3300_DX

CN2

26 25 24 23 22 21

SD_CDZ[17]

SIM_DET[2]

LTE_WAKE_L[10]

USB2_OC_L[26]

USB2_PWR_EN[26]

PLTRST#[7,13,19,21,26]

LTE_DISABLE_L[10]

SD_CDZ SIM_DET LTE_WAKE_L

USB2_OC_L USB2_PWR_EN

PLTRST# LTE_DISABLE_L

20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

USB_BTB_CONN_26P

USB 2.0

WWAN

3A

+5V x2 USBP7+ USBP7-

2A

USB_OC3# USBON# GND x 2 +3V x 3 USBP0+ USBP0RF_KILL# PLTRST# GND x 4 +3V x 1

CR

USBP6+ USBP6-

1A

GND x 1

PP3300_DXPP3300_RTC

2 2

ght sensor/Lid

Li

I2C1_SDA_GPIO6[10,20]

I2C1_SCL_GPIO7[10,20]

ALS_INT_L[2] LID_OPEN[17,26]

R265 *0/J_4S R283 *0/J_4S R226 *0/J_4S

INT PU at CPU side

SEN_SDATA SEN_SCLK ALS_INT_R

C5635 0.1U/10V/X5R_4

CN31 check footprint /pin define

1 1

A

B

C

C359 0.1U/10V/X5R_4

C5634 1u/10V/X5R_4

CN31

8 7 6 5 4 3 2 1

ALS_CONN_8P

PP3300_DSW PP3300_RTC PP3300_DX PP5000

PP3300_PCH PP3300_PCH_SUS PP1050_PCH_SUS

D

PP3300_DSW [5,7,8,10,11,13,20,21,24,25,26,28,29,33] PP3300_RTC [8,11,23,25,26,27,28] PP3300_DX [8,16,18,20,21,23,25,26,29] PP5000 [11,18,20,23,24,25,28,30,31,32,34]

PP3300_PCH [2,7,8,9,10,11,13,20,25,29] PP3300_PCH_SUS [7,8,9,10,11,13,20,25,29] PP1050_PCH_SUS [8,11,13,31]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

USB2.0/WWAN/CR/ALS/Thermal IC

Date:

Friday, August 16, 2013

E

Sheet :

of

22 42

Rev.Size

1A

5

Codec(ADO)

D D

L30 HCB1608KF_1.5A_6

C245

0.1U/10V/X5R_4

Moat

check status

+5VA

L40 HCB1608KF_1.5A_6

C5652

C5653

10u/6.3V/X5R_4

0.1U/10V/X5R_4

Close to Codec

C C

Internal Speaker

1 2 345

6

SPK_CONN_4P

40mil for each signal

L_SPK+_1 L_SPK+ L_SPK-_1 L_SPKR_SPK-_1

C353

C355

*68p/50V/COG_4

C5647

10u/6.3V/X5R_4

L50 TI160808U600 L51 TI160808U600 L52 TI160808U600 L53 TI160808U600

C365

C354

*68p/50V/COG_4

+1.5VAPP1500_PCH_TS

Place next to pin 40

C214

C5646

0.1U/10V/X5R_4

10u/6.3V/X5R_4

ADOGND

C240

0.1U/10V/X5R_4

C229

C232

0.1U/10V/X5R_4 R125 10K/J_4

10u/6.3V/X5R_4

Analog

Digital

R_SPKR_SPK+R_SPK+_1

Close to Codec

L_SPK+ L_SPKR_SPKR_SPK+

PP3300_DX

DMIC_DAT_L[16] DMIC_CLK_L[16]

ADOGND

4

placed close to codec

C343 1u/10V/X5R_4

C371 10u/6.3V/X5R_4

PD#

Low to power done amplifier output

L55 HCB1608KF_1.5A_6

C364

0.1U/10V/X5R_4

Place next to pin 1

C38110u/6.3V/X5R_4

+AZA_VDD

35

36

CBN

CPVDD

37

CBP

38

AVSS2

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-L+

43

SPK-L-

44

SPK-R-

45

SPK-R+

46

PVDD2

47

PDB

48

SPDIFO/GPIO2

49

DGND

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DVSS4SDATA-OUT5BIT-CLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESETB11PCBEEP

+AZA_VDD

C366 10u/6.3V/X5R_4

C3281u/10V/X5R_4

34

33

CPVEE

32

31

HP-OUT-L

HP-OUT-R

MIC1-VREFO-L

ALC283

HPR HPL

MIC1-VREFO-L

MIC1-VREFO-R

MIC2-VREFO

CODEC_VREF

INT_AMIC-VREFO

27

28

29

30

VREF

MIC2-VREFO

MIC1-VREFO-R

C370 10u/6.3V/X5R_4

ACZ_SDIN

C335 *22p/50V/NPO_4

3

T3 T2

C329 2.2U/6.3V/X5R_4 C332 10u/6.3V/X5R_4

0.1U/10V/X5R_4

25

26

U17

AVSS1

AVDD1

24

LDO1-CAP

LINE2-L

23

LINE2-R

22

LINE1-L

21

LINE1-R

20

MIC1-R

19

MIC1-L

18

MIC2-R

17

MIC2-L

16

MONO-OUT

15

JDREF

14

Sense B

13

Sense A

12

C324 1u/10V/X5R_4

PCBEEP BEEP_1 BEEP_2

PCH_AZ_CODEC_RST#

R355 33/J_4

ADOGND ADOGND

L57 HCB1608KF_1.5A_6

C323

C325

10u/6.3V/X5R_4

ADOGND

LINE2-L LINE2-R LINE1-R LINE1-L MIC1_R1 MIC1_L1 SLEEVE RING2

CODEC_JDREF

T4 T5 T1 T8 T7

C380 10u/6.3V/X5R_4

R351 20K/F_4

R346 39.2K/F_4

Placement near Audio Codec

1.6Vrms

C314 100p/50V/NPO_4

PCH_AZ_CODEC_RST# [8] PCH_AZ_CODEC_SYNC [8]

PCH_AZ_CODEC_SDIN0 [8] PCH_AZ_CODEC_BITCLK [8]

PCH_AZ_CODEC_SDOUT [8]

+5VA

Place next to pin 26

Close to Codec

ADOGND

SLEEVE/RING2 PCB trace width at least 40 mil

ADOGND

HP_JD#SENSEA

double check

R327 47K/J_4CN16

R326

4.7K/J_4

R406 *0/J_6 R6457 0/J_6

C327

0.1U/10V/X5R_4

Place next to pin 9

Analog

Digital

SPKR [8,10]

PP1500_PCH_TS

C331 10u/6.3V/X5R_4

PP3300_DX

2

Grounding circuit

PIN1, PIN4, PIN3, PIN6 are ANALOG

ADOGND

Q37

1

4 3

2N7002DW

6 2

5

SLEEVE

RING2

Reserve in MV stage (8/13)

3

1

ADOGND

R6576

*100K/J_4

R6577 0/J_4

2

Q69

*2N7002

PP3300_DSW PP3300_RTC PP3300_DX PP5000

PP3300_RTC

double check

R837

100K/J_4

R6578 *100K/J_4

1

PP3300_DX

R838

3

*100K/J_4

2

Q39

C326

2N7002K

*1u/10V/X5R_4

1

MIC2-VREFO

PP3300_DSW [5,7,8,10,11,13 ,20,21,24,25,26,28,29,33] PP3300_RTC [8,11,22,25,26,27,28] PP3300_DX [8,16,18 ,20,21,22,25,26,29] PP5000 [11,18,20,22,24,25 ,28,30,31,32,34]

PCH_AZ_CODEC_RST#

23

Mute(ADO)Power (+5V)

R6566 10K/J_4

AVDD1

C1011

0.1U/10V/X7R_4

R6455 10K/J_4

C1010

0.047U/10V/X7R_4

PP3300_DX

PP5000

C1009 1U/6.3V/X5R_4

check PP5000 power status

PP5000 +5VA

B B

+5VA

C345

C346

10u/6.3V/X5R_6

0.1U/10V/X7R_4

ADOGND

1

2

12

U5008

Vout

G524A1T11U

C581 *AZ2015-01H

Vin OC EN4GND

L16 *HCB1608KF_1.5A_6

Moat

5 3

Vset=1.242V

R6572 100K/J_4

Modify in PV stage (7/15)

A A

5

4

+AZA_VDD

R138 *1K/J_4

PD# PCH_AZ_CODEC_RST#

R341 *10K/J_4

under U17

R6465 *0_8/S

C5624 1000p/50V/X7R_4 C5625 1000p/50V/X7R_4 C5626 1000p/50V/X7R_4 C5627 1000p/50V/X7R_4 C5628 1000p/50V/X7R_4

R6534 *0/J_8

ADOGND

D43BAS316

HEADPHONE/Mic Combo Jack

SLEEVE

SLEEVE/RING2 PCB trace width at least 40 mil

3

RING2

HPL HPR HPR-1 HPR_SYS

L1 *0/J_6S L5 *0/J_6S

R385 *1K/J_4

MIC2-VREFO

R357 56/F_4 R389 56/F_4

R380 *1K/J_4

R1007

2.2K/J_4

HPL-1_TIP_SENSE

R1005

2.2K/J_4

L20 0/J_6 L22 0/J_6

C249

C253

C3

2200p/50V/X7R_4

*100P/50V/NPO_4

D19 *14V/38V/100P_4

SLEEVE_R

D17 *14V/38V/100P_4

HPR_SYS

D18 *14V/38V/100P_4

HPL_SYS

D20 *14V/38V/100P_4

RING2_R

ESD 2'nd CY00G050B00

2

C2

*100P/50V/NPO_4

ADOGND

1 2 1 2 1 2 1 2

SLEEVE_R RING2_R HPL_SYS

HP_JD#

ADOGND

CN5

4 3 1

2 5 6

COMBOJACK_6P

P/N: DFTJ06FR611 PIN1 --> L PIN2 --> R PIN3 --> GND/MIC PIN4 --> MIC/GND PIN5 --> AGND PIN6 --> JD

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

Document Number

Custom

ALC283/HP/DMIC/SPK

Date:

Monday, August 19, 2013

Date:

Monday, August 19, 2013

Date:

Monday, August 19, 2013

PROJECT : A23

Sheet :

1

of

23 42

of

23 42

of

23 42

Rev.Size

1A

5

4

3

2

1

USB3.0

double confrim if active high

USB_PWR_EN need check

USB3_TXN0_C USB3_TXP0_C

USB1_PWR_EN[26]

L32

1

1 443

DLW21HN900SQ2L

R56 *0/J_4S

R57 *0/J_4S

R58 *0/J_4S

R59 *0/J_4S

2

3

D D

USBP0-[9]

USBP0+[9]

USB3_RXN0[9] USB3_RXP0[9]

C C

USB3_TXN0[9] USB3_TXP0[9]

USBP0USBP0+

USB3_RXN0 USB3_RXP0

C40 0.1U/10V/X7R_4 C41 0.1U/10V/X7R_4

PP5000 +5V_USBP0

VC12

TVM0G5R5M261R_4

USBP0-_R USBP0+_R USB3_RXN0_R USB3_RXP0_R USB3_TXN0_R USB3_TXP0_R

U30

2

VIN1

3

VIN2

4

EN

1

GND

C793

G547N1P81U

1U/6.3V/X5R_4

USB1_OC_L[26]

USBP0-_R USBP0+_R

USB3_RXN0_R USB3_RXP0_R

USB3_TXN0_R USB3_TXP0_R

D33 *5V/0.2p_4

1 2

D32 *5V/0.2p_4

1 2

D5 *5V/0.2p_4

1 2

D6 *5V/0.2p_4

1 2

D7 *5V/0.2p_4

1 2

D8 *5V/0.2p_4

1 2

+5V_USBP0

80 mils (Iout=2A)

8

+5V_USBP0

OUT3

7

OUT2

6

OUT1

5

OC

C741 470p/50V/X7R_4 C5648 0.1U/10V/X5R_4 C791 470p/50V/X7R_4

C782 220U/6.3V/ESR35_3528

VC13 TVM0G5R5M261R_4

USB 3.0 Connector

CN8

1

VBUS

1

2

D-

2

3

D+

3

4

GND

5

SSRX-

5

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

9

11111010131312

USB3.0_CONN_9P

12

PP5000

+

Modify in PV stage (7/18)

USBP1-[9]

USBP1+[9]

USB3_RXN1[9] USB3_RXP1[9]

USB3_TXN1[9] USB3_TXP1[9]

USBP1USBP1+

USB3_RXN1 USB3_RXP1

C42 0.1U/10V/X7R_4 C43 0.1U/10V/X7R_4

USB3_TXN1_C USB3_TXP1_C

PP5000 [11,18,20,22,23,25,28,30,31,32,34]

L34

1

2

1

2

3

443

DLW21HN900SQ2L

R60 *0/J_4S

R61 *0/J_4S

R65 *0/J_4S

R66 *0/J_4S

USBP1-_R USBP1+_R USB3_RXN1_R USB3_RXP1_R USB3_TXN1_R USB3_TXP1_R

+5V_USBP0

USBP1-_R USBP1+_R

USB3_RXN1_R USB3_RXP1_R

USB3_TXN1_R USB3_TXP1_R

D35 *5V/0.2p_4

1 2

D36 *5V/0.2p_4

1 2

D12 *5V/0.2p_4

1 2

D13 *5V/0.2p_4

1 2

D14 *5V/0.2p_4

1 2

D15 *5V/0.2p_4

1 2

USB 3.0 Connector

CN9

1

VBUS

1

2

D-

2

3

D+

3

4

GND

5

SSRX-

5

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

9

11111010131312

USB3.0_CONN_9P

12

24

HOLE(OTH)

HOLE1 *h-c315d110p2

B B

A A

1

HOLE7

*H-TC276BC220D150P2

1

HOLE11 *h-a23-1

1

HOLE13 *h-tc157bc197d98p2

1

*H-TC276I110BC315D110P2

5

HOLE2

1

HOLE8

*H-TC276BC220D150P2

1

HOLE12 *h-c276d110p2

1

HOLE15 *h-tc157bc197d98p2

1

HOLE3 *h-tc276bc315d110p2

1

HOLE9

*H-TC276BC220D150P2

1

1 3

PAD1

*PAD1

HOLE4 *H-C217D102P2

1

HOLE10

*H-TC276BC220D150P2

1

Write-Protect Switch

HOLE5 *H-TC315BE315X315D106NP2

SPI_WP_R_HOLE

2

4

R6549 1K/J_4

20130611 DEL Slide SW.

PAD2

*PAD2

4

SPI_WP_ME [8,26]

EMI Cap.

VIN

EC10

EC11

0.1U/25V/X5R_4

EC12

0.1U/25V/X5R_4

Cross Power Plan Cap.

VIN

C5665

C5662

PP3300_DSW

3

C5661

0.1U/25V/X5R_4

EC13

0.1U/25V/X5R_4

RF Cap.

VIN VIN

12

EC33 1U/25V/X5R_6

EC34 470p/50V/X7R_4

Reserve for RF Reserve for RF

VIN

12

EC40 1U/25V/X5R_6

Reserve for RF

C

Date:

2

Date:

12

EC37 1U/25V/X5R_6

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

USB3/SW/Hole

Friday, August 16, 2013

1

EC36 470p/50V/X7R_4

Sheet :

EC35 47p/50V/NPO_4

of

24 42

Rev.Size

1A

5

4

3

2

1

TOUCHPAD BOARD CONN (TPD)

Ad

PP3300_DSW PP3300_PCH_SUS

R6556 *0/J_6S

D D

C C

K/B (KBC)

Check pin define 0321 DFFC30FR058 footprint 51510-03001-001-30p-l

KB_ROW12[26] KB_ROW08[26] KB_ROW09[26] KB_ROW11[26] KB_ROW10[26]

KB_ROW05[26] KB_ROW06[26]

KB_ROW03[26]

KB_COL00[26]

KB_ROW01[26] KB_ROW04[26]

KB_COL03[26]

KB_ROW00[26] KB_COL05[26] KB_COL04[26]

KB_ROW07[26] KB_COL06[26] KB_COL07[26] KB_COL01[26]

PWR_BTN_L[13,17,26] PP3300_DX

R78 *0/J_4S

R281 *300/J_4

KB_ROW12 KB_ROW08 KB_ROW09 KB_ROW11 KB_ROW10

KB_ROW05 KB_ROW06

KB_ROW03

KB_ROW02_SW

KB_COL00 KB_ROW01 KB_ROW04 KB_COL03

KB_COL02_SW

KB_ROW00 KB_COL05 KB_COL04 KB_ROW07 KB_COL06 KB_COL07 KB_COL01

KB_PWR_ON_L

KB_LED

CN24

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

KB_CONN_28P

C5671 *1u/10V/X5R_4

30 29

TP_SHDN_L[20,26]

I2C0_SDA_GPIO4[10] I2C0_SCL_GPIO5[10]

R6555 *0/J_6

5 4 3

R6571 100K/F_4

R426 *0/J_4S R425 *0/J_4S

R6570 *0/J_6 U5010

IN IN ON/OFF

IC(5P) G5243AT11U

Q66 2N7002DW

1

4 3

+VCC_TPD

d in PV stage (7/15)

1

OUT

2

GND

PP3300_PCH

6 2

5

+VCC_TPD

C5670 1u/10V/X5R_4

C5633 *10p/50V/C0G_4

ff in MV stage (8/13)

Stu

check this power status

R6410 10K/J_4

+VCC_TPD

R6409 10K/J_4

+VCC_TPD

30mil

C5632 *10p/50V/C0G_4

I2C_TP_SDA_R I2C_TP_SCL_R

TRACKPAD_INT_L_R

TP104

Modify Net name in MV stage (8/13)

L38 *0/J_6S

C727

0.1U/10V/X5R_4

CN21

1

2

3

4

5

6

TP_CONN_6P

8 7

check pin define 0322 footprint 50506-00641-001-6p-l

DFFC06FR050

25

7 8 5

6

3

4

1

2

CP8 *100p/50Vx4

7 8 5

6

3

4

1

2

CP5 *100p/50Vx4

KB_ROW12 KB_ROW08 KB_ROW09 KB_ROW11

KB_ROW02_SW KB_COL00 KB_ROW01 KB_ROW04

7 8 5

6

3

4

1

2

CP9 *100p/50Vx4

7 8 5

6

3

4

1

2

CP10 *100p/50Vx4

KB_ROW10 KB_ROW05 KB_ROW06 KB_ROW03

KB_COL03 KB_COL02_SW KB_ROW00 KB_COL05

7 8 5 3 1

CP6 *100p/50Vx4 C481 *100P/50V/NPO_4

C479 *100P/50V/NPO_4

6 4 2

KB_COL04 KB_ROW07 KB_COL06 KB_COL07

KB_COL01 KB_PWR_ON_L

Touch Panel interrupt

check power status

TRACKPAD_INT_L[10]

TRACKPAD_INT_DX[2]

DSW

D44 TPL@RB500V-40

R6417

1

Q65 TPL@2N7002K

TPL@10K/J_4

PP3300_DSW PP3300_RTC PP3300_DX PP5000

PP3300_PCH PP3300_PCH_SUS

PP3300_DSW [5,7,8,10,11,13,20,21,24,26,28,29,33] PP3300_RTC [8,11,22,23,26,27,28] PP3300_DX [8,16,18,20,21,22,23,26,29] PP5000 [11,18,20,22,23,24,28,30,31,32,34]

PP3300_PCH [2,7,8,9,10,11,13,20,29] PP3300_PCH_SUS [7,8,9,10,11,13,20,29]

2

3

KEYBOARD BACK LIGHT

Removed in PV stage (7/15)

B B

Connect to EC reset pin Connect to GPIO on CPU with PU to GPIO power well

PP3300_RTC

HOLELESS RESET 2-CHIP

R6411 10K/J_4

U27

PWR_BTN_L EC_RST#

ACIN[26,27]

A A

R428 *4K4137@0/J_4

TP111

modify no BATT_EN function

5

BATT_ENABLE_4137 EC_IN_RW ACPRESENT_4137 KB_ROW02_SW KB_COL02_SW

R6553 100K/J_4

2 3 4 5 6

SLG4K4137VTR(TDFN-12)

4

PWR_BTN_L A Y KSO_SW KSI_SW

1

VDD

EC_RST_L

EC_IN_RW

EC_ENTERING_RW

GND

PAD_GND

7

13

C729

0.1U/10V/X7R_4

12 11 10

EC_ENTERING_RW

9

KSO

8

KSI

co-layout 4K4108 and 4K4137 SLG4K4108 (AL004108000) SLG4K4137 (AL004137000) 4K4137 PIN3 is BATT_ENABLE 4K4137 PIN4 is AC_PRESENT

EC_RST# [17,26]

EC_IN_RW [10]

EC_ENTERING_RW [26]

KB_ROW02 [26]

KB_COL02 [26]

3

Connect to EC pin C5 (must be low when EC IN RESET)

PP3300_DX

PP3300_DSW

EC_FAN_PWM[26]

CPU FAN1 (THM)

R6520 *0/J_4 R6521 *0/J_4S

R730 *1K/J_4

2

1 3

Q64 *MMBT3904-7-F

R6519 *0/J_4S

check with PWM signal is 3V or 5V ,if 3V can skip some circuit

PP3300_FAN

PP5000 PP5000

R729 *10K/J_4

FAN_PWM_CN1

30mil

2

EC_FAN_TACH[26]

Date:

R6518 10K/J_4

C5666 *0.1U/10V/X7R_4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

KB/KB LIGHT/TP/FAN

Friday, August 16, 2013

R732 *0/J_8S

CN15

+5V_FAN1

1 2 345

6

FAN_CONN_4P

Check FAN power leakage

Sheet :

1

of

25 42

Rev.Size

1A

5

EC(KBC)

PP3300_EC

C283

0.1U/10V/X5R_4

LPC_LAD0[8,19,21] LPC_LAD1[8,19,21] LPC_LAD2[8,19,21] LPC_LAD3[8,19,21]

PLTRST#[7,13,19,21,22]

EC_SCI_L[8]

IRQ_SERIRQ[10,21]

KB_COL00[25] KB_COL01[25] KB_COL02[25] KB_COL03[25] KB_COL04[25] KB_COL05[25] KB_COL06[25] KB_COL07[25]

KB_ROW00[25] KB_ROW01[25] KB_ROW02[25] KB_ROW03[25] KB_ROW04[25] KB_ROW05[25] KB_ROW06[25] KB_ROW07[25] KB_ROW08[25] KB_ROW09[25] KB_ROW10[25] KB_ROW11[25] KB_ROW12[25]

TP531

TP522

R431 *0/J_4 R432 *0/J_4S

TP533 TP106

TP107 TP108

TP109

TP112 TP532

TP519 TP520

C215 0.1U/10V/X5R_4

C284

0.1U/10V/X5R_4

EC_LPCPD#

KB_COL00 KB_COL01 KB_COL02 KB_COL03 KB_COL04 KB_COL05 KB_COL06 KB_COL07

KB_ROW00 KB_ROW01 KB_ROW02 KB_ROW03 KB_ROW04 KB_ROW05 KB_ROW06 KB_ROW07 KB_ROW08 KB_ROW09 KB_ROW10 KB_ROW11 KB_ROW12

PWR_BTN_L LID_OPEN_L EC_SPI_WP_D RECOVERY_L FAN_ALERT# PROCHOT_EC BAT_TEMP AD_TYPE PP3300_LTE_EN EC_ENTERING_RW

TP_SHDN_L PWR_LED# PP3300_DX_EN PP3300_DSW_GATED_EN WLAN_OFF_L

CPU_PGOOD

VCORE_EN_R

IMVP_PWRGD_3V_R SUSP_VR_EN PP1050_PGOOD PP1350_EN PP1350_PGOOD PP5000_EN PP5000_PGOOD PP3300_DSW_EN

BAT_LED0 BAT_LED1 KB_LED_EN USB2_PWR_EN USB2_ILIM_SEL USB2_STATUS_L USB2_OC_L USB1_CTL1 USB1_CTL2 ICMNT USB1_PWR_EN USB1_ILIM_SEL D/C# USB1_OC_L

EC_BRD_ID1 EC_BRD_ID2 EC_BRD_ID3

EC_RST#

1 2 3

56

USB2_OC_L[22]

USB_OC3#[9]

ICMNT[27]

USB1_OC_L[24]

USB_OC0#[9]

1U/6.3V/X5R_4

KB_COL03 KB_COL02 KB_COL01 KB_COL00

EC_PECI_RX

R835

*100K/J_4

R836

100K/J_4

C195 1U/6.3V/X5R_4

2

WLAN_OFF_L[19]

CPU_PGOOD[4] VCORE_EN[32] IMVP_PWRGD_3V[10] SUSP_VR_EN[31] PP1050_PGOOD[5,13,31] PP1350_EN[30] PP1350_PGOOD[30]

PP5000_EN[28,33]

PP5000_PGOOD[28,33]

PP3300_DSW_EN[28]

C5650 *22u/6.3V/X5R_8

D D

PP3300_EC

RP5 10K/J_10P8R

10

9

KB_COL07

8

KB_COL06

7 4

KB_COL05 KB_COL04

PP1050_PCH

EC_PECI_TX

H_PECI[4]

C C

B B

PP3300_EC

A A

R33943/J_4

4/23 modify, remove DSW_GATED power

BAT_LED0[27] BAT_LED1[27]

USB2_PWR_EN[22]

USB1_PWR_EN[24]

R831

*100K/J_4

R832

R834

100K/J_4

C274

0.1U/10V/X5R_4

3

Q46

2N7002K

1

R344 330/J_4

PP3300_LTE_EN[10] EC_ENTERING_RW[25]

PP3300_DX_EN[29]

R430 0/J_4

R429 0/J_4

EC_RST#[17,25]

EC_BRD_ID1 EC_BRD_ID2 EC_BRD_ID3

C281

0.1U/10V/X5R_4

LPC_LFRAME#[8,19,21]

PWR_BTN_L[13,17,25]

RECOVERY_L[17] FAN_ALERT#[22]

AD_TYPE[27]

TP_SHDN_L[20,25]

PWR_LED#[21]

CLK_PCI_EC[9]

C48 1000p/50V/X7R_4

4

C39 1000p/50V/X7R_4

D7

E6

E8

E9

J10

U5007

B13

PL3/LPC0AD0/T1CCP1/WT1CCP1

A13

PL2/LPC0AD1/T1CCP0/WT1CCP0

C12

PL1/LPC0AD2/T0CCP1/WT0CCP1

D11

PL0/LPC0AD3/T0CCP0/WT0CCP0

H12

PM5/LPC0CLK

D12

PL4/LPC0FRAME_L/T2CCP0/WT2CCP0

F13

PM0/LPC0PD_L/T4CCP0/WT4CCP0

C13

PL5/LPC0RESET_L/T2CCP1/WT2CCP1

F12

PM1/LPC0SCI_L/T4CCP1/WT4CCP1

H13

PM4/LPC0SERIRQ

G2

PK0/AIN16/SSI3CLK

G1

PK1/AIN17/SSI3FSS

H1

PK2/AIN18/SSI3RX

H2

PK3/AIN19/SSI3TX

B11

PK4/RTCCLK/U7RX

B12

PK5/U7TX

C11

PK6/FAN0PWM1/WT1CCP0

A12

PK7/FAN0TACH1/WT1CCP1

M13

PP0/T4CCP0

L12

PP1/T4CCP1

M5

PP2/T5CCP0

J12

PP3/T5CCP1

J13

PP4/WT0CCP0

L5

PP5/WT0CCP1

D8

PP6/WT1CCP0

K6

PP7/WT1CCP1

D4

PQ0/WT2CCP0

E4

PQ1/WT2CCP1

F5

PQ2/WT3CCP0

N5

PQ3/WT3CCP1

N6

PQ4/WT4CCP0

M2

PA2/SSI0CLK

M3

PA3/SSI0FSS

L4

PA4/SSI0RX

N1

PA5/SSI0TX

F11

PB0/T2CCP0/U1RX

E11

PB1/T2CCP1/U1TX

B6

PB4/AIN10/SSI2CLK/T1CCP0

A6

PB5/AIN11/SSI2FSS/T1CCP1

C2

PD2/AIN13/SSI1RX/SSI3RX/WT3CCP0

C1

PD3/AIN12/SSI1TX/SSI3TX/WT3CCP1

B8

PN1/AIN22

N11

PN6/FAN0PWM4/WT4CCP0

A9

PJ2/T2CCP0/U5RX

C8

PJ3/T2CCP1/U5TX

D5

PJ4/C2_P/T3CCP0/U6RX

L2

PC4/C1_M/U1RX/U4RX/WT0CCP0

L1

PC5/C1_P/U1TX/U4TX/WT0CCP1

K1

PC6/C0_P/U3RX/WT1CCP0

K2

PC7/C0_M/U3TX/WT1CCP1

J3

PH4/SSI2CLK/WT3CCP0

H4

PH5/SSI2FSS/WT3CCP1

H3

PH6/SSI2RX/WT4CCP0

G4

PH7/SSI2TX/WT4CCP1

A8

PN0/AIN23

M12

HIB_L

B2

PD0/AIN15/I2C3SCL/SSI1CLK/SSI3CLK/WT2CCP0

B1

PD1/AIN14/I2C3SDA/SSI1FSS/SSI3FSS/WT2CCP1

A4

PD4/AIN7/U6RX/WT4CCP0

B4

PD5/AIN6/U6TX/WT4CCP1

A3

PD6/AIN5/U2RX/WT5CCP0

B3

PD7/AIN4/NMI/U2TX/WT5CCP1

F1

PE0/AIN3/U7RX

F2

PE1/AIN2/U7TX

E1

PE2/AIN1

E2

PE3/AIN0

A5

PE4/AIN9/I2CSCL/U5RX

B5

PE5/AIN8/I2CSDA/U5TX

A7

PE6/AIN21

B7

PE7/AIN20

K5

PQ5/WT4CCP1

M6

PQ6/WT5CCP0

L6

PQ7/WT5CCP1

G12

OSC0

G13

OSC1

G10

RST_L

TM4E1G31H6ZRBI

R433 *0/J_4SR833

4/22 modify, reserve path for th

PP1350_EN PP5000_EN PP3300_DSW_EN

F10

VDD1

VDD2

VDD3

VDD4

VDD5

PERIPHERAL INTF

ermal shut down

R247 100K/J_4

D3

J9

J7

VDD8

VDD6

VDD7

LPC

SMBUS INTF

TO PCH

KB

FAN

PECI

LOAD SW

UNUSED

UART

VR CTRL

JTAG

USB CHARGE CTRL

BRD ID

SYS_SHDN# [10,22,28,33]

R248

R251

100K/J_4

4/23 modify, add PD

C196

2.2U/6.3V/X5R_4

K13

VDDA

VDDC1D6VDDC2J1VDDC3J6VDDC4

PB2/I2C0SCL/T3CCP0 PB3/I2C0SDA/T3CCP1

PB6/I2C5SCL/SSI2RX/T0CCP0 PB7/I2C5SDA/SSI2TX/T0CCP1

PF0/NMI/SSI1RX/T0CCP0/TRD2

PF1/SSI1TX/T0CCP1/TRD1

PF2/NMI/SSI1CLK/T1CCP0/TRD0

PF3/SSI1FSS/T1CCP1/TRCLK

PF6/I2C2SCL/T3CCP0 PF7/I2C2SDA/T3CCP1 PG0/I2C3SCL/T4CCP0

PG1/I2C3SDA/T4CCP1

PG2/I2C4SCL/T5CCP0

PG3/I2C4SDA/T3CCP1 PG4/I2C1SCL/U2RX/WT0CCP0 PG5/I2C1SDA/U2TX/WT0CCP1

PG6/I2C5SCL/WT1CCP0

PG7/I2C5SDA/U2TX/WT1CCP0

PH0/SSI3CLK/WT2CCP0

PH1/SSI3FSS/WT2CCP1 PH2/FAN0PWM5/SSI3RX/WT5CCP0 PH3/FAN0TACH5/SSI3TX/WT5CCP1

PM2/LPC0CLKRUN_L/T5CCP0/WT5CCP0

PL6/T3CCP0/WT3CCP0 PL7/T3CCP1/WT3CCP1

PN2/FAN0PWM2/WT2CCP0

PN3/FAN0TACH2/WT2CCP1

PN4/FAN0PWM3/WT3CCP0

PN5/FAN0TACH3/WT3CCP1

PM3/T5CCP1/WT5CCP1

PM6/FAN0PWM0/WT0CCP0 PM7/FAN0TACH0/WT0CCP1 PN7/FAN0TACH4/WT4CCP1

PJ5/C2_M/T3CCP1/U6TX

PC0/SWCLK/T4CCP0/TCK PC1/SWDIO/T4CCP1/TMS

PC3/SWO/T5CCP0/TDO

PP3300_EC

EC_SPI_WP_D

3

C280 1U/6.3V/X5R_4

VREFA_P

VREFA_M

PA6/I2C1SCL PA7/I2C1SDA

PF4/T2CCP0/TRD3

PF5/T2CCP1

PJ7/PECI0RX PJ6/PECI0TX

PJ0/T1CCP0/U4RX PJ1/T1CCP1/U4TX

PA0/U0RX PA1/U0TX

PC2/T5CCP1/TDI

VBAT

WAKE_L

XOSC1 XOSC0

GNDX

GNDA1 GNDA2

GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9

GND10

BLM18AG121SN1D/0.2A/120ohm_6 R3722.2/J_6

C182

C211

0.1U/10V/X5R_4

1U/6.3V/X5R_4

EC_SMB0_CLK EC_SMB0_DATA

EC_SMB1_CLK EC_SMB1_DATA

EC_SMB2_CLK EC_SMB2_DATA

PCH_WAKE_L PCH_RSMRST_L NMI_DBG_L PCH_SUSACK_L EC_SMI_L PCH_PWROK PCH_RTCRST PCH_SRTCRST PCH_DPWROK PCH_HDA_SDO PCH_SUSWARN_L PCH_SLP_SUS_L PCH_UART_RXD_R PCH_UART_TXD_R PCH_SLP_S0_L PCH_SLP_S3_L PCH_PWRBTN_L PCH_SLP_S5_L SYS_PWROK EC_ACIN LPC_CLKRUN_L EC_RCIN_L PCH_BL_PWM_R

EC_FAN_PWM EC_FAN_TACH

EC_PECI_RX EC_PECI_TX

PCH_BL_EN_R EC_BL_PWM EC_BL_EN TOUCH_RST_L PP3300_WLAN_EN PCH_EDP_VDD_EN_R EC_EDP_VDD_EN

EC_UART0_RX EC_UART0_TX

EC_JTAG_TCK EC_JTAG_TMS EC_JTAG_TDO EC_JTAG_TDI

PP3300_RTC EC_WAKE_L

ECGND

R6436 *0/J_4S R6437 *0/J_4S

R6440 *0/J_4S

R6430 *0/J_4S

R6421 *0/J_4S

R417 *0/J_4S

ECGND

SM Bus 0

SM Bus 1 LVDS Converter

NC

C279

0.1U/10V/X5R_4

D2 D1

E10 D13

M4 N2

F4 F3

M9 N9 L10 K10 L9 K9 N8 M8 L8 K8 N7 M7 K7 L7 N4 N3 K3 K4 J4 J2 G11 E12 E13

G3 D10 L11 N12

C4 C6

H10 H11 L13 M11 C9 B9 C5

L3 M1

C10 A10 A11 B10

A2 K12 N13

N10 M10 K11

C3 E3

A1 C7 D9 E5 F9 H5 H9 J11 J5 J8

SM Bus 2

R368 100K/J_4 R366 100K/J_4

4/23 modify for WP circuit

2

PP3300_ECPP3300_EC_ANA

C184 1U/6.3V/X5R_4

12

C230

0.1U/10V/X5R_4

ECGND

C307 22P/50V/NPO_4

Y4

32.768KHZ C311 18p/50V/C0G_4

L28

C189

0.01u/16V/X7R_4

TP530 TP529

TP521

PP3300_RTC

PP3300_EC_ANA

ECGND

EC_SMB0_CLK [27]

EC_SMB0_DATA [27]

EC_SMB1_CLK [16]

EC_SMB1_DATA [16] EC_SMB2_CLK [22]

EC_SMB2_DATA [22]

PCH_WAKE_L [7] PCH_RSMRST_L [7,13]

PCH_SUSACK_L [7] EC_SMI_L [8]

PCH_PWROK [5,7] PCH_RTCRST [8,13] PCH_SRTCRST [8] PCH_DPWROK [7]

PCH_HDA_SDO [8]

PCH_SUSWARN_L [7]

PCH_SLP_SUS_L [7,29] PCH_UART_RXD [17] PCH_UART_TXD [17]

PCH_SLP_S0_L [7,13]

PCH_SLP_S3_L [7,13,29,30,31,33]

PCH_PWRBTN_L [7]

PCH_SLP_S5_L [7,13,29,30]

SYS_PWROK [5,7,13]

LPC_CLKRUN_L [7] EC_RCIN_L [10] PCH_BL_PWM [2,16]

EC_FAN_PWM [25] EC_FAN_TACH [25]

PCH_BL_EN [2,16]

EC_BL_PWM [16]

EC_BL_EN [16]

TOUCH_RST_L [20]

PP3300_WLAN_EN [10,19,29] PCH_EDP_VDD_EN [2,16]

EC_EDP_VDD_EN [16]

EC_UARTRX [17] EC_UARTTX [17]

EC_JTAG_TCK [17] EC_JTAG_TMS [17] EC_JTAG_TDO [17] EC_JTAG_TDI [17]

EC32K_X1

R312 20M/J_4

EC32K_X2

SM BUS ARRANGEMENT TABLE

BATT and CHARGER

THERMAL SENSOR

SPI_WP_ME [8,24]

PP3300_DSW

PP3300_EC

C191

0.01u/16V/X7R_4

R6565 10K/J_4

LID_OPEN[17,22]

SM BUS/I2C PU(KBC)

EC HIB WAKE SOURCES

ACIN

C193 0.22U/10V/X5R_4

PP3300_DX[8,16,18,20,21,22,23,25,29] PP3300_RTC[8,11,22,23,25,27,28] PP1050_PCH[5,11,13,31]

PP3300_DX

PP3300_RTC PP1050_PCH

NMI_DBG_L

D39 RB500V-40

NMI_DBG_L FAN_ALERT# DC_LED EC_ACIN TOUCH_RST_L EC_RST# EC_LPCPD#

LID_OPEN_L

ACIN EC_ACIN

ACIN[25,27]

C288

0.1U/10V/X5R_4

D/C#

BATT and CHARGER / LCD BL

EC_SMB0_CLK EC_SMB0_DATA

LVDS converter

EC_SMB1_CLK EC_SMB1_DATA

THERMAL SENSOR

EC_SMB2_CLK EC_SMB2_DATA

PROCHOT_EC

R329 100K/J_4

PWR_BTN_L

2

R328 47K/J_4

For test only

1

PCH_NMI_DBG_L [8]

R350 10K/J_4 R356 10K/J_4 R358 *10K/J_4C185 R359 10K/J_4 R363 10K/J_4 R343 10K/J_4 R342 10K/J_4

D37 RB500V-40

R352 4.7K/J_4 R334 4.7K/J_4

R331 4.7K/J_4 R330 4.7K/J_4

2

D38 RB500V-40

3

Q41

2N7002K

1

PP3300_EC

D49 RB500V-40

4/22 modify for if EC in HOB, this pin is float

R365 *100K/J_4

PP3300_EC

PP3300_DX

R332 4.7K/J_4 R340 4.7K/J_4

3

Q40

2N7002K

1

LID_OPEN

PP3300_DX

C299 0.22U/10V/X5R_4

3 5

6

Power Switch

26

R333 47K/J_4

2 14

PP3300_RTC

2

PWR_BTN_LPWR_BTN_LSYS_SHDN#EC_RST#

PP3300_RTC

R139 1K/J_4

3

Q43

2N7002K

1

R362 10K/J_4

Modify in PV stage (7/8)

H_PROCHOT# [4,17,32]

EC_WAKE_L

SW5

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

KBC TI TM4E1G31H6ZRBI

Date:

Friday, August 16, 2013

5

4

3

2

Friday, August 16, 2013

Sheet :

1

of

26 42

Rev.Size

1A

5

4

3

2

1

27

PD29

REGN6V

PQ28

*SBR1045SP5-13

2

3

1

PQ23 FDMS7698

3

D

S

2

5

1

G

4

VIN

678

4.7U/25V_8

PQ25 EMB20N03V

35241

678

PR246 *2.2_6

PC247 *2200P/50V_4

35241

PC251

0.1U/25V_4

EMI request for ISN

*10U/25V/X5R_8

2

PC241

EC2

BAT-V

PC231

0.01U/50V_4

PL24

4.7uH/5.5A

PC242 2200P/50V_4

BQLR

CSOP CSON

EC3

22U/25V/X5R_8

PC225

0.1U/25V_4

PC234

*100P/50V_4

RC1206-R010

PR248 *0_2/S

VIN

EC4

*10U/25V/X5R_8

Custom

Date:

PL21 *0_8/S

PL23 *0_8/S

PR245

PC226

0.1U/25V_4

PR228

PR227

330_4

2 1

PD34

PDZ5.6B

PD35 PDZ5.6B

21

PC244 10U/25V_8

PR249 *0_2/S

EC5 22U/25V/X5R_8

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

BQ24738

Friday, August 16, 2013

2S2P (52.32W)

PJ1

11

PACK+

10

PACK+

9

PACK+

8

PACK+

7

NC

6

SMD

5

SMC

4

GND

3

GND

2

GND

1

GND

BATT CON_11P

EC_SMB0_CLK [26]EC_SMB0_DATA[26]

PC235 *100P/50V_4

BAT-V

PC245 10U/25V_8

Sheet :

1

13 12

PC246

0.1U/25V_4

PD37 SX34

of

27 42

of

27 42

of

27 42

Rev.Size

1A

Place this ZVS close to

DC_JACK 45W

D D

C C

B B

A A

AD_ID

6

CN1 EC1 1000p/50V_4

PR233 100/F_4

PC232 100P/50V_4

LED0 LED1

5

8 7

2 1

PR237

12.1K/F_4

VDD VDD

AD_ID

GND

WLED

GND

ALED

GND GND

DC-IN_CONN_8P

PD33

1SS355

1 2

3 4 9 10

PP3300_RTC

PC233

0.1U/10V_4

place those components close with EC

PP5000_DSW

PR240

LED0

LED1

2.43K/F_6

PQ26

AO3409

PC248 *0.1U/25V_4

PQ30

AO3409

PC256 *0.1U/25V_4

1

3

1 3

PP5000_DSW

PR256

2.43K/F_6

1

3

1 3

PR267

220K_4

2

PQ29 DRC5144E0L

PR268

220K_4

2

PQ33 DRC5144E0L

5

2

PR234 10K_4

1 3

PL20 *0_8/S

PL22 *0_8/S

PC222

0.1U/25V_4

AD_TYPE [26]

PQ27 DRC5144E0L

2

BAT_LED1 [26,27]

PQ31 DRC5144E0L

2

BAT_LED0 [26,27]

+VA

PC229

0.1U/25V_4

BAT_LED0 [26,27]

BAT_LED1 [26,27]

2 1

6 7 8

SMAJ20A

PR225

PQ21 EMB20P03V

4

IDEA_G

1M_4

PQ24

MMDT2907A

+VAD

PR241 1M_4

PR238 220K_4

ACPRESENT[7]

15 2 3

PC230

0.1U/25V_4PD30

+VA

PR230 1K_6

3

Q1

Q2

2 1654

PR239 220K_4

ACIN[25,26]

PR250 22_8

4

Diode away +VIN

Do Not add test pad on BATDIS_G signal

PC228

PR235

4.02K/F_4

PR251 *0_4/S

PR253 *0_4/S

2

PR259 *88.7K/F_4

3

1

+PRWSRC

BQCMSRC

BQACDRV

BQVCC

PP3300_RTC

PQ32

*2N7002K

+VAD

2 1

PD38

1SS355

PC249

0.47U/25V_6

+VAD

ACDET=13V

MIN. BATV=7.2V

+PRWSRC

PQ22 QM3016D

4 3

1

PC227

0.1U/25V_4

2200P/50V_4

BATDIS_G

REGN6V

PR242

4.7K/F_4

PR247

4.7K/F_4

EC_SMB0_DATA BQDATA

EC_SMB0_CLK BQCLK

PR255 430K/F_4

PR257

69.8K/F_4

PR262 *1M_4

PR264 *1M_4

PR236

4.02K/F_4

PC236

0.1U/25V_4

ACIN

*0.1U/50V_6

PR223

RC1206-R010

21

PR232

PR231

*0_2/S

CSIN

CSIP

PC240

0.1U/25V_4

1

2

ACP

3

CMSRC

4

ACDRV

5

ACPRES

20

VCC

8

SDA

9

SCL

PC253

PR261 100K/F_4

ACN

PU19

BQ24738

ACDET

ILIM

6

10

PR263 *100K/F_4

3

PC237

0.1U/25V_4

16

7

Place this ZVS close to Far-Far away VIN

PD31

P4SMAJ20A

2 1

REGN6V

PC239 1U/16V_4

HIDRV

REGN

BTST

PHASE

LODRV

GND GND GND GND GND GND

SRP

SRN

BATDRV

IOUT

BQIOUT

PR258 10/F_4

PC254 100P/50V_4

Place this cap close to EC

VIN

PC223

0.1U/25V_4

BQBATDRV BATDIS_ID_DOD

0.1U/25V_4

18

17

BQB_2

19

15

14 21 22 23 24 25

13

BQSRP

12

BQSRN

11

BQBATDRV

BQHIDRV

PR243 0_6

BQPHASE

BQLODRV

PC255

0.01U/50V_4

RB501V-40

BQB_1

PR252 0_4

PR254 0_4

ICMNT [26]

PD36

0.047U/25V_4

PC224 2200P/50V_4

PR224

4.02K/F_4

PC238

21

PC243

EMB20N03V

PC250

0.1U/25V_4

PC252

0.1U/25V_4

5

4

3

2

1

VIN[24,27,30,31,32,33,34]

PP3300_DSW[5,7,8,10,11,13,20,21,24,25,26,29,33]

PP5000[11,18,20,22,23,24,25,30,31,32,34] PP3300_RTC[8,11,22,23,25,26,27] PP5000_DSW[27,30,31,32,33]

PP3300_DSW_EN[26]

+15V

PP5000_PGOOD

PR46 *0_4

PC43

0.1U/25V_4

PR50

2.2_6

PP3300_EC

PR44 *0_4/S

PP5000_EN 51225_DH1 51225_VBST1

51225_SW1 51225_DL1 51225_FB1

10U/6.3V_6

PR47 100K/F_4

20 16 17 18 15

14

7

2

PC40

PGOOD EN1 DRVH1 VBST1 SW1 DRVL1 VFB1 VO1

PP5000_DSW

13

VREG5

TPS51225RUKR

CS11CS2

VCLK

5

19

PU3

PR43 0_6

+3VPCU_VIN

PC41

0.1U/25V_4

51225_VIN

3

12

VIN

26

PR45

0_6

PP3300_RTC

PC34

4.7U/6.3V_6

PR48 *0_4/S

6

EN2

VREG3

DRVH2

VBST2

SW2

DRVL2

VFB2

GND GND

GND23GND24GND25GND

10 9 8 11 4 21 22

51225_DH2 51225_VBST2 51225_SW2 51225_DL2 51225_FB2

SYS_SHDN#[10,22,26,33]

PC258 470P/50V_4

PP5000_PGOOD[26,33]

PP5000_EN[26,33]

678

PQ10 EMB20N03V

35241

678

PQ13 MDV1595SURH

35241

D D

VIN

12

+

PL7 *0_8/S

PC37

15u/25V_7343

+5V_SRC

PC45

0.1U/10V_4

+5VPCU_VIN

PC38

4.7U/25V_8

PC39 2200P/50V_4

PL8

2.2uH/8A(PCMC063T-2R2MN)

PR51

15.4K/F_4

PR55 10K/F_4

*2.2_6

PC49

*2200P/50V_4

PR53

PP5000 5 Volt +/- 5% TDC : 3.08A PEAK : 4.1A OCP : 5A Width : 125mil

PP5000

12

PJP1

*POWER_JP/S

C C

220uF/6.3V_7343

PC44

+

PP3300_EC[17,26,30,31]

470P/50V_4

PP3300_DSW_EN

PR49

2.2_6

0.1U/25V_4

MDV1595SURH

PC259

678

PC42

35241

678

PQ12

35241

Rds(on) <13m ohm@4.5V

+3VPCU_VIN

PC35 2200P/50V_4

PQ11 EMB20N03V

PL9

2.2uH/8A(PCMC063T-2R2MN)

PR54 *2.2_6

PC48 *2200P/50V_4

PL6 *0_8/S

PC36

4.7U/25V_8

VIN

+3V_SRC

PR52

6.81K/F_4

Vfb=2V

PR56 10K/F_4

PC162

0.1U/25V_4

0.1U/10V_4

PC46

PP3300_DSW

3.3 Volt +/- 5% TDC : 5.01A PEAK : 6.68A OCP : 8A Width : 210mil

PP3300_DSW

12

PJP2 *POWER_JP/S

+

PC47 220uF/6.3V_7343

28

CH1=5V fsw=300KHz

51225_CS1

51225_CS2

+5V_SRC

OCP:5A

L(ripple current) =(9-5)*5/(2.2u*0.3M*9) =3.367A

B B

Iocp=5-(3.367/2)=3.316A Vth=(3.316A*14mOhm)+1mV=47.43mV R(Ilim)=(47.43mV*8)/10uA =37.94K

+15V

PC220

*0.1U/25V_4

PR222 *0_6

2

PD27 *1PS302

1

2

PD28 *1PS302

1

PC221 *0.1U/25V_4

3

PC218 *0.1U/25V_4

PR221 *0_6

PC219 *0.1U/25V_4

PR57

38.3K/F_4

PR58

64.9K/F_4

CH2=3.3V fsw=355KHz

OCP:8A

L(ripple current) =(9-3.3)*3.3/(2.2u*0.355M*9) ~2.676A Iocp=8-(2.676/2)=6.662A Vth=(6.662A*14mOhm)+1mV=94.27mV R(Ilim)=(94.27mV*8)/10uA =75.41K

Low drop out LDO

PR60

VIN PP3300_RTC

A A

5

4

*0_6

PC50

*4.7U/25V_8

PU4

2

1

*TLV70433

IN

GND

OUT

3 5

NC

4

NC

3

PR61 *0_6

PC51 *1U/10V_4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

SYSTEM 5V/3V (TPS51225)

Date:

Friday, August 16, 2013

2

Friday, August 16, 2013

1

Sheet :

of

28 42

Rev.Size

1A

5

4

3

2

1

29

D D

PP3300_DX_EN[26]

PP3300_DSW

PC58

C C

PCH_SLP_S3_L[7,13,26,30,31,33]

B B

0.1U/10V_4

PR175 *0_4/S

PR64

100K/F_4

PP3300_DSW

PU7

A2 B2

IN EN

GND

TPS22930

OUT

A1 B1

place close with CPU

PP3300_PCH

PC59 *10U/6.3V_6

PP3300_PCH [2,7,8,9,10,11,13,20,25]

PC60

0.1U/10V_4

PCH_SLP_SUS_L[7,26] PCH_SLP_S5_L[7,13,26,30]

0.1U/10V_4

PR173 *0_4/S

PR171 *0_4/S

PR172

*0_4

PP3300_DSW

PC52

PR63

100K/F_4

PP3300_DSW

PC61

0.1U/10V_4

PU6

A2

IN1

B2

IN2

C2

EN

TPS22964CYZPR

A2 B2

PR65 100K/F_4

OUT1 OUT2

GND

PU8

IN EN

GND

TPS22930

OUT

PP3300_DX

A1 B1 C1

A1 B1

PC53 *10U/6.3V_6

PC62 *10U/6.3V_6

PP3300_PCH_SUS

PP3300_DX [8,16,18,20,21,22,23,25,26]

PC54

0.1U/10V_4

PP3300_PCH_SUS [7,8,9,10,11,13,20,25]

PC63

0.1U/10V_4

PC65 *10U/6.3V_6PR174

PP3300_WLAN

PC66

0.1U/10V_4

PP3300_WLAN [19]

PC64

0.1U/10V_4

PP3300_WLAN_EN[10,19,26]

PR66

*0_4/S

100K/F_4

A2 B2

PU9

IN

OUT

EN

GND

TPS22930

A1 B1

place close with CPU

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

SYSTEM 5V/3V (TPS51225)

Date:

Friday, August 16, 2013

5

4

3

2

Friday, August 16, 2013

1

Sheet :

of

29 42

Rev.Size

1A

1

2

3

4

5

30

A A

+1.35V +/- 5% Countinue current:6A Peak current:10A

VIN+VIN_DDR

PC71 2200P/50V_4

PL10 *0_8/S

PR71 *0_2/S

PC72

0.1U/25V_4

+

330u/2V_7343

( VTT/2A )

+DDR_VTT_RUN +1.35VSUS_S

+DDR_VTT_RUN[14,15]

PC68

10U/6.3V_6

PP5000

PR68 *100/F_4

PC75 *0.1U/10V_4

PR73 *0_4/S

PR74 120K/F_4

47K/F_4

PR81 *0_4/S

PR78

PC76

0.22U/10V_4

51216S3

51216S5 51216PG

51216TRIP

51216MODE

PR79 *0_4

( 3mA )

PP1350_VREF[14,15]

PR70

B B

PCH_SLP_S3_L[7,13,26,29,31,33] PCH_SLP_S5_L[7,13,26,29]

*0_4/S

PR72 *0_4

PP3300_EC

PP1350_PGOOD[26]

PC79

*0.1U/10V_4

PR75 100K/F_4

PR77 *0_4/S

PP1350_EN[26]

PP5000_DSW

PU10

VTT3VLDOIN

1

VTTSNS

4

VTTGND

7

GND

21

GND

5

VTTREF

17

S3

16

S5

20

PGOOD

18

TRIP

19

MODE

12

V5IN

G5316RZ1U

PC83 1U/6.3V_4

DRVH

VBST

DRVL

PGND

VDDQSNS

VREF

REFIN

2

PC73 *10U/6.3V_6

14

15

13

SW

11

10

9

6

8

51216DRVH

PR67

51216VBST

51216SW 51216SW

51216DRVL

51216VDDQSNS

+1.8VREF

PC81

0.1U/10V_4

51216REFIN

PC82

0.01U/25V_4

2.2_6

51216VBST_S

PR76 10K/F_4

PR80

31.6K/F_4

470P/50V_4

PC74

0.1U/25V_4

PC260

PQ15

MDV1595SURH

Rds(on) 14m ohm

35241

678

PC69

0.1U/25V_4

PQ14 EMB20N03V

PR69 *2.2_6

PC80 *2200P/50V_4

PC70

4.7U/25V_8

0.82uH/13A(EM-82BM05V04)

PC67

4.7U/25V_8

PL11

Mode Frequency Discharge mode

C C

47K 400K non Tracking Discharge

S0

S3 (mainon off)

S4/S5

S3 S5 1

0

TTREF+1.35VSUS

V 1

1

ON

O

ON ON OFF

OFF OFF0 0

N ON

OFF

OCP minimum:12A

VIN [24,27,28,31,32,33,34]

+1.35VSUS_S

PC77

0.1U/10V_4

PC78

PP1350

1 2

PJP3 *POWER_JP/S

D D

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

DDR 1.35V(TPS51216)

Date:

Friday, August 16, 2013

1

2

3

4

Friday, August 16, 2013

Sheet :

5

of

30 42

Rev.Size

1A

5

4

3

2

1

31

D D

PU11

7

AIN

VCC

1

PGOOD

3

PFM

2

EN

SS

AOZ1237QI-02

1237TON

6

TON

PC101

0.1U/10V_4

PR83

PR87 *0_4/S

PR89 *0_2/S

PR92 *0_4/S

PC100

0.1U/10V_4

*0_4

PR84 *0_4/S

PC89

1U/6.3V_4

PC99 *0.1U/10V_4

1237SS

PCH_SLP_S3_L[7,13,26,29,30,33]

21

1237PG

1237PFM

1237EN

23

PP5000

PP5000_DSW

PP3300_EC

PR85

100K/F_4

PP1050_PGOOD[5,13,26]

C C

PR91

SUSP_VR_EN[26]

B B

A A

*0_4/S

PR93

*100K/F_4

PR82 100K/F_4

8

IN

9

IN

22

IN

20

BST

10

LX

11

LX

16

LX

17

LX

18

LX

12

PGND

13

PGND

14

PGND

15

PGND

19

PGND

4

AGND

5

FB

PP1050_PCH_SUS

PR265 *0_4/S

1237BST

1237LX

1237FB

PC84

0.1U/25V_4

PR86

PR95

7.68K/F_4

A2 B2

C2

PR96 100K/F_4

0_6

1237BST_S

PR94

2.4K/F_4

PU12

IN1

OUT1

IN2

OUT2

EN

GND

TPS22964CYZPR

+VIN_1.05V

PC85

4.7U/25V_8

0.1U/25V_4

1237FB_S

A1 B1 C1

PC90

PC86

4.7U/25V_8

1uH/11A(PCMC063T-1R0MN)

PR88 *2.2_6

PC98 *2200P/50V_4

PC102 *10U/6.3V_6

PC87 2200P/50V_4

PL13

TDC : 2.08A PEAK : 2.77A Width : 85mil

PP1050_PCH

PC261 470P/50V_4

PC103

0.1U/10V_4

PL12 *0_8/S

PR90 *0_2/S

VIN

PC91

PC88

0.1U/25V_4

+1.05V_S2

0.1U/10V_4

VIN [24,27,28,30,32,33,34]

PC92

PC93

22U/6.3V_8

05V Volt +/- 5%

+1. Countinue current:4A Peak current:7.7A OCP minimum:9A

PP1050_PCH_SUS

1 2

PC95

PC94

22U/6.3V_8

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PC96

22U/6.3V_8

PJP4 *POWER_JP/S

PC97

22U/6.3V_8

PROJECT : A23

of

31 42

Rev.Size

1A

Document Number

B

Date:

5

4

3

2

Date:

+1.05V(TPS51211)

Friday, August 16, 2013

Sheet :

1

5

4

3

2

1

place close to inductor

PC104

81101IOUT

20

PR125 *0_4/S PR126 *0_4/S PR127 *0_4/S

*0_4/S PR130 *0_4/S

IOUT

220P/50V_4

PC105

1500P/50V_4

PR106 15.4K/F_4

CSCOMP

CSSUM

81101ILIM

19

21

18

ILIM

CSCOMP

PU13

NCP81101MNTWG

ENABLE1VR_HOT#2SDIO3ALERT#

SDIO

VR_HOT#

PR99

165K/F_4

PR101

68.1K/F_6

PP5000_DSW

PC109 1000P/50V_4

PR107 100K/F_4

16

IMAX

SCLK

15

PVCC

TSENSE

VR_RDY

7

6

VR_RDY

81101VRMP

PC111

2.2U/6.3V_6

14

VBOOT

13 9

HG

11

PGND

8

BST

10

SW

12

LG

VRMP

+VIN_VCC_CORE

PC123

0.01U/50V_4

VBOOT TSENSE

81101_BST 81101_PH 81101_LG

PR123 1K/F_4

CSREF

17

CSREF

CSSUM

4

5

ALERT#

SCLK

D D

POP Rb and no POP Ra for nex version.

PR108 1K/F_4

PC112

*2200P/50V_4

PR114 *0_4/S PC120

1000P/50V_4

PP5000_DSW

PP5000

PC107

330P/50V_4

VR_SVID_ALERT#[5]

PR118 *0_4/S

VR_SVID_DATA[5]

VCORE_PGOOD[5,10]

PR119 *0_4

H_PROCHOT#[4,17,26]

VR_SVID_CLK[5]

*1500P/50V_4

PR104

49.9/F_4

C C

0_4

VSS_SENSE[12]

VCC_SENSE[5]

B B

PR120 *0_4/S

PR116 0_4

PC110

PR110 *0_4/S

PC108 10P/50V_4

Ra

PR109

6.04K/F_4

470P/50V_4

Rb

81101ROSC 81101COM

81101DIFFOUT

81101VSN

PC122 1U/6.3V_4

H_PROCHOT#

81101VSP 81101VCC

PR117

2.2_6

VCORE_EN[26]

VRON_CPU[5]

PC106

PR111

18.7K/F_4

81101FB

PR105

23.2K/F_4

22

ROSC

23

COMP

24

FB

25

DIFFOUT

26

VSN

27

VSP

28

VCC

29

GND

PR122 *0_4

PR121 *0_4/S

12

PR97 75K/F_4

SWN

Boot Voltage Table

R_boot V_boot

30.1K 0V

49.9K 1.65V

69.8K 1.7V

PR112 69.8K/F_4

PC113 0.01U/25V_4 PR115 1_6 PC121

0.22U/25V_6

S1/D2

9

0.36uH/30A

1

G2

8

PL15

TSENSE

2

D1D1G1

S2

765

Place close to MOSFET

PR98 220K_4 NTC

1.75V90.9K

81101_HG_G81101_HG

81101_LG

DCR=1.2 m-ohm+/-5% ( 10 x 10)

*2.2_6

PC132 *2200P/50V_4

PR100 0_4

12

PR103

PR102

8.25K/F_4

NCP15WF104F03RC

PC115

PC114

4.7U/25V_8

D1

81101_HG_G +VIN_VCC_CORE

PQ16 FDMS3669S

S2

9

81101_LG

PR132 *0_2/S

PR137 *0_2/S

PC124 22U/6.3V_8

PR133 10/F_4

PC125 22U/6.3V_8

+VIN_VCC_CORE

PC117

PC116

4.7U/25V_8

1

2

D1

G1

S1/D2

G2

S2

765

8

CSREF

SWN

0.1U/25V_4

D1

S2

PC126 22U/6.3V_8

VIN[24,27,28,30,31,33,34]

+VCCIN[5]

PP3300_EC[17,26,28,30,31]

PC118 2200P/50V_4

PQ34 *FDMS3669S

PC127 22U/6.3V_8PR129

VIN

PL14 *0_8/S

PC262 470P/50V_4

Icc_Max=32A I_TDC=14A I_Dynamic=27A V_Operate=1.6V~1.8V DC_LL=2m AC_LL=7m AC_LL_VOS=9.4m VBOOT=1.7V

+VCCIN

PC128 *22U/6.3V_8

22U/6.3V_8

PC119

0.1U/25V_4PR113

PC129

PC130 *22U/6.3V_8PR128

32

PC131

22U/6.3V_8

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

NCP81101MNTXG

Date:

Friday, August 16, 2013

5

4

3

2

Friday, August 16, 2013

Sheet :

1

of

32 42

Rev.Size

1A

1

2

3

4

5

33

PR156 *200K/F_4

2.469V

LM393_PIN2

PP3300_DSW PCH_SLP_S3_L

PR149 *1M_4

1 3

1

2

PQ17

*AO3409

3

PR152 *0_6

PC145 *0.1U/25V_4

84

3

+

1

2

-

PU17A *BA10393F

5

+

7

6

-

PU17B *BA10393F

PR157 *200K_6

PC149 *0.1U/25V_4

2

SYS_SHDN# [10,22,26,28]

3

PQ19 *2N7002K

1

A A

PP3300_DSW[5,7,8,10,11,13,20,21,24,25,26,28,29]

PCH_SLP_S3_L[7,13,26,29,30,31]

PD8

*1SS355

VIN

Thermal protection

+1.5V +/- 5% Countinue current:1.3A Peak current:1.5A

PJP6

*POWER_JP/S

PR139 *0_4

PR141 *0_4/S

PC136

0.1U/10V_4

12

PC134

4.7U/6.3V_6 PU14

5

PG

AWP8824CTI

1

EN

PR145 10K/F_4

4

VIN

LX

GND

FB

6

R2

3

2

PR143 15K/F_4

VO=(0.6(R1+R2)/R2)

1uH/2.6A_2520

R1

PL16

B B

C C

PP3300_DSW

PP5000_PGOOD[26,28]

PCH_SLP_S3_L

OCP current:2A

PP1500_PCH_TS

1 2

PR140 *0_2/S

PC137 10U/6.3V_6

PJP5 *POWER_JP/S

PC135

0.1U/10V_4

Need fine tune for thermal protect point

Note placement position

PP5000_EN[26,28]

PP5000_EN

PR161

PP5000_EN

PP5000_DSW

2

*0_4

3

1

PR155 *887/F_4

*2N7002K

PR160 *10K_4_NTC

PQ20

PR150

*0_4

2

PQ18

*DRC5144E0L

PP5000_DSW

PR162 *200K/F_4

For EC control thermal protection (output 3.3V)

D D

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

+1.2V/+1.5V/+1.8V/Thermal protect

Date:

Friday, August 16, 2013

1

2

3

4

Friday, August 16, 2013

Sheet :

5

of

33 42

Rev.Size

1A

5

4

3

2

1

LCD Back light

34

D D

12V/0.2A

Boost Converter

VLED

PL17

PP5000

C C

PR166

EC_BL_EN_CONN[16]

*0_4/S

PR167 1M/F_4

PC150

0.1U/10V_4 PR163

PC158 *0.1U/10V_4

PC151 10U/6.3V_8

1U/6.3V_4

G5110_SHDN#

PC156

PR164 10/F_4

PC159

0.1U/10V_4

PL18

PCMC063T-6R8MN/4.5A

PU18 G5110RE1U

8

VCC

3

SHDN#

9

FSL

10

SS

GND4PAD

GND

5

PD9

G5110SW

6

SW

7

SW

2

G5110FB

FB

1

G5110COMP

COMP

11

PC160

10P/50V_4

SS1040FL

PR170 100K/F_4

G5110FB_S

R1

PR165 100K/F_4

R2

PR169

11.5K/F_4

PC157

*22P/50V_4

Vout=1.24(1+R1/R2)

*0_2/S

VCC_7V

PC155 10U/16V_8

VIN

PC152 *10U/16V_8

*80/5A

PL19 *0_8/S

PC153

0.1U/25V_4

PC154

0.1U/25V_4

VLED [16]PP5000[11,18,20,22,23,24,25,28,30,31,32]

PC161 680P/50V_4

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

Custom

LED back light

Date:

Friday, August 16, 2013

5

4

3

2

Friday, August 16, 2013

Sheet :

1

of

34 42

Rev.Size

1A

5

4

3

2

1

35

VI

N

3V/5V

VR

EN2

HW

0

ohm

PG

EN

1

EN1

NBSWON#

30

PG

+0.75V_ON

HWPG_1.05V_EC#

?

+1.05V_VCCST

+VCCIN

IMVP_PWRGD

VRON_CPU

VRON

+5VPCU

+15V

33

3

32a

32b

VL

2

depend on A measure re

sult to implement

for B test

4

DSW_ON

5a

6

DPWROK

13

RSMRST#

14

EC

VRON

EC_PWROK

32b30a

S5_ON

SUSON

MAINON

8172131

SB_ACDC DNBSWON#

15

SUSC# SUSB#

PCH_SUSACK# PCH_SUSPWARN# PCH_SLP_SUS#

34

1

3

12

31

36

4

30

a

Battery Mode

D D

Support Deep Sx

+5VPCU

3

+3VPCU

S5 PWR

+5V_S5

+3V_S5

11

10

3 3

VPCU

+3

3V_LDO

2

3

S5_ON

VIN

1

DDR VDDQ VR

S3

C C

S5

+3VPCU

3

1.5V VR

EN

+1.35V_SUS

DDR_VTTREF

+DDR_VTT_RUN

HWPG_VDDR

PG

DDR_PG_CTRL

MAINON

+0.75V_ON

SUSON

26

+1.5V

HW

PG

PG_1.5V

MAINON

RUN PWR

+5VPCU

B B

3

9

+

3VPCU

+1.05V_S5

PCH

A A

3

MOS1 MOS2

S3

MO

G

VIN

1

+1.05V_S5

VR

EN

S5_ON

M

PG

AINON

+5V

+3V

+1.05V

MAINON

9

+1.05V_S5

HWPG_1.05V

21

8

PWR

C

37

SVID

PU

BTN

7

+1.05V

VIN

1

IM VR

VP

18

19

23

24

22

21

?

17

24

HWPG_VDDR

HWPG_1.05V

12

HWPG_1.5V

2929

1

2

28

27

25

21

12

8

3

16 20

31

35 38

IM

VP_PWRGD

EC_PWROK

HWPG_1.05V

EC_PWROK

SYS_PWROK

PG_1.05V_EC#

HW

HWPG+1ms

+3VPCU

+3.3V_DSW

EN

Delay DSW power well 10ms

EC_PWROK PCH_CLK PLTRST#

VCCST_PWRGD_EN

5b

+3.3V_DSW

SYS_PWROK

36

10K ohm

1

CHARGER

DPWROK

MRST#

RS

ACPRESENT PWRBTN# SLP_S4# SLP_S3# SUSACK SUSWRAN SLP_SUS#

APWROK PCH_PWROK

PLTRST#

SYS_PWROK

38

PLTRST#

PROCPWRGD

SVID

37

BAT-VVIN

Battery

3

+3VPCU or +3.3V_DSW

DSW PWR

SUS PWR

W PWR

AS

SPI PWR

HSIO PWR

PLL PWR

PCH

CORE PWR

IO PWR

SD

HDA PWR

CORE PWR

U

CP

VDDQ PWR

RESET#

VCCST PWR

VR_READY

SM_PG_CNTL1

VCCST_PWRGD

DDR_PG_CTRL

IMVP_PWRGD

VCCST_PWRGD_EN

34

22

32a

+3VCC_S5

+1.05V

+3V_S5

+V1.05DX_MODPHY

+1.05V

+3V

+3V_S5

+VCCIN

+1.35V_SUS

+1.05V_VCCST

VR_ENVRON_CPU

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Power Sequence

Date:

Friday, August 16, 2013

5

4

3

2

Friday, August 16, 2013

Sheet :

1

of

35 42

Rev.Size

1A

1

2

3

4

5

6

7

8

36

+3V_S5

A A

SMB_PCH_CLK

AP2

SMB_

AH1

2.2K2.2K

PCH_DAT

+3.3V_RUN

2N7002DW Level shift

CLK_SCLK CLK_SDATA

+3V

LTE

4.7K4.7K

SDRAM

Touch PAD

+WL_VDD

+3V_S5

Haswell ULT

B B

AN1

SMB_ME0_CLK

AK1

SMB_ME0_DAT

+3V_S5

2N7002DW Level shift

2.2K2.2K

WLAN_CLK_SCLK WLAN_CLK_SDATA

4.7K

XDP

WLAN

+3V_S5

*2.2K*2.2K

AU3

SMB_ME1_CLK

AH3

SMB_ME1_DAT

+3V_S5

*2N7002DW Level shift

3V3MISC

C C

2ND_MBDATA

116

2ND_MBCLK

115

SIO

10K10K

+3V_GFX

2N7002DW Level shift

+3VPCU

100

4.7K4.7K

dGPU

ITE8587

10K10K

110

MBCLK

111 MBDATA

D D

1

2

3

4

100

5

Battery

Charger

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

SMBUS

Date:

Friday, August 16, 2013

6

Friday, August 16, 2013

7

Sheet :

8

of

36 42

Rev.Size

1A

5

4

3

2

1

37

(ALW)

PP5000_ALW

PWRGDPP5000_EN

3V/5V

TPS51225

VREG3

VCORE_PGOOD

PWRGD

TPS51622 EN

PWRGDPP1350_EN

+1.35V_SUS

TPS51216

Vin

PP5000_PGOOD

S5_Vout

S3_Vout

Vout

PP1350_PGOOD

S5_Vout

S3_Vout

(S3)

PP5000

(DSW)

PP3300_DSW

(AL

PP3300_RTC

(S0)

+VCCIN

(S3)

1350

PP

(S3)

PP1350_VREF

(S0)

+DDR_VTT_RUN

W)

TPS22930

PCH

PCH_SLP_SUS_L

TPS22964CYZPR

EC

PP3300_DX_EN

TPS22930

PCH

PCH_SLP_S3_L

TPS22930

PP3300_WLAN_EN

EC

PP5000_PGOOD

D D

EC

PP3300_DSW_EN

EN1

EN2

VREG5

Vin

VIN

C C

VIN

CPU

VRON_CPU

EC

B B

PCH

PCH_SLP_S3_L

Vin

CPU VCCIN

S5 EN

S3 EN

PCH

LVDS converter

MODPHY_EN

EC

USB1_PWR_EN

EC

USB2_PWR_EN

EC_BL_EN_CONN

(S3)

PP3300_PCH_SUS

(S0)

PP3300_DX

(S0)

PP3300_PCH

PP3300_WLAN

SLG5NT1477V

G547N1P81U

G547E1P81U

G5110RE1U

(S0)

+V1.05DX_MODPHY

+5V_USBP0

+5V_USBP7

VLED

VIN

PCH

PCH_SLP_S3_L

PP1050_PGOOD

PWRGD

VIN

A A

E

C

5

Vin

SUSP_VR_EN

+1.05V_S3

AOZ1237

EN

Vout

4

PP1050_PCH_SUS

PCH

TPS22964

PCH_SLP_S3_L

PWRGD

+1.5V

Vin

AWP8824CTI

Vout

EN

(S0)

PP1500_PCH_TS

PP1050_PCH

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

ULT PWR TREE

Date:

Friday, August 16, 2013

3

2

Friday, August 16, 2013

Sheet :

1

of

37 42

Rev.Size

1A

5

4

3

2

1

38

Model

D D

Version

1A

1. CN4.18 connect to PP3300_EC. (5/3)

CHANGE LIST

2. U27 change part number to SLG4K4137. (5/3)

3. Reserve Q67 , R6419 , R6418 and add bypass (R6516 and R6517). (5/3)

4. Stuff R266 and reserve R80. (5/3)

5. Reserve PP3300_DX power and PP3300_DSW power to pull up EC_FAN_TACH. (5/3)

6. Reserve Q64, R730, and R729, and use R6519 to bypass Fan PWM. (5/3)

7. Change USB2.0 port: MB_USB3.0_A → USBP0, MB_USB3.0_B → USBP1, and WWAN → USBP4. (5/3)

8. LED1 change PN to BEWH0046Z00. (5/6)

9. Add test point on SPI ROM for ICT. (5/6)

10. Modify EC_SMB0_DATA/CLK to EC_SMB2_DATA/CLK. (5/7)

11. Modify footprint of Hole6, Hole7, Hole8, and Hole9. (5/7)

C C

12. Quantity of USB3.0 Power switch IC change from two to one. (5/7)

13. USB2.0 port: OC# → USB2_OC_L, Power enable → USB2_PWR_EN. (5/7)

14. Reserve EC_SMB1_CLK / EC_SMB1_DATA for LVDS converter debug. (5/7)

15. Stuff R6508 and reserve U6 because of LVDS power controling from RTD2132. (5/7)

16. Stuff R6498 because of Blacklight ON controling from RTD2132. (5/7)

17. Reserve U8 for LVDS converter debug. (5/7)

18. Remove R6414 (HDMI does not connect to LCDVCC). (5/7)

19. Remove D26 and PCBEEP_EC path. (5/7)

20. Stuff Q68, R280, and R279 for LVDS converter debug. (5/7)

21. Reserve PP1350_VREF to Vref_CA and Vref_DQ of DDR3L. (5/8)

22. R229 modity PN to CS31202FB15 (12K ohm +/-1%). (5/8)

23. C348 modity to 22uF (Realtek FAE recommend). (5/8)

24. Change PN and footprint of CN18 (MINIPCI Connector). (5/8)

B B

25. Change PN of U28 (TPM IC). (5/8)

26. Change U5009 (thermal IC) to G708. (5/9)

27. KB_LED_EN connect to U5007.N12 (EC), and reserve 0 ohm. (5/9)

28. PWR_LED# connect to U5007.A6 (EC), and reserve 0 ohm. (5/9)

29. CN18 (MINIPCI CONN) add debug port signal. (5/9)

30. PP3300_EC add one 22uF cap. (5/9)

31. C259 change from 10uF to 22 uF. (5/9)

32. VIN add four 0.1uF/25V cap. (EC11, EC12, EC13, EC14). (5/9)

33. Audio +5V add one AZ2015-01H. (5/9)

34. Power circuit update. (5/9)

35. Audio codec confirm OK. (5/10)

36. Modify PN and footprint of connectors and key part IC byDick' confirmation. (5/10)

A A

37. C782 change to 220uF_3528. (5/10)

38. SPI_WP_ME connect to CN27.13 (LVDS connector), and reserve 0 ohm. (5/10)

39. Modify footprint of Hole 2. (5/10)

40. Modify TP pin define. (5/10)

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

DOC NO.

PROJECT MODEL :

RT NUMBER: DRAWING BY: REVISON:

PA

5

APPROVED BY:

4

DATE:

3

2

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Change list-1

Date:

Friday, August 16, 2013

Rev.Size

1A

Sheet :

1

of

38 42

1A

5

4

3

2

1

39

Model

D D

Version

1A

41. Modify only one net from layout house. (5/10)

CHANGE LIST

42. Remove Hole 16. (5/10)

43. Modify footprint of Hole 10 to be the same with Hole Hole8. (5/10)

44. Modify off page net by Michael. (5/10)

45. Modify pin define of Fan connector. (5/13)

46. Modify PN and footprint of connectors and key part IC byDick' confirmation. (5/13)

47. Modify footprint and PN of CN28 (NGFF SSD connector). (5/13)

48. C259 change from 22 uF to 10 uF, and C225 change from 10 uF to 22 uF. (5/13)

49. Remove Net: +3V_ADO, +1.5V, and +3VCC_S5. (5/13)

50. Remove RTC connector and its circuits. (5/13)

51. Remove off page Net: +3V_RTC, +V1.05S_APLLOPI, +V3.3DX_1.5DX_1.8DX_Audio. (5/13)

C C

52. Modify pin define of CN4 (G-debug), follow 0C2. (5/13)

53. R6454 connect from +VCC_TS to PP3300_PCH_SUS. (5/13)

54. Q28.2 and R243 connect from PP3300_PCH_SUS to +VCC_TS. (5/13)

55. U5.3 connect to TP_SHDN_L (U5007.B8). (5/13)

56. Reserve R6469 and R6470 (USB interface of Touch screen). (5/13)

57. PWR_LED# connect to U5007.N11, and AD_TYPE connect to U5007.A6. (5/13)

58. Stuff R433 (SYS_SHD# connect to EC_EST#), and reserve PR46. (5/13)

59. KB_LED_EN connect to U5007.A4, BAT_LED0 connect to U5007.B2, and BAT_LED1 connect to U5007.B1. (5/13)

60. Swap pin3 and pin4 of Speaker connector. (5/13)

61. Update power circuit. (5/13)

62. Hole3 connect to ADOGND. (5/14)

63. Modify footprint of Hole7, Hole8, Hole9, and Hole10. (5/14)

64. Delete Hole6 and Hole14. (5/14)

B B

65. Stuff R651, R598, and R649 for GPIO pull up resistor. (5/15)

66. Add R6536, R6537, R6538, R6539, R6540, R6541, R6542, and R6545 for GPIO pull up resistor. (5/15)

67. Un-stuff R679 for GPIO pull up resistor. (5/15)

68. Swap USBP6+ and USBP6- for layout. (5/15)

69. Add R6543 and R6544 for split J17 from R21 and T21 power plane. (5/15)

70. Power update. (5/15)

71. Add C5655 and C5654 for RF. (5/15)

72. R6472 change from 0805 type to 0603 type. (5/15)

73. Update power circuit. (5/16)

74. Delete un-used off page net. (5/16)

75. CN27.13 connect to GND, remove Write Protect. (5/16)

76. Reserve EC14, EC15, and EC16 to +VCCIN; EC17 to +WL_VDD; EC18 to +1.5V_MINI1_VDD; EC20, EC21, EC22, EC23, EC24, EC25, EC29, EC30, and EC31 to PP3300_DX; EC26, EC27, and EC28 to PP5000; EC32~EC40 to VIN for RF. (5/16)

A A

77. Modify pin name of CN28.41, CN28.43, CN28.47, and CN28.49. (5/16)

78. Add three 10uF cap. and two 2.2uF cap. on VDDQ for Intel suggestion. (5/16)

79. Modify C88, C77, C89, and C79 from 47uF to 22uF for Intel suggestion. (5/16)

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

DOC NO.

PROJECT MODEL :

RT NUMBER: DRAWING BY: REVISON:

PA

5

APPROVED BY:

4

DATE:

3

2

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Change list-1

Date:

Friday, August 16, 2013

Rev.Size

1A

Sheet :

1

of

39 42

1A

5

4

3

2

1

40

Model

D D

Version

1A (DB)

80. Modify L33, L14, and L21 from 22uH to 0 ohm (R6546, R6547, and R6548) for Intel suggestion. (5/16)

CHANGE LIST

81. Swap CN22.4 and CN22.6 for Intel suggestion. (5/16)

82. Add C5661~ C5665 for cross power plan cap. of VIN and PP3300_DSW. (5/16)

83. Un-stuff SW6 and R6511, and modify Hole5 to Write Protect function. (5/16)

84. R354 change from 100K ohm to 10K ohm, and reserve R6550 for Intel check list. (5/16)

85. CN28.69 connect to GND for SSD spec. (5/16)

86. C280 change to 1uF cap. and un-stuff C5650 for EC FAE suggestion. (5/16)

87. BAT_TEMP and D/C# add test point. (5/16)

88. R691 change from 120 ohm to 121 ohm for Intel suggestion. (5/17)

89. Remove EC16, EC22, EC23, EC25, EC26, EC32, EC38, EC39, C5663, and C5664 beacuse layout does not implement. (5/17)

90. Add R6551 and R6552 for I2C interface of touch screen. (5/17)

C C

91. Change U27.6 from KB_COL02_SW to KB_COL03_SW, and Change U27.8 from KB_COL02 to KB_COL03. (5/17)

92. Reverse Pin define of Touch Pad. (5/17)

93. Add PAD1 and PAD2. (5/17)

94. Un-stuff C436, C434, C394, C703, C400, C374, and C438 for Intel suggestion. (5/17)

95. Modify R387 to 2.7 ohm, R345 to 5 ohm, and R474 to 5 ohm. (5/20)

96. Swap USB3 port 1 TX/RX signal for Layout. (5/20)

97. Reserve C5666 (0.1uF cap.) to GND on EC_FAN_TACH. (5/20)

98. Un-stuff R6494 and stuff R6495 for Intel suggestion. (5/20)

99. Un-stuff R428 and add R6553 (100k ohm) on U27.4. (5/20)

100. Power update. (5/20)

101. Add R6554 pull up to +1.05V_VCCST and 0.1 uF to GND. (5/20)

102. Stuff Intel XDP function. (5/23)

103. L1 and L5 change to 0 ohm. (5/23)

B B

2A (SI)

104. L1 and L5 change to 0 ohm (0603), and stuff R362. (6/11)

105. Remove SW6. (6/13)

106. Power of CN1 are selected between PP3300_DSW and PP3300_PCH_SUS. (6/13)

107. Add PP3300_DSW for touch screen power. (6/13)

108. Modify R6419 and R6418 pull up to +VCC_TS. (6/13)

109. Stuff Q67, R6419, and R6418, un-stuff R6516 and R6517. (6/13)

110. CN32.9 and CN32.52 connect to PP1050_PCH_SUS. (6/13)

111. Stuff C203, C204, and C205 for Power suggection. (6/13)

112. Modify footprint of CN24. (6/13)

113. Power update. (6/13)

114. Change R6455 to pull up to PP3300_DX, and U17.41/U17.46 connect to +5VA. (6/17)

A A

115. Un-stuff L16, stuff U5008, C1012, C346, and C345, and add L57 on Audio IC. (6/17)

116. Change footprint and pin define of CN5. (6/17)

117. Change C307 to 22pF, C311 to 18pF, C624 to 12pF, and C625 to 12pF for Crystal cap. (6/17)

118. Power update. (6/17)

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

DOC NO.

PROJECT MODEL :

RT NUMBER: DRAWING BY: REVISON:

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5

APPROVED BY:

4

DATE:

3

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Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Change list-1

Date:

Friday, August 16, 2013

Rev.Size

1A

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1

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40 42

1A

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Version

2A (SI) 119. Change C193 and C299 to 0.22uF for fix AC Insert issue. (6/18)

CHANGE LIST

120. Un-stuff PC128 and C567 for layout mistake. (6/18)

121. Stuff R6489, U6, R6423, and C22, un-stuff R6498, R6507, and R6508 for LVDS control. (6/18)

122. R6489, R6438, and R6498 change to 1k ohm. (6/20)

Power change list:

123. Stuff PR47, PR85, PR75, PC116, PC128, PR240, PR256, PC129, PC130, and PC131, and un-stuff PR262, PR264, PQ32, and PR259. (6/20)

124. PU13 pin5 power source change from +5VS to PP5000_DSW. (6/20)

125. Delete PR139, PR244, and PR260. (6/20)

126. Change footprint of PJ1. (6/20)

127. PL6, PL7, PL10, PL12, PL14, PL19, PL20, PL22 change to 0 ohm. (6/20)

128. PL6, PL7, PL10, PL12, PL14, PL19, PL20, and PL22 change to short pad. (6/20)

C C

129. PQ26 and PQ30 change from N-MOS to P-MOS. (6/20)

130. PC242 and PR247 Change from 100k_0402 to 4.7k_0402. (6/20)

131. Un-stuff R478, R479, R477, and R480. (6/21)

132. Change Value of L32, L12, L13, L34, L19, and L15 to DLP11SA900HL2. (6/21)

133. Stuff U5, R6453, and R88, un-stuff R6452 and R89. (6/21)

134. Reverse PD38. (6/21)

135. Modify PR101 from 69.8k ohm to 68.1k ohm for Loadline, and PR105 from 23.7k ohm to 23.2k ohm for Iout. (6/24)

3A (PV)

136. Add R6558, R6559, R6560, R6561, and R6562 for current leakage debug. (7/9)

137. Change R6489, R6438, and R6498 to 0 ohm, and add R6563 on BL_ON curcuit. (7/9)

138. Add PCH_RSMRST_L to connect to CN32.50. (7/9)

139. Add R6565 pull up to PP3300_DSW, and D49 on LID curcuit. (7/9)

140. Un-stuff CN11 and CN22. (7/9)

B B

Power change list:

141. Change PN of PJ1 from DFHD11MS013 to DFHD11MS014. (7/12)

142. Rotate the direction of PD38. (7/12)

143. Un-stuff PD27, PD28, PC218, PC219, PC220, PC221, PR221, PR222 for BAT_LED control from P-MOS. (7/12)

144. PC151 change from CH6101KEA00 to CH61001KA94, PL11 change from CV+82D0MZ04 to CV+8213MZ00, PQ16 change from BAM03S30000 to BAM36690000, and stuff PC104. (7/12)

145. R204 change to PP3300_PCH, and un-stuff R225 and R6531 for power leakage. (7/12)

146. Change material and circuit of U5008. (7/15)

147. Remove KB Light circuit. (7/15)

148. Add U5010 and its circuit for TouchPad power. (7/15)

149. Un-stuff R717, and stuff R704. (7/15)

150. C299 connect to LID_OPEN. (7/15)

A A

151. Add R6572 (100k ohm) for U5008 enable pin, and R6573/R6574 for LVDS PWM. (7/15)

152. Un-stuff all Touch screen circuit. (7/15)

153. Change PL16 from 2.2uH to 1.0uH, and modify footprint of PJ1. (7/15)

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

DOC NO.

PROJECT MODEL :

ART NUMBER: DRAWING BY: REVISON:

P

5

APPROVED BY:

4

DATE:

3

2

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Change list-1

Date:

Friday, August 16, 2013

Rev.Size

1A

Sheet :

1

of

41 42

1A

5

4

3

2

1

41

Model

D D

Version

3A (PV) 154. Change footprint of Hole4. (7/16)

CHANGE LIST

155. Change R6565 pull up from PP3300_DSW to PP3300_EC. (7/16)

156. Change 0 ohm to short pad on R45,R69,R215,R236,R237,R274,R277,R288,R404,R513,R591,R639,R652,R653,R656,R596,R78,R86,R87,R6532,R173,R545,R587,R625 R641,R226,R265,R283,R295,R453,R425,R426,R432,R6421,R6430,R6440,R568,R582,R6400,R6403,R6404,R771,R773,R816,R6413. (7/17)

Power change list:

157. Change PN of PU13 from AL081101001 to AL081101000. (7/17)

158. Un-stuff PU4, PC50, and PC51 for reserve PP3300_RTC. (7/17)

159. Un-stuff PU17,PQ19,PQ20,PQ18,PQ17,PD8,PR160,PR156,PR162,PR157,PR155,PR149,PR152,PR150,PR161,PC145,PC149 for reserve Thermal protection. (7/17)

160. Change PL8 and PL9 from 1.5uH to 2.2uH. (7/17)

161. Change C345 from 22uF (0805) to 10uF (0603). (7/17)

162. Change CN4 from DFHS50FS025 to DFHS50FS056. (7/17)

C C

163. Change C782 from 150uF to 220uF for USB3.0 port Voltage drop. (7/18)

164. Stuff C45,C46,C222,C207,L36,C273,C357,C639,EC33,EC37,EC40,EC34,EC36,EC35, and un-stuff R725,R724 for RF suggestion. (7/18)

165. Stuff L56,L32,L34, and un-stuff R494,R495,R493,R492,R6467,R6468 for EMI suggestion. (7/18)

Power change list:

166. Stuff EC3,EC5 for EMI suggestion, and stuff PC92,PC93,PC94 for RF suggestion. (7/18)

167. Change PJ1 from DFHD11MS014 to DFHD11MS013. (7/18)

168. Un-stuff PC128 and PC130 because height-limit . (7/18)

169. Change L12,L13,L15,L19,L32,L34,L36 from DC09004A014 to CX1HN900000. (7/19)

170. Stuff R717, and un-stuff R704 for Google suggestion. (7/23)

3B (MV)

171. Modify Net name of CN21.5. (8/13)

B B

172. Add R6575 pull up to PP3300_DX. (8/13)

173. Stuff C5670. (8/13)

174. Reserve Q69, R6576, R6577, and R6578 for Audio codec FAE suggestion. (8/13)

175. R239,R353,R417,R433,R541,R546,R547,R548,R549,R552,R553,R570,R573,R6315,R6316,R6432,R6436,R6437R6519,R6558,R6559,R6560,R6561,R6562,R664,R719,R722,

R757,R786,R813,L1,L38,L5,R107,R111,R158,R194,R197,R204,R212,R233,R234,R254,R337,R338,R373,R382,R411,R627,R6472,R6543R6544,R6556,R165,R170,R179,R190, R217,R270,R323,R559,R560,R6473,R6546,R6547,R6548,R732,R749 change from 0 ohm resistor to short pad. (8/13)

176. Modify M_A_A<9> connecting to R379, and M_A_A<3> connecting to R783. (8/14)

177. Modify M_A_DIM0_CK_DDR0_DP connecting to R769, and M_A_DIM0_CK_DDR0_DN connecting to R755. (8/14)

178. Footprint of Hole5 change to H-TC315BE315X315D106NP2. (8/15)

Power change list:

179. PR70,PR77,PR73,PR81,PR48,PR44,PR171,PR173,PR174,PR175,PR265,PR87,PR92,PR84,PR91,PR118,PR121,PR125,PR126,PR127,PR129,PR130,PR110,PR114,PR166,PR141

change from 0 ohm resistor to short pad. (8/15)

180. PL18 change from CV-6825MZ00 to CV-6845MZ05 for change to common part. (8/15)

A A

181. Un-staff CN4, and Hole13 change to floating. (8/16)

182. Remove R725,R724,R6467,R6468,L27,L29,R493,R492,L12,L13,R494,R495,L19,L15 for canceling colay of USB port. (8/16)

183. R99,R100,R101,R102,R56,R59,R60,R61,R65,R66,R544,R6521,R6495,R88,R90,R266 change from 0 ohm resitstor to short pad. (8/16)

DOC NO.

PROJECT MODEL :

ART NUMBER: DRAWING BY: REVISON:

P

5

APPROVED BY:

4

DATE:

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : A23

Document Number

C

Change list-1

Date:

Friday, August 16, 2013

3

2

Friday, August 16, 2013

Sheet :

1

of

42 42

Rev.Size

1A

HP 14-Q070NR Schematics

Specifications and Main Features

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User Manual