Holtek Semiconductor Inc HTG1390 Datasheet
HTG1390
Preliminary
Features
•
Operating voltage: 1.2V ~1.8V
•
7 input lines
•
3 output lines
•
Halt feature reduces power con sumption
•
Up to 16µs instruction cycle with 256kHz
system clock at V
•
All instructions in 1 or 2 machine cycles
•
4K×8 program ROM
•
Data memory RAM size 128×4 bits
General Description
The HTG1390 is the processor from Holtek’s
4-bit stand alone single chip microcontroller
range specifically designed for LCD product applications. The d evice is ide ally s uited for mul -
DD
=1.5V
4-bit Microcontroller
•
27×3 segment LCD driver
•
8-bit table read instruction
•
5 working registers
•
Internal timer overflow interrupt
•
One level subroutine nesting
•
RC oscillator for system clock
•
8-bit timer with internal clo ck source
•
Sound effect circuit
tiple LCD low power applications among which
are calculators, scales, and hand held LCD
products.
1 17th Nov ’98
Block Diagram
Preliminary
HTG1390
Notes: ACC: Accumulator
PC: Program counter
R0~R4: Working registers
PA: Output port
PS,PP: Input ports
2 17th Nov ’98
Pad Assignment
Preliminary
HTG1390
Chip size: 1960 × 2300 (µm)
* The IC substrate should be connected to VSS in the PCB layout artwork.
3 17th Nov ’98
2
Preliminary
HTG1390
Pad Coordinates Unit: µm
Pad No. X Y Pad No. X Y
1 –843.74 866.29 27* 853.56 –644.11
2 –843.74 674.39 28* 853.56 –524.11
3* –843.74 554.39 29* 853.56 –404.11
4* –843.74 434.39 30* 853.56 –284.11
5 –843.74 314.39 31* 853.56 –164.11
6 –843.74 194.39 32* 853.56 –44.11
7 –843.74 74.39 33 853.56 75.89
8 –843.74 –45.61 34* 853.56 195.89
9* –843.74 –165.61 35* 853.56 315.89
10* –843.74 –285.61 36* 853.56 435.89
11 –843.74 –405.61 37* 853.56 555.89
12 –843.74 –525.61 38* 853.56 675.89
13 –843.74 –645.61 39* 838.76 935.39
14 –798.04 –856.71 40* 718.76 935.39
15 –668.04 –882.11 41* 598.76 935.39
16 –415.94 –809.01 42* 478.76 935.39
17 –287.94 –853.41 43* 358.76 935.39
18 –154.74 –853.41 44* 238.76 935.39
19* –25.94 –853.41 45* 118.76 935.39
20* 107.26 –853.41 46* –1.24 935.39
21* 236.26 –853.41 47* –121.24 935.39
22* 398.66 –940.91 48* –241.24 935.39
23 518.66 –940.91 49* –361.24 935.39
24 638.66 –940.91 50* –481.24 935.39
25 853.56 –884.11 51* –601.24 935.39
26 853.56 –764.11 52* –721.24 935.39
∗ These pins must be bonded out for functional testing.
4 17th Nov ’98
Preliminary
HTG1390
Pad Description
Pad No. Pad Name I/O Mask Option Function
17, 18 BZ,BZ O Note 1 Sound effect outputs
For test mode only
8
9
5~7 COM2~COM0 O Note 2 Output for LCD panel common plate
10~13 PS3~PS0 I
16 VSS I — Negative power supply, GND
15
14
19~21 PA2~PA0 O
22~24 PP0~PP2 I
25
26~52 SEG0~SEG26 O — LCD driver outputs for LCD panel segment
1 VDD I — Positive power supply
4 V3 I — LCD system power 1/2 bias generated
2, 3 C1, C2 I —
TEST1
TEST2
OSCI
OSCO
RES I —
I
I
Pull-high or
None. Note 3
I
O
NMOS Open
Pull-high or
None. Note 2
—
—
CMOS or
Drain
TEST1 and TEST2 are left open when the
HTG1390 is in normal operation (with an internal
pull high resistor).
4-bit port for input only
OSCI,OSCO are connected to an external resistor
for an internal system clock
3-bit latch port for output only
3-bit port for input only
Input to reset an internal LSI
Reset is active on logical low level
LCD system voltage booster condensor connecting
terminal
Notes: The system clock provides 6 different sources selectable by mask option to drive the sound
effect clock. If the Holtek sound library is used only 128K and 64K are acceptable.
Each bit of ports PS and PP can be a trigger source of the HALT interrupt, selectable by mask
option.
Absolu te Maximu m R a tin g s *
Supply Voltage.................................–0.3V~5.5V Input Voltage.....................VSS–0.3V~VDD+0.3V
Storage Temperature....................–50°C~125°C Operating Temperature......................0°C~70°C
*Note: These are stress ra tings on ly. Stresses exceeding the range specified under “Ab solute Maxi -
mum Ratings” ma y cause substantial damage to the device. Functional operation of this
device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme condition s may affect device reliability.
5 17th Nov ’98
Preliminary
HTG1390
D.C. Characteristics Ta=25°C
Symbol Parameter
V
DD
I
DD
I
STB
V
IL
V
IH
I
OL1
I
OH1
I
OL2
I
OH2
R
PH
Operating Voltage — — 1.2 1.5 1.8 V
Operating Current 1.5V
Standby Current 1.5V
Input Low Voltage 1. 5V — 0 — 0.4 V
Input High Voltage 1.5V — 1.0 — 1.5 V
Port A, BZ & BZ Output Sink
Current
Port A, BZ & BZ Output
Source Current
Segment Output Sink
Current
Segment Output Source
Current
Pull–high Resist an c e 1.5V PS, PP, RES 30 — 300 kΩ
Test Conditions
V
DD
No load,
f
=256kHz
SYS
No load,
HALT mode
VDD=1.5V,
1.5V
V
=0.15V
OL
VDD=1.5V,
1.5V
V
=1.35V
OH
1.5V V
1.5V V
LCD
LCD
Conditions
Min. Typ. Max. Unit
—20—
—— 1 µA
95 100 —
600 700 —
=3V, VOL=0.3V 100 150 — µA
=3V, VOH=2.7V –20 –40 — µA
µA
µA
µA
A.C. Characteristics Ta=25°C
Symbol Parameter
f
SYS
f
LCD
t
COM
t
CY
t
RES
f
SOUND
Notes: * In general, f
System Clock 1.5V R:36kΩ~2MΩ 38 — 400 kHz
LCD Clock 1.5V — — 128* — Hz
LCD Common Period — 1/3 duty — (1/f
Cycle Time — f
Reset Pulse Width — — 5 — — ms
Sound Effect Clock — — —
is selected and optimized by Holtek depending upon f
LCD
Test Conditions
V
DD
Conditions
=256kHz — 16 — µs
SYS
Min. Typ. Max. Unit
)×3— s
LCD
64 or 128
**
SYS
voltage.
** Only these two clocking signal frequencies are supported by the Holtek sound library.
6 17th Nov ’98
— kHz
and the operating
Preliminary
HTG1390
System Architect ure
Program counter – PC
This counter a ddresses the program ROM and
is arranged as an 12-bit binary counter from
PC0 to PC11 whose contents specify a maximum of 4096 addresses. The program counter
counts with an increm ent of 1 or 2 with each
execution of an instruction.
When executing the jump instruction (JMP,
JNZ, JC, JTMR,...), a subroutine call, initial
reset, internal i nterrupt, extern al interrupt or
returning from a subroutine, the program
counter is loaded with the corresponding instruction data as shown in the table.
Notes: P0~P11: Instruction code
@: PC11 keeps current value
S0~S11: Stack register bits
Program memory – ROM
The program memory is the executable memory
and is arranged in a 4096
address is specified by the program counter
(PC). Four special lo cati on s are rese rved as de scribed as follows.
•
Location 0
Activating the pro cessor
first instruction to be fetched from location 0.
•
Location 4
Contains the timer interrupt resulting from a
TIMER overflow . If the interrupts ar e enabled it
causes the program to jump to this s ubroutine.
Mode
Initial reset 0 0 0 0 0 0 0 0 0 0 0 0
Internal interrupt 0 0 0 0 0 0 0 0 0 1 0 0
External interrupt 0 0 0 0 0 0 0 0 1 0 0 0
Jump, call instruction P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Conditional branch @ P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Return from subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
×8 bit format. The
RES pin caus es the
PC1 1 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
•
Location 8
Activating the PS or PP input pins of the
processor with the interrup ts enabled during
Halt mode causes the program to jump to this
location.
•
Locations n00H to nFFH
These are the 256 bytes of each page in pro-
gram memory. This area from n00H to nFFH
and F00H to FFFH can be used as a look–up
table. Instructions such as READ R4A, READ
MR0A, READF R4A, READF MR0A can rea d
the table and transfer the contents of the
table to ACC and R4 or to ACC and a data
memory address specified by the register pair
R1,R0. However as R1,R0 can only store 8
bits, these instructions cannot fully specify
the full 12 bit program m emory address. F or
this reason a jum p instruction should be first
used to place the program counter in the right
page. The above instructions can then be used
to read the look up table data.
Program Counter
Program memory
Program memory
7 17th Nov ’98
Preliminary
HTG1390
Note that the page number n must be greater
than zero as some lo cations in page 0 are reserved for specific usage as mentioned. This
area may functio n as n ormal pro gram m em ory
as required.
The program memory mapping is shown in the
diagram.
In the execution o f an instruction the program
counter is added before the execution phase, so
careful manipulation of READ MR0A and
READ R4A is needed in the page margin.
Stack register
The stack register is a group of registers used to
save the contents of th e program counter (PC)
and is arranged in 13 bits
×1 level. One bit is
used to store the carry flag. An interrupt will
force the contents o f the PC and the carry flag
onto the stack registe r. A subroutine call will
also cause the PC contents to be pushed onto
the stack; however the carry flag will not be
stored. At the end o f a subroutine or a n interrupt (indicated by a retu rn instruction RET or
RETI), the contents of the stack register are
returned to the PC.
Executing “RETI” instruction will restore the
carry flag from st ack r egist er, but “RET” doesn’t.
Working registers – R0,R1,R2,R3,R 4
There are 5 working registers (R0,R1,R2,R3,
R4) usually used to store the frequently accessed intermed iate re su lts . Usin g the instru ctions INC Rn and DEC Rn the working
registers can increment (+1) or decrement (–1).
The JNZ Rn (n=0,1,4) instruction makes efficient use of the working registers as a program
loop counter. Also the register pairs R0,R1 and
R2,R3 are used as a data memory pointer when
the memory transfer instruction is executed.
Data memory – RAM
The static data memory (RAM) is arranged in
256
×4 bit format and is used to store data. All of
the data memory locations are indirectly addressable through the register pair R1,R0 or
R3,R2; for example MOV A,[R3R2] or MOV
[R3R2],A.
There are two areas in the data memory, the
temporary data area and the display data area.
Access to the temporary data area is from 00H
to 7FH. Loca tions E0H to FAH represent the
display data area. The locations between the
temporary and display data areas are undefined and cannot be used .
When data is written into the display data area
it is automatically read by the LCD driver
which then genera tes the corresponding LCD
driving signals.
Data memory
Accumulator – ACC
The accumulator is the most important data
register in the processor. It is one of the sources
of input to the ALU and the destina tion of the
results of the operations performed in the ALU.
Data to and from the I/O ports and memory also
passes through the accumulator.
Arithmetic and logic unit – ALU
This circuit performs the following arithmetic
and logical operations ...
•
Add with or without carry
•
Subtract with or without carry
•
AND, OR, Exclusive-O R
•
Rotate right, left through carry
•
BCD decimal adjust for addition
•
Increment, decrement
•
Data transfers
•
Branch decisions
The ALU not only outputs the results of data
operations, but also sets the status of the carry
flag (CF) in some instructions.
8 17th Nov ’98
Preliminary
HTG1390
Timer
The HTG1390 contains a programmable 8-bit co unt up counter which can be used as a clock to generate
an accurate time base.
The Timer may be set and read with software
instructions and stopped by a hardware reset or
a TIMER OFF instruction. T o restart the timer
load the counter with the value XXH and the n
issue a TIMER ON instruction. Note that XX is
the desired start count imme diate value of the
8 bits. Once the Timer/Counter is started it
increments to a maximum count of FFH and
then overflows to zero (00H). It then continue s
to count until stopped by a TIMER OFF instruction or a reset.
The increment from the maximum count of
FFH to a zero (00H) triggers a timer flag TF and
an internal interrupt request. The interrupt
may be enabled or disabled by executing the EI
and DI instructio n. If the interrupt is ena bled
the timer over flow will cau se a su broutine call
to l ocati on 4 . The state of the timer flag is also
testable with the conditional jump instruction
JTMR. The timer flag is cleared after the interrupt or the JTMR instruction is executed.
If an internal source is used the frequency is
determined by the system clock and the parameter n as defined in the equatio n. The frequency of the internal frequency source can be
selected by mask option.
Frequency of TIMER clock
where n=0,1,2 ...13 selectable by mask option.
Note that n cannot have the value of 6, which is
reserved for internal use .
Interrupt
The HTG1390 provides both internal and external interrupt modes. The DI and EI instructions are used to disable and enable the
interrupts. Durin g Halt mode, if the P P or PS
input pin is triggered on a high to low transition
in the enable interrupt mo de and the program
is not within a CALL subroutin e, the external
interrupt is acti ved. This causes a sub routine
call to location 8 and resets the interrupt latch.
system clock
=
n
2
Likewise when th e timer flag is set in the en able interrupt mode and the program is not
within a CALL subrouti ne the internal interrupt is activated. T his cau ses a su brouti ne cal l
to location 4 and resets the timer flag.
When runni ng un de r a C AL L subrou tin e o r DI
the interrupt acknowle dge is on hold until th e
RET or EI instruction is invoked. The CALL
instruction should no t be used wi thi n an i nte rrupt routine as unpredictable behaviour may
occur. If within a CALL subroutine internal
interrupt occur, the internal interru pt will be
serviced after leaving the CALL subroutine.
The interrupts are disabled by a hardware reset
or a DI instruction. They remain disabled until
the EI instruction is executed.
Each input port pin can be programmed by
mask option to have an external interrupt function in the HALT mode.
Initial reset
The HTG1390 provides an RES pin for system
initialization. Thi s pin is equipp ed with an internal pull high resistor and in combination
with an external 0.1
an internal rese t pulse of sufficient length
guarantee a reset to all intern al circuits. If the
reset pulse is generated externally , the
must be held low for at least 5ms. Normal circuit operation will not commence until the
pin returns high.
The reset performs the following functions:
µ~1µF capacitor, provides
to
RES pin
RES
PC 000H
TIMER Stop
Time flag Reset (Low)
SOUND
Output Port A high (or floating state)
Interrupt Disabled
BZ and
BZ output Low level
Sound off and one sing
mode
9 17th Nov ’98
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