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Holtek Semiconductor Inc
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HTG12N0
Datasheet
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Holtek Semiconductor Inc HTG12N0 Datasheet

Features

•
Operating voltage: 2.4V ~3.5V
•
Seven input line s
•
Six output lines
•
Halt feature reduces power con sumption
•
Up to 4µs instruction cycle with 1MHz system clock
•
4K × 8 × 4 program ROM
•
Data memory RAM size 256 × 4 bits
•
64 segments × 8 commons, 1/5 bias LCD driver

General Description

The HTG12N0 is the processor from HOL TEK’ s 4-bit stand alone single chip microcontroller specially designed for LCD display and time piece product applications.
HTG12N0
4-Bit Microcontroller
•
8-bit table read instruction
•
Five working registers
•
Internal timer overflow
•
One level subroutine nesting
•
RC oscillator and 32768Hz crystal oscillator
•
8-bit timer with internal or external cl ock source
•
Sound effect circuit
It is ideally suited for multiple LCD time piece low power applications among which are calcu­lators, scales, calendar and hand held LCD products.
1 18th Mar ’99

Block Diagram

HTG12N0
Notes: ACC: Accumulator R0~R4: Working registers PB0, PB1: ROM bank switch PC0: RAM bank switch PC1: LCD On/Off switch PA, PC2~PC3: Output ports PS, PM0~PM2: Input ports
2 18th Mar ’99

Pad Assignment

HTG12N0
Chip size: 3430 × 3730 (µm)
* The IC substrate should be connected to VSS in the PCB layout artwork.
3 18th Mar ’99
2
HTG12N0

Pad Coordinates Unit: µm

Pad No. X Y Pad No. X Y Pad No. X Y
1 –1592.40 1448.48 34 –10.08 –1598.48 67 1578.80 850.32 2 –1592.40 1324.64 35 119.04 –1598.48 68 1578.80 970.96 3 –1592.40 1207.36 36 290.48 –1706.56 69 1578.80 1091.28 4 –1592.40 1083.52 37 409.20 –1706.56 70 1578.80 1211.92 5 –1553.16 508.96 38 527.92 –1706.56 71 1578.80 1332.24 6 –1592.40 367.52 39 646.64 –1706.56 72 1578.80 1452.88 7 –1592.40 246.48 40 765.36 –1706.56 73 1578.80 1573.20 8 –1592.40 125.44 41 884.48 –1706.56 74 1578.80 1695.12
9 –1592.40 4.40 42 1001.44 –1706.56 75 1306.40 1706.56 10 –1592.40 –116.64 43 1117.60 –1706.56 76 1185.65 1706.56 11 –1592.40 –237.68 44 1233.44 –1706.56 77 1066.56 1706.56 12 –1592.40 –358.72 45 1349.60 –1706.56 78 947.12 1706.56 13 –1592.40 –479.76 46 1465.44 –1706.56 79 828.00 1706.56 14 –1592.40 –600.80 47 1584.16 –1706.56 80 708.56 1706.56 15 –1592.40 –721.84 48 1578.80 –1438.64 81 589.44 1706.56 16 –1592.40 –842.88 49 1578.80 –1318.32 82 470.00 1706.56 17 –1592.40 –963.92 50 1578.80 –1197.68 83 350.88 1706.56 18 –1592.40 –1084.96 51 1578.80 –1077.36 84 2 31.44 1706.56 19 –1592.40 –1206.00 52 1578.80 –956.72 85 112.32 1706.56 20 –1592.40 –1327.04 53 1578.80 –836.40 86 –7.12 1706.56 21 –1592.40 –1448.08 54 1578.80 –715.76 87 –126.24 1706.56 22 –1579.60 –1706.56 55 1578.80 –595.44 88 –245.68 1706.56 23 –1459.36 –1706.56 56 1578.80 –474.80 89 –364.80 1706.56 24 –1338.80 –1706.56 57 1578.80 –354.48 90 –484.24 1706.56 25 –1218.56 –1706.56 58 1578.80 –233.84 91 –603.36 1706.56 26 –1097.52 –1706.56 59 1578.80 –113.52 92 –722.80 1706.56 27 –965.12 –1598.48 60 1578.80 7.12 93 –841.92 1706.56 28 –823.20 –1598.48 61 1578.80 127.44 94 –961.36 1706.56 29 –694.08 –1598.48 62 1578.80 248.08 95 –1080.48 1706.56 30 –552.16 –1598.48 63 1578.80 368.40 96 –1199.92 1706.56 31 –423.04 –1598.48 64 1578.80 489.04 97 –1319.04 1706.56 32 –281.12 –1598.48 65 1578.80 609.36 98 –1438.48 1706.56 33 –152.00 –1598.48 66 1578.80 730.00 99 –1557.60 1706.56
4 18th Mar ’99

Pad Description

HTG12N0
Pad No. Pad Name I/O
38~99 1~2
3 4
5 VDD I — Positive power supply 6
7 8
29 17 18
9~16 COM7~COM0 O — Output for LCD panel common plate 22~25
21~19 26 VSS I — Negative power suppl y, GND 27, 28 BZ,
33~30 35~34
36
37 TMCLK I
SEG63~SEG2 SEG1~SEG0
XIN XOUT
OSCI OSCO
T512 T1D TEST1 TEST2
PS3~PS0 PM2~PM0
BZ O Note 1 Sound effect outputs
PA3~PA0 PC3~PC2
RES I —
O — LCD driver outputs for LCD panel segment
I
O
I
O O
O
I I
I
O
Mask
Option
—
—
Pull-high or
None, Note 2
CMOS or
NMOS Open
Drain
Pull-high or
None, Note 3
Description
32768Hz crystal oscillator for time base, LCD clock
An external resistor between OSCI and OSC0 is needed for the internal system clock.
For test mode only TEST1 and TEST2 are left open when the chip is in normal operation (with an internal pull-high resistor).
Input pins for input only
Output latch pins for output only
Input to reset an internal LSI Reset is active on logical low level
Input for TIMER clock TIMER can be clocked by an external clock or an internal frequency source.
Notes:
1. The system clock provides six different sources selectable by mask option to drive the sound effect clock. If the Holtek sound library is used, only 128K and 64K are acceptable.
2. Each bit of ports PM0~PM2, PS can be a trigger source of the HALT interrupt, selectable by mask option.
3.14 internal clock sources can be selected by mask option to drive TMCLK. Note that TMCLK should not be connected to a pull high resistor if an internal source is used.
5 18th Mar ’99
HTG12N0

Absolu te Maximu m R a tin g s

Supply Voltage .................................–0.3V~5.5V Storage Temperature....................–50°C~125°C
Input V oltage.....................V
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute M axi-
mum Ratings” ma y cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme condition s may affect device reliability.

D.C. Characteristics Ta=25°C

–0.3V~VDD+0.3V Operating Temperature.....................0°C~70 °C
SS
Symbol Parameter
V
DD
I
DD
I
STB1
I
STB2
V
IL
V
IH
I
OL1
I
OH1
I
OL2
I
OH2
R
PH
Operating Voltage — — 2.4 3 3.5 V Operating Current
(LCD ON) Standby Current
(LCD OFF) Standby Current
(LCD ON) Input Low Voltage 3V — 0 — 0.2V Input High Voltage 3V — 0.8V PA, PC, BZ and BZ
Output Sink Current PA, PC, BZ and BZ
Output Source Current Segment Output Sink
Current Segment Output Source
Current Pull-high Resistor 3V
Test Conditions
V
DD
3V
Conditions
No load, f
=512kHz
SYS
Min. Typ. Max. Unit
—100200
3V HALT mode — 2 5
3V HALT mode — 10 20
—VDDV
3V V
3V V
3V V
3V V
DD
=0.3V 1.5 3 — mA
OL
=2.7V –0.5 –1 — mA
OH
=0.3V 30 60 — µA
OL
=2.7V –50 –100 — µA
OH
PS, PM, TMCLK
RES,
15 100 200 k
DD
µA
µA
µA
V
Ω
6 18th Mar ’99
HTG12N0

A.C. Characteristics Ta=25°C

Symbol Parameter
f
SYS
f
LCD
t
COM
t
CY
f
TIMER
t
RES
f
SOUND
System Clock 3V R=620kΩ~36kΩ 128 — 1000 kHz LCD Clock 3V — — 256 — Hz LCD Common Period — 1/8 duty — (1/f Cycle Time 3V f Timer I/P Frequency
(TMCLK) Reset Pulse Width — — 5 — — ms Sound Effect Clock — — — *64 or 128 — kHz
Test Conditions
V
DD
Conditions
=1MHz — 4 — µs
SYS
Min. Typ. Max. Unit
)×8— s
LCD
3V — 0 — 1000 kHz
*: Only these two clocking signal frequencies are supported by Holtek’s sound library.
7 18th Mar ’99

Functional Description

Program counter – PC
This counter a ddresses the program ROM and is arranged as a 12-bit binary counter from PC0 to PC11 whose contents specify a maximum of 4096 addresses. The program counter counts with an in­cr ement of 1 or 2 w ith each execution of an instruction.
When executing the jump instruction (JMP, JNZ, JC, JTMR,...), a subroutine call, initial reset, internal inte rrupt, RTC interrupt or re­turning from a subroutine, the program counter is loaded with the corresponding instruction data as shown in the table.
Notes: P0~P11: Instruction code
@: PC11 keeps the curre nt value S0~S11: Stack register bits PB0 and PB1 are set to 0 at power on
reset.
Program memory – ROM
The program memory is the executable memory and is arranged in a 4096 four banks for the program memory in HTG12N0 , each bank shown in the figure can be switched by the assignment of PB0 and PB1. The address is specified by the program counter (PC). Four sp e­cial locations are reserved as shown below .
Mode
Initial reset
Internal interrupt
External interrupt
Jump, call instruction
Conditional branch
Return from subroutine
PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PB1PB00 0 0000000000
PB1PB00 0 0000000100
PB1PB00 0 0000001000
PB1 PB0 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
PB1 PB0 @ P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
PB1PB0S11S10S9S8S7S6S5S4S3S2S1S0
×8 bit format. There a re
Program memory PB0=0, PB1=0
Program memory PB0=1, PB1=0
•
Location 0 Activating the pro cessor
first instruction to be fetched from location 0.
Program Counter
HTG12N0
RES pin caus es the
Program memory
8 18th Mar ’99
•
Location 4 Contains the timer interrupt resulting from a
TIMER overflow. If the interrupts are enabled, it causes the program to jump to this subrou­tine.
•
Location 8 Activating the RTC of the processor with the
interrupts enabled causes the program to jump to this location.
•
Locations n00H to nFFH Each page in the program memory consists of
256 bytes. This area from n00H to nFFH and F00H to FFFH can be used as a look-up table. Instructions such as READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or to ACC and a data memory address specified by the register pair R1,R0. However as R1,R0 can only store 8 bits, these instructions cannot fully specify the full 12-bit program memory ad dress. For this reason a jump instruction should be used first to place the program counter in the right page. The above instructions can then be used to read the look up table data.
Note that the page number n must be greater than zero as some lo cations in page 0 are re­served for specific usage as mentioned. This area may functio n as n ormal pro gram m em ory as required.
The program memory mapping is shown in the diagram.
Stack register
The stack register is a group of registers used to save the contents of th e program counter (PC) and is arranged in 13 bits
× 1 level. One bit is
used to store the carry flag. An interrupt will force the contents o f the PC and the carry flag onto the stack registe r. A subroutine call will
HTG12N0
Program memory PB0=0, PB1=1
Program memory PB0=1, PB1=1
also cause the PC contents to be pushed onto the stack; however the carry flag will not be stored. At the end o f a subroutine or a n inter­rupt routine wh ich is signaled by a re turn in­struction, RET or RETI restore the program counter to its previous value from the stack register. Executing “RETI” instruction will re­store the carry flag from the stack register, but “RET” will not.
Working registers – R0, R1, R2, R3, R4
There are five working regi sters (R0, R1, R2, R3, R4) usually used to store the frequently accessed inter­mediate results. Usin g the instruct ions INC Rn and DEC Rn the working registers can increment (+1) or decrement (–1). The JNZ Rn (n=0,1,4) instruction makes efficient use of the wo rking registers as a program loop counter . Also the r egister pairs R0,R1 and R2,R3 are use d as a data memory pointer when the memory transf er instru ction is executed.
9 18th Mar ’99
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