Holtek Semiconductor Inc HT9580 Datasheet

HT9580

Preliminary

Character Pager Controller

Features

Operating voltage: 2.4V~3.5V

Temperature range: -30°Cto+85°C

low power, high performance M6502 core

low power crystal oscillator control

512/1200/2400 bps data rate operation

²CCIR Radio Paging Code No.1² (POCSAG)

compatible

76.8kHz crystal for all available data rates

High/low system clock switching capability

44 Kbytes program ROM

848 bytes global data RAM

Internal 2 Mbits Character ROM

256 Kbits internal SRAM

External option up to 2 Mbits Character

ROM or 2 Mbits SRAM SED15X(KSX), MC141X and HD66410

series LCD driver compatible interface option 46 bytes message buffer

One 16-bit timer and one 8-bit timer

General Description

The HT9580 is a high performance pager controller which can be used for Chinese Pager system applications. The HT9580 4-in-1 Character Pager Controller combines a POCSAG decoder with a M6502 microprocessor core, 2 Mbits Character ROM and 256 Kbits SRAM to provide both high decoder performance and excellent system flexibility. The decoder utilizes a 2-bit random error correction algorithm and

Internal 2Hz or 1Hz RTC or Real Time

Clock option Single buzzer generator output (BZ) with

duty cycle control low current HALT mode operation

16-bit watchdog timer

Built-in data filter (16-times over-sampling )

and bit clock recovery Advanced synchronization algorithm

2-bit random and (optional) 4-bit burst er

ror correction for address and message Up to 6 user addresses and 6 user frames,

independently programmable 3 RF power-on timing control pins

and Received data inversion (optional) Built in SPI circuit

Out-of-range condition indicator

One internal 8-bit D/A converter

Battery fail and battery low detection

80-pin LQFP package

therefore provides excellent decoder sensitivity. The controller contains a full function pager decoder at a 512, 1200, 2400 bps data rates. Using an M6502 core takes advantage of a flexible external control interface, LCD driver chips and abundant programming resources from worldwide providers. The internal SPI would communicate with SPI of FLEX speed pager decoder.

high

FLEXTMis a trademark of Motorola Inc.

1 April 28, 2000

Block Diagram

Preliminary

HT9580

A10

A11

A12

A13

A14

A15

RA14 RA15 RA16 RA17

P_MO DE

LC D _E

LC D _R W

LCD_CS0

LCD_CS1

LCD_CL

LCD_A0

RSSI

R egister S ection C ontrol Section

Index

R egister

Program

ROM

Index

R egister

S tack P o int R egister (s)

ALU

A ccum ulator

PCL

PCH

Input Data

Latch

(D L )

Data Bus

B u ffe r

C haracter

ROM

WDT

RTC

SRAM

Special B us

Processor Status R egister P

PAC

PBC

PCC

Tone G enerator

ABL

ABH

Address D ecoder

In te rfa c e

M 6502 C o re

LC D

Driver

In te rn a l A D L

Legend

=8 Bit Line

=1 Bit Line

RES

Interrupt

Logic

Instruction

D ecoder

TM R 0 (8 bit)

TM R 1 (16 bit)

IR Q

Interrupt

Logic

NMI

P re -scale r

Logic

NMI IR Q

Tim ing C ontrol

Clock

G enerator/

O scillator

MUX

D u ty C yc le C o n tro l

RDY

SYNC

P H I2 (IN )

PHI1 (OU T) PHI2 (O UT) SO R/W BE

MUX

S ystem C lock

MUX

S ystem C lock

RESET

OSC1

OSC2

D0 D1 D2 D3 D4 D5 D6 D7

TM R 1

PA0~PA5

PB0~PB7

PC0~PC1

BAF

DA_OUT

8-bit D/A

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

Digital

F ilte r

BCH Code

D ecoder

C ontroller

Status

D ata Phase

R eco very

U ser Address

C onfiguration

POCSAG Decoder

R F P ow er C ontroller

and

Memory

D ecoder

Data O utput C ontrol

SPI

Circuit

SPI Control

BS1/SS BS2/SCK BS3/M OSI

D I/M IS O

BAL/SRDY

2 April 28, 2000

Pin Assignment

Preliminary

RESET

OSC2

OSC1

TSC

VSS

TS1

PA2

PA1

PA0

HT9580

BS3/M OSI

BS2/SCK

D I/M IS O

BS1/SS

PA5

PA4

PA3

RSSI

VDD LC D _C S 1 LC D _C S 0

LC D _C L LC D _A 0

LC D _R W

LC D _E

D7 D6 D5 D4 D3 D2 D1 D0

R/W

SRAM _CE MASK_CE

PSEN

H T9580

80 LQ FP

21 40

RA17

RA16

RA15

RA14

P_M ODE

A15

VSS

VDD

A14

A13

A12

A11

A10

6180

DA_OUT BAF

SRD Y/BAL VSS VDD BZ PC1 PC0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 TM R1

A0 A1 A2

3 April 28, 2000

Preliminary

HT9580

Pin Description

Pin No. Pin Name I/O Description

1, 25, 56 VDD

2 LCD_CS1 3 LCD_CS0 4 LCD_CL O LCD driver clock output 5 LCD_A0 O LCD driver data/command select control 6 LCD_RW O LCD Driver Read/Write signal output 7 LCD_E O LCD driver enable clock control 15~8 D0~D7 I/O 8-bit, tristate, bidirectional I/O data bus. 16 R/W

17 SRAM_CE

18 MASK_CE

19 OE

20 PSEN O

21~24 RA17~RA14 O Extended address bus pins

26 P_MODE I

27, 57, 78 VSS

43~28 A0~A15 O

44 TMR1 I Schmitt trigger input for timer1 counter with pull-high resisor.

45~52 PB0~PB7 I/O

53~54 PC0~PC1 I/O

55 BZ O Buzzer non-inverting BZ output

Positive power supply

O LCD driver chip select control (for slave LCD driver) O LCD driver chip select control (for master LCD driver)

O Read/Write signal output

SRAM chip Enable. This signal is generated from the HT9580 to

provide read or write timing for external SRAM devices. (See Ap plication Circuit)

Mask ROM Chip Enable. This signal is generated from the

HT9580 to provide read timing for external Mask ROM devices. (See Application Circuit)

Mask ROM or SRAM Output Enable. This signal is generated

from the HT9580 to provide read timing for external Mask ROM and SRAM devices. (See Application Circuit)

Program Store Enable. This pin is used to connect the OE pins of the external 44 Kbytes program ROM when the ²MODE_P² internal pad is connected to VSS. (See note)

Internal or external program ROM selection without pull-high resistor. If the pin connects to VDD, the internal program ROM will be fetched (normal type), otherwise the external program ROM will be fetched when the pin connects to VSS (Romless).

Negative power supply

Address bus pins. This is used for memory and I/O exchanges on the data bus.

General Input/Output Port B. The input cell structures can be se lected as CMOS or CMOS with pull-high resistors.

General Input/Output Port C. The input cell structures can be se lected as CMOS or CMOS with pull-high resistors.

and CE

4 April 28, 2000

Preliminary

Pin No. Pin Name I/O Description

BAL I Battery voltage detector input with pull-high resistor.

SPI slave ready ¾ This slave ready pin is a Schmitt trigger input

59 BAF 60 DA_OUT O D/A converter output. This pin is an 8-bit D/A analog output

61 RSSI I

66 TS

72~67 PA0~PA5 I/O

73 RESET I Schmitt trigger reset input, active low.

74 TSC

75 TS1

77 76

80 79

SRDY

DI I

MISO I

BS3 O PLL power control enable, CMOS output

MOSI O

BS2 O RF quick charge control enable, CMOS output

SCK I/O

BS1 O Pager receiver power control enable output, CMOS output

OSC1 OSC2

X1 X2

with pull-high resistor. When the slave initiates the SPI transfer,

a high to low transition activates an interrupt. When the master initiates the SPI transfer, a high to low transition trigger the master to start the transfer.

I Battery fail indication input, active low.

RSSI output from IF circuit. This pin should be pulled high or low externally when this pin is not used.

POCSAG code input serial data. CMOS input with pull-high re sistor.

SPI master-in-slave-out ¾ this is the data input with pull-high resistor for SPI communications.

SPI master-out-slave-in ¾ this is the data output for SPI commu nications.

SPI serial clock ¾ the SCK signal is used to synchronize the data transfer. If HT9580 is in the master mode, the SCK is output clock. Otherwise, SCK is input clock if HT9580 is in the slave mode.

SPI slave select ¾ this signal is used to enable the SPI slave for

transfer.

I Decoder test mode input pin, active low with pull-high resistor.

General Input/Output Port A. These ports can be programmed to have a wake-up capability for applications in keyboard operations or as normal I/O. Also the input cell structures are all Schmitt trigger types and can be selected between CMOS or CMOS with pull-high resistors.

mC test mode input pin, active low with internal pull-high resis

tor. The test circuit will be activated when this pin pulls low. Decoder test mode input pin, active low with pull-high resistor.

The internal test mode will be activated when this pin pulls low.

IOOSC1 and OSC2 are connected to an RC network to form a main

clock oscillator

IOX1 and X2 are connected to a crystal to form an internal low power

clock oscillator (32.768kHz, 76.8kHz, or 153.6kHz)

HT9580

5 April 28, 2000

Absolute Maximum Ratings

Preliminary

HT9580

Supply Voltage ..............................-0.3V to 3.6V

Input Voltage .................V

Current Drain Per Pin Excluding V

-0.5V to VDD+0.5V

and VSS............................................................................10mA

Storage Temperature.................-55°Cto150°C

Operating Temperature ..............-30°Cto85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage tothe device.Functional operation of this de vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Symbol Parameter

Operating Voltage

Test Conditions

Conditions

3V application 2.4 3.0 3.5 V

Min. Typ. Max. Unit

Ta=25°C

No load,

STP

IL1

IH1

IL2

IH2

OL1

OH1

OL2

OH2

OSC

Operating Current 3V

HALT Mode Current 3V

Input low Voltage for I/O Port

Input High Voltage for I/O Port

Input low Voltage 3V

Input High Voltage 3V

Input low Voltage (BAF)3V

Input High Voltage (BAF)3V

Output low Voltage 3V

Output High Voltage 3V

I/O Port Sink Current 3V

I/O Port Source Current 3V

BZ, PC0~PC1 Sink Current 3V

BZ, PC0~PC1 Source Current 3V

BS1, BS2, BS3 Sink Current 3V

BS1, BS2, BS3 Source Current 3V

RC Oscillator Resistor 3V

I/O Port Pull-high Resistance

OSC1=1MHz f

=76.8kHz

No load, mC clock stop,

=76.8kHz

¾ ¾ 0.7´V ¾ ¾ ¾¾¾ ¾

=0.3V

=2.7V

=0.3V

=2.7V

=0.3V

=2.7V

=1MHz

OSC

0.7´V

1.0

2.3

2.0 3.6

-1.2 -2.2 ¾

-1.5 -2.5 ¾

350

-1.0 ¾¾

100 250

300

¾¾

0.3´V

¾ 0.3´V ¾ ¾ ¾

¾¾

2 4.5

¾¾mA

¾mA

100

0.9 V

0.4 V

¾ kW

6 April 28, 2000

Preliminary

HT9580

A.C. Characteristics

Symbol Parameter

OSC1

RESET

Main Clock (RC OSC) 3V

Main Clock Duty Cycle 3V

Pager Clock Input (Crystal OSC) 3V

RESET Input Pulse Width

Functional Description

Memory map

0000H

003BH

0040H

006D H

0080H

01C FH 01D 0H

01FFH 0200H

03FFH

1000H

2FFFH 3000H

4FFFH 5000H

I/O and Data Space

G lobal D ata M em ory

60 Bytes

M essage B uffer

46 Bytes

336 Bytes

S tacks

48 Bytes

512 Bytes

Internal/External

C haracter R O M

8 Kbytes

Internal/External

SRAM

8 Kbytes

Test Conditions

Conditions

¾ ¾ ¾

¾¾

1000H

C haracter R O M

2FFFH

Bank0~B ank31 (2 M bits)

1000H

C haracter R O M

2FFFH

Bank0~B ank31 (2 M bits)

Ta=25°C

Min. Typ. Max. Unit

76.8 1000 2000 kHz

40 50 60 %

32.768 76.8 153.6 kHz

Internal

Space (Bank 0) 8 Kbytes

External

Space (Bank 0) 8 Kbytes

¾¾

BFFFH

C 000H

FFFAH

FFFBH

FFFCH

FFFDH

FFFEH

FFFFH

Program R O M S pace

28 KB ytes

Program R O M S pace

16378 Bytes

NMI-L

NMI-H

RESET-L

RESET-H

IR Q - L

IR Q - H

3000H

4FFFH

3000H

4FFFH

Internal

SRAM

Space (Bank 0) 8 Kbytes

Bank0~B ank3 (32 K B ytes)

External

SRAM

Space (Bank 0) 8 Kbytes

Bank0~B ank31 (256 K B ytes)

7 April 28, 2000

Preliminary

HT9580

HT9580 memory mapping table (I/O and data space)

Address

0000H Config. HALT CLK_SEL OSC_MOD LPM RTC BZ_CLK MDUT MGEN 0001 0000

0001H WDT-TMR X X TMR0_PR1 TMR0_PR0 WDTEN WS2 WS1 WS0 0000 0111

0002H CLR WDT X X X X X X X X uuuu uuuu

0003H BZ-L BZL7 BZL6 BZL5 BZL4 BZL3 BZL2 BZL1 BZL0 0000 0000

0004H BZ-H BZH7 BZH6 BZH5 BZH4 BZH3 BZH2 BZH1 BZH0 0000 0000

0005H INT ctrl 0 0 0 RTCEN ORMSK RTCMSK TM1IMSK TM0IMSK 0000 1111

0006H INT flag 0 RTC_FG DR_FG BF_FG WDTOVFG OR_FG TM1OVFG TM0OVFG 0000 0000

0007H TMRC TMR1MOD X TMR1CLK TMR0CLK TMR1EDG TMR0EDG TMR1EN TMR0EN 0000 0000

0008H TMR1L TM1D7 TM1D6 TM1D5 TM1D4 TM1D3 TM1D2 TM1D1 TM1D0 uuuu uuuu

0009H TMR1H TM1D15 TM1D14 TM1D13 TM1D12 TM1D11 TM1D10 TM1D9 TM1D8 uuuu uuuu

000AH TMR0 TM0D7 TM0D6 TM0D5 TM0D4 TM0D3 TM0D2 TM0D1 TM0D0 uuuu uuuu

000BH PA data X X PA5 PA4 PA3 PA2 PA1 PA0 uu11 1111

000CH PB data PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 1111 1111

000DH PC data X X X X X X PC1 PC0 uuuu uu11

000EH PAC X X PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 uu11 1111

000FH PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC3 PBC1 PBC0 1111 1111

0010H PCC X X X X X X PCC1 PCC0 uuuu uu11

0011H PA WUE X X PAWUE5 PAWUE4 PAWUE3 PAWUE2 PAWUE1 PAWUE0 uu00 0000

0012H PA IM X X PAIM5 PAIM4 PAIM3 PAIM2 PAIM1 PAIM0 uu11 1111

0013H PB IM PBIM7 PBIM6 PBIM5 PBIM4 PBIM3 PBIM2 PBIM1 PBIM0 1111 1111

0014H PC IM X X X X X X PCIM1 PCIM0 uuuu uu11

0015H MROM-BP BP_MODM1 BP_MODM0 M_BP5 M_BP4 M_BP3 M_BP2 M_BP1 M_BP0 0000 0000

0016H SRAM-BP BP_MODS1 BP_MODS0 S_BP5 S_BP4 S_BP3 S_BP2 S_BP1 S_BP0 0000 0000

0017H LCD_CTRL LCD-CHIP1 LCD-CHIP0 LCD-CLK CLK-MOD LCD-CS1 LCD-CS0 LCD-A0 LCD-WRB 0000 1101

0018H LCD_CMD LCD_D7 LCD_D6 LCD_D5 LCD_D4 LCD_D3 LCD_D2 LCD_D1 LCD_D0 uuuu uuuu

0019H

001AH~

002EH

002FH D/A-L DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0000 0000

0030H D/A-H X X X X X D/A_PD RSSI BAT uuuu u1uu

0031H

0032H SPI-CONFIG S/M LEN1 LEN0 REQST SPIFG CLK_EDG SPI_EN START 0111 1000

0033H SPI-SPEED SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 0000 0000

0034H SPI-OUT3 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000

0035H SPI-OUT2 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000

0036H SPI-OUT1 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000

0037H SPI-OUT0 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000

0038H SPI-IN3 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000

0039H SPI-IN2 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000

003AH SPI-IN1 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000

003BH SPI-IN0 D7 D6 D5 D4 D3 D2 D1 D0 0000 0000

Name

Decoder Control/

flag

Decoder

Configuration

Memory

Buffer

Status

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

XBL

MSG_END X count_5 count_4 count_3 count_2 count_1 count_0 0uuu uuuu

OR X STB X RES ON uu0u uu01

State on

uuuu uuuu

POR

8 April 28, 2000

Preliminary

HT9580

HT9580 memory attribute table (I/O and data space)

Address

0000H Config. R/W R/W R/W R/W R/W R/W R/W R/W 0001 0000

0001H WDT-TMR X X R/W R/W R/W R/W R/W R/W 0000 0111

0002H CLR WDT W W W W W W W W uuuu uuuu

0003H BZ-L R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0004H BZ-H R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0005H INT ctrl 0 0 0 R/W R/W R/W R/W R/W 0000 1111

0006H INT flag 0 R/W R/W R R/W R/W R/W R/W 0000 0000

0007H TMRC R/W X R/W R/W R/W R/W R/W R/W 0000 0000

0008H TMR1L R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu

0009H TMR1H R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu

000AH TMR0 R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu

000BH PA data X X R/W R/W R/W R/W R/W R/W uuuu uuuu

000CH PB data R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu

000DH PC data X X X X X X R/W R/W uuuu uuuu

000EH PAC X X R/W R/W R/W R/W R/W R/W uu11 1111

000FH PBC R/W R/W R/W R/W R/W R/W R/W R/W 1111 1111

0010H PCC X X X X X X R/W R/W uuuu uu11

0011H PA WUE X X R/W R/W R/W R/W R/W R/W uu00 0000

0012H PA IM X X R/W R/W R/W R/W R/W R/W uu00 0000

0013H PB IM R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0014H PC IM X X X X X X R/W R/W uuuu uu00

0015H MROM-BP R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0016H SRAM-BP R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0017H LCD_CTRL R/W R/W R/W R/W R/W R/W R/W R/W 0000 1101

0018H LCD_CMD R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu

0019H

001AH~

002EH

002FH D/A-L R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0030H D/A-H X X X X X R/W R R uuuu u1uu

0031H

0032H SPI-CONFIG R/W R/W R/W R R R/W R/W R/W 0111 1000

0033H SPI-SPEED R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0034H SPI-OUT3 R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0035H SPI-OUT2 R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0036H SPI-OUT1 R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0037H SPI-OUT0 R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000

0038H SPI-IN3 R R R R R R R R 0000 0000

0039H SPI-IN2 R R R R R R R R 0000 0000

003AH SPI-IN1 R R R R R R R R 0000 0000

003BH SPI-IN0 R R R R R R R R 0000 0000

Note:

Name

Decoder Control/

flag

Decoder

Configuration

Memory

Buffer

Status

²R² Read Only ²W² Write Only ²R/W² Read or Write ²X² N/A

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X R/W R X R X R/W R/W uu0u uu01

R/W R/W R/W R/W R/W R/W R/W R/W uuuu uuuu

R X R R R R R R 0uuu uuuu

State on

POR

9 April 28, 2000y

Preliminary

HT9580

Configuration register

Address

0000H Config. HALT CLK_SEL OSC_MOD LPM RTC BZ_CLK MDUT MGEN 0001 0000

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

State on

POR

Oscillator configuration

There are two clock source input pins on the chip, the main clock and the pager decoder in put clock. The main clock is generated by an RC network. The system clock may be the OSC in put or the X1-clock depending on bit ²CLK_SEL². The pager decoder input clock co mes from two external pins, X1 and X2. The fre quency of the sub-clock will be double that of the X1, X2 input clock. The OSC1 main clock will be generated from an RC network that needs an external resistor (see Application Cir cuit). The system clock may be X1-clock, DF or RC clock. If no higher frequency (RC) is needed, the external resistor between OSC1 and OSC2 can be removed. The system clock can be switched by bit ²CLK_SEL².If²CLK_SEL²=0 (POR State), the system clock will be X1-clock. In other cases, with ²CLK_SEL²=1, the OSC in put clock will be the system clock. The clock switching function will assist software programmers to change the mC system clock within an adequate time if necessary. The

OSC1

OSC_MOD

0: R C 1 : D F

OSC

C ontrol

OSC Input

HALT

Main

Clock

Frequency

Sub-clock

²OSC_MOD² bit selects the OSC input clock to be either RC or DF. If ²OSC_MOD² is set to ²low² then the RC configuration is selected, oth

erwise the DF application is selected. The pro

grammer should note that the condition of

²CLK_SEL², ²HALT² and ²OSC_MOD² assures

that the system clock is working properly. It is

recommended that the OSC clock source is ei

ther DF or RC. If DF and RC are necessary, it is

required to switch the system clock to X1-clock before switching between DF and RC. Then switch the system clock back to the OSC input

by using bit CLK_SEL if the switching action of

DF and RC is complete. Before enter HALT mode, the system clock must select X1-clock.

The HT9580 will generate two RTC frequen cies, 1Hz and 2Hz respectively, determined by bit RTC. If the bit is logic low, the 1Hz RTC fre

quency will be selected, otherwise the 2Hz RTC frequency will be selected. The RTC counter is enabled/disabled by bit RTCEN and can be masked or not masked as determined by the bit RTCMSK of the interrupt control register

SST

D oubler

X1-clock

10-bit R ipple

C ounter

SST Control

X1-clock

C lock S e lect

CLK_SEL

C ounter

S ystem C lock

0: X 1-clock 1: O SC Input

1H z & Tim e O ut

2H z & Tim e O ut

RTC block diagram

10 April 28, 2000

RTC Tim e Out

RTC

Preliminary

(0005H). If the RTC counter is enabled, the RTC counter will start to count. The RTC coun ter source clock is the X1-clock, so the X1 clock setting via by SPF12, SPF13 and SPF14 should be correct.

In order to guarantee that the system clock has started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulse when the system is powered up.

Select 2Hz as the

RTC

The low power oscillator of the pager decoder input clock should be crystal type. The decoder subsystem low power oscillator, on the other hand, is of a crystal type which is designed with a power on start-up function to reduce the sta bilization time of the oscillator. This start-up function is enabled by bit ²LPM² which is ini tially set high at power on reset, and should be cleared to low so as to enable the low-power os cillator function. The oscillator configuration is running in the low power mode.

The system clock oscillator can be enabled/dis abled by the register bit, ²HALT². The system clock circuit is powered down, when the bit is set to high. On the other hand, the system clock

Select 1Hz as the RTC

100k

50k

100k

VSS

L o w p o w e r o s c illa to r fu n c t io n

LPM (Low power m ode control)

H T 9580

low power oscillator

circuit is powered up, when the bit is low. When this bit is set high, the CPU is also stopped.

When this bit is cleared low, the CPU core re turns to its normal operation. After this is set

HIGH by the software, it may also be cleared

low when reset, interrupt (IRQ

timeout, and port wake-up conditions are met.

or NMI), RTC

HALT

System clock enable

System clock powered down

The WDT is a 16-bit counter and sourced by the

HT9580

WDT-TMR (Watchdog timer) register

Address

0001H WDT-TMR X X TMR0_PR1 TMR0_PR0 WDTEN WS2 WS1 WS0 0000 0011

0002H CLR WDT XXXXXXXXuuuu uuuu

sub-clock divided by 8. The counter is seg mented as a 9-bit prescaler and a 7-bit user pro grammable counter. The input clock is first divided by 512 (9-stage) to get the nominal time-out period. The output of the 9-bit pre-scaler can then be divided by a 7-bit pro grammable counter to generate the longer watchdog time-out depending on the user¢sre quirements. The 7-bit programmable counter is controlled by 3 register bits, WS0~2. The watchdog timer is enabled/disabled by a control bit WDTEN. To prevent the overflow of this

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

be executed before the timer overflows. The clear-WDT operation is to write any number to

the register, CLRWDT (0002H). When the watchdog timer overflows (checked by bit 3 of 0006H ²WDTOVFG²), the program counter is

set to FFFC H and FFFD H to read the program start vector. The definitions of the control bits are listed below.

WDTEN

Enable the watchdog timer

Disable the watchdog timer

watchdog timer, a clear-WDT operation should

11 April 28, 2000

State on

POR

Preliminary

HT9580

The WDT 7-bit counter is programmed by bits WS0~WS2. The division ratio for the counter is listed in the table.

WS2 WS1 WS0

Division

Ratio

0001:1 0011:2 0101:4 0111:8 1 0 0 1:16

The other pair ²TMR0_PR0² and ²TMR0_PR1² are used to select the prescaler ratio for timer0. The definition is shown in the table.

TMR0

TMR0_PR1 TMR0_PR0

Prescaler

Ratio

0 0 1/4

0 1 1/8

1 0 1/16

1 1 1/32

1 0 1 1:32 1 1 0 1:64 1 1 1 1:128

X1-clock

W S0~2 W DT tim e-out

7-bit C ounter1 /8 9-bit P rescaler

8 to 1 M U X

Buzzer generator registers

Address

0003H BZ-L BZL7 BZL6 BZL5 BZL4 BZL3 BZL2 BZL1 BZL0 0000 0000

0004H BZ-H BZH7 BZH6 BZH5 BZH4 BZH3 BZH2 BZH1 BZH0 0000 0000

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

State on

POR

The buzzer generator is composed of a 16-bit PFD counter and aduty cycle control. The counter value is set by two registers, namely BZ-H and BZ-L. The source for this generator may be the system clock or the X1-clock. The buzzer generator is enabled/disabled by the register bit ²MGEN² in the configuration regis ter(0000H). When this bit is set high, the buzzer generator is activated. There is another bit in the configuration register(0000H) which controls the buzzer output volume, bit ²MDUT². If the bit is logic high, the output of the BZ will be modulated by the X1-clock. The

clock source of the buzzer is selected by bit ²BZ_CLK². When BZ_CLK=0, the clock source is the system clock. On the other hand, when BZ_CLK=1, the value of the selector will be the X1-clock.

The truth table for enabling/disabling the

buzzer generator is shown in the table.

MGEN

12 April 28, 2000

Enable the buzzer generator

Disable the buzzer generator

Preliminary

HT9580

When BZ-L and BZ-H are all 00H, the tone gen erator is disabled and BZ is high. The value of the frequency divider, ranges from 2 (BZ-L=01H, BZ-H=00H)~65536 (BZ-L=FFH, BZ-H=FFH). Writing to BZ-L only writes the data into a low byte buffer, while writing to BZ-H will write the high byte data and the con tents of the low byte buffer into the PFD coun ter.

When the buzzer generator is disabled by clearing the ²MGEN² bit in the configuration register (0000H), the BZ pin remains at its last state. If the BZ pin is low, the BZ transistor in

System C lock

X1-clock

BZ_C LK=0

BZ_C LK=1

BZ_C LK

MDUT=0

MDUT=1

the application circuits is always active. There

fore it is recommended that both BZ-L and BZ-H be cleared and that the ²MGEN² bit in the configuration register (0000H) also be cleared, when it is desired to disable or stop the buzzer.

The output of the 16-bit PFD counter is divided

by 2 to generate a BZ output with or without

modulation. For example, if the desired output

of BZ is 1.6kHz with modulation and the fre quency source is X1-clock (76.8kHz), then the value of 16-bit PFD counter is set to BZ-L=17H, BZ-H=00H and ²MDUT² is set high.

X1-clock

16-bit

PFD C ounter

MGEN

PW M

M odulator

MDUT

Interrupt registers

Address

0005H INT ctrl 0 0 0 RTCEN ORMSK RTCMSK TM1IMSK TM0IMSK 0000 1111

0006H INT flag 0 RTC_FG DR_FG BF_FG WDTOVFG OR_FG TM1OVFG TM0OVFG 0000 0000

Name

There are two interrupts for the HT9580: a Non-Mask Interrupt (NMI) and a generic interrupt request (IRQ). The data ready interrupt and battery fail interrupt share the NMI call lo cation. Which interrupt occurred can be deter mined by checking bit BF_FG and the data ready interrupt bit DR_FG or SPI complete flag SPIFG (in SPI-CONFIG register). DR_FG is the data ready interrupt indication bit. When a valid call is detected, data begins to transfer. Either one call is terminated or a message buffer is full or one batch is over but the mes sage is not terminated, the data ready inter rupt will occur and DR_FG is set high. The DR_FG bit should be cleared low by the mC soft ware after a data ready condition has occurred.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

A battery fail condition is triggered by a high to low transition on pin BAF

and will set the bat-

tery fail interrupt request flag BF_FG to logic

high. For details, refer to the POCSAG Decoder

section. The sources for the IRQ are timer 0 overflow, timer 1 overflow, out-of-range status changes and RTC time out. The four interrupt sources all could be masked, but the four corre sponding interrupt flags will still be set when the interrupt conditions are met. All the four flags are readable/writeable. When an inter

rupt condition is met, a flag will be set. If an in

terrupt routine is performed, the software should check which flag is set to high then de termine what kind of interrupt source occurred.

The WDTOVFG is the flag for the watchdog

13 April 28, 2000

State on

POR

Preliminary

HT9580

timer overflow and RTC_FG is an indicator for the RTC time out interrupt request flag. The OR_FG will be set high when an out-of-range status from low to high or high to low transition occurrs. Those flags such as TM0OVFG, TM1OVFG, BF_FG, DR_FG, OR_FG and RTC_FG should be cleared by the software af ter they are activated.

RTCEN

RTCMSK

TM0IMSK

TM1IMSK

ORMSK

RTC counter is enabled

RTCinterrupt

is masked

Timer 0 overflow interrupt is masked

Timer 1 overflow interrupt is masked

Out-of-range interrupt is masked

RTC counter is disabled

RTC interrupt is not masked

Timer0overflow interruptisnot masked

Timer 1 overflow interrupt is not masked

Out-of-range interrupt is not masked

D ata R eady

SPI Reqst

TM 0/1IM S K

TM 0/1O VFG

RTC_FG

RTCM SK

OR_FG

ORMSK

B a tte ry F a il

TM0OVFG

TM1OVFG

WDTOVFG

BF_FG

DR_FG

OR_FG

RTC_FG

NMI

M 6502

Core

IR Q

Timer 0 overflows

Timer 1 overflows

Watchdog timer has overflown

Battery fail request

Data ready request

Out-of-range request

RTC interrupt request

No timer 0 overflow

No timer 1 overflow

No watchdog timer overflow

No battery fail request

No data ready request

No out-of-range request

No RTC interrupt request

Block diagram of NMI and IRQ

14 April 28, 2000

Preliminary

HT9580

IR Q

TM 0IM SK

TM 1IM SK

TM 0OV FG

TM 1OV FG

tim e r 0

overflow

M asked by TM 0OV FG

tim e r 1

overflow

Timer0 and Timer1 timing diagram

Reset conditions

The HT9580 will reset the whole chip when the following conditions are met:

Power On

The external RESET pin is held low for at least 1 ms

The WDT overflows

The input is used to reset the mC. Reset must be held low at least 1 ms after VDD reaches operating voltage from a power down. A positive

tim e r 0

overflow

C leared by softw are C leare d by softw are

overflow

M asked by

TM 0IM SK

tim e r 1

tim e r 0

overflow

M asked by TM 1OV FG

tim e r 0

overflow

C leared by softw areC leare d by softw areC leared by softw are

tim e

transition on the chip reset will then cause an initialization sequence to begin. After the sys tem is operating, a low on this line of at least 1 ms in duration will cause mC activity. When a positive edge is detected, there is an initialization sequence lasting 8-clock cycles. Then the interrupt mask flag is set, the decimal mode is cleared and the program counter is loaded with the restart vector from locations FFFC (low byte) and FFFD (high byte). This is the start location for program control. This input should be high during normal operation.

15 April 28, 2000

5000H

FFFAH

FFFBH

FFFCH

Preliminary

Program R O M Space

D ata R eady & Battery Fail Service R outine Vector Low B yte

D ata R eady & Battery Fail Service R outine Vector H igh Byte

Program R eset Vector Low B yte

HT9580

RESET

VDD

RESET

OSC Tim e-Out

FFFDH

FFFEH

FFFFH

RESET

Program R eset Vector H igh Byte

IR Q S ervice R outine Vector Low Byte

IR Q S ervice R outine Vector H igh B yte

In te rn a l P u ll-u p

S ystem C lock

10-bit R ipple Counter

1024 C lock C ycles

H T 9580

Pow er O n Detector

C hip R eset G enerator

W DT O verflow

VDD

8 C lo ck C ycles

RESET

WDT Time-Out

C hip R eset

Power on reset timing

C hip R eset

RESET active and WDT time-out

16 April 28, 2000

Preliminary

HT9580

Timer registers

Address

0007H TMRC TMR1MOD X TMR1CLK TMR0CLK TMR1EDG TMR0EDG TMR1EN TMR0EN 0u00 0000

0008H TMR1L TM1D7 TM1D6 TM1D5 TM1D4 TM1D3 TM1D2 TM1D1 TM1D0 uuuu uuuu

0009H TMR1H TM1D15 TM1D14 TM1D13 TM1D12 TM1D11 TM1D10 TM1D9 TM1D8 uuuu uuuu

000AH TMR0 TM0D7 TM0D6 TM0D5 TM0D4 TM0D3 TM0D2 TM0D1 TM0D0 uuuu uuuu

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

State on

POR

In addition to the watchdog timer, the HT9580 provides two timers: an 8-bit timer (timer 0) and one 16-bit timer (timer 1). Those two timers are controlled and configured by the register TMRC. Both timers are programmable up-count coun ters whose clocks may be derived from the X1-clock (32.768kHz, 76.8kHz or 153.6kHz). To program the timers, TMR0, TMR1L, and TMR1H should be written with a start value. When the timers are enabled, they will count-up from the start value. If the timers overflow, cor responding interrupts will be generated. When the timers are disabled, the counter contents will not be reset. To reset the counter contents, the software should write the start value again. Since timer1 is a 16-bit counter, it is important to note the method of writing data to both TMR1L and TMR1H. Writing to TMR1L only writes the data into a low byte buffer, while writing to TMR1H will simultaneously write the high byte data and the contents of the low byte

Labels (TMRC0

and TMRC1)

TMR0EN, TMR1EN

TMR0EDG, TMR1EDG

TMR0CLK 4

TMR1CLK 5

TMR1MOD 7

Bits Function

01Enable/disable timer counting

(0=disable; 1=enable)

23Define the TMR0 and TMR1 active edge

(0=active on low to high; 1=active on high to low)

Select TMR0 clock source (0=X1-clock; 1=OSC1 input clock/system clock)

Select TMR1 clock source if internal clock input is selected (0=X1-clock; 1=OSC1 input clock/system clock)

Define the TMR1 operation mode (0=internal clock input; 1=external clock input)

buffer into the Timer Counter preload register (16-bit). Note that the Timer counter preload register contents are changed by a TMR1H write operation while writing to TMR1L does not change the contents of the preload register.

Reading TMR1H will also latch the contents of TMR1L into the byte buffer to avoid false timing problem. Reading TMR1L returns the contents of the low byte buffer. In other words, the low byte of the timer counter cannot be read directly. It must first read TMR1H to latch the low byte

contents of the timer counter into the buffer. TMRC is the timer counter control register, which defines the timer counter options. The timer1 clock source can be selected from either the internal clock or an external input clock by bit TMR1MOD of the TMRC register. The timer0/timer1 can also select its clock source by bits TMR0CLK/TMR1CLK. TMRC as shown in the table.

17 April 28, 2000

S ystem C lock

X1-Clock

TM R0CLK

Preliminary

Tim er C ounter

Preload R egister

HT9580

Data Bus

R eload

S ystem C lock

X1-Clock

TM R1

P re scaler

TM R1CLK

TM R1M O D

Edge S elect

TM R0ED GTM R 0_PR 0TM R 0_PR 1

Timer 0 block diagram

Tim er/event C ounter

Preload R egister

Edge S elect

TM R1ED G

Timer 1 block diagram

Tim er 0 C ounter

(8 -b it)

TM R0EN

Tim er 1 C ounter

(16-bit)

TM R1EN

O verflow To Interrupt

Data Bus

R eload

O verflow T o In te rru p t

18 April 28, 2000

Preliminary

HT9580

I/O port configuration registers

Address

000BH PA data X X PA5 PA4 PA3 PA2 PA1 PA0 uu11 1111

000CH PB data PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 1111 1111

000DH PC data XXXXXXPC1PC0uuuu uu11

000EH PAC X X PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 uu11 1111

000FH PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 1111 1111

0010H PCC XXXXXXPCC1 PCC0 uuuu uu11

0011H PA WUE X X PAWUE5 PAWUE4 PAWUE3 PAWUE2 PAWUE1 PAWUE0 uu00 0000

0012H PA IM X X PAIM5 PAIM4 PAIM3 PAIM2 PAIM1 PAIM0 uu11 1111

0013H PB IM PBIM7 PBIM6 PBIM5 PBIM4 PBIM3 PBIM2 PBIM1 PBIM0 1111 1111

0014H PC IM XXXXXXPCIM1 PCIM0 uuuu uu11

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

State on

POR

The HT9580 has three general purpose I/O ports. The I/O cell structures are configurable. Details are shown in the table.

Port A

Port A is a general-purpose I/O port. The PAC register controls the data directions for port A. When set as input data type, this port has wake-up capability and the input cell struc tures are schmitt trigger types. While in a ²HALT² condition, a falling edge signal on Port A can wake-up the mC. In addition, the input cell structures can be configured as pull-high or non-pull-high. When set as an output datatype, the output structures are CMOS outputs.

The pin output logic high

The pin output logic low

PAC As input pin As output pin

PAWUE

PAIM

The pin has wake-up capability

CMOS input structure with pull-high resistor

The pin has no wake-up capability

CMOS input structure without pull-high resistor

Port B

Port B is a general-purpose I/O port controlled by the PBC register. The PBIM register con trols the input cell structures: normal CMOS inputs or CMOS inputs with pull-high resis tors.

Pin output logic high

Pin output logic low

PBC Input pin Output pin

PBIM

CMOS input structure with pull-high resistor

CMOS input structure without pull-high resistor

Port C

This is a general-purpose I/O port contolled by the PCC register. The PCIM register controls the input cell structures: normal CMOS inputs or CMOS inputs with pull-high resistors.

The pin output logic high

The pin output logic low

PCC As input pin As output pin

CMOS input structure without pull-high resistor

PCIM

CMOS input structure with pull-high resistor

19 April 28, 2000

+ 44 hidden pages

Holtek Semiconductor Inc HT9580 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pin Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description