counter with PFD (programmable fre
quency divider) function
LCD driver with 33 ´ 3or32´ 4 segments
·
4K ´ 15 program memory ROM
·
160 ´ 8 data memory RAM
·
Real Time Clock (RTC)
·
8-bit prescaler for RTC
·
Watchdog timer
·
General Description
The HT49C50 is an 8-bit high performance single
chip microcontroller. Its single cycle instruction
and two-stage pipeline architecture make it suit
able for high speed applications. The device is
suited for use in multiple LCD low power applica-
HT49C50
8-Bit Microcontroller
Buzzer output
·
On-chip crystal and RC oscillator
·
Halt function and wake-up feature reduce
·
power consumption
6-level subroutine nesting
·
-
-
Bit manipulation instruction
·
15-bit table read instruction
·
Up to 1ms instruction cycle with 4MHz
·
system clock
63 powerful instructions
·
All instructions in 1 or 2 machine cycles
·
80/100-pin QFP package
·
tions among which are calculators, clock timers,
games, scales, leisure products, other hand held
LCD products, and battery system in particular.
* The IC substrate should be connected to VSS in the PCB layout artwork.
5August 18, 1999
Pin Description
HT49C50
Pin NameI/O
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
PB0/INT0
PB1/INT1
PB2/TMR0
PB3/TMR1
PB4~PB7
PC0~PC3I/O
VSSI
VLCDI
V1,V2,C1,C2I
SEG32/COM3
COM2~COM0
SEG31~SEG0O
OSC4
OSC3
VDD
OSC2
OSC1
RES
I/O
O
O
I
¾¾
OICrystal or
I
I
Mask
Option
Wake-up
Pull-high
or None
CMOS or
NMOS
¾
Pull-high
or None
CMOS or
NMOS
¾
¾
¾
1/3 or 1/4
Duty
¾
¾
RC
¾
Description
PA0~PA7 constitute an 8-bit bidirectional input/output port
with Schmitt trigger input capability. Each bit on port can be
configured as a wake-up input by mask option. PA0~PA3 can be
configured as a CMOS output or NMOS input/output with or
without pull-high resistor by mask option. PA4~PA7 are al
ways pull-high NMOS input/output. Of the eight bits,
PA0~PA1 can be set as I/O pins or buzzer outputs by mask op
tion. PA3 can be set as an I/O pin or as a PFD output also by
mask option.
PB0~PB7 constitute an 8-bit Schmitt trigger input port. Each
bit on port are pull-high resistor. Of the eight bits, PB0 and PB1
can be set as input pins or as external interrupt control pins
(INT0
) and (INT1) respectively, by software application. PB2
and PB3 can be set as an input pin or as a timer/event counter
input pin TMR0 and TMR1 also by software application.
PC0~PC3 constitute a 4-bit bidirectional input/output port
with a schmitt trigger input capability. On the port, such can be
configured as CMOS output or NMOS input/output with or
without pull-high resistor by mask option.
Negative power supply, GND
LCD power supply
Voltage pump
SEG32 can be set as a segment or as a common output driver for
LCD panel by mask option. COM2~COM0 are outputs for LCD
panel plate.
LCD driver outputs for LCD panel segments
Real time clock oscillators
Positive power supply
OSC1 and OSC2 are connected to an RC network or a crystal
(by mask option) for the internal system clock. In the case of RC
operation, OSC2 is the output terminal for 1/4 system clock.
Schmitt trigger reset input, active low
-
-
6August 18, 1999
Absolute Maximum Ratings
HT49C50
Supply Voltage........................VSS-0.3V to 5.5V
Input Voltage .................V
-0.3V to VDD+0.3V
SS
Storage Temperature.................-50°Cto125°C
Operating Temperature ..............-25°Cto70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo
sure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
SymbolParameter
V
I
DD1
I
DD2
I
STB1
I
STB2
V
V
V
V
I
OL
DD
IL
IH
IL1
IH1
Operating Voltage
Operating Current
(Crystal OSC)
Operating Current (RC OSC)
Standby Current
(RTC Enable, LCD ON)
Standby Current
(RTC Disable, LCD OFF)
I/O Port Input Low Voltage
I/O Port Input High Voltage
Input Low Voltage
(RES
, INT0, INT1, TMR0, TMR1)
Input High Voltage
(RES
, INT0, INT1, TMR0, TMR1)
I/O Ports Sink Current
DD
Conditions
V
¾¾
3V
No load,
f
=4MHz
SYS
5V
3V
No load,
=2MHz
f
SYS
5V
3V
No load,
system halt
5V
3V
No load,
system halt
5V
3V
5V
3V
5V
3V
RES
¾
¾
¾
¾
=0.5V
DD
INT0/1=0.3V
5V0
TMR0/1=0.3V
3V
0.8V
5V4.0
3V
5V
DD
=3V,
V
DD
V
=0.3V
OL
=5V,
V
DD
V
=0.5V
OL
Min. Typ. Max. Unit
2.2
¾
¾
¾
¾
¾
12mA
2.55mA
0.751.5mA
1.53mA
¾¾
¾¾
¾¾
¾¾
0
¾
0
¾
2.1
3.5
DD
DD
2.4
¾
¾
0
¾
¾
1.5/0.9V
2.5/1.5V
¾
¾
1.52.5
46
5.2V
5
mA
10
mA
1
mA
2
mA
0.9V
1.5V
3V
5V
3V
5V
mA
¾
mA
¾
-
-
7August 18, 1999
HT49C50
SymbolParameter
I
OH
R
PH
I/O Ports Source Current
Pull-high Resistance of
I/O Ports and INT0
A.C. Characteristics
SymbolParameter
f
SYS1
f
SYS2
f
TIMER
t
WDTOSC
t
RES
t
SST
t
INT
System Clock (Crystal OSC)
System Clock (RC OSC)
Timer I/P Frequency
(TMR0/TMR1)
Watchdog Oscillator
External Reset Low
Pulse Width
System Start-up
Timer Period
Interrupt Pulse Width
, INT1
Test Conditions
DD
Conditions
=3V,
V
DD
V
=2.7V
OH
V
=5V,
DD
V
=4.5V
OH
¾
¾
V
3V
5V
3V
5V
Test Conditions
V
DD
3V
5V
3V
5V
3V
5V
3V
5V
Conditions
V
=3V
DD
V
=5V
DD
V
=3V
DD
V
=5V
DD
V
=3V
DD
V
=5V
DD
V
=3V
DD
V
=5V
DD
¾¾
Power-up or
¾
wake-up from halt
¾¾
Min. Typ. Max. Unit
-1-1.5¾
-2-3¾
406080
103050
mA
mA
kW
kW
Ta=25°C
Min.Typ.Max. Unit
455
455
400
400
0
0
4590180
3565130
1
1024
¾
1
4000kHz
¾
4000kHz
¾
2000kHz
¾
3000kHz
¾
4000kHz
¾
4000kHz
¾
ms
ms
¾¾ms
t
¾
SYS
¾¾ms
Note: t
SYS
= 1/f
SYS
8August 18, 1999
Functional Description
Execution flow
The system clock is derived from either a crys
tal or an RC oscillator. It is internally divided
into four non-overlapping clocks. One instruc
tion cycle consists of four system clock cycles.
Instruction fetching and execution are
pipelined in such a way that a fetch takes one
instruction cycle while decoding and execution
takes the next instruction cycle. The pipelining
scheme causes each instruction to effectively
execute in a cycle. If an instruction changes the
value of the program counter, two cycles are re
quired to complete the instruction.
Program counter - PC
The program counter (PC) is of 12 bits wide and
controls the sequence in which the instructions
stored in the program ROM are executed. The
contents of the PC can specify a maximum of
4096 addresses.
After accessing a program memory word to
fetch an instruction code, the value of the PC is
incremented by one. The PC then points to the
memory word containing the next instruction
code.
When executing a jump instruction, conditional
skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a
subroutine, the PC manipulates the program
transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instruc
tions. Once the condition is met, the next in
struction, fetched during the current
instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruc
tion; otherwise proceed with the next instruc
tion.
The lower byte of the PC (PCL) is a readable
and writeable register (06H). Moving data into
the PCL performs a short jump. The destina
tion is within 256 locations.
When a control transfer takes place, an addi
tional dummy cycle is required.
Program memory - ROM
The program memory (ROM) is used to store
the program instructions which are to be exe
cuted. It also contains data, table, and inter
rupt entries, and is organized into 4096 ´ 15
bits which are addressed by the PC and table
pointer.
Certain locations in the ROM are reserved for
special usage:
·
Location 000H
Location 000H is reserved for program initial-
ization. After chip reset, the program always
begins execution at this location.
HT49C50
-
-
-
-
-
-
-
-
S ystem C lock
OSC2 (RC only)
PC
T1T2T3T4T1T2T3T4T1T2T3T4
PCPC+1PC+2
F e tc h IN S T ( P C )
Execute IN S T (P C-1)
F e tc h IN S T ( P C + 1 )
Execute IN S T (P C)
F e tc h IN S T ( P C + 2 )
Execute IN S T (P C+1)
Execution flow
9August 18, 1999
HT49C50
·
Location 004H
Location 004H is reserved for the external in
terrupt service program. If the INT0
input
pin is activated, and the interrupt is enabled,
and the stack is not full, the program begins
execution at location 004H.
·
Location 008H
Location 008H is reserved for the external in
terrupt service program also. If the INT1
put pin is activated, and the interrupt is
in
-
-
-
000H
004H
008H
00C H
010H
014H
018H
D evice initialization program
External interrupt 0 subroutine
External interrupt 1 subroutine
Tim er/event counter 0 interrupt subroutine
Tim er/event counter 1 interrupt subroutine
T im e B a s e In te rr u p t
R T C In te rru p t
Program
ROM
enabled, and the stack is not full, the program
begins execution at location 008H.
·
Location 00CH
n00H
nFFH
Look-up table (256 w ords)
Location 00CH is reserved for the timer/event
counter 0 interrupt service program. If a
timer interrupt results from a timer/event
counter 0 overflow, and if the interrupt is en
abled and the stack is not full, the program
begins execution at location 00CH.
·
Location 010H
Location 010H is reserved for the timer/event
counter 1 interrupt service program. If a
timer interrupt results from a timer/event
Mode
*11 *10 *9*8*7*6*5*4*3*2*1*0
FFFH
-
counter 1 overflow, and if the interrupt is en
abled and the stack is not full, the program
begins execution at location 010H.
Program Counter
Look-up table (256 w ords)
15 bits
N o te : n r a n g e s fro m 0 to F
Program memory
Initial Reset00000000 00 00
External Interrupt 00000000001 00
External Interrupt 10000000010 00
Timer/event counter 0 overflow000000001100
Timer/event counter 1 overflow000000010000
Time Base Interrupt0000000101 00
RTC Interrupt0000000110 00
SkipPC+2
Loading PCL*11 *10*9*8@7 @6@5@4@3@2@1@0
Jump, Call Branch#11 #10 #9#8#7#6#5#4#3#2#1#0
Return From SubroutineS11 S10 S9S8S7S6S5S4S3S2S1S0
-
Notes: *11~*0: Program counter bits
#11~#0: Instruction code bits
Program counter
S11~S0: Stack register bits
@7~@0: PCL bits
10August 18, 1999
·
Location 014H
Location 014H is reserved for the Time Base
interrupt service program. If a Time Base in
terrupt occurs, and the interrupt is enabled,
and the stack is not full, the program begins
execution at location 014H.
·
Location 018H
Location 018H is reserved for the real time
clock interrupt service program. If a real time
clock interrupt occurs, and the interrupt is
enabled, and the stack is not full, the program
begins execution at location 018H.
·
Table location
Any location in the ROM can be used as a
look-up table. The instructions ²TABRDC
[m]² (the current page, 1 page=256 words)
and ²TABRDL [m]² (the last page) transfer
the contents of the lower-order byte to the
specified data memory, and the contents of
the higher-order byte to TBLH (Table
Higher-order byte register) (08H). Only the
destination of the lower-order byte in the ta
ble is well-defined; the other bits of the table
word are all transferred to the lower portion
of TBLH, and the remaining 1 bit is read as
²0². The TBLH is read only, and the table
pointer (TBLP) is a read/write register (07H),
indicating the table location. Before accessing
the table, the location should be placed in
TBLP. All the table related instructions require 2 cycles to complete the operation.
These areas may function as a normal ROM
depending upon the user¢s requirements.
Stack register - STACK
The stack register is a special part of the mem
ory used to save the contents of the PC. The
stack is organized into 6 levels and is neither
part of the data nor part of the program, and is
neither readable nor writeable. Its activated
level is indexed by a stack pointer (SP) and is
neither readable nor writeable. At a commence
ment of a subroutine call or an interrupt ac
knowledgment, the contents of the PC is
pushed onto the stack. At the end of the subrou
tine or interrupt routine, signaled by a return
instruction (RET or RETI), the contents of the
PC is restored to its previous value from the
stack. After chip reset, the SP will point to the
top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag is re
corded but the acknowledgment is still inhib
ited. Once the SP is decremented (by RET or
RETI), the interrupt is serviced. This feature
prevents stack overflow, allowing the program
-
mer to use the structure easily. Likewise, if the
stack is full, and a ²CALL² is subsequently exe
cuted, a stack overflow occurs and the first en
try is lost (only the most recent six return
addresses are stored).
Data memory - RAM
The data memory (RAM) is designed with
192´8 bits, and is divided into two functional
groups, namely special function registers and
general purpose data memory, most of which
are readable/writeable, although some are read
only.
HT49C50
-
-
-
-
-
-
-
-
-
Instruction(s)
*11*10*9*8*7*6*5*4*3*2*1*0
Table Location
TABRDC [m]P11P10P9P8@7@6@5@4@3@2@1@0
TABRDL [m]1111@7@6@5@4@3@2@1@0
Table location
Notes: *11~*0: Table location bits
P11~P8: Current program Counter bits
@7~@0: Table pointer bits
11August 18, 1999
HT49C50
Ind irect A ddressing R egister 0
00H
01H
Ind irect A ddressing R egister 1
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0C H
0D H
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1C H
1D H
1EH
1FH
60H
FFH
MP0
MP1
BP
ACC
PCL
TBLP
TBLH
RTCC
STATUS
IN T C 0
TM R 0
TM R 0C
TM R 1
TM R 1C
PA
PB
PC
IN T C 1
G eneral P urpose
DATA M EMO RY
(160 Bytes)
Special P urpose
DATA M EMO RY
: U nused.
R ead as ²00
²
RAM mapping
Of the two types of functional groups, the special
function registers consist of an Indirect address
ing register 0 (00H), a Memory pointer register 0
(MP0;01H), an Indirect addressing register 1
(02H), a Memory pointer register 1 (MP1;03H), a
Bank pointer (BP;04H), an Accumulator
(ACC;05H), a Program counter lower-order byte
register (PCL;06H), a Table pointer (TBLP;07H),
a Table higher-order byte register (TBLH;08H), a
Real time clock control register (RTCC;09H), a
Status register (STATUS;0AH), an Interrupt
control register 0 (INTC0;0BH), a timer/event
counter 0 (TMR0;0DH), a timer/event counter 0
control register (TMR0C;0EH), a timer/event
counter 1 (TMR1;10H), a timer/event counter 1
control register (TMR1C;11H), I/O registers
(PA;12H, PB;14H, PC;16H), and Interrupt con
trol register 1 (INTC1;1EH). On the other hand,
the general purpose data memory, addressed
from 60H to FFH, is used for data and control in
formation under instruction commands.
The areas in the RAM can directly handle
arithmetic, logic, increment, decrement, and
rotate operations. Except some dedicated bits,
each bit in the RAM can be set and reset by
²SET [m].i²and ²CLR [m].i². They are also indi
rectly accessible through the Memory pointer
register 0 (MP0;01H) or the Memory pointer
register 1 (MP1;03H).
Indirect addressing register
Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and
MP1(03H) respectively. Reading location 00H
or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The function of data movement between two indirect addressing registers is not supported. The
memory pointer registers, MP0 and MP1, are
both 8-bit registers used to access the RAM by
combining corresponding indirect addressing registers. MP0 can only be applied to data memory,
while MP1 can be applied to data memory and
LCD display memory.
-
Accumulator - ACC
The accumulator (ACC) is related to the ALU
operations. It is also mapped to location 05H of
the RAM and is capable of operating with im
mediate data. The data movement between two
data memory locations must pass through the
ACC.
-
-
-
-
12August 18, 1999
HT49C50
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic
operations and provides the following func
tions:
·
Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
·
Logic operations (AND, OR, XOR, CPL)
·
Rotation (RL, RR, RLC, RRC)
·
Increment and Decrement (INC, DEC)
·
Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data op
eration but also changes the status register.
Status register - STATUS
The status register (0AH) is of 8 bits wide and
contains, a carry flag (C), an auxiliary carry flag
(AC), a zero flag (Z), an overflow flag (OV), a
power down flag (PD), and a watchdog time-out
flag (TO). It also records the status information
and controls the operation sequence.
Except the TO and PD flags, bits in the status
register can be altered by instructions similar
to other registers. Data written into the status
register does not alter the TO or PD flags. Oper
ations related to the status register, however,
may yield different results from those intended.
The TO and PD flags can only be changed by a
watchdog timer overflow, chip power-up, or
clearing the watchdog timer and executing the
²HALT² instruction. The Z, OV, AC, and C flags
reflect the status of the latest operations.
On entering the interrupt sequence or execut
ing the subroutine call, the status register will
not be automatically pushed onto the stack. If
the contents of the status is important, and if
the subroutine is likely to corrupt the status
register, the programmer should take precau
tions and save it properly.
Interrupts
The HT49C50 provides two external inter
rupts, two internal timer/event counter inter
rupts, an internal time base interrupt, and an
internal real time clock interrupt. The inter
rupt control register 0 (INTC0;0BH) and inter
rupt control register 1 (INTC1;1EH) both
contain the interrupt control bits that are used
to set the enable/disable status and interrupt
request flags.
-
LabelsBitsFunction
C is set if the operation results in a carry during an addition operation or if a bor-
C0
row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or no
AC1
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Z2
OV3
PD4
TO5
¾
¾
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD is cleared by either a system power-up or executing the ²CLR WDT² instruc
tion. PD is set by executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² in
struction. TO is set by a WDT time-out.
6
Undefined, read as ²0²
7
Undefined, read as ²0²
-
-
-
-
-
-
-
-
Status register
13August 18, 1999
HT49C50
Once an interrupt subroutine is serviced, other
interrupts are all blocked (by clearing the EMI
bit). This scheme may prevent any further in
terrupt nesting. Other interrupt requests may
take place during this interval, but only the in
terrupt request flag will be recorded. If a cer
tain interrupt requires servicing within the
service routine, the EMI bit and the correspond
ing bit of the INTC0 or of INTC1 may be set in
order to allow interrupt nesting. Once the stack is
RegisterBit No.LabelFunction
Control the master (global) interrupt
(1=enabled; 0=disabled)
Control the external interrupt 0
(1=enabled; 0=disabled)
Control the external interrupt 1
(1=enabled; 0=disabled)
Control the timer/event counter 0 interrupt
(1=enabled; 0=disabled)
External interrupt 0 request flag
(1=active; 0=inactive)
External interrupt 1 request flag
(1=active; 0=inactive)
Internal timer/event counter 0 request flag
(1=active; 0=inactive)
Control the timer/event counter 1 interrupt
(1=enabled; 0=disabled)
Control the time base interrupt
(1=enabled; 0:disabled)
Control the real time clock interrupt
(1=enabled; 0:disabled)
Internal timer/event counter 1 request flag
(1=active; 0=inactive)
Time base request flag
(1=active; 0=inactive)
Real time clock request flag
(1=active; 0=inactive)
INTC0
(0BH)
INTC1
(1EH)
0EMI
1EEI0
2EEI1
3ET0I
4EIF0
5EIF1
6T0F
7
0ET1I
1ETBI
2ERTI
3
4T1F
5TBF
6RTF
7
¾Unused bit, read as ²0²
¾Unused bit, read as ²0²
¾Unused bit, read as ²0²
full, the interrupt request will not be acknowl
edged, even if the related interrupt is enabled,
until the SP is decremented. If immediate service
is desired, the stack should be prevented from be
coming full.
-
All these interrupts can support a wake-up
function. As an interrupt is serviced, a control
transfer occurs by pushing the contents of the
PC onto the stack followed by a branch to a sub
-
-
-
INTC register
14August 18, 1999
HT49C50
routine at the specified location in the ROM.
Only the contents of the PC is pushed onto the
stack. If the contents of the register or of the
status register (STATUS) is altered by the in
terrupt service program which corrupts the de
sired control sequence, the contents should be
saved in advance.
External interrupts are triggered by a high to
low transition of INT0
interrupt request flag (EIF0; bit 4 of INTC0,
EIF1; bit 5 of INTC0) is set as well. After the in
terrupt is enabled, the stack is not full, and the
external interrupt is active, a subroutine call to
location 04H or 08H occurs. The interrupt re
quest flag (EIF0 or EIF1) and EMI bits are all
cleared to disable other interrupts.
The internal timer/event counter 0 interrupt is
initialized by setting the timer/event counter 0
interrupt request flag (T0F; bit 6 of INTC0),
which is normally caused by a timer overflow.
After the interrupt is enabled, and the stack is
not full, and the T0F bit is set, a subroutine call
to location 0CH occurs. The related interrupt
request flag (T0F) is reset, and the EMI bit is
cleared to disable further interrupts. The
timer/event counter 1 is operated in the same
manner but its related interrupt request flag is
T1F (bit 4 of INTC1) and its subroutine call location is 10H.
The time base interrupt is initialized by setting
the time base interrupt request flag (TBF; bit 5
of INTC1), that is caused by a regular time base
signal. After the interrupt is enabled, and the
stack is not full, and the TBF bit is set, a subroutine call to location 14H occurs. The related
interrupt request flag (TBF) is reset and the
EMI bit is cleared to disable further interrupts.
The real time clock interrupt is initialized by
setting the real time clock interrupt request
flag (RTF; bit 6 of INTC1), that is caused by a
regular real time clock signal. After the inter
rupt is enabled, and the stack is not full, and
the RTF bit is set, a subroutine call to location
18H occurs. The related interrupt request flag
(RTF) is reset and the EMI bit is cleared to dis
able further interrupts.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are all held
or INT1, and the related
until the ²RETI² instruction is executed or the
EMI bit and the related interrupt control bit are
set both to 1 (if the stack is not full). To return
-
from the interrupt subroutine, ²RET² or ²RETI²
-
may be invoked. RETI sets the EMI bit and en
ables an interrupt service, but RET does not.
Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses
are serviced on the latter of the two T2 pulses if
the corresponding interrupts are enabled. In
-
the case of simultaneous requests, the priori
ties in the following table apply. These can be
masked by resetting the EMI bit.
-
No. Interrupt Source Priority Vector
aExternal interrupt 0104H
bExternal interrupt 1208H
Timer/event
c
counter 0 overflow
Timer/event
d
counter 1 overflow
Time base
e
interrupt
Real time clock
f
interrupt
The timer/event counter 0 interrupt request
flag (T0F), external interrupt 1 request flag
(EIF1), external interrupt 0 request flag
(EIF0), enable timer/event counter 0 interrupt
bit (ET0I), enable external interrupt 1 bit
(EEI1), enable external interrupt 0 bit (EEI0),
and enable master interrupt bit (EMI) make up
of the Interrupt Control register 0 (INTC0)
which is located at 0BH in the RAM. The real
time clock interrupt request flag (RTF), time
base interrupt request flag (TBF), timer/event
counter 1 interrupt request flag (T1F), enable
real time clock interrupt bit (ERTI), and enable
time base interrupt bit (ETBI), enable
timer/event counter 1 interrupt bit (ET1I) on
the other hand, constitute the Interrupt Con
trol register 1 (INTC1) which is located at 1EH
in the RAM. EMI, EEI0, EEI1, ET0I, ET1I,
ETBI, and ERTI are all used to control the en
able/disable status of interrupts. These bits
prevent the requested interrupt from being ser
30CH
410H
514H
618H
-
-
-
-
-
15August 18, 1999
HT49C50
viced. Once the interrupt request flags (RTF,
TBF, T0F, T1F, EIF1, EIF0) are all set, they re
main in the INTC1 or INTC0 respectively until
the interrupts are serviced or cleared by a soft
ware instruction.
It is recommended that a program not use the ²CALL
subroutine² within the interrupt subroutine. It¢s
because interrupts often occur in an unpredictable
manner or require to be serviced immediately in
some applications. At this time, if only one stack is
left, and enabling the interrupt is not well con
trolled, operation of the ²call² in the interrupt
subroutine may damage the original control se
quence.
Oscillator configuration
The HT49C50 provides two oscillator circuits
for system clocks, i.e., RC oscillator and crystal
oscillator, determined by mask option. No mat
ter what type of oscillator is selected, the signal
is used for the system clock. The HALT mode
stops the system oscillator and ignores external
signal to conserve power.
Of the two oscillators, if the RC oscillator is
used, an external resistor between OSC1 and
VSS is required, and the range of the resistance
should be from 51kW to 1MW. The system clock,
divided by 4, is available on OSC2 with
pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However,
the frequency of the oscillation may vary with
VDD, temperature, and the chip itself due to
process variations. It is therefore, not suitable
for timing sensitive operations where accurate
oscillator frequency is desired.
OSC1
OSC1
VDD
On the other hand, if the crystal oscillator is se
lected, a crystal across OSC1 and OSC2 is
needed to provide the feedback and phase shift
required for the oscillator, and no other exter
nal components are required. A resonator may
be connected between OSC1 and OSC2 to re
place the crystal and to get a frequency refer
ence, but two external capacitors in OSC1 and
OSC2 are required.
There is another oscillator circuit designed for
the real time clock. In this case, only the
-
32.768kHz crystal oscillator can be applied.
The crystal should be connected between OSC3
and OSC4, and two external capacitors along
with one external resistor are required for the
oscillator circuit in order to get a stable fre
quency.
The RTC oscillator circuit can be controlled to
oscillate quickly by setting the ²QOSC² bit (bit
4 of RTCC). It is recommended to turn on the
quick oscillating function upon power on, and
turn it off after 2 seconds.
OSC3
OSC4
RTC oscillator
The WDT oscillator is a free running on-chip
RC oscillator, and no external components are
required. Although the system enters the
power down mode, the system clock stops, and
the WDT oscillator still works with a period of
approximately 78ms. The WDT oscillator can be
disabled by mask option to conserve power.
-
-
-
-
-
OSC2
C rystal O scillator
System oscillator
f
SYS
/4
OSC2
R C O s c illa to r
16August 18, 1999
Watchdog timer - WDT
The WDT clock source is implemented by a ded
icated RC oscillator (WDT oscillator) or an in
struction clock (system clock/4) or a real time
clock oscillator (RTC oscillator). The timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The WDT can be
disabled by mask option. But if the WDT is dis
abled, all executions related to the WDT lead to
no operation.
After the WDT clock source is selected, the
time-out period is f
/215~fS/216.
S
If the WDT clock source chooses the internal
WDT oscillator, the time-out period may vary
with temperature, VDD, and process variations.
On the other hand, if the clock source selects the
instruction clock and the ²halt² instruction is exe
cuted, WDT may stop counting and lose its pro
tecting purpose, and the logic can only be
restarted by an external logic.
When the device operates in a noisy environ
ment, using the on-chip RC oscillator (WDT
OSC) is strongly recommended, since the HALT
can stop the system clock.
The WDT overflow under normal operation
initializes a ²chip reset² and sets the status bit
²TO². In the HALT mode, the overflow
initializes a ²warm reset², and only the PC and
SP are reset to zero. To clear the contents of the
WDT, there are three methods to be adopted,
i.e., external reset (a low level to RES
instruction, and a ²HALT² instruction. There
are two types of software instructions; ²CLR
WDT² and the other set -²CLR WDT1² and²CLR WDT2². Of these two types of instruction,
only one type of instruction can be active at a
time depending on the mask option -²CLR
-
WDT times selection option².Ifthe²CLR WDT²
is selected (i.e., CLR WDT times equal one), any
execution of the ²CLR WDT² instruction clears
the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e., CLR WDT times
equal two), these two instructions have to be ex
ecuted to clear the WDT; otherwise, the WDT
may reset the chip due to time-out.
Multi-function timer
The HT49C50 provides a multi-function timer for
the WDT, time base and RTC but with different
time-out periods. The multi-function timer con
sists of a 7-stage divider and an 8-bit prescaler,
with the clock source coming from the WDT OSC
or RTC OSC or the instruction clock (i.e.., system
clock divided by 4). The multi-function timer also
provides a selectable frequency signal (ranges
/22to fS/28) for LCD driver circuits, and a
from f
S
selectable frequency signal (ranges from f
f
/29) for the buzzer output by mask option. It is
S
recommended to select a near 4kHz signal to
LCD driver circuits for proper display.
HT49C50
), software
/22to
S
-
-
S ystem C lock/4
RTC
32768H z
OSC
WDT
12kHz
OSC
Mask
Option
Select
f
S
D ivider
Prescaler
CK TRCK T
W D T C lear
17August 18, 1999
R
Tim e-out R eset
1516
f
/2 ~ fS/2
S
Time base
The time base offers a periodic time-out period
to generate a regular internal interrupt. Its
time-out period ranges from f
/212to fS/215se
S
lected by mask option. If time base time-out oc
curs, the related interrupt request flag (TBF;
bit 5 of INTC1) is set. But if the interrupt is en
abled, and the stack is not full, a subroutine call
to location 14H occurs. The time base time-out
signal also can be applied to be a clock source of
timer/event counter 1 for getting a longer
timer-out period.
Real time clock - RTC
The real time clock (RTC) is operated in the
same manner as the time base that is used to
supply a regular internal interrupt. Its
time-out period ranges from f
/28to fS/215by
S
software programming . Writing data to RT2,
RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields
various time-out periods. If the RTC time-out
occurs, the related interrupt request flag (RTF;
bit 6 of INTC1) is set. But if the interrupt is en
abled, and the stack is not full, a subroutine call
to location 18H occurs. The real time clock
time-out signal also can be applied to be a clock
source of timer/event counter 0 for getting a
longer time-out period.
-
RT2 RT1RT0
-
-
0002
0012
0102
RTC Clock Divided
Factor
0112
1002
1012
1102
1112
Power down operation - HALT
The HALT mode is initialized by the ²HALT²
instruction and results in the following.
·
The system oscillator turns off but the WDT
oscillator keeps running (if the WDT oscilla
tor or the real time clock is selected).
-
·
The contents of the on-chip RAM and of the
registers remain unchanged.
·
The WDT is cleared and start recounting (if
the WDT clock source is from the WDT oscillator or the real time clock oscillator).
HT49C50
8
9
10
11
12
13
14
15
-
f
s
D ivider
L C D D riv e r (fS/2 ~ fS/2 )
B uzzer (f
Mask Option
28
29
/2 ~ fS/2 )
S
Prescaler
Mask
Option
T im e B a s e In te rru p t
(fS/2 ~ fS/2 )
15
12
Time base
f
S
D ivider
RT2
RT1
RT0
P re scale r
8 to 1
Mux.
12
fS/2 ~ fS/2
RTC Interrupt
15
Real time clock
18August 18, 1999
HT49C50
·
All I/O ports maintain their original status.
·
The PD flag is set but the TO flag is cleared.
·
LCD driver is still running (if the WDT OSC
or RTC OSC is selected).
The system quits the HALT mode by an external
reset, an interrupt, an external falling edge sig
nal on port A, or a WDT overflow. An external re
set causes device initialization, and the WDT
overflow performs a ²warm reset². After examin
ing the TO and PD flags, the reason for chip re
set can be determined. The PD flag is cleared by
system power-up or by executing the ²CLR
WDT² instruction, and is set by executing the
²HALT² instruction. On the other hand, the TO
flag is set if WDT time-out occurs, and causes a
wake-up that only resets the PC (Program
Counter) and SP, and leaves the others at their
original state.
The port A wake-up and interrupt methods can
be considered as a continuation of normal exe
cution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the pro
gram resumes execution of the next instruc
tion. On the other hand, awakening from an
interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is
enabled but the stack is full, the program resumes execution at the next instruction. But if
the interrupt is enabled, and the stack is not
full, the regular interrupt response takes place.
When an interrupt request flag is set before entering the ²halt² status, the system cannot be
awaken using that interrupt.
If wake-up events occur, it takes 1024 t
SYS
(sys
tem clock period) to resume normal operation.
In other words, a dummy period is inserted af
ter the wake-up. If the wake-up results from an
interrupt acknowledgment, the actual inter
rupt subroutine execution is delayed by more
than one cycle. However, if the Wake-up results
in the next instruction execution, the execution
will be performed immediately after the
dummy period is finished.
To minimize power consumption, all the I/O
pins should be carefully managed before enter
ing the HALT status.
Reset
There are three ways in which reset may occur.
-
·
-
-
-
RES is reset during normal operation
·
RES is reset during HALT
·
WDT time-out is reset during normal
operation
The WDT time-out during HALT differs from
other chip reset conditions, for it can perform a
²warm reset² that resets only the PC and SP
and leaves the other circuits at their original
state. Some registers remain unaffected during
any other reset conditions. Most registers are
reset to the ²initial condition² once the reset
conditions are met. Examining the PD and TO
flags, the program can distinguish between dif
ferent ²chip resets².
-
VDD
-
-
RES
Reset circuit
TOPDRESET Conditions
-
-
-
00RES
uu
01RES
1u
reset during power-up
reset during normal
RES
operation
Wake-up HALT
WDT time-out during normal
operation
11WDT Wake-up HALT
Note:
²u² means ²unchanged²
-
-
19August 18, 1999
To guarantee that the system oscillator is started
and stabilized, the SST (System Start-up Timer)
provides an extra-delay of 1024 system clock
pulses when the system awakes from the HALT
state or during power up. Awaking from the
HALT state or system power-up, the SST delay is
added.
An extra SST delay is added during the
power-up period, and any wake-up from the
HALT may enable only the SST delay.
The functional unit chip reset status is shown
below.
²*² refers to warm reset
²u² means unchanged
²x² means unknown
21August 18, 1999
HT49C50
Timer/event counter
Two timer/event counters are implemented in
the HT49C50. Both of them contain an 8-bit
programmable count-up counter.
The timer/event count 0 clock source may come
from the system clock or system clock/4 or RTC
time-out signal or external source. System
clock source or system clock/4 is selected by
mask option.
The timer/event count 1 clock source may come
from TMR0 overflow or system clock or time
base time-out signal or system clock/4 or exter
nal source, and the three former clock source is
selected by mask option.
The external clock input allows the user to
count external events, measure time intervals
or pulse widths, or to generate an accurate time
base.
The two timer/event counters are operated al
most in the same manner, except the clock
source and related registers.
There are two registers related to the
timer/event counter 0, i.e., TMR0 ([0DH]) and
TMR0C ([0EH]), and two registers related to
the timer/event counter 1, i.e., TMR1 ([10H],
and TMR1C ([11H]). There are also two physical registers are mapped to TMR0 (TMR1) location; writing TMR0 (TMR1) places the starting
value in the timer/event counter preload register, while reading it yields the contents of the
timer/event counter. TMR0C and TMR1C are
timer/event counter control registers used to
define some options.
The TN0 and TN1 bits define the operation
mode. The event count mode is used to count ex
ternal events, which means that the clock
source is from an external (TMR0, TMR1) pin.
The timer mode functions as a normal timer
with the clock source coming from the internal
selected clock source. Finally, the pulse width
measurement mode can be used to count the
high or low level duration of the external signal
(TMR0, TMR1), and the counting is based on
the internal selected clock source.
In the event count or timer mode, the timer/event
counter starts counting at the current contents in
the timer/event counter and ends at FFH. Once
an overflow occurs, the counter is reloaded from
the timer/event counter preload register, and
generates an interrupt request flag (T0F; bit 6 of
INTC0, T1F; bit 4 of INTC1).
-
In the pulse width measurement mode with
the values of the TON and TE bits equal to
one, after the TMR0 (TMR1) has received a
transient from low to high (or high to low if
the TE bit is ²0²), it will start counting until
the TMR0 (TMR1) returns to the original
level and resets the TON. The measured result remains in the timer/event counter even
if the activated transient occurs again. In
other words, only one cycle measurement can
be made until the TON is set. The cycle measurement will re-function as long as it receives
-
System C lock
S y s te m C lo c k /4
RTC O ut
Mask
Option
Select
TN2
TM R 0
TN1
TN0
TO N
M
U
X
TN1
TN0
TE
Pulse W idth
M easurem ent
M ode C ontrol
Timer/event counter 0
D ata bus
Tim er/event counter 0
Preload R egister
Tim er/event
counter 0
PA3 Data CTRL
22August 18, 1999
R eload
O verflow
T o In te r ru p t
TQ
PFD0
HT49C50
Label
(TMR0C)
¾
TE3
TON4
TN25
BitsFunction
0~2
Unused bits, read as ²0²
To define the TMR0 active edge of timer/event counter
(0=active on low to high; 1=active on high to low)
To enable/disable timer counting
(0=disabled; 1=enabled)
2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0=RTC outputs; 1= system clock or system clock/4)
further transient pulse. In this operation mode,
the timer/event counter begins counting accord
ing not to the logic level but to the transient
edges. In the case of counter overflows, the coun
ter is reloaded from the timer/event counter
preload register and issues an interrupt request,
as in the other two modes, i.e., event and timer
modes.
To enable the counting operation, the Timer ON
bit (TON; bit 4 of TMR0C or TMR1C) should be
set to 1. In the pulse width measurement mode,
the TON is automatically cleared after the
measurement cycle is completed. But in the
other two modes, the TON can only be reset by
instructions. The overflow of the timer/event
counter 0/1 is one of the wake-up sources and
can also be applied to a PFD (Programmable
Frequency Divider) output at PA3 by mask op
tion. Only one PFD (PFD0 or PFD1) can be ap
plied to PA3 by mask option . No matter what the
operation mode is, writinga0toET0I or ET1I
disables the related interrupt service. When the
PFD function is selected, executing ²CLR [PA].3²
instruction to enable PFD output and executing
²SET [PA].3² instruction to disable PFD output.
In the case of timer/event counter OFF
condition, writing data to the timer/event counter
preload register also reloads that data to the
-
-
TM R 0 O verflow
S ystem C lock
Tim e B ase O ut
S y s te m C lo c k /4
Mask
Option
Select
TN2
TM R 1
TN1
TN0
TO N
M
U
X
TN1
TN0
TE
Pulse W idth
M easurem ent
M ode C ontrol
Timer/event counter 1
D ata bus
Tim er/event counter 1
Preload R egister
Tim er/event
counter 1
PA3 Data CTRL
23August 18, 1999
R eload
O verflow
T o In te r ru p t
TQ
PFD1
HT49C50
Label
(TMR1C)
¾
TE3
TON4
TN25
TN1
TN0
timer/ event counter. But if the timer/event
counter is turn on, data written to the
timer/event counter is kept only in the
timer/event counter preload register. The
timer/event counter still continues its opera
tion until an overflow occurs.
When the timer/event counter (reading
TMR0/TMR1) is read, the clock is blocked to
avoid errors. As this may results in a counting
error, blocking of the clock should be taken into
account by the programmer.
It is strongly recommended to load a desired
value into the TMR0/TMR1 register first, then
turn on the related timer/event counter for
proper operation. Because the initial value of
TMR0/TMR1 is unknown.
Due to the timer/event scheme, the programmer should pay special attention on the instruc
tion to enable then disable the timer for the
first time, whenever there is a need to use the
timer/event function, to avoid unpredicatable
result. After this procedure, the timer/event
function can be operated normally. The exam
ple given below, using two 8-bit width Timer¢s
(timer 0 ;timer 1) cascade into 16-bit width.
BitsFunction
0~2
Unused bits, read as ²0²
To define the TMR1 active edge of timer/event counter
(0= active on low to high; 1= active on high to low)
To enable/disable timer counting
(0= disabled; 1= enabled)
2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0= mask option clock source; 1= system clock/4)
To define the operating mode
01= Event count mode (External clock)
mov a, 09h; Set ET0I&EMI bits to
mov intc0, a ; enable timer 0 and
mov a, 01h; Set ET1I bit to enable
mov intc1, a ; timer 1 interrupt
mov a, 80h; Set operating mode as
mov tmr1c, a ; timer mode and select mask
mov a, 0a0h ; Setoperating mode astimer
mov tmr0c, a ; mode and select system
set tmr1c.4; Enable then disable timer 1
clrtmr1c.4 ; for the first time
mov a, 00h; Load a desired value into
mov tmr0, a ; the TMR0/TMR1 register
mov a, 00h;
mov tmr1, a ;
-
set tmr0c.4 ; Normal operating
set tmr1c.4 ;
; global interrupt
; option clock source
; clock/4
END
24August 18, 1999
Input/output ports
There are a 12-bit bidirectional input/output
port, an 8-bit input port intheHT49C50,labeled
PA, PB and PC which are mapped to [12H],
[14H] and [16H] of the RAM, respectively.
PA0~PA3 can be configured as CMOS (output)
or NMOS (input/output) with or without
pull-high resistor by mask option. PA4~PA7 are
always pull-high and NMOS (input/output).Ifyou
choose NMOS (input), each bit on the port
(PA0~PA7) can be configured as a wake-up input.
PB can only be used for input operation, and each
bit on theport can be configured with pull-high re
sistor. PC can be configured as CMOS output or
NMOS input/output with or without pull-high re
sistor by maskoption. All the port forthe input op
eration (PA, PB and PC), these ports are
non-latched, that is, the inputs should be ready at
the T2 rising edge of the instruction ²MOV A, [m]²
(m=12H or 14H). For PA, PC output operation, all
data are latched and remain unchanged until the
outputlatch is rewritten.
D ata bus
Write
C hip R eset
D
CK
S
When the PA and PC structures are open drain
NMOS type, it should be noted that, before
reading data from the pads, a ²1² should be
written to the related bits to disable the NMOS
device. That is executing first the instruction
²SET [m].i² (i=0~7 for PA) to disable related
NMOS device, and then ²MOV A, [m]² to get
stable data.
After chip reset, these input lines remain at the
high level or are left floating (by mask option).
Each bit of these output latches can be set or
-
cleared by the ²SET [m].i² and ²CLR [m].i²
(m=12H or 16H) instructions.
-
Some instructions first input data and then fol
-
low the output operations. For example, ²SET
[m].i², ²CLR [m].i², ²CPL [m]², ²CPLA[m]² read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or to the ac
cumulator.
VDD
VDD
Mask
option
Q
Q
(P A 0 ~
PA3, PC )
PC
W eak
Pull-up
M ask o ption
(P A 0 ~ P A 3 , P C )
PA0~PA7
PB0~PB7
PC0~PC3
HT49C50
-
-
R ead I/O
System W ake-up (P A only)
M ask o ption
Input/output ports
25August 18, 1999
LCD display memory
The HT49C50 provides an area of embedded
data memory for LCD display. This area is lo
cated from 40H to 60H of the RAM at Bank 1.
Bank pointer (BP; located at 04H of the RAM) is
the switch between the RAM and the LCD dis
play memory. When the BP is set as ²1², any
data written into 40H~60H will effect the LCD
display. When the BP is cleared to ²0², any data
written into 40H~60H means to access the gen
eral purpose data memory. The LCD display
41H42H43H5E H5F H60HB it
COM
40H
memory can be read and written to only by indi
rect addressing mode using MP1. When data is
-
written into the display data area, it is auto
matically read by the LCD driver which then
generates the corresponding LCD driving sig
-
nals. To turn the display on or off, a ²1² or a ²0²
is written to the corresponding bit of the display
memory, respectively. The figure illustrates the
mapping between the display memory and LCD
-
pattern for the HT49C50.
HT49C50
-
-
-
0
1
2
3
SEG MENT
0
1
2
3
0123303132
Display memory
26August 18, 1999
HT49C50
LCD driver output
The output number of the HT49C50 LCD driver
can be 33´2or33´3or32´4 by mask option (i.e.,
1/2 duty or 1/3 duty or 1/4 duty). The bias type of
LCD driver can be ²R² type or ²C² type. If the ²R²
bias type is selected, no external capacitor is re
quired. If the ²C² bias type is selected, a capacitor
mounted between C1 and C2 pins is needed. The
bias voltage of LCD driver can be 1/2 bias or 1/3
bias by mask option. If 1/2 bias is selected, a ca
pacitor mounted between V2 pin and ground is
required. If 1/3 bias is selected, two capacitors are
needed for V1 and V2 pins. Refer to application
diagram.
D urin g a R eset Pulse:
COM 0,COM 1,CO M2
All LC D driver outputs
N o rm a l O p e r a tio n M o d e :
COM 0
COM 1
COM 2
LC D segm ents on C O M
0,1,2 sides being unlit
O nly LC D segm ents on
C O M 0 side being lit
O nly LC D segm ents on
C O M 1 side being lit
O nly LC D segm ents on
C O M 2 side being lit
LC D segm ents on
C O M 0,1 sides being lit
LC D segm ents on
C O M 0,2 sides being lit
LC D segm ents on
C O M 1,2 sides being lit
LC D segm ents on
C O M 0,1,2 sides being lit
H a lt M o d e :
COM 0,COM 1,CO M2
All LC D driver outputs
Buzzer
HT49C50 provides a pair of buzzer output BZ
and BZ
, which share pins with PA0 and PA1 re
spectively, ad determined by mask option. Its
output frequency can be selected by mask op
tion.
-
When the buzzer function is selected, setting
the PA.0 and PA.1 ²0² simultaneously, will en
ables the buzzer output and sets the PA.0 ²1² to
disable the buzzer output.
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
VLCD
1/2 V LCD
VSS
-
-
-
LCD driver output (1/3 duty, 1/2 bias, R/C type)
27August 18, 1999
3/2 V LC D
VLCD
HT49C50
COM 0
COM 1
COM 2
COM 3
LC D segm ents O N
C O M 2 side lighted
1/2 V LC D
VSS
3/2 V LC D
VLCD
1/2 V LC D
VSS
3/2 V LC D
VLCD
1/2 V LC D
VSS
3/2 V LC D
VLCD
1/2 V LC D
VSS
3/2 V LC D
VLCD
1/2 V LC D
VSS
LCD driver output (1/4 duty, 1/3 bias, C type)
28August 18, 1999
Register Bit No. Label Read/Write ResetFunction
RTCC
(09H)
RT0
0~2
RT1
R/W0
RT2
3
¾¾¾Unused bits, this bit must dear to ²0²
4QOSCR/W0
8 to 1 multiplexer control inputs to select the
real time clock prescaler output
Control the RTC OSC to oscillate quickly
²0² enable
²1² disable
5~7
¾¾¾Unused bits, read as ²0²
RTCC register
Mask option
The following shows 18 kinds of mask options
in the HT49C50. All these options should be de
fined in order to ensure proper system function
-
ing.
No.Mask Option
OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as sys
1
tem clock.
WDT Clock source selection. RTC and Time Base. There are three types of selection: sys
2
tem clock/4 or RTC OSC or WDT OSC.
3WDT enable/disable selection. WDT can be enabled or disabled by mask option.
CLR WDT times selection. This option defines how to clear the WDT by instruction. ²One
4
time² means that the ²CLR WDT² can clear the WDT. ²Two times² means only if both of
the ²CLR WDT1² and ²CLR WDT2² have been executed, the WDT can be cleared.
Time Base time-out period selection. The Time Base time-out period ranges from
5
6
7
8
12
clock/2
uzzer output frequency selection. There are eight types of frequency signals for buzzer
output: Clock/2
to clock/215. ²Clock² means the clock source selected by mask option.
2
~Clock/29. ²Clock² means the clock source selected by mask option.
Wake-up selection. This option defines the wake-up capability. External I/O pins (PA
only) all have the capability to wake-up the chip from a HALT by a falling edge.
Pull-high selection. This option is to decide whether the pull-high resistance is visible or
not on the PA0~PA3 and PC. (PB and PA4~PA7 are always pull-high)
PA0~PA3 and PC CMOS or NMOS selection.
The structure of PA0~PA3 and PC each 4 bits can be selected as CMOS or NMOS individ
9
ually. When the CMOS is selected, the related pins only can be used for output opera
tions. When the NMOS is selected, the related pins can be used for input or output
operations. (PA4~PA7 are always NMOS)
HT49C50
-
-
-
-
-
29August 18, 1999
No.Mask Option
Clock source selection of timer/event counter 0. There are two types of selection: system
10
clock or system clock/4.
Clock source selection of timer/event counter 1. There are three types of selection: TMR0
11
overflow, system clock or Time Base overflow.
I/O pins share with other functions selection.
12
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
LCD common selection. There are three types of selection: 2 common (1/2 duty) or 3 com
mon (1/3 duty) or 4 common (1/4 duty). If the 4 common is selected, the segment output
13
pin ²SEG32² will be set as a common output.
LCD bias power supply selection.
14
There are two types of selection: 1/2 bias or 1/3 bias.
LCD bias type selection.
15
This option is to decide what kind of bias is selected, R type or C type.
LCD driver clock selection. There are seven types of frequency signals for the LCD driver
16
circuits: f
/22~fS/28. ²fS² means the clock source selection by mask option.
S
PFD selection.
If PA3 is set as PFD output, there are two types of selection; One is PFD0 as the PFD out
17
put, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of
the timer/event counter 0, timer/event counter 1 respectively.
HT49C50
-
-
30August 18, 1999
Application Circuits
R C o s c illa t o r a p p lic a t io nC ry s t a l o s c illa to r a p p lic a t io n
HT49C50
VDD
OSC1
OSC2
RES
OSC3
OSC4
IN T 0
IN T 1
TM R 0
TM R 1
SEG0~31
HT49C50
PA0~PA7
PB0~PB7
PC0~PC3
COM 0~3
VLCD
C1
C2
V1
V2
LCD
PANEL
LCD Power
Supply
0.1mF
0.1mF
0.1mF
OSC1
VDD
f
/4
SYS
OSC2
VDD
RES
OSC3
OSC4
IN T 0
IN T 1
TM R 0
TM R 1
SEG0~31
HT49C50
PA0~PA7
PB0~PB7
PC0~PC3
COM 0~3
VLCD
C1
C2
V1
V2
LCD
PANEL
LCD Power
Supply
0.1mF
0.1mF
0.1mF
31August 18, 1999
HT49C50
Instruction Set Summary
MnemonicDescriptionFlag Affected
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Increment
and
Decrement
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry with result in
data memory
Decimal adjust ACC for addition with result in data memory
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
Clear bit of data memory
Set bit of data memory
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
33August 18, 1999
None
None
HT49C50
MnemonicDescriptionFlag Affected
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Notes: x: 8-bit immediate data
m: 7-bit data memory address
A: accumulator
i: 0~7 number of bits
addr: 10-bit program memory address
Ö: Flag(s) is affected
-: Flag(s) is not affected
*: Flag(s) may be affected by the execution status
**: For the old version of the E.V. chip, the zero flag (Z) can be affected by executing the
MOV A,[M] instruction.
For the new version of the E.V. chip, the zero flag cannot be changed by executing the
MOV A,[M] instruction.
No operation
Clear data memory
Set data memory
Clear Watchdog timer
Pre-clear Watchdog timer
Pre-clear Watchdog timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
None
None
None
TO,PD
TO*,PD*
TO*,PD*
None
None
TO,PD
34August 18, 1999
HT49C50
Instruction Definition
ADC A,[m]Add data memory and carry to the accumulator
DescriptionThe contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
Affected flag(s)
ADCM A,[m]Add the accumulator and carry to data memory
DescriptionThe contents of the specified data memory, accumulator and the carry flag
Operation
Affected flag(s)
ADD A,[m]Add data memory to the accumulator
DescriptionThe contents of the specified data memory and the accumulator are added.
Operation
Affected flag(s)
ACC ¬ ACC+[m]+C
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
are added simultaneously, leaving the result in the specified data memory.
[m] ¬ ACC+[m]+C
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
The result is stored in the accumulator.
ACC ¬ ACC+[m]
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
ADD A,xAdd immediate data to the accumulator
DescriptionThe contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
Affected flag(s)
ACC ¬ ACC+x
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
35August 18, 1999
HT49C50
ADDM A,[m]Add the accumulator to the data memory
DescriptionThe contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
Affected flag(s)
AND A,[m]Logical AND accumulator with data memory
DescriptionData in the accumulator and the specified data memory perform a bitwise
Operation
Affected flag(s)
AND A,xLogical AND immediate data to the accumulator
DescriptionData in the accumulator and the specified data perform a bitwise logi
Operation
Affected flag(s)
[m] ¬ ACC+[m]
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
logical_AND operation. The result is stored in the accumulator.
ACC ¬ ACC ²AND² [m]
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
cal_AND operation. The result is stored in the accumulator.
ACC ¬ ACC ²AND² x
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
-
ANDM A,[m]Logical AND data memory with the accumulator
DescriptionData in the specified data memory and the accumulator perform a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
Affected flag(s)
[m] ¬ ACC ²AND² [m]
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
36August 18, 1999
HT49C50
CALL addrSubroutine call
DescriptionThe instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this ad
dress.
Operation
Affected flag(s)
CLR [m]Clear data memory
DescriptionThe contents of the specified data memory are cleared to zero.
Operation
Affected flag(s)
CLR [m].iClear bit of data memory
DescriptionThe bit i of the specified data memory is cleared to zero.
Operation
Affected flag(s)
Stack ¬ PC+1
PC ¬ addr
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
[m] ¬ 00H
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
[m].i ¬ 0
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
-
CLR WDTClear watchdog timer
DescriptionThe WDT is cleared (re-counting from zero). The power down bit (PD) and
time-out bit (TO) are cleared.
Operation
Affected flag(s)
WDT ¬ 00H
PD and TO ¬ 0
TC2 TC1TOPDOVZACC
¾¾
00
37August 18, 1999
¾¾¾¾
HT49C50
CLR WDT1Preclear watchdog timer
DescriptionThe TD, PD flags and WDT are all cleared (re-counting from zero), if the
other preclear WDT instruction has been executed. Only execution of this in
struction without the other preclear instruction sets the indicated flag which
implies that this instruction has been executed and the TO and PD flags re
main unchanged.
Operation
Affected flag(s)
CLR WDT2Preclear watchdog timer
DescriptionThe TO, PD flags and WDT are all cleared (re-counting from zero), if the
Operation
Affected flag(s)
WDT ¬ 00H*
PD and TO ¬ 0*
TC2 TC1TOPDOVZACC
¾¾
other preclear WDT instruction has been executed. Only execution of this in
struction without the other preclear instruction sets the indicated flag which
implies that this instruction has been executed and the TO and PD flags re
main unchanged.
WDT ¬ 00H*
PD and TO ¬ 0*
TC2 TC1TOPDOVZACC
¾¾
0*0*
0*0*
¾¾¾¾
¾¾¾¾
-
-
-
-
CPL [m]Complement data memory
Description
Operation
Affected flag(s)
Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a one are changed to zero and
vice-versa.
[m] ¬ [m
TC2 TC1TOPDOVZACC
]
¾¾¾¾¾Ö¾¾
38August 18, 1999
HT49C50
CPLA [m]Complement data memory and place result in the accumulator
Description
Operation
Affected flag(s)
DAA [m]Decimal-Adjust accumulator for addition
DescriptionThe accumulator value is adjusted to the BCD (Binary Code Decimal) code.
OperationIf ACC.3~ACC.0 >9 or AC=1
Affected flag(s)
Each bit of the specified data memory is logically complemented (1¢s comple
ment). Bits which previously contained a one are changed to zero and
vice-versa. The complemented result is stored in the accumulator and the
contents of the data memory remain unchanged.
ACC ¬ [m
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the ac
cumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾ Ö
]
-
-
DEC [m]Decrement data memory
DescriptionData in the specified data memory is decremented by one.
Operation
Affected flag(s)
[m] ¬ [m]-1
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
39August 18, 1999
HT49C50
DECA [m]Decrement data memory and place result in the accumulator
DescriptionData in the specified data memory is decremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
HALTEnter power down mode
DescriptionThis instruction stops program execution and turns off the system clock. The
Operation
Affected flag(s)
ACC ¬ [m]-1
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
contents of the RAM and registers are retained. The WDT and prescaler are
cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
TC2 TC1TOPDOVZACC
¾¾
01
¾¾¾¾
INC [m]Increment data memory
DescriptionData in the specified data memory is incremented by one.
Operation
Affected flag(s)
INCA [m]Increment data memory and place result in the accumulator
DescriptionData in the specified data memory is incremented by one, leaving the result
Operation
Affected flag(s)
[m] ¬ [m]+1
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
in the accumulator. The contents of the data memory remain unchanged.
ACC ¬ [m]+1
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
40August 18, 1999
HT49C50
JMP addrDirectly jump
DescriptionThe contents of the program counter are replaced with the directly-specified
address unconditionally, and control is passed to this destination.
Operation
Affected flag(s)
MOV A,[m]Move data memory to the accumulator
DescriptionThe contents of the specified data memory are copied to the accumulator.
Operation
Affected flag(s)
MOV A,xMove immediate data to the accumulator
DescriptionThe 8-bit data specified by the code is loaded into the accumulator.
Operation
Affected flag(s)
PC ¬ addr
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
ACC ¬ [m]
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
ACC ¬ x
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
MOV [m],AMove the accumulator to data memory
DescriptionThe contents of the accumulator are copied to the specified data memory (one
of the data memories).
Operation
Affected flag(s)
NOPNo operation
DescriptionNo operation is performed. Execution continues with the next instruction.
Operation
Affected flag(s)
[m] ¬ ACC
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
PC ¬ PC+1
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
41August 18, 1999
HT49C50
OR A,[m]Logical OR accumulator with data memory
DescriptionData in the accumulator and the specified data memory (one of the data
memories) perform a bitwise logical_OR operation. The result is stored in
the accumulator.
Operation
Affected flag(s)
OR A,xLogical OR immediate data to the accumulator
DescriptionData in the accumulator and the specified data perform a bitwise logical_OR
Operation
Affected flag(s)
ORM A,[m]Logical OR data memory with the accumulator
DescriptionData in the data memory (one of the data memories) and the accumulator
Operation
Affected flag(s)
ACC ¬ ACC ²OR² [m]
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
operation. The result is stored in the accumulator.
ACC ¬ ACC ²OR² x
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
perform a bitwise logical_OR operation. The result is stored in the data
memory.
[m] ¬ ACC ²OR² [m]
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
RETReturn from subroutine
DescriptionThe program counter is restored from the stack. This is a two-cycle instruc-
tion.
Operation
Affected flag(s)
PC ¬ Stack
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
42August 18, 1999
HT49C50
RET A,xReturn and place immediate data in the accumulator
DescriptionThe program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
Affected flag(s)
RETIReturn from interrupt
DescriptionThe program counter is restored from the stack, and interrupts are enabled
Operation
Affected flag(s)
RL [m]Rotate data memory left
DescriptionThe contents of the specified data memory are rotated one bit left with bit 7
Operation
Affected flag(s)
PC ¬ Stack
ACC ¬ x
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).
PC ¬ Stack
EMI ¬ 1
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
rotated into bit 0.
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
RLA [m]Rotate data memory left and place result in the accumulator
DescriptionData in the specified data memory is rotated one bit left with bit 7 rotated
into bit 0, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
Affected flag(s)
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
43August 18, 1999
HT49C50
RLC [m]Rotate data memory left through carry
DescriptionThe contents of the specified data memory and the carry flag are rotated one
bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the
bit 0 position.
Operation
Affected flag(s)
RLCA [m]Rotate left through carry and place result in the accumulator
DescriptionData in the specified data memory and the carry flag are rotated one bit left.
Operation
Affected flag(s)
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾ Ö
Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 po
sition. The rotated result is stored in the accumulator but the contents of the
data memory remain unchanged.
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾ Ö
-
RR [m]Rotate data memory right
DescriptionThe contents of the specified data memory are rotated one bit right with bit 0
rotated to bit 7.
Operation
Affected flag(s)
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
44August 18, 1999
HT49C50
RRA [m]Rotate right-place result in the accumulator
DescriptionData in the specified data memory is rotated one bit right with bit 0 rotated
into bit 7, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
Affected flag(s)
RRC [m]Rotate data memory right through carry
DescriptionThe contents of the specified data memory and the carry flag are together ro
Operation
Affected flag(s)
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
tated one bit right. Bit 0 replaces the carry bit; the original carry flag is ro
tated into the bit 7 position.
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾ Ö
-
-
RRCA [m]Rotate right through carry-place result in the accumulator
DescriptionData of the specified data memory and the carry flag are rotated one bit
right. Bit 0 replaces the carry bit and the original carry flag is rotated into
the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾ Ö
45August 18, 1999
HT49C50
SBC A,[m]Subtract data memory and carry from the accumulator
DescriptionThe contents of thespecifieddatamemory and the complementofthecarry flag
aresubtractedfromtheaccumulator,leaving the resultin theaccumulator.
Operation
Affected flag(s)
SBCM A,[m]Subtract data memory and carry from the accumulator
DescriptionThe contents of the specified data memory and the complement of the carry
Operation
Affected flag(s)
SDZ [m]Skip if decrement data memory is zero
DescriptionThe contents of the specified data memory are decremented by one. If the re
Operation
Affected flag(s)
ACC ¬ ACC+[m
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
flag are subtracted from the accumulator, leaving the result in the data
memory.
[m] ¬ ACC+[m
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
sult is zero, the next instruction is skipped. If the result is zero, the following
instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle).
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
]+C
]+C
-
SDZA [m]Decrement data memory and place result in ACC, skip if zero
DescriptionThe contents of the specified data memory are decremented by one. If the re
sult is zero, the next instruction is skipped. The result is stored in the accu
mulator but the data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction (two
cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Affected flag(s)
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
46August 18, 1999
-
-
HT49C50
SET [m]Set data memory
DescriptionEach bit of the specified data memory is set to one.
Operation
Affected flag(s)
SET [m].iSet bit of data memory
Description
Operation
Affected flag(s)
SIZ [m]Skip if increment data memory is zero
DescriptionThe contents of the specified data memory are incremented by one. If the re
Operation
Affected flag(s)
[m] ¬ FFH
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
Bit ²i² of the specified data memory is set to one.
[m].i ¬ 1
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
sult is zero, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper in
struction (two cycles). Otherwise proceed with the next instruction (one cy
cle).
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
-
-
-
SIZA [m]Increment data memory and place result in ACC, skip if zero
DescriptionThe contents of the specified data memory are incremented by one. If the re-
sult is zero, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction (two
cycles). Otherwise proceed with the next instruction (one cycle).
Operation
Affected flag(s)
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
47August 18, 1999
HT49C50
SNZ [m].i
Description
Operation
Affected flag(s)
SUB A,[m]Subtract data memory from the accumulator
DescriptionThe specified data memory is subtracted from the contents of the accumula
Operation
Affected flag(s)
SUBM A,[m]Subtract data memory from the accumulator
DescriptionThe specified data memory is subtracted from the contents of the accumula-
Operation
Affected flag(s)
Skip if bit ²i² of the data memory is not zero
If bit ²i² of the specified data memory is not zero, the next instruction is
skipped. If bit ²i² of the data memory is not zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (two cycles). Otherwise proceed
with the next instruction (one cycle).
Skip if [m].i¹0
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
tor, leaving the result in the accumulator.
ACC ¬ ACC+[m
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
tor, leaving the result in the data memory.
[m] ¬ ACC+[m
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
]+1
]+1
-
SUB A,xSubtract immediate data from the accumulator
DescriptionThe immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
Affected flag(s)
ACC ¬ ACC+x
TC2 TC1TOPDOVZACC
¾¾¾¾ÖÖÖÖ
+1
48August 18, 1999
HT49C50
SWAP [m]Swap nibbles within the data memory
DescriptionThe low-order and high-order nibbles of the specified data memory (one of
the data memories) are interchanged.
Operation
Affected flag(s)
SWAPA [m]Swap data memory-place result in the accumulator
DescriptionThe low-order and high-order nibbles of the specified data memory are inter
Operation
Affected flag(s)
SZ [m]Skip if data memory is zero
DescriptionIf the contents of the specified data memory are zero, the following instruc
OperationSkip if [m]=0
Affected flag(s)
[m].3~[m].0 « [m].7~[m].4
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
changed, writing the result to the accumulator. The contents of the data
memory remain unchanged.
tion, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (two cycles). Otherwise
proceed with the next instruction (one cycle).
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
-
-
SZA [m]Move data memory to ACC, skip if zero
DescriptionThe contents of the specified data memory are copied to the accumulator. If
the contents is zero, the following instruction, fetched during the current in
struction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (two cycles). Otherwise proceed with the next instruction
(one cycle).
Operation
Affected flag(s)
Skip if [m]=0, ACC ¬ [m]
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
49August 18, 1999
-
HT49C50
SZ [m].i
Description
OperationSkip if [m].i=0
Affected flag(s)
TABRDC [m]Move the ROM code (current page) to TBLH and data memory
DescriptionThe low byte of ROM code (current page) addressed by the table pointer
Operation
Affected flag(s)
TABRDL [m]Move the ROM code (last page) to TBLH and data memory
DescriptionThe low byte of ROM code (last page) addressed by the table pointer (TBLP)
Operation
Affected flag(s)
Skip if bit ²i² of the data memory is zero
If bit ²i² of the specified data memory is zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (two cycles). Otherwise proceed
with the next instruction (one cycle).
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
is moved to the data memory and the high byte transferred to TBLH directly.
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
TC2 TC1TOPDOVZACC
¾¾¾¾¾¾¾¾
XOR A,[m]Logical XOR accumulator with data memory
DescriptionData in the accumulator and the indicated data memory perform a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
Affected flag(s)
ACC ¬ ACC ²XOR² [m]
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
50August 18, 1999
HT49C50
XORM A,[m]Logical XOR data memory with the accumulator
DescriptionData in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
zero flag is affected.
Operation
Affected flag(s)
XOR A,xLogical XOR immediate data to the accumulator
DescriptionData in the the accumulator and the specified data perform a bitwise logical
Operation
Affected flag(s)
[m] ¬ ACC ²XOR² [m]
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
Exclusive_OR operation. The result is stored in the accumulator. The zero
flag is affected.
ACC ¬ ACC ²XOR² x
TC2 TC1TOPDOVZACC
¾¾¾¾¾Ö¾¾
51August 18, 1999
HT49C50
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Microelectronics Enterprises Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
52August 18, 1999
-
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