Holtek Semiconductor Inc HT49C50 Datasheet

Features

Operating voltage: 2.2V~5.2V

8 input lines

12 bidirectional I/O lines

Two external interrupt input

Two 8-bit programmable timer/event

counter with PFD (programmable fre quency divider) function LCD driver with 33 ´ 3or32´ 4 segments

4K ´ 15 program memory ROM

160 ´ 8 data memory RAM

Real Time Clock (RTC)

8-bit prescaler for RTC

Watchdog timer

General Description

The HT49C50 is an 8-bit high performance single chip microcontroller. Its single cycle instruction and two-stage pipeline architecture make it suit able for high speed applications. The device is suited for use in multiple LCD low power applica-

HT49C50

8-Bit Microcontroller

Buzzer output

On-chip crystal and RC oscillator

Halt function and wake-up feature reduce

power consumption 6-level subroutine nesting

Bit manipulation instruction

15-bit table read instruction

Up to 1ms instruction cycle with 4MHz

system clock 63 powerful instructions

All instructions in 1 or 2 machine cycles

80/100-pin QFP package

tions among which are calculators, clock timers, games, scales, leisure products, other hand held LCD products, and battery system in particular.

1 August 18, 1999

Block Diagram

HT49C50

Program

ROM

Instructio n

R egister

Instructio n

D ecoder

Tim ing

Generation

OSC2 OSC1

RES VDD VSS

Program

C ounter

STACK

MUX

ALU

S h ifte r

ACC

LCD DRIVER

M U X

Interrupt

Circuit

DATA

Memory

STATUS

LCD

Memory

IN T C

Tim er CLK0~1

TM R 0 TM R 1

TM R 0C TM R 1C

RTC

WDT

Tim e Base

PORT B

PORT A

M U X

SYS C LK/4

M U X

WDT OSC

TM R 0~1

RTC O SC

PC0~PC3

PB0/IN T0

PB1/IN T1 PB2/TMR 0 PB3/TMR 1

PB4~PB7

PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7

OSC3

OSC4

COM 0~ COM 2

COM 3~ SEG32

SEG 0~ SEG 31

2 August 18, 1999

Pin Assignment

NCNCNCNCNC

HT49C50

OSC3

OSC4

OSC2

OSC1

VDD

RES

SEG 0

PA0/BZ PA1/BZ

PA2

PA3/PFD

PA4 PA5 PA6

PA7 PB0/IN T0 PB1/IN T1

PB2/TMR0 PB3/TMR1

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

VSS

NC NC NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

26 27 28 29 30 31 32 33 343536

VLCDV1V2C1C2

H T49C 50 8 0 Q F P

COM 0

COM 1

COM 2

65666768697071727374757677787980

SEG 1

SEG 2

SEG 3

SEG 4

SEG 5

SEG 6

SEG 7

SEG 8

SEG 9

SEG 10

SEG 11

SEG 12

SEG 13

SEG 14

SEG 15

SEG 16

SEG 17

SEG 18

SEG 19

SEG 20

SEG 21

SEG 22

SEG 23

SEG 24

SEG 26

SEG 27

SEG 28

SEG 25

SEG 31

SEG 30

SEG 29

37 38 39 40

SEG 32/COM 3

3 August 18, 1999

HT49C50

OSC4

OSC3

OSC2

OSC1

VDD

RES

NC NC NC NC

NC PA0/BZ PA1/BZ

PA2

PA3/PFD

PA4 PA5 PA6

PA7 PB0/INT0 PB1/INT1

PB2/TM R0 PB3/TM R1

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

NC NC NC NC NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50

VLCD

VSS

HT49C50 100 Q FP

SEG32/C OM 3

COM 2

COM 1

COM 0C2C1

SEG27

SEG28

SEG29

SEG30

SEG31

81828384858687888990919293949596979899100

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

4 August 18, 1999

Pad Assignment

PA2

PA4

PA5

PA6

PA7

PB4

PB5

PB6

PB7

PC0

PC1

PC2

PC3

VSS

PA0/BZ

PA1/BZ

PA3/PFD

PB0/IN T0

PB1/IN T1

PB2/TMR 0

PB3/TMR 1

HT49C50

OSC2

COM 1

COM 2

VDD

(0 ,0 )

31 32 33 34 35 36 37

SEG 32/C OM 3

SEG 31

OSC4

OSC3

SEG 30

SEG 29

SEG 28

SEG 27

SEG 26

SEG 25

SEG 0

6162

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG 24

SEG23

OSC1

C1C2COM 0

26 27 28

RES

VLCD

* The IC substrate should be connected to VSS in the PCB layout artwork.

5 August 18, 1999

Pin Description

HT49C50

Pin Name I/O

PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7

PB0/INT0 PB1/INT1 PB2/TMR0 PB3/TMR1 PB4~PB7

PC0~PC3 I/O

VSS I

VLCD I

V1,V2,C1,C2 I

SEG32/COM3 COM2~COM0

SEG31~SEG0 O

OSC4 OSC3

VDD

OSC2 OSC1

RES

I/O

¾¾

OICrystal or

Mask

Option

Wake-up Pull-high

or None

CMOS or

NMOS

Pull-high

or None

CMOS or

NMOS

1/3 or 1/4

Duty

Description

PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trigger input capability. Each bit on port can be configured as a wake-up input by mask option. PA0~PA3 can be configured as a CMOS output or NMOS input/output with or without pull-high resistor by mask option. PA4~PA7 are al ways pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by mask op tion. PA3 can be set as an I/O pin or as a PFD output also by mask option.

PB0~PB7 constitute an 8-bit Schmitt trigger input port. Each bit on port are pull-high resistor. Of the eight bits, PB0 and PB1 can be set as input pins or as external interrupt control pins (INT0

) and (INT1) respectively, by software application. PB2 and PB3 can be set as an input pin or as a timer/event counter input pin TMR0 and TMR1 also by software application.

PC0~PC3 constitute a 4-bit bidirectional input/output port with a schmitt trigger input capability. On the port, such can be configured as CMOS output or NMOS input/output with or without pull-high resistor by mask option.

Negative power supply, GND

LCD power supply

Voltage pump

SEG32 can be set as a segment or as a common output driver for LCD panel by mask option. COM2~COM0 are outputs for LCD panel plate.

LCD driver outputs for LCD panel segments

Real time clock oscillators

Positive power supply

OSC1 and OSC2 are connected to an RC network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

Schmitt trigger reset input, active low

6 August 18, 1999

Absolute Maximum Ratings

HT49C50

Supply Voltage........................VSS-0.3V to 5.5V

Input Voltage .................V

-0.3V to VDD+0.3V

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-25°Cto70°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo sure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Symbol Parameter

DD1

DD2

STB1

STB2

IL1

IH1

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Standby Current (RTC Enable, LCD ON)

Standby Current (RTC Disable, LCD OFF)

I/O Port Input Low Voltage

I/O Port Input High Voltage

Input Low Voltage (RES

, INT0, INT1, TMR0, TMR1)

Input High Voltage (RES

, INT0, INT1, TMR0, TMR1)

I/O Ports Sink Current

Conditions

¾¾

No load, f

=4MHz

SYS

No load,

=2MHz

SYS

No load, system halt

RES

=0.5V

INT0/1=0.3V

5V 0

TMR0/1=0.3V

0.8V

5V 4.0

=3V,

=0.3V

=5V,

=0.5V

Min. Typ. Max. Unit

2.2

12mA

2.5 5 mA

0.75 1.5 mA

1.5 3 mA

¾¾

2.1

3.5

2.4

1.5/0.9 V

2.5/1.5 V

1.5 2.5

5.2 V

0.9 V

1.5 V

7 August 18, 1999

HT49C50

Symbol Parameter

I/O Ports Source Current

Pull-high Resistance of

I/O Ports and INT0

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

TIMER

WDTOSC

RES

SST

INT

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency

(TMR0/TMR1)

Watchdog Oscillator

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

, INT1

Test Conditions

Conditions

=3V,

=2.7V

=5V,

=4.5V

Test Conditions

Conditions

=3V

=5V

=3V

=5V

=3V

=5V

=3V

=5V

¾¾

Power-up or

wake-up from halt

¾¾

Min. Typ. Max. Unit

-1 -1.5 ¾

-2 -3 ¾

40 60 80

10 30 50

Ta=25°C

Min. Typ. Max. Unit

455

400

45 90 180

35 65 130

1024

4000 kHz

2000 kHz

3000 kHz

4000 kHz

¾¾ms

SYS

¾¾ms

Note: t

SYS

= 1/f

SYS

8 August 18, 1999

Functional Description

Execution flow

The system clock is derived from either a crys tal or an RC oscillator. It is internally divided into four non-overlapping clocks. One instruc tion cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the value of the program counter, two cycles are re quired to complete the instruction.

Program counter - PC

The program counter (PC) is of 12 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 4096 addresses.

After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program

transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instruc

tions. Once the condition is met, the next in

struction, fetched during the current

instruction execution, is discarded and a dummy cycle replaces it to get a proper instruc tion; otherwise proceed with the next instruc tion.

The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destina

tion is within 256 locations.

When a control transfer takes place, an addi tional dummy cycle is required.

Program memory - ROM

The program memory (ROM) is used to store the program instructions which are to be exe cuted. It also contains data, table, and inter rupt entries, and is organized into 4096 ´ 15 bits which are addressed by the PC and table pointer.

Certain locations in the ROM are reserved for special usage:

Location 000H Location 000H is reserved for program initial-

ization. After chip reset, the program always begins execution at this location.

HT49C50

S ystem C lock

OSC2 (RC only)

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

PC PC+1 PC+2

F e tc h IN S T ( P C )

Execute IN S T (P C-1)

F e tc h IN S T ( P C + 1 )

Execute IN S T (P C)

F e tc h IN S T ( P C + 2 )

Execute IN S T (P C+1)

Execution flow

9 August 18, 1999

HT49C50

Location 004H Location 004H is reserved for the external in

terrupt service program. If the INT0

input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.

Location 008H Location 008H is reserved for the external in

terrupt service program also. If the INT1 put pin is activated, and the interrupt is

000H

004H

008H

00C H

010H

014H

018H

D evice initialization program

External interrupt 0 subroutine

External interrupt 1 subroutine

Tim er/event counter 0 interrupt subroutine

Tim er/event counter 1 interrupt subroutine

T im e B a s e In te rr u p t

R T C In te rru p t

Program ROM

enabled, and the stack is not full, the program begins execution at location 008H.

Location 00CH

n00H

nFFH

Look-up table (256 w ords)

Location 00CH is reserved for the timer/event counter 0 interrupt service program. If a timer interrupt results from a timer/event counter 0 overflow, and if the interrupt is en abled and the stack is not full, the program begins execution at location 00CH.

Location 010H Location 010H is reserved for the timer/event

counter 1 interrupt service program. If a timer interrupt results from a timer/event

Mode

*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

FFFH

counter 1 overflow, and if the interrupt is en abled and the stack is not full, the program begins execution at location 010H.

Program Counter

Look-up table (256 w ords)

15 bits

N o te : n r a n g e s fro m 0 to F

Program memory

Initial Reset 0 0000000 00 00

External Interrupt 0 0 000000001 00

External Interrupt 1 0 000000010 00

Timer/event counter 0 overflow 0 00000001100

Timer/event counter 1 overflow 0 00000010000

Time Base Interrupt 0 000000101 00

RTC Interrupt 0 000000110 00

Skip PC+2

Loading PCL *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return From Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Notes: *11~*0: Program counter bits

#11~#0: Instruction code bits

Program counter

S11~S0: Stack register bits

@7~@0: PCL bits

10 August 18, 1999

Location 014H Location 014H is reserved for the Time Base

interrupt service program. If a Time Base in terrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H.

Location 018H Location 018H is reserved for the real time

clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H.

Table location Any location in the ROM can be used as a

look-up table. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the ta ble is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH, and the remaining 1 bit is read as ²0². The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the user¢s requirements.

Stack register - STACK

The stack register is a special part of the mem

ory used to save the contents of the PC. The

stack is organized into 6 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a commence ment of a subroutine call or an interrupt ac knowledgment, the contents of the PC is pushed onto the stack. At the end of the subrou tine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag is re corded but the acknowledgment is still inhib ited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the program

mer to use the structure easily. Likewise, if the stack is full, and a ²CALL² is subsequently exe cuted, a stack overflow occurs and the first en try is lost (only the most recent six return addresses are stored).

Data memory - RAM

The data memory (RAM) is designed with 192´8 bits, and is divided into two functional groups, namely special function registers and general purpose data memory, most of which are readable/writeable, although some are read only.

HT49C50

Instruction(s)

*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Notes: *11~*0: Table location bits

P11~P8: Current program Counter bits

@7~@0: Table pointer bits

11 August 18, 1999

HT49C50

Ind irect A ddressing R egister 0

00H

01H

Ind irect A ddressing R egister 1

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH 1FH

60H

FFH

MP0

MP1

ACC

PCL

TBLP

TBLH

RTCC

STATUS

IN T C 0

TM R 0

TM R 0C

TM R 1

TM R 1C

IN T C 1

G eneral P urpose DATA M EMO RY

(160 Bytes)

Special P urpose DATA M EMO RY

: U nused.

R ead as ²00

RAM mapping

Of the two types of functional groups, the special function registers consist of an Indirect address ing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H),

a Table higher-order byte register (TBLH;08H), a Real time clock control register (RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a timer/event counter 0 (TMR0;0DH), a timer/event counter 0 control register (TMR0C;0EH), a timer/event counter 1 (TMR1;10H), a timer/event counter 1 control register (TMR1C;11H), I/O registers (PA;12H, PB;14H, PC;16H), and Interrupt con trol register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 60H to FFH, is used for data and control in formation under instruction commands.

The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by ²SET [m].i²and ²CLR [m].i². They are also indi rectly accessible through the Memory pointer register 0 (MP0;01H) or the Memory pointer register 1 (MP1;03H).

Indirect addressing register

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation.

The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0 can only be applied to data memory, while MP1 can be applied to data memory and LCD display memory.

Accumulator - ACC

The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with im mediate data. The data movement between two data memory locations must pass through the ACC.

12 August 18, 1999

HT49C50

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operations and provides the following func tions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ etc.)

The ALU not only saves the results of a data op eration but also changes the status register.

Status register - STATUS

The status register (0AH) is of 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PD), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence.

Except the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PD flags. Oper

ations related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a

watchdog timer overflow, chip power-up, or

clearing the watchdog timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the latest operations.

On entering the interrupt sequence or execut ing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status

tions and save it properly.

Interrupts

The HT49C50 provides two external inter rupts, two internal timer/event counter inter rupts, an internal time base interrupt, and an internal real time clock interrupt. The inter rupt control register 0 (INTC0;0BH) and inter rupt control register 1 (INTC1;1EH) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags.

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor-

row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

AC 1

borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

OV 3

PD 4

TO 5

¾ ¾

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by either a system power-up or executing the ²CLR WDT² instruc tion. PD is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² in struction. TO is set by a WDT time-out.

Undefined, read as ²0²

Status register

13 August 18, 1999

HT49C50

Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This scheme may prevent any further in terrupt nesting. Other interrupt requests may take place during this interval, but only the in terrupt request flag will be recorded. If a cer tain interrupt requires servicing within the service routine, the EMI bit and the correspond ing bit of the INTC0 or of INTC1 may be set in order to allow interrupt nesting. Once the stack is

Control the master (global) interrupt (1=enabled; 0=disabled)

Control the external interrupt 0 (1=enabled; 0=disabled)

Control the external interrupt 1 (1=enabled; 0=disabled)

Control the timer/event counter 0 interrupt (1=enabled; 0=disabled)

External interrupt 0 request flag (1=active; 0=inactive)

External interrupt 1 request flag (1=active; 0=inactive)

Internal timer/event counter 0 request flag (1=active; 0=inactive)

Control the timer/event counter 1 interrupt (1=enabled; 0=disabled)

Control the time base interrupt (1=enabled; 0:disabled)

Control the real time clock interrupt (1=enabled; 0:disabled)

Internal timer/event counter 1 request flag (1=active; 0=inactive)

Time base request flag (1=active; 0=inactive)

Real time clock request flag (1=active; 0=inactive)

INTC0

(0BH)

INTC1

(1EH)

0 EMI

1 EEI0

2 EEI1

3 ET0I

4 EIF0

5 EIF1

6 T0F

0 ET1I

1 ETBI

2 ERTI

4 T1F

5 TBF

6 RTF

¾ Unused bit, read as ²0²

full, the interrupt request will not be acknowl edged, even if the related interrupt is enabled, until the SP is decremented. If immediate service

is desired, the stack should be prevented from be coming full.

All these interrupts can support a wake-up

function. As an interrupt is serviced, a control

transfer occurs by pushing the contents of the

PC onto the stack followed by a branch to a sub

INTC register

14 August 18, 1999

HT49C50

routine at the specified location in the ROM. Only the contents of the PC is pushed onto the stack. If the contents of the register or of the status register (STATUS) is altered by the in terrupt service program which corrupts the de sired control sequence, the contents should be saved in advance.

External interrupts are triggered by a high to low transition of INT0 interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the in terrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The interrupt re quest flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts.

The internal timer/event counter 0 interrupt is initialized by setting the timer/event counter 0 interrupt request flag (T0F; bit 6 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable further interrupts. The timer/event counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 4 of INTC1) and its subroutine call location is 10H.

The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC1), that is caused by a regular time base signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts.

The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC1), that is caused by a regular real time clock signal. After the inter rupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to dis able further interrupts.

During the execution of an interrupt subroutine, other interrupt acknowledgments are all held

or INT1, and the related

until the ²RETI² instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return

from the interrupt subroutine, ²RET² or ²RETI²

may be invoked. RETI sets the EMI bit and en ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In

the case of simultaneous requests, the priori ties in the following table apply. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External interrupt 0 1 04H

b External interrupt 1 2 08H

Timer/event

counter 0 overflow

Timer/event

counter 1 overflow

Time base

interrupt

Real time clock

interrupt

The timer/event counter 0 interrupt request flag (T0F), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable timer/event counter 0 interrupt bit (ET0I), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), timer/event counter 1 interrupt request flag (T1F), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), enable

timer/event counter 1 interrupt bit (ET1I) on the other hand, constitute the Interrupt Con trol register 1 (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ET0I, ET1I,

ETBI, and ERTI are all used to control the en able/disable status of interrupts. These bits prevent the requested interrupt from being ser

3 0CH

4 10H

5 14H

6 18H

15 August 18, 1999

HT49C50

viced. Once the interrupt request flags (RTF, TBF, T0F, T1F, EIF1, EIF0) are all set, they re main in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a soft ware instruction.

It is recommended that a program not use the ²CALL subroutine² within the interrupt subroutine. It¢s because interrupts often occur in an unpredictable manner or require to be serviced immediately in some applications. At this time, if only one stack is left, and enabling the interrupt is not well con trolled, operation of the ²call² in the interrupt subroutine may damage the original control se quence.

Oscillator configuration

The HT49C50 provides two oscillator circuits for system clocks, i.e., RC oscillator and crystal oscillator, determined by mask option. No mat ter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator and ignores external signal to conserve power.

Of the two oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 51kW to 1MW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.

OSC1

VDD

On the other hand, if the crystal oscillator is se lected, a crystal across OSC1 and OSC2 is

needed to provide the feedback and phase shift required for the oscillator, and no other exter

nal components are required. A resonator may be connected between OSC1 and OSC2 to re place the crystal and to get a frequency refer ence, but two external capacitors in OSC1 and OSC2 are required.

There is another oscillator circuit designed for the real time clock. In this case, only the

32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3

and OSC4, and two external capacitors along with one external resistor are required for the oscillator circuit in order to get a stable fre quency.

The RTC oscillator circuit can be controlled to oscillate quickly by setting the ²QOSC² bit (bit

4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and turn it off after 2 seconds.

OSC3

OSC4

RTC oscillator

The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 78ms. The WDT oscillator can be disabled by mask option to conserve power.

OSC2

C rystal O scillator

System oscillator

SYS

OSC2

R C O s c illa to r

16 August 18, 1999

+ 36 hidden pages

Holtek Semiconductor Inc HT49C50 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pin Assignment

Pad Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description