Holtek Semiconductor Inc HT49C10 Datasheet

Features

Operating voltage: 2.2V~5.2V

Eight bidirectional I/O lines

Six input lines

Two external interrupt input

8-bit programmable timer/event counter

withPFD(programmablefrequencydivider) Watchdog timer

On-chip crystal and RC oscillator

1K´14 program memory ROM

64´8 data memory RAM

Real Time Clock (RTC)

8-bit prescaler for RTC

General Description

The HT49C10 is an 8-bit high performance single chip microcontroller. Its single-cycle instruction and two-stage pipeline architecture make it suit able for high speed applications. The device is

HT49C10

8-Bit Microcontroller

Buzzer output

Halt function and wake-up feature reduce

power consumption LCD driver with 19´3or18´4 segments

4-level subroutine nesting

Bit manipulation instruction

14-bit table read instruction

Up to 1ms instruction cycle with 4MHz

system clock 63 powerful instructions

All instructions in 1 or 2 machine cycles

48-pin SSOP package

also suited for multiple LCD low power applica tions among which are calculators, clock timers, games, scales, leisure products, other hand held

LCD products, and battery systems in particular.

1 September 28, 1999

Block Diagram

HT49C10

Program

ROM

Instruction

R egister

Instruction

D ecoder

Tim ing

G enerator

OSC2

OSC1 RES

VDD VSS

Program

C ounter

MUX

ALU

Shifter

ACC

LCD DRIVER

STACK

M U X

Interrupt

Circuit

DATA

Memory

STATUS

LC D

Memory

IN T C

Tim er CLK

TM R

TM R C

RTC

WDT

Tim e Base

PORT B

PORT A

M U X

SYS CLK/4

M U X

WDT OSC

PB0/IN T0

PB1/IN T1 PB2/TM R PB3~PB5

PA0/BZ PA1/BZ

PA2 PA3/PFD PA4~PA7

TM R

RTC OSC

OSC3

OSC4

COM 0~ COM 2

COM 3/ SEG18

SEG0~ SEG17

2 September 28, 1999

Pin Assignment

HT49C10

PA0/BZ

PA1/BZ

PA2

PA3/PFD

PA4

PA5

PA6

PA7

PB0/IN T0

PB1/IN T1

PB2/TMR

PB3

PB4

PB5

VSS

VLCD

COM 0

COM 1

COM 2

SEG 18/CO M 3

HT49C10

48 SS O P

RES

OSC1

OSC2

VDD

OSC3

OSC4

SEG 0

SEG 1

SEG 2

SEG 3

SEG 4

SEG 5

SEG 6

SEG 7

SEG 8

SEG 9

SEG 10

SEG 11

SEG 12

SEG 13

SEG 14

SEG 15

SEG 16

SEG 17

3 September 28, 1999

Pad Assignment

PA4

HT49C10

PA3/PFD

PA2

PA0/BZ

PA1/BZ

RES

OSC1

OSC2

VDD

PA5

PA6

PA7

PB0/INT0

PB1/INT1

PB2/TMR

PB3

PB4

PB5

VSS

VLCD

14 15 16 17 18 19 20 21 22 23 24 25 26 27

464748

COM0

(0,0)

COM1

COM2

SEG18/COM3

SEG17

SEG16

SEG15

SEG14

SEG13

OSC3

OSC4

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG12

SEG11

* The IC substrate should be connected to VSS in the PCB layout artwork.

4 September 28, 1999

Pad Description

HT49C10

Pad No. Pad Name I/O

45 46 47 48 1~4

5 6 7 8~10

11 VSS I

12 VLCD I

13~16 V1,V2,C1,C2 I

PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7

PB0/INT0 PB1/INT1 PB2/TMR PB3~PB5

I/O

Mask

Option

Wake-up

Pull-high

or None

CMOS or

NMOS

Description

PA0~PA7 constitute an 8-bit bidirectional input/ out put port with Schmitt trigger input capability. Each bit on port can be configured as wake-up input by mask option. PA0~PA3 can be configured as CMOS (output) or NMOS (input/output) and with or without pull-high resistor by mask option, PA4~PA7 always pull-high and NMOS (input/output). Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by mask option. PA3 can be set as an I/O pin or a PFD output also by mask option.

PB0~PB5 constitute a 6-bit Schmitt trigger input port. Each bit on port are pull-high resistor. Of the six bits, PB0 can be set as input pin or external interrupt control pin (INT0 set as input pin or an external interrupt control pin (INT1

) by software application. While PB2 can be set as input pin or timer/event counter input pin also by software application.

Negative power supply, GND

LCD power supply

Voltage pump

) by software application. PB1 can be

20 19~17

21~38 SEG17~SEG0 O

39 40

41 VDD

42 43

44 RES

SEG18/COM3 COM2~COM0

OSC4 OSC3

OSC2 OSC1

1/3 or 1/4

Duty

¾¾

OICrystal or

SEG18 can be set as segment or common output driver for LCD panel by mask option. COM2~COM0 are outputs for LCD panel plate.

LCD driver outputs for LCD panel segments

Real time clock oscillators

Positive power supply

OSC1 and OSC2 are connected to an RC network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output termi nal for 1/4 system clock.

Schmitt trigger reset input, active low

5 September 28, 1999

Absolute Maximum Ratings

HT49C10

Supply Voltage..............................-0.3V to 5.5V

Input Voltage.................V

-0.3V to VDD+0.3V

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-25°Cto70°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo sure to extreme conditions may affect device reliability.

D.C. Characteristics

Symbol Parameter

DD1

DD2

STB1

STB2

IL1

IH1

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Standby Current (RTC Enable, LCD On)

Standby Current (RTC Disable, LCD Off)

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES

, INT0, INT1, TMR)

Input High Voltage (RES

, INT0, INT1, TMR)

I/O Ports Sink Current

I/O Ports Source Current

Pull-high Resistance of I/O Ports and INT0

, INT1

Test Conditions

Conditions

Min. Typ. Max. Unit

¾¾

No load,

=4MHz

SYS

No load,

=2MHz

SYS

No load,

system Halt

No load,

system Halt

5V 0

5V 4.0

RES

=0.5V

INT0/1=0.3V

TMR=0.3V

0.8V

=0.3V

=0.5V

=2.7V

=4.5V

2.2

0.7 1.5 mA

23mA

0.5 1 mA

12mA

¾¾

2.1

3.5

2.4

1.5 2.5

-1 -1.5 ¾

-2 -3 ¾

40 60 80

10 30 50

Ta=25°C

5.2 V

0.9 V

1.5 V

1.5/0.9 V

2.5/1.5 V

6 September 28, 1999

HT49C10

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

TIMER

WDTOSC

RES

SST

INT

Note: t

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency (TMR)

Watchdog Oscillator

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

=1/f

SYS

Test Conditions

Conditions

¾¾

Power-up or

wake-up from halt

¾¾

Ta=25°C

Min. Typ. Max. Unit

455

400

45 90 180

35 65 130

1024

4000 kHz

2000 kHz

3000 kHz

4000 kHz

¾¾ms

SYS

¾¾ms

7 September 28, 1999

Functional Description

Execution flow

The system clock is derived from either a crys tal or an RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction.

Program counter - PC

The 10-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 1024 ad dresses.

After accessing a program memory word to fetch an instruction code, the value of the PC is incre mented by one. The PC then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates program transfer by loading the address corresponding to each instruction.

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

S ystem C lock

The conditional skip is activated by instructions. Once the condition is met, the next instruction,

fetched during the current instruction execu tion, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed with the next instruction.

The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destina tion is within 256 locations.

When a control transfer takes place, an addi tional dummy cycle is required.

Program memory - ROM

The program memory (ROM) is used to store the program instructions which are to be exe cuted. It also contains data, table, and inter rupt entries, and is organized into 1024´14 bits which are addressed by the PC and table

pointer.

Certain locations in the ROM are reserved for special usage:

Location 000H Location 000H is reserved for program initial-

ization. After chip reset, the program always begins execution at this location.

Location 004H Location 004H is reserved for the external in-

terrupt service program. If the INT0 pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H.

HT49C10

input

OSC2 (RC only)

PC PC+1 PC+2

F e tc h IN S T (P C )

Execute IN S T (P C -1)

F e tc h IN S T (P C + 1 )

Execute IN S T (P C )

Execution flow

8 September 28, 1999

F e tc h IN S T (P C + 2 )

Execute IN S T (P C +1)

HT49C10

Location 008H

Location 008H is reserved for the external in terrupt service program. If the INT1

input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins exe cution at location 008H.

Location 00CH Location 00CH is reserved for the timer/event

counter interrupt service program. If a timer interrupt resulting from a timer/event coun ter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.

Location 010H Location 010H is reserved for the time base

interrupt service program. If a time base in terrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 010H.

Location 014H Location 014H is reserved for the real time

clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is en abled, and the stack is not full, the program begins execution at location 014H.

000H

004H

008H

00C H

010H

014H

D evice initialization program

External interrupt0 subroutine

External interrupt1 subroutine

Tim er/event counter interrupt subroutine

Tim e base interrupt

RTC interrupt

Program ROM

n00H

nFF H

3FFH

Look-up table (256 w ords)

14 bits

N ote: n ranges from 0 to 3

Program memory

Table location Any location in the ROM can be used as a

look-up table. The instructions²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL[m]² (the last page) transfer the con-

Mode

Program Counter

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Initial reset 0000000000

External interrupt 0 0000000100

External interrupt 1 0000001000

Timer/event Counter overflow 0000001100

Time Base Interrupt 0000010000

RTC Interrupt 0000010100

Skip PC+2

Loading PCL *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return From Subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *9~*0: Program counter bits

#9~#0: Instruction code bits

9 September 28, 1999

S9~S0: Stack register bits @7~@0: PCL bits

HT49C10

tents of the lower-order byte to the specified data memory, and the contents of the higher-order byte toTBLH (table higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH, and the remaining two bits are both read as ²0². TheTBLH isread only, and the ta ble pointer (TBLP) is a read/write register (07H), indicating the table location. Before ac cessing the table, the location should be placed in TBLP. All the table related instructions re quire two cycles to complete the operation. These areas may function as a normal ROM dependingupontherequirements.

Stack register - STACK

The stack register is a special part of the mem ory used to save the contents of the PC. The stack is organized into four levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a commence ment of a subroutine call or an interrupt ac knowledgment, the contents of the PC is pushed onto the stack. At the end of the subroutine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the in

terrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a ²CALL² is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent four return addresses are stored).

Data memory - RAM

The data memory (RAM) is designed with 81´8 bits, and is divided into two functional groups,

namely special function registers and general

purpose data memory, most of which are read

able/writeable, although some are read only.

Of the two types of functional groups, the special function registers consist of an indirect addressing register 0 (00H), a memory pointer register 0 (MP0; 01H), an indirect addressing register 1 (02H), a memory pointer register 1 (MP1;03H), a bank

pointer (BP;04H), an accumulator (ACC;05H), a

program counter lower-order byte register (PCL;06H), a table pointer (TBLP;07H), a table higher-order byte register (TBLH;08H), a real time clock control register (RTCC;09H), a status register (STATUS;0AH), an interrupt control reg

ister 0 (INTC0;0BH), a timer/event counter

(TMR;0DH), a timer/event counter control register

(TMRC; 0EH), I/O registers (PA;12H, PB;14H), and interrupt control register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 20H to 5FH, is used for data and control information under instruction commands.

The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except for some dedicated bits, each bit in the RAM can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indi

rectly accessible through the memory pointer

Instruction(s)

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *9~*0: Table location bits

@7~@0: Table pointer bits

Table Location

P9~P8: Current program counter bits

10 September 28, 1999

HT49C10

Indirect Addressing R egister 0

00H

01H

Ind irect A dd ressing R eg ister1

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH

1FH 20H

5FH

MP0

MP1

ACC

PCL

TBLP

TBLH

RTCC

STATUS

IN T C 0

TM R

TM R C

IN T C 1

G eneral Purpose

D ata M em ory

(64 B ytes)

Special P urpose D ata M em ory

: U n u s e d

R ead as "00"

RAM mapping

Indirect addressing register

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] ac cesses the RAM pointed to by MP0 (01H) and

MP1 (03H) respectively. Reading location 00H

or 02H indirectly returns the result 00H, while, writing it leads to no operation.

The function of data movement between two in direct addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 7-bit registers used to access the RAM by combining corresponding indirect address ing registers. The bit 7 of MP0 and MP1 are un defined and reading will return the result 1 . Any writing operation to MP0 and MP1 will only transfer the lower 7-bit data.

Only MP0 can be applied to data memory, while MP1 can be applied to data memory and LCD display memory.

Accumulator - ACC

The accumulator (ACC) is related to ALU oper ations. It is also mapped to location 05H of the RAM and is capable of carrying out immediate data operations. The data movement between two data memory locations has to pass through the ACC.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operations and provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ etc.)

The ALU not only saves the results of a data operation but also changes the status register.

Status register - STATUS

The status register (0AH) is 8-bit wide and con tains a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PD), and a watchdog time-out flag (TO). It also records the status information and controls the operation sequence.

Except for the TO and PD flags, bits in the status

other registers. Data written into the status reg

11 September 28, 1999

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor

AC 1

OV 3

PD 4

TO 5

row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by either a system power-up or executing the ²CLR WDT² instruc tion. PD is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² in struction. TO is set by a WDT time-out.

6, 7

Undefined, read as ²0²

STATUS register

HT49C10

ister does not alter the TO or PD flags. Opera tions related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a watch dog timer overflow, chip power-up, or clearing the watchdog timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of the latest operations.

On entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, precautions should be taken to save it properly.

Interrupts

The HT49C10 provides two external interrupts, an internal timer/event counter interrupt, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the inter rupt control bits that are used to set the en able/disable status and interrupt request flags.

Once an interrupt subroutine is serviced, other

interrupts are all blocked (by clearing the EMI

bit). This scheme may prevent any further in terrupt nesting. Other interrupt requests may take place during this interval, but only the in

terrupt request flag will be recorded. If a certain interrupt requires servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of INTC0 or of INTC1 in order to allow interrupt nesting. Once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack should be prevented from becoming full.

All these interrupts have the wake-up capability. When an interrupt is serviced, a control trans fer occurs by pushing the PC onto the stack, fol lowed by a branch to subroutines at the specified locations in the ROM. Only the PC is pushed onto the stack. If the contents of the reg ister or of the status register (STATUS) is al tered by the interrupt service program which corrupts the desired control sequence, the con

tents should be saved first.

External interrupts are triggered by a high to low transition of INT0

or INT1, and the related

12 September 28, 1999

Control the master (global) interrupt (1= enabled; 0= disabled)

Control the external interrupt 0 (1= enabled; 0= disabled)

Control the external interrupt 1 (1= enabled; 0= disabled)

Control the timer/event counter interrupt (1= enabled; 0= disabled)

External interrupt 0 request flag (1= active; 0= inactive)

External interrupt 1 request flag (1= active; 0= inactive)

Internal timer/event counter request flag (1= active; 0= inactive)

Control the time base interrupt (1= enabled; 0= disabled)

Control the real time clock interrupt (1= enabled; 0= disabled)

Time base request flag (1= active; 0= inactive)

Real time clock request flag (1= active; 0= inactive)

INTC0

(0BH)

INTC1

(1EH)

0 EMI

1 EEI0

2 EEI1

3 ETI

4 EIF0

5 EIF1

6TF

0 ETBI

1 ERTI

2, 3

4 TBF

5 RTF

6, 7

¾ Unused bit, read as ²0²

HT49C10

INTC register

interrupt request flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well. After the in terrupt is enabled, and the stack is not full, and the external interrupt is active, a subroutine call to location 04H or 08H occurs. The inter rupt request flag (EIF0 or EIF1) and EMI bits are all cleared to disable other interrupts.

The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 6 of INTC0), that is caused by a timer overflow. After the inter rupt is enabled, and the stack is not full, and the TF bit is set, a subroutine call to location 0CH occurs. The related interrupt request flag

(TF) is reset, and the EMI bit is cleared to disable further interrupts.

The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 4

of INTC1), that is caused by a regular time base

signal. After the interrupt is enabled, and the stack is not full, and the TBF bit is set, a sub routine call to location 10H occurs. The related interrupt request flag (TBF) is reset and the EMI bit is cleared to disable further interrupts.

The real time clock interrupt is initialized by

setting the real time clock interrupt request flag (RTF; bit 5 of INTC1), that is caused by a

13 September 28, 1999

HT49C10

regular real time clock signal. After the inter rupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 14H occurs. The related interrupt request flag (RTF) is reset and the EMI bit is cleared to dis able further interrupts.

During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the ²RETI² instruction is executed or the EMI bit and the related interrupt control bit are set both to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI sets the EMI bit and en ables an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External interrupt 0 1 04H

b External interrupt 1 2 08H

Timer/event

counter overflow

3 0CH

d Time base interrupt 4 10H

Real time clock

interrupt

5 14H

The timer/event counter interrupt request flag (TF), external interrupt 1 request flag (EIF1), external interrupt 0 request flag (EIF0), enable timer/event counter interrupt bit (ETI), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0), and enable master inter rupt bit (EMI) make up of the interrupt control register (INTC0) which is located at 0BH in the RAM. The real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit (ETBI), on the other hand, constitute the other interrupt con trol register (INTC1) which is located at 1EH in the RAM. EMI, EEI0, EEI1, ETI, ETBI, and ERTI are all used to control the enable/disable

status of the interrupts. These bits prevent the

requested interrupt from being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF1, EIF0) are all set, they remain in the INTC1 or INTC0 respectively until the inter

rupts are serviced or cleared by a software in struction.

It is recommended that a program not use the ²CALL subroutine² within the interrupt sub routine. It¢s because interrupts often occur in an unpredictable manner or require to be ser viced immediately in some applications. At this time, if only one stack is left, and enabling the

interrupt is not well controlled, operation of the ²call subroutine² in the interrupt subroutine may damage the original control sequence.

Oscillator configuration

The HT49C10 provides two oscillator circuits for system clocks, i.e., RC oscillator and crystal oscillator, determined by mask option. No mat ter what type of oscillator is selected, the signal is used for the system clock. The HALT mode stops the system oscillator and ignores an ex ternal signal to conserve power.

Of the two oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 51kW to 1MW. The system clock,

OSC1

OSC2

C r y s t a l O s c illa t o r R C O s c illa to r

System oscillator

SYS

OSC3

OSC4

RTC oscillator

OSC1

OSC2

14 September 28, 1999

HT49C10

divided by 4, is available on OSC2 with pull-high resistor, which can be used to syn chronize external logic. The RC oscillator pro vides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.

On the other hand, if the crystal oscillator is se lected, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. A resonator may be connected between OSC1 and OSC2 to replace the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are needed.

There is another oscillator circuit designed for the real time clock. In this case, only the

32.768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4, and two external capacitors along with one external resistor are required for the oscil lator circuit in order to get a stable frequency.

The RTC oscillator circuit can be controlled to oscillate quickly by setting ²QOSC² bit (bit 4 of RTCC). It is recommended to turn on the quick oscillating function upon power on, and turn it off after two seconds.

The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although the system enters the power down mode, the system clock stops, and the WDT oscillator still works with a period of approximately 78 ms. The WDT oscillator can be disabled by mask option to conserve power.

Watchdog timer - WDT

The WDT clock source is implemented by a ded

icated RC oscillator (WDT oscillator) or an in

struction clock (system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The WDT can be disabled by mask option. But if the WDT is dis

abled, all executions related to the WDT lead to no operation.

After the WDT clock source is selected, it time-out period is fs/2

~fs/216.

If the WDT clock source chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process varia tions. On the other hand, if the clock source se lects the instruction clock and the ²halt² instruction is executed, WDT may stop count ing and lose its protecting purpose, and the logic can only be restarted by external logic.

When the device operates in a noisy environ ment, using the on-chip RC oscillator (WDT

OSC) is strongly recommended, since the HALT

can stop the system clock.

The WDT overflow under normal operation initializes a ²chip reset² and sets the status bit ²TO². In the HALT mode, the overflow initializes a ²warm reset², and only the PC and SP are reset to zero. To clear the contents of the WDT, there are three methods to be adopted, i.e., external reset (a low level to RES instruction, and ²HALT² instruction. There are two sets of software instructions, ²CLR WDT² and the other set -²CLR WDT1² and ²CLR WDT2². Of these two types of instructions, only one type of instruction can be active at a time depending on the mask option -²CLR WDT

), software

S ystem C lo ck/4

RTC

32768H z

OSC

WDT

12kHz

OSC

Mask Option Select

D ivider

P rescale r

CK T CK T

W D T C lear

Tim e-out

15 16

R e s e t fs /2 ~ fs /2

Watchdog timer

15 September 28, 1999

+ 32 hidden pages

Holtek Semiconductor Inc HT49C10 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pin Assignment

Pad Assignment

Pad Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description