Holtek Semiconductor Inc HT49C10 Datasheet

Features

Operating voltage: 2.2V~5.2V

·

Eight bidirectional I/O lines

·

Six input lines

·

Two external interrupt input

·

8-bit programmable timer/event counter

·

withPFD(programmablefrequencydivider)
Watchdog timer

·

On-chip crystal and RC oscillator

·

1K´14 program memory ROM

·

64´8 data memory RAM

·

Real Time Clock (RTC)

·

8-bit prescaler for RTC

·

General Description

The HT49C10 is an 8-bit high performance single
chip microcontroller. Its single-cycle instruction
and two-stage pipeline architecture make it suit
able for high speed applications. The device is

HT49C10

8-Bit Microcontroller

Buzzer output

·

Halt function and wake-up feature reduce

·

power consumption
LCD driver with 19´3or18´4 segments

·

4-level subroutine nesting

·

Bit manipulation instruction

·

14-bit table read instruction

·

Up to 1ms instruction cycle with 4MHz

·

system clock
63 powerful instructions

·

All instructions in 1 or 2 machine cycles

·

48-pin SSOP package

·

also suited for multiple LCD low power applica
tions among which are calculators, clock timers,
games, scales, leisure products, other hand held

­LCD products, and battery systems in particular.

-

1 September 28, 1999

Block Diagram

HT49C10

Program

ROM

Instruction

R egister

Instruction

D ecoder

Tim ing

G enerator

OSC2

OSC1
RES

VDD
VSS

Program

C ounter

MP

MUX

ALU

Shifter

ACC

LCD DRIVER

STACK

M
U
X

Interrupt

Circuit

DATA

Memory

STATUS

BP

LC D

Memory

IN T C

Tim er CLK

TM R

TM R C

RTC

WDT

Tim e Base

PB

PA

PORT B

PORT A

M
U
X

SYS CLK/4

M
U
X

WDT OSC

PB0/IN T0

PB1/IN T1
PB2/TM R
PB3~PB5

PA0/BZ
PA1/BZ

PA2
PA3/PFD
PA4~PA7

TM R

RTC OSC

OSC3

OSC4

COM 0~
COM 2

COM 3/
SEG18

SEG0~
SEG17

2 September 28, 1999

Pin Assignment

HT49C10

PA0/BZ

PA1/BZ

PA2

PA3/PFD

PA4

PA5

PA6

PA7

PB0/IN T0

PB1/IN T1

PB2/TMR

PB3

PB4

PB5

VSS

VLCD

V1

V2

C1

C2

COM 0

COM 1

COM 2

SEG 18/CO M 3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

HT49C10

48 SS O P

RES

OSC1

OSC2

VDD

OSC3

OSC4

SEG 0

SEG 1

SEG 2

SEG 3

SEG 4

SEG 5

SEG 6

SEG 7

SEG 8

SEG 9

SEG 10

SEG 11

SEG 12

SEG 13

SEG 14

SEG 15

SEG 16

SEG 17

3 September 28, 1999

Pad Assignment

PA4

HT49C10

PA3/PFD

PA2

PA0/BZ

PA1/BZ

RES

OSC1

OSC2

VDD

PA5

PA6

PA7

PB0/INT0

PB1/INT1

PB2/TMR

PB3

PB4

PB5

VSS

VLCD

V1

1

2

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26 27

V2

C1

464748

45

C2

COM0

43

44

(0,0)

COM1

COM2

SEG18/COM3

SEG17

42

41

SEG16

SEG15

SEG14

SEG13

OSC3

40

OSC4

39

SEG0

38

SEG1

37

SEG2

36

35

SEG3

34

SEG4

33

SEG5

32

SEG6

31

SEG7

SEG8

30

29

SEG9

28

SEG10

SEG12

SEG11

* The IC substrate should be connected to VSS in the PCB layout artwork.

4 September 28, 1999

Pad Description

HT49C10

Pad No. Pad Name I/O

45
46
47
48
1~4

5
6
7
8~10

11 VSS I

12 VLCD I

13~16 V1,V2,C1,C2 I

PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7

PB0/INT0
PB1/INT1
PB2/TMR
PB3~PB5

I/O

I

Mask

Option

Wake-up

Pull-high

or None

CMOS or

NMOS

¾

¾

¾

¾

Description

PA0~PA7 constitute an 8-bit bidirectional input/ out
put port with Schmitt trigger input capability. Each
bit on port can be configured as wake-up input by
mask option. PA0~PA3 can be configured as CMOS
(output) or NMOS (input/output) and with or without
pull-high resistor by mask option, PA4~PA7 always
pull-high and NMOS (input/output). Of the eight bits,
PA0~PA1 can be set as I/O pins or buzzer outputs by
mask option. PA3 can be set as an I/O pin or a PFD
output also by mask option.

PB0~PB5 constitute a 6-bit Schmitt trigger input
port. Each bit on port are pull-high resistor. Of the six
bits, PB0 can be set as input pin or external interrupt
control pin (INT0
set as input pin or an external interrupt control pin
(INT1

) by software application. While PB2 can be set
as input pin or timer/event counter input pin also by
software application.

Negative power supply, GND

LCD power supply

Voltage pump

) by software application. PB1 can be

-

20
19~17

21~38 SEG17~SEG0 O

39
40

41 VDD

42
43

44 RES

SEG18/COM3
COM2~COM0

OSC4
OSC3

OSC2
OSC1

1/3 or 1/4

O

Duty

¾

O

I

¾¾

OICrystal or

I

¾

RC

¾

SEG18 can be set as segment or common output driver
for LCD panel by mask option. COM2~COM0 are out­puts for LCD panel plate.

LCD driver outputs for LCD panel segments

Real time clock oscillators

Positive power supply

OSC1 and OSC2 are connected to an RC network or a
crystal (by mask option) for the internal system clock.
In the case of RC operation, OSC2 is the output termi
nal for 1/4 system clock.

Schmitt trigger reset input, active low

5 September 28, 1999

-

Absolute Maximum Ratings

HT49C10

Supply Voltage..............................-0.3V to 5.5V

Input Voltage.................V

-0.3V to VDD+0.3V

SS

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-25°Cto70°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo
sure to extreme conditions may affect device reliability.

D.C. Characteristics

Symbol Parameter

V

I

DD1

I

DD2

I

STB1

I

STB2

V

V

V

V

I

OL

I

OH

R

DD

IL

IH

IL1

IH1

PH

Operating Voltage

Operating Current
(Crystal OSC)

Operating Current
(RC OSC)

Standby Current
(RTC Enable, LCD On)

Standby Current
(RTC Disable, LCD Off)

Input Low Voltage for I/O Ports

Input High Voltage for I/O
Ports

Input Low Voltage
(RES

, INT0, INT1, TMR)

Input High Voltage
(RES

, INT0, INT1, TMR)

I/O Ports Sink Current

I/O Ports Source Current

Pull-high Resistance of I/O
Ports and INT0

, INT1

Test Conditions

V

DD

Conditions

Min. Typ. Max. Unit

¾¾

3V

No load,

=4MHz

f

SYS

5V

3V

No load,

=2MHz

f

SYS

5V

3V

No load,

system Halt

5V

3V

No load,

system Halt

5V

3V

5V

3V

5V

3V

5V 0

3V

5V 4.0

3V

5V

3V

5V

3V

5V

¾

¾

¾

¾

RES

=0.5V

DD

INT0/1=0.3V

TMR=0.3V

0.8V

DD

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

¾

¾

DD

DD

2.2

¾

¾

¾

¾

¾

0.7 1.5 mA

23mA

0.5 1 mA

12mA

¾¾

¾¾

¾¾

¾¾

0

0

2.1

3.5

0

¾

¾

¾

¾

¾

¾

2.4

¾

¾

1.5 2.5

46

-1 -1.5 ¾

-2 -3 ¾

40 60 80

10 30 50

Ta=25°C

5.2 V

5

mA

10

mA

1

mA

2

mA

0.9 V

1.5 V

3V

5V

1.5/0.9 V

2.5/1.5 V

3V

5V

mA

¾

mA

¾

mA

mA

kW

kW

-

-

6 September 28, 1999

HT49C10

A.C. Characteristics

Symbol Parameter

f

SYS1

f

SYS2

f

TIMER

t

WDTOSC

t

RES

t

SST

t

INT

Note: t

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency (TMR)

Watchdog Oscillator

External Reset Low Pulse
Width

System Start-up Timer
Period

Interrupt Pulse Width

=1/f

SYS

SYS

Test Conditions

V

DD

3V

5V

3V

5V

3V

5V

3V

5V

Conditions

¾

¾

¾

¾

¾

¾

¾

¾

¾¾

Power-up or

¾

wake-up from halt

¾¾

Ta=25°C

Min. Typ. Max. Unit

455

455

400

400

0

0

45 90 180

35 65 130

1

1024

¾

1

4000 kHz

¾

4000 kHz

¾

2000 kHz

¾

3000 kHz

¾

4000 kHz

¾

4000 kHz

¾

ms

ms

¾¾ms

t

¾

SYS

¾¾ms

7 September 28, 1999

Functional Description

Execution flow

The system clock is derived from either a crys
tal or an RC oscillator. It is internally divided
into four non-overlapping clocks. One instruction
cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined
in such a way that a fetch takes one instruction
cycle while decoding and execution takes the
next instruction cycle. The pipelining scheme
causes each instruction to effectively execute in
a cycle. If an instruction changes the value of
the program counter, two cycles are required to
complete the instruction.

Program counter - PC

The 10-bit program counter (PC) controls the
sequence in which the instructions stored in the
program ROM are executed. The contents of
the PC can specify a maximum of 1024 ad
dresses.

After accessing a program memory word to fetch
an instruction code, the value of the PC is incre
mented by one. The PC then points to the mem­ory word containing the next instruction code.

When executing a jump instruction, conditional
skip execution, loading a PCL register, a sub­routine call, an initial reset, an internal inter­rupt, an external interrupt, or returning from a
subroutine, the PC manipulates program
transfer by loading the address corresponding
to each instruction.

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

S ystem C lock

The conditional skip is activated by instructions.
Once the condition is met, the next instruction,

-

fetched during the current instruction execu
tion, is discarded and a dummy cycle replaces it
to get a proper instruction; otherwise proceed
with the next instruction.

The lower byte of the PC (PCL) is a readable
and writeable register (06H). Moving data into
the PCL performs a short jump. The destina
tion is within 256 locations.

When a control transfer takes place, an addi
tional dummy cycle is required.

Program memory - ROM

The program memory (ROM) is used to store
the program instructions which are to be exe
cuted. It also contains data, table, and inter
rupt entries, and is organized into 1024´14 bits
which are addressed by the PC and table

­pointer.

Certain locations in the ROM are reserved for
special usage:

-

·

Location 000H
Location 000H is reserved for program initial-

ization. After chip reset, the program always
begins execution at this location.

·

Location 004H
Location 004H is reserved for the external in-

terrupt service program. If the INT0
pin is activated, and the interrupt is enabled,
and the stack is not full, the program begins
execution at location 004H.

HT49C10

-

-

-

-

-

input

OSC2 (RC only)

PC

PC PC+1 PC+2

F e tc h IN S T (P C )

Execute IN S T (P C -1)

F e tc h IN S T (P C + 1 )

Execute IN S T (P C )

Execution flow

8 September 28, 1999

F e tc h IN S T (P C + 2 )

Execute IN S T (P C +1)

HT49C10

·

Location 008H

Location 008H is reserved for the external in
terrupt service program. If the INT1

input pin
is activated, and the interrupt is enabled, and
the stack is not full, the program begins exe
cution at location 008H.

·

Location 00CH
Location 00CH is reserved for the timer/event

counter interrupt service program. If a timer
interrupt resulting from a timer/event coun
ter overflow, and if the interrupt is enabled
and the stack is not full, the program begins
execution at location 00CH.

·

Location 010H
Location 010H is reserved for the time base

interrupt service program. If a time base in
terrupt occurs, and the interrupt is enabled,
and the stack is not full, the program begins
execution at location 010H.

·

Location 014H
Location 014H is reserved for the real time

clock interrupt service program. If a real time
clock interrupt occurs, and the interrupt is en
abled, and the stack is not full, the program
begins execution at location 014H.

000H

-

-

004H

008H

00C H

010H

014H

D evice initialization program

External interrupt0 subroutine

External interrupt1 subroutine

Tim er/event counter interrupt subroutine

Tim e base interrupt

RTC interrupt

Program
ROM

-

n00H

nFF H

3FFH

-

Look-up table (256 w ords)

Look-up table (256 w ords)

14 bits

N ote: n ranges from 0 to 3

Program memory

·

Table location
Any location in the ROM can be used as a

-

look-up table. The instructions²TABRDC [m]²
(the current page, 1 page=256 words) and
²TABRDL[m]² (the last page) transfer the con-

Mode

Program Counter

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Initial reset 0000000000

External interrupt 0 0000000100

External interrupt 1 0000001000

Timer/event Counter overflow 0000001100

Time Base Interrupt 0000010000

RTC Interrupt 0000010100

Skip PC+2

Loading PCL *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return From Subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *9~*0: Program counter bits

#9~#0: Instruction code bits

9 September 28, 1999

S9~S0: Stack register bits
@7~@0: PCL bits

HT49C10

tents of the lower-order byte to the specified
data memory, and the contents of the
higher-order byte toTBLH (table higher-order
byte register) (08H). Only the destination of
the lower-order byte in the table is
well-defined; the other bits of the table word
are all transferred to the lower portion of
TBLH, and the remaining two bits are both
read as ²0². TheTBLH isread only, and the ta
ble pointer (TBLP) is a read/write register
(07H), indicating the table location. Before ac
cessing the table, the location should be placed
in TBLP. All the table related instructions re
quire two cycles to complete the operation.
These areas may function as a normal ROM
dependingupontherequirements.

Stack register - STACK

The stack register is a special part of the mem
ory used to save the contents of the PC. The
stack is organized into four levels and is neither
part of the data nor part of the program, and is
neither readable nor writeable. Its activated
level is indexed by a stack pointer (SP) and is
neither readable nor writeable. At a commence
ment of a subroutine call or an interrupt ac
knowledgment, the contents of the PC is
pushed onto the stack. At the end of the subrou­tine or interrupt routine, signaled by a return
instruction (RET or RETI), the contents of the
PC is restored to its previous value from the
stack. After chip reset, the SP will point to the
top of the stack.

If the stack is full and a non-masked interrupt
takes place, the interrupt request flag is recorded
but the acknowledgment is still inhibited. Once
the SP is decremented (by RET or RETI), the in

terrupt is serviced. This feature prevents stack
overflow, allowing the programmer to use the
structure easily. Likewise, if the stack is full,
and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only
the most recent four return addresses are stored).

Data memory - RAM

-

The data memory (RAM) is designed with 81´8
bits, and is divided into two functional groups,

­namely special function registers and general

purpose data memory, most of which are read

­able/writeable, although some are read only.

Of the two types of functional groups, the special
function registers consist of an indirect addressing
register 0 (00H), a memory pointer register 0
(MP0; 01H), an indirect addressing register 1 (02H),
a memory pointer register 1 (MP1;03H), a bank

­pointer (BP;04H), an accumulator (ACC;05H), a

program counter lower-order byte register
(PCL;06H), a table pointer (TBLP;07H), a table
higher-order byte register (TBLH;08H), a real
time clock control register (RTCC;09H), a status
register (STATUS;0AH), an interrupt control reg

­ister 0 (INTC0;0BH), a timer/event counter

­(TMR;0DH), a timer/event counter control register

(TMRC; 0EH), I/O registers (PA;12H, PB;14H),
and interrupt control register 1 (INTC1;1EH). On
the other hand, the general purpose data memory,
addressed from 20H to 5FH, is used for data and
control information under instruction commands.

The areas in the RAM can directly handle
arithmetic, logic, increment, decrement, and
rotate operations. Except for some dedicated
bits, each bit in the RAM can be set and reset by
²SET [m].i² and ²CLR [m].i². They are also indi

­rectly accessible through the memory pointer

-

-

-

Instruction(s)

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *9~*0: Table location bits

@7~@0: Table pointer bits

Table Location

P9~P8: Current program counter bits

10 September 28, 1999

HT49C10

register 0 (MP0;01H) or the memory pointer reg
ister 1 (MP1;03H).

Indirect Addressing R egister 0

00H

01H

Ind irect A dd ressing R eg ister1

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH

1FH
20H

5FH

MP0

MP1

BP

ACC

PCL

TBLP

TBLH

RTCC

STATUS

IN T C 0

TM R

TM R C

PA

PB

IN T C 1

G eneral Purpose

D ata M em ory

(64 B ytes)

Special P urpose
D ata M em ory

: U n u s e d

R ead as "00"

RAM mapping

Indirect addressing register

Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] and [02H] ac
cesses the RAM pointed to by MP0 (01H) and

MP1 (03H) respectively. Reading location 00H

­or 02H indirectly returns the result 00H, while,
writing it leads to no operation.

The function of data movement between two in
direct addressing registers is not supported.
The memory pointer registers, MP0 and MP1,
are both 7-bit registers used to access the RAM
by combining corresponding indirect address
ing registers. The bit 7 of MP0 and MP1 are un
defined and reading will return the result 1 .
Any writing operation to MP0 and MP1 will
only transfer the lower 7-bit data.

Only MP0 can be applied to data memory, while
MP1 can be applied to data memory and LCD
display memory.

Accumulator - ACC

The accumulator (ACC) is related to ALU oper
ations. It is also mapped to location 05H of the
RAM and is capable of carrying out immediate
data operations. The data movement between
two data memory locations has to pass through
the ACC.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic
operations and provides the following functions:

·

Arithmetic operations
(ADD, ADC, SUB, SBC, DAA)

·

Logic operations (AND, OR, XOR, CPL)

·

Rotation (RL, RR, RLC, RRC)

·

Increment and Decrement (INC, DEC)

·

Branch decision (SZ, SNZ, SIZ, SDZ etc.)

The ALU not only saves the results of a data op­eration but also changes the status register.

Status register - STATUS

The status register (0AH) is 8-bit wide and con
tains a carry flag (C), an auxiliary carry flag
(AC), a zero flag (Z), an overflow flag (OV), a
power down flag (PD), and a watchdog time-out
flag (TO). It also records the status information
and controls the operation sequence.

Except for the TO and PD flags, bits in the status

­register can be altered by instructions, similar to

other registers. Data written into the status reg

-

-

-

-

-

-

11 September 28, 1999

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor

C0

AC 1

Z2

OV 3

PD 4

TO 5

¾

row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.

OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by either a system power-up or executing the ²CLR WDT² instruc
tion. PD is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² in
struction. TO is set by a WDT time-out.

6, 7

Undefined, read as ²0²

STATUS register

HT49C10

-

-

-

ister does not alter the TO or PD flags. Opera
tions related to the status register, however, may
yield different results from those intended. The
TO and PD flags can only be changed by a watch
dog timer overflow, chip power-up, or clearing the
watchdog timer and executing the ²HALT² in­struction. The Z, OV, AC, and C flags reflect the
status of the latest operations.

On entering the interrupt sequence or execut­ing the subroutine call, the status register will
not be pushed onto the stack automatically. If
the contents of the status is important, and if
the subroutine is likely to corrupt the status
register, precautions should be taken to save it
properly.

Interrupts

The HT49C10 provides two external interrupts,
an internal timer/event counter interrupt, an
internal time base interrupt, and an internal
real time clock interrupt. The interrupt control
register 0 (INTC0;0BH) and interrupt control
register 1 (INTC1;1EH) both contain the inter
rupt control bits that are used to set the en
able/disable status and interrupt request flags.

Once an interrupt subroutine is serviced, other

interrupts are all blocked (by clearing the EMI

­bit). This scheme may prevent any further in
terrupt nesting. Other interrupt requests may
take place during this interval, but only the in

­terrupt request flag will be recorded. If a cer­tain interrupt requires servicing within the
service routine, the programmer may set the
EMI bit and the corresponding bit of INTC0 or of
INTC1 in order to allow interrupt nesting. Once
the stack is full, the interrupt request will not be
acknowledged, even if the related interrupt is en­abled, until the SP is decremented. If immediate
service is desired, the stack should be prevented
from becoming full.

All these interrupts have the wake-up capability.
When an interrupt is serviced, a control trans
fer occurs by pushing the PC onto the stack, fol
lowed by a branch to subroutines at the
specified locations in the ROM. Only the PC is
pushed onto the stack. If the contents of the reg
ister or of the status register (STATUS) is al
tered by the interrupt service program which
corrupts the desired control sequence, the con

­tents should be saved first.

­External interrupts are triggered by a high to
low transition of INT0

or INT1, and the related

-

-

-

-

-

-

-

12 September 28, 1999

Register Bit No. Label Function

Control the master (global) interrupt
(1= enabled; 0= disabled)

Control the external interrupt 0
(1= enabled; 0= disabled)

Control the external interrupt 1
(1= enabled; 0= disabled)

Control the timer/event counter interrupt
(1= enabled; 0= disabled)

External interrupt 0 request flag
(1= active; 0= inactive)

External interrupt 1 request flag
(1= active; 0= inactive)

Internal timer/event counter request flag
(1= active; 0= inactive)

Control the time base interrupt
(1= enabled; 0= disabled)

Control the real time clock interrupt
(1= enabled; 0= disabled)

Time base request flag
(1= active; 0= inactive)

Real time clock request flag
(1= active; 0= inactive)

INTC0

(0BH)

INTC1

(1EH)

0 EMI

1 EEI0

2 EEI1

3 ETI

4 EIF0

5 EIF1

6TF

7

0 ETBI

1 ERTI

2, 3

4 TBF

5 RTF

6, 7

¾ Unused bit, read as ²0²

¾ Unused bit, read as ²0²

¾ Unused bit, read as ²0²

HT49C10

INTC register

interrupt request flag (EIF0; bit 4 of INTC0,
EIF1; bit 5 of INTC0) is set as well. After the in
terrupt is enabled, and the stack is not full, and
the external interrupt is active, a subroutine
call to location 04H or 08H occurs. The inter
rupt request flag (EIF0 or EIF1) and EMI bits
are all cleared to disable other interrupts.

The internal timer/event counter interrupt is
initialized by setting the timer/event counter
interrupt request flag (TF; bit 6 of INTC0), that
is caused by a timer overflow. After the inter
rupt is enabled, and the stack is not full, and
the TF bit is set, a subroutine call to location
0CH occurs. The related interrupt request flag

(TF) is reset, and the EMI bit is cleared to dis­able further interrupts.

-

The time base interrupt is initialized by setting
the time base interrupt request flag (TBF; bit 4

­of INTC1), that is caused by a regular time base

signal. After the interrupt is enabled, and the
stack is not full, and the TBF bit is set, a sub
routine call to location 10H occurs. The related
interrupt request flag (TBF) is reset and the
EMI bit is cleared to disable further interrupts.

­The real time clock interrupt is initialized by

setting the real time clock interrupt request
flag (RTF; bit 5 of INTC1), that is caused by a

13 September 28, 1999

-

HT49C10

regular real time clock signal. After the inter
rupt is enabled, and the stack is not full, and
the RTF bit is set, a subroutine call to location
14H occurs. The related interrupt request flag
(RTF) is reset and the EMI bit is cleared to dis
able further interrupts.

During the execution of an interrupt subroutine,
other interrupt acknowledgments are all held
until the ²RETI² instruction is executed or the
EMI bit and the related interrupt control bit are
set both to 1 (if the stack is not full). To return
from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI sets the EMI bit and en
ables an interrupt service, but RET does not.

Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses
are serviced on the latter of the two T2 pulses if
the corresponding interrupts are enabled. In
the case of simultaneous requests, the following
table shows the priority that is applied. These
can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External interrupt 0 1 04H

b External interrupt 1 2 08H

Timer/event

c

counter overflow

3 0CH

d Time base interrupt 4 10H

Real time clock

e

interrupt

5 14H

The timer/event counter interrupt request flag
(TF), external interrupt 1 request flag (EIF1),
external interrupt 0 request flag (EIF0), enable
timer/event counter interrupt bit (ETI), enable
external interrupt 1 bit (EEI1), enable external
interrupt 0 bit (EEI0), and enable master inter
rupt bit (EMI) make up of the interrupt control
register (INTC0) which is located at 0BH in the
RAM. The real time clock interrupt request flag
(RTF), time base interrupt request flag (TBF),
enable real time clock interrupt bit (ERTI), and
enable time base interrupt bit (ETBI), on the
other hand, constitute the other interrupt con
trol register (INTC1) which is located at 1EH in
the RAM. EMI, EEI0, EEI1, ETI, ETBI, and
ERTI are all used to control the enable/disable

status of the interrupts. These bits prevent the

­requested interrupt from being serviced. Once
the interrupt request flags (RTF, TBF, TF,
EIF1, EIF0) are all set, they remain in the
INTC1 or INTC0 respectively until the inter

­rupts are serviced or cleared by a software in
struction.

It is recommended that a program not use the
²CALL subroutine² within the interrupt sub
routine. It¢s because interrupts often occur in
an unpredictable manner or require to be ser
viced immediately in some applications. At this
time, if only one stack is left, and enabling the

­interrupt is not well controlled, operation of the
²call subroutine² in the interrupt subroutine
may damage the original control sequence.

Oscillator configuration

The HT49C10 provides two oscillator circuits
for system clocks, i.e., RC oscillator and crystal
oscillator, determined by mask option. No mat
ter what type of oscillator is selected, the signal
is used for the system clock. The HALT mode
stops the system oscillator and ignores an ex
ternal signal to conserve power.

Of the two oscillators, if the RC oscillator is
used, an external resistor between OSC1 and
VSS is required, and the range of the resistance
should be from 51kW to 1MW. The system clock,

OSC1

V

DD

OSC2

C r y s t a l O s c illa t o r R C O s c illa to r

-

System oscillator

f

SYS

OSC3

OSC4

/4

-

RTC oscillator

-

-

-

-

-

-

OSC1

OSC2

14 September 28, 1999

HT49C10

divided by 4, is available on OSC2 with
pull-high resistor, which can be used to syn
chronize external logic. The RC oscillator pro
vides the most cost effective solution. However,
the frequency of the oscillation may vary with
VDD, temperature, and the chip itself due to
process variations. It is, therefore, not suitable
for timing sensitive operations where accurate
oscillator frequency is desired.

On the other hand, if the crystal oscillator is se
lected, a crystal across OSC1 and OSC2 is
needed to provide the feedback and phase shift
required for the oscillator, and no other external
components are required. A resonator may be
connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but
two external capacitors in OSC1 and OSC2 are
needed.

There is another oscillator circuit designed for
the real time clock. In this case, only the

32.768kHz crystal oscillator can be applied. The
crystal should be connected between OSC3 and
OSC4, and two external capacitors along with
one external resistor are required for the oscil
lator circuit in order to get a stable frequency.

The RTC oscillator circuit can be controlled to
oscillate quickly by setting ²QOSC² bit (bit 4 of
RTCC). It is recommended to turn on the quick
oscillating function upon power on, and turn it
off after two seconds.

The WDT oscillator is a free running on-chip
RC oscillator, and no external components are
required. Although the system enters the power
down mode, the system clock stops, and the
WDT oscillator still works with a period of ap­proximately 78 ms. The WDT oscillator can be
disabled by mask option to conserve power.

Watchdog timer - WDT

­The WDT clock source is implemented by a ded

­icated RC oscillator (WDT oscillator) or an in

struction clock (system clock/4) or a real time
clock oscillator (RTC oscillator). The timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The WDT can be
disabled by mask option. But if the WDT is dis

-

abled, all executions related to the WDT lead to
no operation.

After the WDT clock source is selected, it
time-out period is fs/2

15

~fs/216.

If the WDT clock source chooses the internal
WDT oscillator, the time-out period may vary
with temperature, VDD, and process varia
tions. On the other hand, if the clock source se
lects the instruction clock and the ²halt²
instruction is executed, WDT may stop count
ing and lose its protecting purpose, and the
logic can only be restarted by external logic.

When the device operates in a noisy environ
ment, using the on-chip RC oscillator (WDT

­OSC) is strongly recommended, since the HALT

can stop the system clock.

The WDT overflow under normal operation
initializes a ²chip reset² and sets the status bit
²TO². In the HALT mode, the overflow
initializes a ²warm reset², and only the PC and
SP are reset to zero. To clear the contents of the
WDT, there are three methods to be adopted,
i.e., external reset (a low level to RES
instruction, and ²HALT² instruction. There are
two sets of software instructions, ²CLR WDT²
and the other set -²CLR WDT1² and ²CLR
WDT2². Of these two types of instructions, only
one type of instruction can be active at a time
depending on the mask option -²CLR WDT

-

-

-

-

-

-

-

), software

S ystem C lo ck/4

RTC

32768H z

OSC

WDT

12kHz

OSC

Mask
Option
Select

fs

D ivider

P rescale r

CK T CK T

W D T C lear

R

Tim e-out

15 16

R e s e t fs /2 ~ fs /2

Watchdog timer

15 September 28, 1999

HT49C10

times selection option².Ifthe²CLR WDT² is se
lected (i.e., CLR WDT times equal one), any ex
ecution of the ²CLR WDT² instruction clears
the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e., CLR WDT times
equal two), these two instructions have to be ex
ecuted to clear the WDT; otherwise, the WDT
may reset the chip because of time-out.

Multi-function timer

The HT49C10 provides a multi-function timer
for WDT, time base and RTC but with different
time-out periods. The multi-function timer con
sists of a 7-stage divider and an 8-bit prescaler,
with the clock source coming from the WDT
OSC or RTC OSC or the instruction clock (i.e.,
system clock divided by 4). The multi-function
timer also provides a selectable frequency sig
nal (ranges from fs/2
circuits, and a selectable frequency signal
(ranges from fs/2

2

to fs/28) for LCD driver

2

to fs/29) for buzzer output by
mask option. It is recommended to select a
4kHz signal for LCD driver circuits for proper
display.

Time base

The time base offers a periodic time-out period to
generate a regular internal interrupt. Its
time-out period ranges from fs/2

12

to fs/215se­lected by mask option. If time base time-out oc­curs, the related interrupt request flag (TBF; bit 4
of INTC1) is set. But if the interrupt is enabled,
and the stack is not full, a subroutine call to loca­tion 10H occurs.

Real time clock - RTC

The real time clock (RTC) is operated in the
same manner as the time base that is used to
supply a regular internal interrupt. Its

fs

D ivider

time-out period ranges from fs/2

­software programming (recommand use 2

­Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of
RTCC;09H) yields various time-out periods. If
the RTC time-out occurs, the related interrupt re
quest flag (RTF; bit 5 of INTC1) is set. But if the

­interrupt is enabled, and the stack is not full, a

subroutine call to location 14H occurs. The real
time clock time-out signal can also be applied as a
clock source of the timer/event counter to get a
longer time-out period.

-

RT2 RT1 RT0

RTC Clock Divided

Factor

000 2

001 2

-

010 2

011 2

100 2

101 2

110 2

111 2

Power down operation - HALT

The HALT mode is initialized by the ²HALT² in­struction and results in the following.

·

The system oscillator turns off but the WDT
oscillator keeps running (if the WDT oscilla­tor or the real time clock is selected).

·

The contents of the on-chip RAM and of the
registers remain unchanged.

·

The WDT is cleared and start recounting (if the
WDT clock source is from the WDT oscillator or
the real time clock oscillator).

Prescaler

8

to fs/215by

12~215

8

9

10

11

12

13

14

15

).

-

M ask O p tion

L C D D r iv e r (fs /2 ~ fs /2 )

B u z z e r (fs /2 ~ fs /2 )

28

29

Time base

Mask

Option

Tim e Base Interrupt

12 15

fs /2 ~ fs /2

16 September 28, 1999

HT49C10

·

All I/O ports maintain their original status.

·

The PD flag is set but the TO flag is cleared.

·

LCD driver is still running (if the WDT OSC
or RTC OSC is selected).

The system quits the HALT mode by an external
reset, an interrupt, an external falling edge sig
nal on port A, or a WDT overflow. An external re
set causes device initialization, and the WDT
overflow performs a ²warm reset². After examin
ing the TO and PD flags, the reason for chip re
set can be determined. The PD flag is cleared by
system power-up or by executing the ²CLR
WDT² instruction, and is set by executing the
²HALT² instruction. On the other hand, the TO
flag is set if WDT time-out occurs, and causes a
wake-up that only resets the PC (Program Coun
ter) and SP, and leaves the others at their origi
nal state.

The port A wake-up and interrupt methods can
be considered as a continuation of normal exe
cution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the pro
gram resumes execution of the next instruction.
On the other hand, awakening from an inter­rupt, two sequences may occur. If the related in­terrupt is disabled or the interrupt is enabled,
but the stack is full, the program resumes exe­cution at the next instruction. But if the inter­rupt is enabled, and the stack is not full, the
regular interrupt response takes place.

When an interrupt request flag is set before en­tering the ²halt² status, the system cannot be
awaken using that interrupt.

If a wake-up event occurs, it takes 1024 t

SYS

(system clock period) to resume normal opera
tion. In other words, a dummy period is in
serted. If the wake-up results from an interrupt

acknowledgment, the actual interrupt subrou
tine execution is delayed by more than one cy
cle. However, if the wake-up results in the next
instruction execution, the execution will be per
formed immediately after the dummy period is
finished.

To minimize power consumption, all the I/O

­pins should be carefully managed before enter

­ing the HALT status.

-

Reset

-

There are three ways in which a reset may occur.

·

RES is reset during normal operation

·

RES is reset during HALT

·

-

-

WDT time-out is reset during normal operation

The WDT time-out during HALT differs from
other chip reset conditions, for it can perform a
²warm reset² that resets only the PC and SP
and leaves the other circuits at their original

­state. Some registers remain unaffected during

any other reset conditions. Most registers are
reset to the ²initial condition² once the reset

­conditions are met. Examining the PD and TO

flags, the program can distinguish between dif­ferent ²chip resets².

TO PD RESET Conditions

0 0 RES

uu

0 1 RES

1u

-

-

1 1 WDT wake-up HALT

reset during power-up

reset during normal

RES
operation

wake-up HALT

WDT time-out during normal
operation

Note: ²u² means ²unchanged²

-

-

-

-

fs

D ivider

RT2
RT1
RT0

P resca le r

8 to 1

Mux.

15

8

(fs /2 ~ fs /2 )

RTC Interrupt

Real time clock

17 September 28, 1999

HT49C10

VDD

RES

SST Tim e-out

Chip Reset

HALT

WDT

RES

OSC1

10-bit R ipple

Reset timing chart

V

DD

RES

Reset circuit

WDT

Tim e-out
Reset

SST

C ounter

External

t

SST

W arm R eset

Cold
Reset

The functional unit chip reset status are shown
below.

PC 000H

Interrupt Disabled

Prescaler, divider Cleared

WDT, RTC, time base

Clear. After master re
set, begins counting

Timer/event counter Off

Input/output ports Input mode

SP

Points to the top of the
stack

-

Power-on Detection

Reset configuration

To guarantee that the crystal oscillator is
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of 1024
system clock pulses when the system powers up
or awakes from the HALT state. Awaking from
the HALT state or system power-up, the SST
delay is added.

An extra SST delay is added during the
power-up period, and any wake-up from HALT
may enable the SST delay only.

18 September 28, 1999

The states of the registers are summarized below.

HT49C10

Register

TMR xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TMRC 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u---

Program Counter 000H 000H 000H 000H

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu

STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu

INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu

INTC1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu

RTCC --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu

Note:

²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²

Reset

(Power On)

WDT Time-out

(Normal

Operation)

Reset

RES

(Normal

Operation)

RES

(HALT)

Reset

WDT

Time-out

(HALT)

000H*

19 September 28, 1999

HT49C10

Timer/event counter

A timer/event counter (TMR) is implemented in
the HT49C10. The timer/event counter contains
an 8-bit programmable count-up counter, and the
clock source may come from the system clock or
instruction clock (systemclock/4) or RTC time-out
signal or external source. System clock source or
instruction clock isselected by maskoption.

The external clock input allows the user to
count external events, measure time intervals
or pulse widths, or generate an accurate time
base.

There are two registers related to the timer/event
counter, i.e., TMR ([0DH]) and TMRC ([0EH]).
And two physical registers are mapped to TMR
location; writing TMR locates the starting value
in the timer/event counter preload register, while
reading it yields the contents of the timer/event
counter. The TMRC is a timer/event counter con
trol register which defines some options.

The TN0 and TN1 bits define the operation
mode. The event count mode is used to count ex
ternal events, which means that the clock
source is from an external (TMR) pin. The timer
mode functions as a normal timer with the
clock source coming from the internal selected
clock source. Finally, the pulse width measure­ment mode can be used to count the high or low
level duration of the external signal (TMR), and
the counting is based on the internal selected
clock source.

In the event count or timer mode, the
timer/event counter starts counting at the cur
rent contents in the timer/event counter and
ends at FFH. Once an overflow occurs, the
counter is reloaded from the timer/event coun
ter preload register, and generates an interrupt
request flag (TF; bit 6 of INTC0).

In the pulse width measurement mode with
the values of the TON and TE bits equal to
one, after the TMR has received a transient
from low to high (or high to low if the TE bit is
²0²), it will start counting until the TMR re
turns to the original level and resets the
TON. The measured result remains in the
timer/event counter even if the activated
transient occurs again. In other words, only
one cycle measurement can be done. Until set
ting the TON, the cycle measurement will
re-function as long as it receives further tran

­sient pulse. In this operation mode, the

timer/event counter begins counting according
not to the logic level but to the transient edges.
In the case of counter overflows, the counter is

­reloaded from the timer/event counter preload
register and issues an interrupt request, as in
the other two modes, i.e., event and timer
modes.

To enable the counting operation, the Timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In
the pulse width measurement mode, the TON
is automatically cleared after the measurement
cycle is completed. But in the other two modes,

-

-

-

-

-

System Clock

S y s te m C lo c k /4

RTC O ut

Mask
Option
Select

TN2

TM R

TN1
TN0

TO N

M
U
X

TN1
TN0

TE

Pulse W idth

M easurem ent

M ode C ontrol

Timer/event counter

Data Bus

Tim er/E vent C ounter

Preload R egister

Tim er/E vent

C ounter

PA3 Data CTRL

20 September 28, 1999

R eload

O verflow
T o In te r ru p t

Q

T

PFD Out

Label (TMRC) Bits Function

¾

TE 3

TON 4

TN2 5

TN0, TN1 7, 6

0~2

Unused bits, read as ²0²

Defines the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)

Enable/disable timer counting
(0=disabled; 1=enabled)

Two to one multiplexer control inputs to select the timer/event counter
clock source (0=RTC output; 1=system clock or system clock/4)

Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse Width measurement mode (external clock)
00=Unused

TMRC register

HT49C10

the TON can only be reset by instructions. The
overflow of the timer/event counter is one of the
wake-up sources and can also be applied to a
PFD (Programmable Frequency Divider) out
put at PA3 by mask option. No matter what the
operation mode is, writinga0toETIdisables the
interrupt service. When the PFD function is se
lected, executing ²CLR [PA].3² instruction to en­able PFD output and executing ²SET [PA].3²
instruction to disable the PFD output.

In the case of timer/event counter OFF
condition, writing data to the timer/event counter
preload register also reloads that data to the
timer/event counter. But if the timer/event coun­ter is turned on, data written to the
timer/event counter is kept only in the
timer/event counter preload register. The
timer/event counter still goes on operating un
til an overflow occurs.

When the timer/event counter (reading TMR)
is read, the clock is blocked to avoid errors. As
this may results in a counting error, this
should be taken into account by the program
mer.

It is strongly recommended to load first a spe
cific value into the TMR register, then turn on
the timer/event counter for proper operation.
Because the initial value of TMR is unknown.

Input/output ports

There is an 8-bit bidirectional input/output port
and a 6-bit input port in the HT49C10, labeled

­PA and PB, which are mapped to [12H] and

[14H] of the RAM, respectively. PA0~PA3 can
be configured as CMOS (output) or NMOS (in

­put/output) and with or without pull-high resis-

tor by mask option, PA4~PA7 always pull-high
and NMOS (input/output). PB can only be used
for input operation, and each bit on the port
with pull-high resistor. Both are for the input
operation, these ports are non-latched, that is,
the inputs should be ready at the T2 rising edge
of the instruction ²MOV A, [m]² (m=12H or
14H). For PA output operation, all data are
latched and remain unchanged until the output
latch is rewritten.

­When the structures of PA are open drain

NMOS type, it should be noted that, before
reading data from the pads, a ²1² should be
written to the related bits to disable the NMOS
device. That is executing first the instruction

-

²SET [m].i² (i=0~7 for PA) to disable any related
NMOS device, and then ²MOV A, [m]² to get
stable data.

-

-

21 September 28, 1999

HT49C10

Data Bus

Write

C hip R eset

R ead I/O

System W ake-up

D

CK

S

M ask O ption

PA input/output port

V

DD

WEAK
Pull-up

C hip R eset

R e a d I/O

PB0~PB5

PB input lines

After chip reset, these input lines remain at a
high level or are left floating (by mask option).
Each bit of these output latches can be set or
cleared by the ²SET [m].i² and ²CLR [m].i²
(m=12H) instructions.

V

DD

Mask
Option
(only

Q

Q

PA0~P A 3)

V

DD

WEAK
Pull-up

M ask O ption
(only P A 0~PA3)

PA0~PA7

Some instructions first input data and then fol
low the output operations. For example, ²SET
[m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or to the ac
cumulator.

LCD display memory

The HT49C10 provides an area of embedded
data memory for LCD display. This area is lo­cated from 40H to 52H of the RAM at Bank 1.
Bank pointer (BP; located at 04H of the RAM) is
the switch between the RAM and the LCD dis­play memory. When the BP is set ²1², any data

-

-

COM

SEGM EN T

41H 42H 43H

0

1

2

3

0123 1718

50H 51H 52H40H

16

Bit

0

1

2

3

Display memory

22 September 28, 1999

Register Bit No. Label Read/Write Reset Function

RTCC

(09H)

RT0

0~2

3

4 QOSC R/W 0

5~7

RT1
RT2

¾¾¾Unused bits, read as ²0²

¾¾¾Unused bits, read as ²0²

R/W 0

RTCC register

8 to 1 multiplexer control inputs to select the
real time clock prescaler output

Control the RTC OSC to oscillate quickly.

²0² enable
²1² disable

HT49C10

written into 40H~52H will affect the LCD dis
play. When the BP is cleared ²0², any data writ
ten into 40H~52H means to access the general
purpose data memory. The LCD display mem
ory can be read and written to, only by indirect
addressing mode using MP1. When data is
writxten into the display data area it is auto
matically read by the LCD driver which then
generates the corresponding LCD driving sig
nals. To turn the display On or Off, a ²1² or a ²0²
is written to the corresponding bit of the display
memory, respectively. The figure illustrates the
mapping between the display memory and LCD
pattern for the HT49C10.

LCD driver output

The output number of the HT49C10 LCD driver
can be 19´2or19´3or18´4 by mask option (i.e.,
1/2 duty or 1/3 duty or 1/4 duty). The bias type of
LCD driver can be ²R² type or ²C² type. If the

-

²R² bias type is selected, no external capacitor

-

is required. If the ²C² bias type is selected, a ca
pacitor mounted between C1 and C2 pins is

-

needed. The bias voltage of LCD driver can be
1/2 bias or 1/3 bias by mask option. If 1/2 bias is
selected, a capacitor mounted between V2 pin

-

and the ground is required. If 1/3 bias is se
lected, two capacitors are needed for V1 and V2

-

pins. Please refer to the application diagram.

Buzzer

HT49C10 provides a pair of buzzer output BZ and
BZ

, which share pins with PA0 and PA1 respec­tively, as determined by mask option. Its output
frequency can be selected by mask option.

When the buzzer function is selected, setting
PA.0 and PA.1 ²0² simultaneously will enable
the buzzer output and setting PA.0 ²1² will dis­able the buzzer output.

-

-

23 September 28, 1999

HT49C10

D u ring a R eset P u lse:

COM 0,COM 1,CO M 2

All LC D driver outputs

Norm al O peration M ode :

COM 0

COM 1

COM 2

LC D segm ents on C O M
0,1,2 sides being unlit

O nly LC D segm ents on
C O M 0 side being lit

O nly LC D segm ents on
C O M 1 side being lit

O nly LC D segm ents on
C O M 2 side being lit

LC D segm ents on
C O M 0,1 sides being lit

LC D segm ents on
C O M 0 ,2 s id e s b e in g lit

LC D segm ents on
C O M 1,2 sides being lit

LC D segm ents on

C O M 0 ,1 ,2 s id e s b e in g lit

Halt M ode:

COM 0,COM 1,CO M 2

All LC D driver outputs

VLC D
1/2 VLC D
VSS

VLC D
1/2 VLC D
VSS

VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS

VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS
VLC D
1/2 VLC D
VSS

VLC D
1/2 VLC D
VSS
VDD
1/2 VLC D

VSS

LCD driver output (1/3 duty, 1/2 bias, R/C type)

24 September 28, 1999

COM 0

COM 1

COM 2

COM 3

HT49C10

3/2V LC D

VLCD

1/2 VLC D

VSS

3/2V LC D

VLCD

1/2 VLC D

VSS

3/2V LC D

VLCD

1/2 VLC D

VSS

3/2V LC D

VLCD

1/2 VLC D

VSS

3/2V LC D

LC D segm ents O N
C O M 2 side lighted

LCD driver output (1/4 duty, 1/3 bias, C type)

VLCD

1/2 VLC D

VSS

25 September 28, 1999

HT49C10

Mask option

The following shows 16 kinds of mask options in the HT49C10. All these options should be defined in
order to ensure proper system functioning.

No. Mask Option

OSC type selection. This option is to decide if an RC or crystal oscillator is selected as sys

1

tem clock.

Clock source selection of WDT, RTC and Time Base. There are three types of selection: sys

2

tem clock/4 or RTC OSC or WDT OSC.

3 WDT enable/disable selection. WDT can be enabled or disabled by mask option.

CLR WDT times selection. This option defines how to clear the WDT by instruction. One

4

time means that the ²CLR WDT² can clear the WDT. ²Two times² means only if both of the
²CLR WDT1² and ²CLR WDT2² have been executed, the WDT can be cleared.

12

Time Base time-out period selection. The Time Base time-out period ranges from fs/2

5

6

7

8

15

. ²fs² means the clock source selected by mask option.

fs/2

Buzzer output frequency selection. There are eight types frequency signals for buzzer out
put: fs/2

2

~fs/29. ²fs² means the clock source selected by mask option.

Wake-up selection. This option defines the wake-up function activity. External I/O pins
(PA only) all have the capability to wake-up the chip from a HALT by a falling edge.

Pull-high selection. This option is to decide whether the pull-high resistance is viable or not
on the PA0~PA3.

PA CMOS or NMOS selection.
PA0~PA3 can be selected as CMOS or NMOS structure, but PA4~PA7 are always NMOS.

9

When the CMOS is selected, the related pins can only be used for output operations. When
the NMOS is selected, the related pins can be used for input or output operations.

Clock source selection of timer/event counter. There are two types of selection: system clock

10

or system clock/4.

I/O pins share with other functions selection.

11

PA0/BZ

, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.

PA3/PFD: PA3 can be set as I/O pins or PFD output.

LCD common selection. There are three types of selection: 2 commons (1/2 duty) or 3 com
mons (1/3 duty) or 4 commons (1/4 duty). If the 4 commons are selected, the segment output

12

pin ²SEG18² will be set as a common output.

LCD bias power supply selection.

13

There are two types of selection: 1/2 bias or 1/3 bias.

LCD bias type selection.

14

This option is to decide what kind of bias is selected, R type or C type.

LCD driver clock selection. There are seven types frequency signals for LCD driver circuits:

15

2

~fs/28. ²fs² means the clock source selected by mask option.

fs/2

to

-

-

-

-

26 September 28, 1999

Application Circuits

R C o s c illa to r a p p lic a tio n C ry s ta l o s c illa to r a p p lic a t io n

HT49C10

OSC1

V

DD

f

/4

SYS

OSC2

V

DD

RES

SEG0~17

COM 0~3

VLCD

C1

C2

LC D

PANEL

LCD Power
Supply

0.1mF

HT49C10

OSC3

OSC4

IN T 0

IN T 1

TM R

V1

V2

PA0~PA7

PB0~PB5

0.1mF

0.1mF

OSC1

SEG0~17

OSC2

V

DD

RES

COM 0~3

VLCD

C1

C2

LC D

PANEL

LCD Power
Supply

0.1mF

HT49C10

OSC3

OSC4

IN T 0

IN T 1

TM R

V1

V2

PA0~PA7

PB0~PB5

0.1mF

0.1mF

27 September 28, 1999

HT49C10

Instruction Set Summary

Mnemonic Description Flag Affected

Arithmetic

ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]

DAA [m]

Logic Operation

AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]

Increment &

Decrement

INCA [m]
INC [m]
DECA [m]
DEC [m]

Rotate

RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]

Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in
data memory
Decimal adjust ACC for addition with result in data memory

AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC

Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory

Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry

Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV

None
None

None
None

C

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

Z
Z
Z
Z

C
C

C
C

28 September 28, 1999

HT49C10

Mnemonic Description Flag Affected

Data Move

MOV A,[m]
MOV [m],A
MOV A,x

Bit Operation

CLR [m].i
SET [m].i

Branch

JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI

Table Read

TABRDC [m]
TABRDL [m]

Miscellaneous

NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT

Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC

Clear bit of data memory
Set bit of data memory

Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt

Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH

No operation
Clear data memory
Set data memory
Clear Watchdog timer
Pre-clear watchdog timer
Pre-clear watchdog timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode

None**

None
None

None
None

None
None
None
None
None
None
None
None
None
None
None
None
None

None
None

None
None
None

TO,PD
TO*,PD*
TO*,PD*

None
None

TO,PD

Note: x: 8-bit immediate data

m: 7 bits data memory address
A: accumulator
i: 0~7 number of bits
addr: 10-bit program memory address

Ö: Flag is affected

-: Flag is not affected

*: Flag may be affected by the execution

status

**: For the old version of the E.V. chip, the zero

flag (Z) can be affected by executing the
MOV A,[M] instruction.

For the new version of the E.V. chip, the
zero flag cannot be changed by executing
the MOV A,[M] instruction.

29 September 28, 1999

HT49C10

Instruction Definition

ADC A,[m] Add data memory and carry to the accumulator

Description The contents of the specified data memory, accumulator and the carry flag

are added simultaneously, leaving the result in the accumulator.

Operation

Affected flag(s)

ADCM A,[m] Add the accumulator and carry to data memory

Description The contents of the specified data memory, accumulator and the carry flag

Operation

Affected flag(s)

ADD A,[m] Add data memory to the accumulator

Description The contents of the specified data memory and the accumulator are added.

Operation

Affected flag(s)

ACC ¬ ACC+[m]+C

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

are added simultaneously, leaving the result in the specified data memory.
[m] ¬ ACC+[m]+C

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

The result is stored in the accumulator.
ACC ¬ ACC+[m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

ADD A,x Add immediate data to the accumulator

Description The contents of the accumulator and the specified data are added, leaving

the result in the accumulator.

Operation

Affected flag(s)

ACC ¬ ACC+x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

30 September 28, 1999

HT49C10

ADDM A,[m] Add the accumulator to the data memory

Description The contents of the specified data memory and the accumulator are added.

The result is stored in the data memory.

Operation

Affected flag(s)

AND A,[m] Logical AND accumulator with data memory

Description Data in the accumulator and the specified data memory perform a bitwise

Operation

Affected flag(s)

AND A,x Logical AND immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logi

Operation

Affected flag(s)

[m] ¬ ACC+[m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

logical_AND operation. The result is stored in the accumulator.
ACC ¬ ACC ²AND² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

cal_AND operation. The result is stored in the accumulator.
ACC ¬ ACC ²AND² x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

-

ANDM A,[m] Logical AND data memory with the accumulator

Description Data in the specified data memory and the accumulator perform a bitwise

logical_AND operation. The result is stored in the data memory.

Operation

Affected flag(s)

[m] ¬ ACC ²AND² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

31 September 28, 1999

HT49C10

CALL addr Subroutine call

Description The instruction unconditionally calls a subroutine located at the indicated

address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this ad
dress.

Operation

Affected flag(s)

CLR [m] Clear data memory

Description The contents of the specified data memory are cleared to zero.

Operation

Affected flag(s)

CLR [m].i Clear bit of data memory

Description The bit i of the specified data memory is cleared to zero.

Operation

Affected flag(s)

Stack ¬ PC+1
PC ¬ addr

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

[m] ¬ 00H

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

[m].i ¬ 0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

-

CLR WDT Clear watchdog timer

Description The WDT is cleared (re-counting from zero). The power down bit (PD) and

time-out bit (TO) are cleared.

Operation

Affected flag(s)

WDT ¬ 00H
PD and TO ¬ 0

TC2 TC1 TO PD OV Z AC C

¾¾

00

32 September 28, 1999

¾¾¾¾

HT49C10

CLR WDT1 Preclear watchdog timer

Description The TD, PD flags and WDT are all cleared (re-counting from zero), if the

other preclear WDT instruction has been executed. Only execution of this in
struction without the other preclear instruction sets the indicated flag which
implies that this instruction has been executed and the TO and PD flags re
main unchanged.

Operation

Affected flag(s)

CLR WDT2 Preclear watchdog timer

Description The TO, PD flags and WDT are cleared (re-counting from zero), if the other

Operation

Affected flag(s)

WDT ¬ 00H*
PD and TO ¬ 0*

TC2 TC1 TO PD OV Z AC C

¾¾

preclear WDT instruction has been executed. Only execution of this instruc
tion without the other preclear instruction sets the indicated flag which im
plies that this instruction has been executed and the TO and PD flags
remain unchanged.

WDT ¬ 00H*
PD and TO ¬ 0*

TC2 TC1 TO PD OV Z AC C

¾¾

0* 0*

0* 0*

¾¾¾¾

¾¾¾¾

-

-

-

-

CPL [m] Complement data memory

Description

Operation

Affected flag(s)

Each bit of the specified data memory is logically complemented (1¢s comple­ment). Bits which previously contained a one are changed to zero and
vice-versa.

[m] ¬ [m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

]

33 September 28, 1999

HT49C10

CPLA [m] Complement data memory and place result in the accumulator

Description

Operation

Affected flag(s)

DAA [m] Decimal-Adjust accumulator for addition

Description The accumulator value is adjusted to the BCD (Binary Code Decimal) code.

Operation If ACC.3~ACC.0 >9 or AC=1

Affected flag(s)

Each bit of the specified data memory is logically complemented (1¢s comple
ment). Bits which previously contained a one are changed to zero and
vice-versa. The complemented result is stored in the accumulator and the
contents of the data memory remain unchanged.

ACC ¬ [m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the ac
cumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.

then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

]

-

-

DEC [m] Decrement data memory

Description Data in the specified data memory is decremented by one.

Operation

Affected flag(s)

[m] ¬ [m]-1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

34 September 28, 1999

HT49C10

DECA [m] Decrement data memory and place result in the accumulator

Description Data in the specified data memory is decremented by one, leaving the result

in the accumulator. The contents of the data memory remain unchanged.

Operation

Affected flag(s)

HALT Enter power down mode

Description This instruction stops program execution and turns off the system clock. The

Operation

Affected flag(s)

ACC ¬ [m]-1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

contents of the RAM and registers are retained. The WDT and prescaler are
cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.

PC ¬ PC+1
PD ¬ 1
TO ¬ 0

TC2 TC1 TO PD OV Z AC C

¾¾

01

¾¾¾¾

INC [m] Increment data memory

Description Data in the specified data memory is incremented by one.

Operation

Affected flag(s)

INCA [m] Increment data memory and place result in the accumulator

Description Data in the specified data memory is incremented by one, leaving the result

Operation

Affected flag(s)

[m] ¬ [m]+1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

in the accumulator. The contents of the data memory remain unchanged.
ACC ¬ [m]+1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

35 September 28, 1999

HT49C10

JMP addr Directly jump

Description The contents of the program counter are replaced with the directly-specified

address unconditionally, and control is passed to this destination.

Operation

Affected flag(s)

MOV A,[m] Move data memory to the accumulator

Description The contents of the specified data memory are copied to the accumulator.

Operation

Affected flag(s)

MOV A,x Move immediate data to the accumulator

Description The 8-bit data specified by the code is loaded into the accumulator.

Operation

Affected flag(s)

PC ¬ addr

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

ACC ¬ [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

ACC ¬ x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

MOV [m],A Move the accumulator to data memory

Description The contents of the accumulator are copied to the specified data memory (one

of the data memories).

Operation

Affected flag(s)

NOP No operation

Description No operation is performed. Execution continues with the next instruction.

Operation

Affected flag(s)

[m] ¬ ACC

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

PC ¬ PC+1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

36 September 28, 1999

HT49C10

OR A,[m] Logical OR accumulator with data memory

Description Data in the accumulator and the specified data memory (one of the data

memories) perform a bitwise logical_OR operation. The result is stored in
the accumulator.

Operation

Affected flag(s)

OR A,x Logical OR immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical_OR

Operation

Affected flag(s)

ORM A,[m] Logical OR data memory with the accumulator

Description Data in the data memory (one of the data memories) and the accumulator

Operation

Affected flag(s)

ACC ¬ ACC ²OR² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

operation. The result is stored in the accumulator.
ACC ¬ ACC ²OR² x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

perform a bitwise logical_OR operation. The result is stored in the data
memory.

[m] ¬ ACC ²OR² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

RET Return from subroutine

Description The program counter is restored from the stack. This is a two-cycle instruc-

tion.

Operation

Affected flag(s)

PC ¬ Stack

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

37 September 28, 1999

HT49C10

RET A,x Return and place immediate data in the accumulator

Description The program counter is restored from the stack and the accumulator loaded

with the specified 8-bit immediate data.

Operation

Affected flag(s)

RETI Return from interrupt

Description The program counter is restored from the stack, and interrupts are enabled

Operation

Affected flag(s)

RL [m] Rotate data memory left

Description The contents of the specified data memory are rotated one bit left with bit 7

Operation

Affected flag(s)

PC ¬ Stack
ACC ¬ x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0;
register INTC).

PC ¬ Stack
EMI ¬ 1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

rotated into bit 0.
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ [m].7

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

RLA [m] Rotate data memory left and place result in the accumulator

Description Data in the specified data memory is rotated one bit left with bit 7 rotated

into bit 0, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.

Operation

Affected flag(s)

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

38 September 28, 1999

HT49C10

RLC [m] Rotate data memory left through carry

Description The contents of the specified data memory and the carry flag are rotated one

bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the
bit 0 position.

Operation

Affected flag(s)

RLCA [m] Rotate left through carry and place result in the accumulator

Description Data in the specified data memory and the carry flag are rotated one bit left.

Operation

Affected flag(s)

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 po
sition. The rotated result is stored in the accumulator but the contents of the
data memory remain unchanged.

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

-

RR [m] Rotate data memory right

Description The contents of the specified data memory are rotated one bit right with bit 0

rotated to bit 7.

Operation

Affected flag(s)

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

39 September 28, 1999

HT49C10

RRA [m] Rotate right-place result in the accumulator

Description Data in the specified data memory is rotated one bit right with bit 0 rotated

into bit 7, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.

Operation

Affected flag(s)

RRC [m] Rotate data memory right through carry

Description The contents of the specified data memory and the carry flag are together ro

Operation

Affected flag(s)

ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

tated one bit right. Bit 0 replaces the carry bit; the original carry flag is ro
tated into the bit 7 position.

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

-

-

RRCA [m] Rotate right through carry-place result in the accumulator

Description Data of the specified data memory and the carry flag are rotated one bit

right. Bit 0 replaces the carry bit and the original carry flag is rotated into
the bit 7 position. The rotated result is stored in the accumulator. The con­tents of the data memory remain unchanged.

Operation

Affected flag(s)

ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

40 September 28, 1999

HT49C10

SBC A,[m] Subtract data memory and carry from the accumulator

Description Thecontents of the specified data memory and the complement of the carry flag

aresubtractedfromtheaccumulator,leavingtheresultintheaccumulator.

Operation

Affected flag(s)

SBCM A,[m] Subtract data memory and carry from the accumulator

Description The contents of the specified data memory and the complement of the carry

Operation

Affected flag(s)

SDZ [m] Skip if decrement data memory is zero

Description The contents of the specified data memory are decremented by one. If the re

Operation

Affected flag(s)

ACC ¬ ACC+[m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

flag are subtracted from the accumulator, leaving the result in the data
memory.

[m] ¬ ACC+[m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

sult is zero, the next instruction is skipped. If the result is zero, the following
instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (two cycles). Oth­erwise proceed with the next instruction (one cycle).

Skip if ([m]-1)=0, [m] ¬ ([m]-1)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

]+C

]+C

-

SDZA [m] Decrement data memory and place result in ACC, skip if zero

Description The contents of the specified data memory are decremented by one. If the re

sult is zero, the next instruction is skipped. The result is stored in the accu
mulator but the data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction (two
cycles). Otherwise proceed with the next instruction (one cycle).

Operation

Affected flag(s)

Skip if ([m]-1)=0, ACC ¬ ([m]-1)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

41 September 28, 1999

-

-

HT49C10

SET [m] Set data memory

Description Each bit of the specified data memory is set to one.

Operation

Affected flag(s)

SET [m].i Set bit of data memory

Description Biti of the specified data memory is set to one.

Operation

Affected flag(s)

SIZ [m] Skip if increment data memory is zero

Description The contents of the specified data memory are incremented by one. If the re

Operation

Affected flag(s)

[m] ¬ FFH

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

[m].i ¬ 1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

sult is zero, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper in
struction (two cycles). Otherwise proceed with the next instruction (one cy
cle).

Skip if ([m]+1)=0, [m] ¬ ([m]+1)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

-

-

-

SIZA [m] Increment data memory and place result in ACC, skip if zero

Description The contents of the specified data memory are incremented by one. If the re-

sult is zero, the next instruction is skipped and the result is stored in the ac­cumulator. The data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction (two
cycles). Otherwise proceed with the next instruction (one cycle).

Operation

Affected flag(s)

Skip if ([m]+1)=0, ACC ¬ ([m]+1)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

42 September 28, 1999

HT49C10

SNZ [m].i

Description

Operation

Affected flag(s)

SUB A,[m] Subtract data memory from the accumulator

Description The specified data memory is subtracted from the contents of the accumula

Operation

Affected flag(s)

SUBM A,[m] Subtract data memory from the accumulator

Description The specified data memory is subtracted from the contents of the accumula-

Operation

Affected flag(s)

Skip if bit ²i² of the data memory is not zero
If bit ²i² of the specified data memory is not zero, the next instruction is

skipped. If bit ²i² of the data memory is not zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (two cycles). Otherwise proceed
with the next instruction (one cycle).

Skip if [m].i¹0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

tor, leaving the result in the accumulator.
ACC ¬ ACC+[m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

tor, leaving the result in the data memory.
[m] ¬ ACC+[m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

]+1

]+1

-

SUB A,x Subtract immediate data from the accumulator

Description The immediate data specified by the code is subtracted from the contents of

the accumulator, leaving the result in the accumulator.

Operation

Affected flag(s)

ACC ¬ ACC+x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

+1

43 September 28, 1999

HT49C10

SWAP [m] Swap nibbles within the data memory

Description The low-order and high-order nibbles of the specified data memory (one of

the data memories) are interchanged.

Operation

Affected flag(s)

SWAPA [m] Swap data memory-place result in the accumulator

Description The low-order and high-order nibbles of the specified data memory are inter

Operation

Affected flag(s)

SZ [m] Skip if data memory is zero

Description If the contents of the specified data memory are zero, the following instruc

Operation Skip if [m]=0

Affected flag(s)

[m].3~[m].0 « [m].7~[m].4

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

changed, writing the result to the accumulator. The contents of the data
memory remain unchanged.

ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

tion, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (two cycles). Otherwise
proceed with the next instruction (one cycle).

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

-

-

SZA [m] Move data memory to ACC, skip if zero

Description The contents of the specified data memory are copied to the accumulator. If

the contents is zero, the following instruction, fetched during the current in
struction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (two cycles). Otherwise proceed with the next instruction
(one cycle).

Operation

Affected flag(s)

Skip if [m]=0, ACC ¬ [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

44 September 28, 1999

-

HT49C10

SZ [m].i

Description

Operation Skip if [m].i=0

Affected flag(s)

TABRDC [m] Move the ROM code (current page) to TBLH and data memory

Description The low byte of ROM code (current page) addressed by the table pointer

Operation

Affected flag(s)

TABRDL [m] Move the ROM code (last page) to TBLH and data memory

Description The low byte of ROM code (last page) addressed by the table pointer (TBLP)

Operation

Affected flag(s)

Skip if bit ²i² of the data memory is zero
If bit ²i² of the specified data memory is zero, the following instruction,

fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction (two cycles). Otherwise proceed
with the next instruction (one cycle).

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.

[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

is moved to the data memory and the high byte transferred to TBLH directly.
[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

XOR A,[m] Logical XOR accumulator with data memory

Description Data in the accumulator and the indicated data memory perform a bitwise

logical Exclusive_OR operation and the result is stored in the accumulator.

Operation

Affected flag(s)

ACC ¬ ACC XOR [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

45 September 28, 1999

HT49C10

XORM A,[m] Logical XOR data memory with the accumulator

Description Data in the indicated data memory and the accumulator perform a bitwise

logical Exclusive_OR operation. The result is stored in the data memory. The
zero flag is affected.

Operation

Affected flag(s)

XOR A,x Logical XOR immediate data to the accumulator

Description Data in the the accumulator and the specified data perform a bitwise logical

Operation

Affected flag(s)

[m] ¬ ACC ²XOR² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

Exclusive_OR operation. The result is stored in the accumulator. The zero
flag is affected.

ACC ¬ ACC ²XOR² x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

46 September 28, 1999

HT49C10

Holtek Semiconductor Inc. (Headquarters)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]

Holtek Semiconductor Inc. (Taipei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]
Fax: [phone] (International sales hotline)

Holtek Microelectronics Enterprises Ltd.

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: [phone]
Fax: [phone]

Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

47 September 28, 1999

-