Holtek Semiconductor Inc HT48R06A-1 Datasheet

HT48R06A-1

Preliminary

8-Bit OTP Microcontroller

Features

Operating voltage:

=4MHz: 3.3V~5.5V

SYS

=8MHz: 4.5V~5.5V

SYS

13 bidirectional I/O lines

An interrupt input shared with an I/O line

8-bit programmable timer/event counter with

overflow interrupt and 8-stage prescaler On-chip crystal and RC oscillator

Watchdog timer

1024´14 program memory PROM

64´8 data memory RAM

Buzzer driving pair and PFD supported

General Description

The device is an 8-bit high performance RISC-like microcontroller designed for multi ple I/O product applications. The device is par ticularly suitable for use in products such as remote controllers, fan/light controllers, wash ing machine controllers, scales, toys and vari-

Halt function and wake-up feature reduce

power consumption Up to 0.5ms instruction cycle with 8MHz

system clock at V Allinstructionsinoneortwomachinecycles

14-bit table read instruction

Two-level subroutine nesting

Bit manipulation instruction

63 powerful instructions

Low voltage reset function

18-pin DIP/SOP package

ous subsystem controllers. A halt feature is included to reduce power consumption.

The program and option memories can be elec

trically programmed, making the microcontrol

ler suitable for use in product development.

=5V

1 February 25, 2000

Block Diagram

Program

ROM

Program

C ounter

Preliminary

IN T /P C 0

Interrupt

Circuit

STACK0

STACK1

IN T C

TM R

TM RC

HT48R06A-1

P resca ler

TM R/PC1

SYS

Instruction

R egister

Instruction

D ecoder

Tim ing

G enerator

OSC2 OSC1

RES VDD VSS

Pin Assignment

MUX

ALU

Shifter

ACC

M U X

PA3

PA2

PA1

PA0

PB2

PB1/BZ

PB0/BZ

VSS

PC0/INT

PC0

DATA

Memory

STATUS

Option

PRO M

H T 48R 06A -1

1 8 D IP /S O P

WDTS

W D T P rescaler

PCC

PBC

PAC

PA4

PA5

PA6

PA7

OSC2

OSC1

VDD

RES

PC1/TMR

PORT C

BZ/BZ

PORT B

PORT A

SYS CLK/4

WDT

PC0~PC 1

PB0~PB2

PA0~PA7

PC1

M U X

RC OSC

2 February 25, 2000

Pin Description

Preliminary

HT48R06A-1

Pin No. Pin Name I/O

4~1 18~15

7 6 5

8 VSS

9 10

11 RES

12 VDD

13 14

PA0~PA7 I/O

PB0/BZ PB1/BZ PB2

PC0/INT PC1/TMR

OSC1 OSC2

I/O

¾¾

I/O Pull-high*

¾¾

ROM Code

Pull-high*

Wake-up

Pull-high*

Option

I/O or

BZ/BZ

Crystal

or RC

Description

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by ROM code option. Software instructions determine the CMOS output or schmitt trigger input with a pull-high resistor (deter mined by pull-high options).

Bidirectional 3-bit input/output port. Software in structions determine the CMOS output or schmitt trigger input with a pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with the BZ and BZ respectively. Once the PB0 and PB1 are selected as buzzer driving outputs, the output signals come from an internal PFD generator (shared with timer/event counter).

Negative power supply, ground

Bidirectional I/O lines. Software instructions deter mine the CMOS output or SCHMITT trigger input with a pull-high resistor (determined by pull-high op tions). The external interrupt and timer input are pin-shared with the PC0 and PC1, respectively. The external interrupt input is activated on a high to low transition.

Schmitt trigger reset input. Active low

Positive power supply

OSC1, OSC2 are connected to an RC network or Crystal (determined by ROM code option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

* All pull-high resistors are controlled by an option bit.

Absolute Maximum Ratings

Supply Voltage ...............VSS-0.3V to VSS+5.5V

Input Voltage.................V

Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maxi

mum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo sure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-40°Cto85°C

3 February 25, 2000

Preliminary

HT48R06A-1

D.C. Characteristics

Symbol Parameter

DD1

DD2

DD3

STB1

STB2

DD1

DD2

IL1

IH1

IL3

IH3

LVR

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Operating Current (Crystal OSC)

Standby Current (WDT Enabled)

Standby Current (WDT Disabled)

Input Low Voltage for I/O Ports, TMR and INT

Input High Voltage for I/O Ports, TMR and INT

Input Low Voltage (RES

)

Input High Voltage (RES

)

Low Voltage Reset

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

Test Conditions

3.3V

Conditions

=4MHz

SYS

=8MHz

SYS

No load, f

SYS

=4MHz

5V No load, fsys=8MHz

3.3V No load, system Halt

3.3V

¾¾

3.3V

=0.1V

=0.9V

Ta=25°C

Min. Typ. Max. Unit

3.3

4.5

¾¾

0.8V

0.9V

5.5 V

12mA

24mA

12mA

24mA

510mA

0.2V

0.4V

3.1 3.2 3.3 V

10 20

-2 -4 ¾

-5 -10 ¾

40 60 80

10 30 50

4 February 25, 2000

Preliminary

HT48R06A-1

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

TIMER

WDTOSC

WDT1

WDT2

RES

SST

INT

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency (TMR)

Watchdog Oscillator

Watchdog Time-out Period (RC)

Watchdog Time-out Period (System Clock)

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

Ta=25°C

Test Conditions

Min. Typ. Max. Unit

3.3V

5V 9 17 35 ms

¾¾

Conditions

Without WDT prescaler

Power-up, reset or wake-up from Halt

400

4000 kHz

8000 kHz

4000 kHz

43 86 168

35 65 130

11 22 43 ms

1024

¾¾ms

1024

¾¾ms

SYS

5 February 25, 2000

Preliminary

Functional Description

Execution flow

The system clock for the microcontroller is de rived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes an in struction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to ef fectively execute in a cycle. If an instruction changes the program counter, two cycles are re quired to complete the instruction.

Program counter - PC

The program counter (PC) controls the se quence in which the instructions stored in pro gram PROM are executed and its contents specify full range of program memory.

After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.

HT48R06A-1

When executing a jump instruction, conditional skip execution, loading PCL register, subrou

tine call, initial reset, internal interrupt, exter nal interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instruc tions. Once the condition is met, the next in

struction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper in

struction. Otherwise proceed with the next in struction.

The lower byte of the program counter (PCL) is

a readable and writable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations.

When a control transfer takes place, an addi

tional dummy cycle is required.

Program memory - PROM

The program memory is used to store the pro gram instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 1024´14 bits, addressed by the program counter and table pointer.

S yste m C lock

OSC2 (RC only)

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

PC PC+1 PC+2

F e tc h IN S T (P C )

Execute IN S T (P C -1)

F e tc h IN S T (P C + 1 )

Execute IN S T (P C )

F e tc h IN S T (P C + 2 )

Execute IN S T (P C +1)

Execution flow

6 February 25, 2000

Preliminary

HT48R06A-1

Certain locations in the program memory are reserved for special usage:

Location 000H This area is reserved for program initializa

tion. After chip reset, the program always be gins execution at location 000H.

Location 004H This area is reserved for the external inter

rupt service program. If the INT

input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.

Location 008H This area is reserved for the timer/event coun

ter interrupt service program. If a timer inter rupt results from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.

Table location Any location in the PROM space can be used

as look-up tables. The instructions "TABRDC [m]" (the current page, 1 page=256 words) and "TABRDL [m]" (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of

000H

004H

008H

n00H

nFFH

3FFH

D evice Initialization P rogram

External Interrupt Subroutine

Tim er/Event C ounter Interrupt S ubroutine

Look-up Table (256 w ords)

14 bits

N ote: n ranges from 0 to 3

Program Memory

Program memory

the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 2 bits are read as "0". The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service

Mode

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial Reset 0000000000

External Interrupt 0000000100

Timer/Event Counter Overflow 0000001000

Skip PC+2

Loading PCL *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *9~*0: Program counter bits S9~S0: Stack register bits

#9~#0: Instruction code bits @7~@0: PCL bits

7 February 25, 2000

Preliminary

HT48R06A-1

Routine) both employ the table read instruc tion, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read in struction in the main routine and the ISR si multaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the inter rupt is supposed to be disabled prior to the ta ble read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to com plete the operation. These areas may function as normal program memory depending upon the requirements.

Stack register - STACK

This is a special part of the memory which is used to save the contents of the program coun ter (PC) only. The stack is organized into 2 lev els and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhib

ited. When the stack pointer is decremented (by

RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more eas ily. In a similar case, if the stack is full and a

"CALL" is subsequently executed, stack over

flow occurs and the first entry will be lost (only the most recent 2 return addresses are stored).

Data memory - RAM

The data memory is designed with 81´8 bits. The data memory is divided into two func

tional groups: special function registers and

general purpose data memory (64´8). Most are read/write, but some are read only.

The special function registers include the indi rect addressing register (00H), timer/event counter (TMR;0DH), timer/event counter con trol register (TMRC;0EH), program counter

lower-order byte register (PCL;06H), memory

pointer register (MP;01H), accumulator

(ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control reg ister (INTC;0BH), watchdog timer option set ting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H). The remaining space before the 40H is reserved for future expanded usage and reading these locations will get "00H". The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under instruction commands.

Instruction

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *9~*0: Table location bits P9, P8: Current program counter bits

@7~@0: Table pointer bits

Table Location

8 February 25, 2000

Preliminary

HT48R06A-1

All of the data memory areas can handle arith metic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by "SET [m].i" and "CLR [m].i". They are also indirectly accessible through memory pointer register (MP;01H).

Indirect addressing register

Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data mem ory pointed to by MP (01H). Reading location 00H itself indirectly will return the result 00H. Writ ing indirectly results in no operation.

The memory pointer register MP (01H) is a 7-bit register. The bit 7 of MP is undefined and reading will return the result 1 . Any writing operation to MP will only transfer the lower 7-bit data to MP.

Accumulator

The accumulator is closely related to ALU oper ations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL) Rota tion (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op eration but also changes the status register.

Status register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), and

Indirect A ddressing R egister

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH

1FH

20H

3FH

40H

7FH

G eneral Purpose DATA M EMO RY

ACC

PCL

TBLP

TBLH

WDTS

STATUS

IN T C

TM R

TM RC

PAC

PBC

PCC

R ead as "00"

(64 B ytes)

RAM mapping

watchdog time-out flag (TO). It also records the status information and controls the operation

sequence.

With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flag. In addition opera

Special P urpose DATA M EMO RY

: U n u s e d

9 February 25, 2000

Preliminary

HT48R06A-1

tions related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the "CLR WDT" or "HALT" instruction. The PD flag can be affected only by executing the "HALT" or "CLR WDT" instruction or a sys tem power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or executing the subroutine call, the status reg ister will not be pushed onto the stack automat ically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly.

Interrupt

The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) con tains the interrupt control bits to set the en able/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all

the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any fur ther interrupt nesting. Other interrupt re quests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the correspond

ing bit of INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in terrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must

be prevented from becoming full.

All these kinds of interrupts have a wake-up ca

pability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a sub routine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the in terrupt service program which corrupts the de

sired control sequence, the contents should be

saved in advance.

External interrupts are triggered by a high to low transition of INT

and the related interrupt

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor-

¾ ¾

row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is

cleared.

OV is set if the operation results in a carry into the highest-order bit but not a

carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by system power-up or executing the "CLR WDT" instruction. PD

is set by executing the "HALT" instruction.

TO is cleared by system power-up or executing the "CLR WDT" or "HALT" in

struction. TO is set by a WDT time-out.

6 Undefined, read as "0"

7 Undefined, read as "0"

Status register

10 February 25, 2000

Preliminary

HT48R06A-1

request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a sub routine call to location 04H will occur. The in terrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts.

During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the "RETI" instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, "RET" or "RETI" may be invoked. RETI will set the EMI bit to en able an interrupt service, but RET will not.

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the

Controls the master (global) interrupt (1= enabled; 0= disabled)

Controls the external interrupt (1= enabled; 0= disabled)

Controls the timer/event counter interrupt (1= enabled; 0= disabled)

Unused bit, read as "0"

External interrupt request flag (1= active; 0= inactive)

Internal timer/event counter request flag (1= active; 0= inactive)

Unused bit, read as "0"

INTC

(0BH)

0 EMI

1 EEI

2 ETI

4 EIF

5TF

¾ ¾

following table shows the priority that is ap plied. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External Interrupt 1 04H

Timer/event

Counter Overflow

The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), en able timer/event counter bit (ETI), enable ex ternal interrupt bit (EEI) and enable master interrupt bit (EMI) constitute an interrupt con trol register (INTC) which is located at 0BH in the data memory. EMI, EEI, ETI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.

It is recommended that a program does not

use the "CALL subroutine" within the inter rupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will

2 08H

INTC register

11 February 25, 2000

Preliminary

HT48R06A-1

be damaged once the "CALL" operates in the in terrupt subroutine.

Oscillator configuration

There are two oscillator circuits in the microcontroller.

OSC1

OSC2

C rystal O scillator R C O scillator

470pF

SYS

N M O S O pen D rain

OSC1

OSC2

System oscillator

Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined by the ROM code option. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power.

If an RC oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 51kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across

OSC1 and OSC2 is needed to provide the feed

back and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resonator can also be con nected between OSC1 and OSC2 to get a fre quency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillat ing frequency is less than 1MHz).

The WDT oscillator is a free running on-chip RC oscillator, and no external components are re quired. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approxi mately 65ms/5V. The WDT oscillator can be dis abled by ROM code option to conserve power.

Watchdog timer - WDT

The clock source of WDT is implemented by a dedicated RC oscillator (WDT oscillator) or in struction clock (system clock divided by 4), de cided by ROM code option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by a ROM code option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with a period of 65ms/5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of approximately

16.6ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and

S yste m C lock/4

WDT

OSC

ROM C ode

Option

Select

W D T P re scaler

8-bit C ounter

7-bit C ounter

8-to-1 M U X

W D T Tim e-out

WS0~WS2

Watchdog timer

12 February 25, 2000

Preliminary

HT48R06A-1

the maximum time-out period is 2.2s/5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and op erate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user's defined flags, which can be used to indicate some specified status.

If the device operates in a noisy environment, us ing the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.

WS2 WS1 WS0 Division Ratio

000 1:1

001 1:2

010 1:4

011 1:8

1 0 0 1:16

1 0 1 1:32

1 1 0 1:64

1 1 1 1:128

WDTS register

The WDT overflow under normal operation will initialize "chip reset" and set the status bit "TO". But in the HALT mode, the overflow will initialize a ²warm reset², and only the PC and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level

), software instruction and a "HALT" in-

to RES struction. The software instruction include "CLR WDT" and the other set - "CLR WDT1" and "CLR WDT2". Of these two types of instruc tion, only one can be active depending on the ROM code option - "CLR WDT times selection option". If the "CLR WDT" is selected (i.e. CLRWDT times equal one), any execution of the "CLR WDT" instruction will clear the WDT. In the case that "CLR WDT1" and "CLR WDT2" are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out.

Power down operation - HALT

The HALT mode is initialized by the "HALT" in

struction and results in the following...

The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is selected).

The contents of the on chip RAM and regis ters remain unchanged.

WDT and WDT prescaler will be cleared and

recounted again (if the WDT clock is from the WDT oscillator).

AlloftheI/Oportsmaintaintheiroriginalstatus.

The PD flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port Aor a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a "warm re set". After the TO and PD flags are examined, the reason for chip reset can be determined. The PD flag is cleared by system power-up or executing the "CLR WDT" instruction and is set when executing the "HALT" instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the others keep their original status.

The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the ROM code option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the inter rupt is enabled and the stack is not full, the reg ular interrupt response takes place. If an interrupt request flag is set to "1" before enter ing the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 t tem clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual inter rupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the

SYS

(sys

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Preliminary

HT48R06A-1

next instruction execution, this will be executed immediately after the dummy period is fin ished.

To minimize power consumption, all the I/O pins should be carefully managed before enter ing the HALT status.

Reset

There are three ways in which a reset can occur:

RES reset during normal operation

RES reset during HALT

WDT time-out reset during normal operation

The WDT time-out during HALT is different from other chip reset conditions, since it can perform a "warm reset" that resets only the PC and SP, leaving the other circuits in their origi nal state. Some registers remain unchanged during other reset conditions. Most registers are reset to the ²initial condition² when the re set conditions are met. By examining the PD and TO flags, the program can distinguish be tween different "chip resets".

TO PD RESET Conditions

0 0 RES

u u RES

0 1 RES

reset during power-up

reset during normal operation

wake-up HALT

WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: "u" means "unchanged"

To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES

reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay.

VDD

RES

SST Tim e-out

Chip Reset

SST

Reset timing chart

RES

HALT

Reset circuit

WDT

RES

SST

OSC1

10-bit R ipple

C ounter

System R eset

Reset configuration

The functional unit chip reset status are shown below.

PC 000H

Interrupt Disable

Prescaler Clear

WDT

Timer/event Counter

Input/output Ports

Clear. After master reset, WDT begins counting

Off

Input mode

Points to the top of the stack

W arm R eset

Cold Reset

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+ 30 hidden pages

Holtek Semiconductor Inc HT48R06A-1 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pin Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description