HOLT HI-8482UT, HI-8482U, HI-8482ST, HI-8482SM-01, HI-8482S Datasheet

February2001

GENERALDESCRIPTION

TheHI-8482businterfaceunitisasilicongateCMOSde­vicedesignedasadualdifferentiallinereceiverinaccor­dancewiththerequirementsoftheARINC429busspec­ification.ThedevicetranslatesincomingARINC429sig­nalstonormalCMOS/TTLlevelsoneachofitstwoinde­pendentreceivechannels.TheHI-8482isalsofunction­allyequivalenttotheFairchild/RaytheonRM3183.

Theself-testinputsforcetheoutputstoeitheraZERO,
ONE,orNULLstateforsystemtests.Whileinself-test
mode,theARINCinputsareignored.

AlltheARINCinputshavebuilt-inhysteresistoreject
n oisethatmaybepresentontheARINCbus.Additional
inputnoisefilteringcanalsobeaccomplishedwithexter­nalcapacitors.

TheHI-8482linereceiverisoneofseveraloptionsof­feredbyHoltIntegratedCircuitstointerfacetotheARINC
bus.Thedigitaldataprocessingforserial-to-parallelcon­versionandclockrecoverycanbeaccomplishedwiththe
HI-6010,HI-8683orsimilardevices.

TheHI-8482isavailableinavarietyofceramic&plastic
packagesincludingSmallOutline(SOIC),
Cerquad,

DIP&LeadlessChipCarrier(LCC).

J-LeadPLCC,

FEATURES

PINCONFIGURATIONS (TopViews)

IN2B-4

OUT2B-5

IN2A-6
CAP2A-7
OUT2A-8

-V-1

S

TESTA-2

CAP2B-3

IN2B-4

OUT2B-5

IN2A-6
CAP2A-7
OUT2A-8

+V-9

L

N/C-10

HI-8482J

HI-8482JT

20-PIN

PLASTIC

J-LEADPLCC

HI-8482PSI

HI-8482PST

20-PIN

PLASTIC

SMALL

OUTLINE

(SOIC)-WB

18-IN1A
17-CAP1B
16-IN1B
15-OUT1A
14-GND

20-TESTB
19-CAP1A
18-IN1A
17-CAP1B
16-IN1B
15-OUT1A
14-GND
13-N/C
12-OUT1B
11-+V S

!

ConvertsARINC429levelstodigitaldata

!

DirectreplacementfortheRM3183

!

Greaterthan2voltreceivinghysteresis

!

TTLandCMOSoutputsandtestinputs

!

Militaryscreeningavailable

!

20-PinSOIC,PLCC,CERQUAD.DIP&
LCCpackagesareavailable

HOLTINTEGRATEDCIRCUITS

TRUTHTABLE

ARINCINPUTSTESTINPUTSOUTPUTS

V(A)-V(B)TESTATESTBOUTAOUTB

Null0000
Zero0001
One0010

Don'tCare0101
Don'tCare1010
Don'tCare1100

1(DS8482Rev.C)02/01

FUNCTIONALDESCRIPTION

HI-8482

TheHI-8482containstwoindependentARINC429receive
channels.ThediagraminFigure1illustratesatypicalHI­8482receivechannel.

ThedifferentialARINCsignalinputisconvertedtoapositive
signalreferencedtogroundthroughlevelshiftersanda
unitygaindifferentialamplifier.

Apositivedifferentialinputsignalisconvertedtoapositive
signalontheplusoutputofthedifferentialamplifier.This
outputisproportionalinamplitudetotheoriginalinput
signal.Atthesametime,thecorrespondingMINUSoutput
ispulledtoGND.Likewisewhenanegativeinputsignalis
p resentattheARINCinputs,apositivesignalispresenton
theMINUSoutputandthePLUSoutputispulledtoGND.

Theoutputsofthedifferentialamplifierarecomparedwith
theONE,ZEROandNULLthresholdlevelstoproducethe
appropriatelogiclevelontheOUTAandOUTBoutputsof
thedevice.TheARINCclocksignalmayberecovered
throughaNORfunctionofOUTAandOUTB.

Thetestinputslogicallydisconnecttheoutputsofthe
comparatorsfromOUTAandOUTBandforcethedevice
outputstooneofthethreevalidstates(Figure5).This
alleviateshavingtogroundtheARINCinputsduringtest
mode operation.

ARINCLEVELS

TheARINC429specificationrequiresthefollowing
detectionlevels:

STATEDIFFERENTIALVOLTAGE

ONE+6.5Vto+13V

NULL+2.5Vto-2.5V

ZERO-6.5Vto-13V

TheHI-8482guaranteesrecognitionoftheselevelswitha
commonmodevoltagewithrespecttoGNDlessthan
±5Vfortheworstcasecondition.

NOISE

Theinputhysteresisissettorejectvoltageleveltransitions
intheundefinedregionbetweenthemaximumZEROlevel
andtheminimumNULLlevelandtheundefinedregion
betweenthemaximumNULLlevelandtheminimumONE
level.Therefore,onceavalidinputdifferentialvoltage
thresholdisdetected,theoutputswillremainatavalidlogic
stateuntilanewvalidinputvoltageisdetected.

Inadditiontothehysteresis,theCapAandCapBpinsmake
itpossibletoaddsimpleRCfilterstotheARINCinputs.

TESTA

TESTB

INA

CAPA

INB

CAPB

LEVEL

SHIFT

LEVEL

SHIFT

Detect
Level

Comp

DIFF
AMP

Detect
Level

Comparators
w/hysteresis

Comp

HOLTINTEGRATEDCIRCUITS

2

HI-8482

TYPICALAPPLICATIONS

APPLICATIONS

ThestandardconnectionsfortheHI-8482areshowninFigure2.
DecouplingofthesupplyshouldbedoneneartheICtoavoid
propagationofnoisespikesduetoswitchingtransients.The

ARINCRECEIVERSTANDARDCONNECTIONS

ARINC

CHANNEL1

39pF
39pF

ARINC

CHANNEL2

39pF
39pF

ground(GND)connectionshouldbesturdyandisolatedfromlarge
switchingcurrentstoprovideaquietgroundreference.

TheHI-8482canbeusedwithHI-8382orHI-8585LineDriversto
provideacompleteanalogARINC429interfacesolution.Asimple
application,whichcanbeusedinsystemsrequiringarepeater
typecircuitforlongtransmissionsorfortestinterfaces,isgivenin
Figure3.MoreHI-8382orHI-8585driversmaybeaddedtotest
multipleARINCchannels,asshown.

+5V

+15V

HI-8482

IN1A
IN1B
CAP1A
CAP1B
IN2A
IN2B
CAP2A
CAP2B

OUT1A
OUT1B

OUT2A
OUT2B

A
B

A
B

CHANNEL1

DATAOUT

TOLOGIC

CHANNEL2

DATAOUT

TOLOGIC

ARINC

INPUT

CHANNEL

LOGIC

TEST

INPUTS

IN1A

IN1B

TESTA
TESTB

ARINCREPEATERCIRCUIT

OUT1A

OUT1B

DATA(A)

DATA(B)

DATA(A)

DATA(B)

-15V

AOUT

BOUT

AOUT

BOUT

N/C
N/C

A
B

A
B

ARINC

OUTPUT

CHANNEL1

ARINC

OUTPUT

CHANNEL2

HOLTINTEGRATEDCIRCUITS

3