HITACHI VTMX900ECT, VTMX900EUK, VTMX905EUK, VTMX905EVPS, VTMX910EUK Service Manual

...

SERVICE MANUAL

VORSICHT:

Data contained within this Service

Verbesserungen

ndern.

MANUEL D’ ENTRETIEN WARTUNGSHANDBUCH

No. 0301

VTMX900ECT VTMX900EUK VTMX905EUK VTMX905EVPS VTMX910EUK VTMX902EL VTMX930EVPS VTMX932EL

CAUTION:

Before servicing this chassis, it is important that the service technician read the “ Safety Precautions” and “ Product Safety Notices” in this service manual.

ATTENTION:

Avant d’ effectuer l’ entretien du châassis, le technicien doit lire les «Précautions de sécurité» et les «Notices de sécurité du produit» présentés dans le présent manuel.

Vor Öffnen des Gehäuses hat der Service-Ingenieur die „ Sicherheitshinweise“ und „ Hinweise zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen

VTFX2000ELN VTFX940EVPS VTFX940EUKN VTFX940ENA VTFX942ELN VTFX940ELN VTFX952ELN

manual is subject to alteration for improvement.

Les données fournies dans le présent manuel d’ entretien peuvent faire l’ objet de modifications en vue de perfectionner le produit.

Die in diesem Wartungshandbuch enthaltenen Spezifikationen können sich zwecks

June 2000

1-6

Safety instructions

– Safety regulations demand that the set be restored to its

original condition and that components identical with the original types be used.

Safety components are marked by the symbol

– All ICs and many other semi-conductors are susceptible to

electrostatic discharges (ESD). Careless handling during repair may reduce life drastically. When repairing, make sure that you are conneted with the same potential as the mass of the set via a wrist wrap with resistance. Keep components and tools on the same potential.

– A set to be repaired should always be connected to the mains

via a suitable isolating transformer.

– Never replace any modules or any other parts while the set is

switched on.

– Use plastic instead of metal alignment tools. This in order to

prelude short-circuit or to prevent a specific circuit from being rendered unstable.

Remarks

– The direct voltages and oscillograms ought to be measured

relative to the set mass. EXCEPTION At the power supply, the DC voltages and the oscillograms at the primary side are measured to LIVE GND.

– The direct voltages and oscillograms mentioned in the

diagrams ought to be measured with a colour bar signal and the picture carrier at 503.25 MHz (C25).

– The oscillograms and direct voltages have been measured in

RECORD or PLAY mode.

– The semiconductors, which are mentioned in the circuit

diagram and in the parts lists, are fully exchangeable per position with the semiconductors in the set, irrespective of the type designation of these semiconductors.

Sicherheitshinweise

– Die Sicherheitsvorschriften erfordern es, daß sich das Gerät

nach der Reparatur in seinem originalen Zustand befindet und daß die zur Reparatur benutzten Ersatzteile mit den Originalersatzteilen identisch sind. Sicherheits-Bauteile sind mit der Markierung versehen

– Alle IC’s und Halbleiter sind empfindlich gegen elektrostatische

Entladungen (ESD). Unvorschriftmässige Behandlung von Halbleitern im Reparaturfall kann zur Zerstörung dieser Bauteile oder zu einer drastischen Reduzierung der Lebensdauer führen. Sorgen Sie dafür, daß Sie sich im Reparaturfall über ein Armband mit Widerstand auf dem gleichen Potential, wie die Masse des Gerätes befinden. Alle Bauteile, Werkzeuge und Hilfsmittel sind auf das gleiche Potential zu legen.

– Ein zu reparierendes Gerät ist immer über einen

Trenntransformator an die Netzspannung anzuschließen.

– Bei eingeschaltetem Gerät dürfen keine Module oder sonstige

Einzelteile ausgetauscht werden.

– Zum Abgleich sind ausschließlich Kunststoffwerkzeuge zu

benutzen (keine Metallwerkzeuge verwenden). Dadurch wird vermieden, daß ein Kurzschluß entstehen kann oder eine Schaltung instabil wird.

Anmerkungen

– Die Gleichspannung und Oszillogramme sind gegen

Gerätemasse zu messen. AUSNAHME Beim Netzteil sind die Gleichspannungen und Oszillogramme auf der Primärseite gegen Live GND gemessen.

– Die Gleichspannungen und Oszillogramme angeführt in den

Schaltbildern sollen unter folgenden Bedingungen gemessen werden: Farbbalkensignal, Bildträger auf 503.25 MHz (C25)

– Die Oszillogramme und Gleichspannungen sind in RECORD

oder PLAY gemessen. Die in den Stücklisten aufgeführten Bauteile sind positionsweise voll auswechselbar gegen die Bauteile in dem Gerät, ungeachtet der etwaigen Typenbezeichungen.

Avertissements

– Les normes de sécurité exigent qu’aprés réparation I’appareil

soit remis dans son état d’origine et que soient utilisées les piéces de rechange identiques à celles spécifiées.

Les composants de sécurité sont marqués

– Tout les IC et beaucoup d’autres semi-conducteurs sont

sensibles aux décharger statiques (ESD). Leur longévité pourrait étre considérablement écourté par le fait qu’aucune précaution n’est prise à leur manipulation. Lors de réparations s’assurer de bien étre relié au méme potential que la masse de l’appareil et enfiler le bracelet serti d’une résistance de sécurité. Veiller à ce que les composants ainsi que les outils que I’on utilise soient également à ce potentiel.

– Toujours alimenter un appareil à réparer à travers un transfo

d’isolement.

– Ne jamais remplacer les modules ni d’autres composants

quand I’appareil est sous tension.

– Pour l’ajustage, utiliser des outils en plastique au lieu

d’instruments métalliques. Ceci afin d’éviter les court-circuits et exclure I’instabilité dans certains circuits.

Observations

– La mésure des tensions continues et des oscillogrammes doit

se faire par rapport à la terre de l’appareil. EXCEPTION Sur l’unité d’alimentation la tension continue et l’oscillogramme sont mesurés sur le côte primaire en Live GND.

– La mésure des tensions continues et des oscillogrammes

figurant sur le schéma doit se faire dans un signal de barre couleur porteuse image sur 503.25 MHz (C25).

– Les oscillogrammes et tension sont mésurées en mode

RECORD ou PLAY.

– Les semi-conducteurs indiqués dans le schéma de principe et

à la liste des compostants, sont interchangeables par repère sur ce chassis avec les semi-conducteurs de l’appareil quelle que soit la désignation de type donnée sur ces semiconducteurs.

Veiligheidsinstructies

– Veiligheidsbepalingen vereisen, dat het apparaat in zijn

oorspronkelijke toestand wordt teruggebracht en dat onderdelen, indentiek aan de oorspronkelijke, worden toegepast. De veiligheidsonderdelen zijn aangeduid met het symbool

– Alle IC’s en vele andere halfgeleiders zijn gevoelig voor

elektrostatische ontladingen (ESD). Onzorgvuldig behandelen tijdens reparatie kan de levensduur drastisch doen verminderen. Zorg ervoor, dat U tijdens reparatie via een polsband met weerstand verbonden bent met hetzelfde potentiaal als de massa van het apparaat. Houd componenten en hulpmiddelen ook op ditzelfde potentiaal.

– Sluit een apparaat dat gerepareerd wordt altijd via een

scheidingstransformator aan op de netspanning.

– Verwissel nooit modules of andere onderdelen terwijl het

apparaat is ingeschakeld.

– Gebruik voor het afregelen plastic i.p.v metalen gereedschap.

Dit om mogelijke kortsluiting te voorkomen of een bepaalde schakeling instabiel te maken.

Opmerkingen

– De gelijksspanningen en oscillogrammen dienen gemeten te

worden ten opzichte van de apparaat aarde.

– De gelijksspanningen en oscillogrammen vermeld in de

schema’s dienen gemeten te worden met een kleurbalkensignaal beelddraaggolf op 503.25 MHz (C25).

– De oscillogrammen en gelijksspanningen zijn in RECORD of

PLAY mode gemeten.

– De halfgeleiders, die in het pricipeschema en in de stuklijsten,

zijn vermeld, zijn per positie volledig uitwisselbaar met de halfgeleiders in het apparaat, ongeacht de typeaanduiding op deze halfgeleiders.

1-7

Avvertimenti

– Le prescrizioni di sicurezza richiedono che l’apparecchio sia

ricondotto alle condizioni originali e che siano usati ricambi originali.

Componenti di sicurezza sono marcati con

– Tutti gli IC e semiconduttori sono sensibili a scariche

elettrostatiche (ESD). Noncuranze durante la riparazione di semiconduttori possono danneggiarli o condurre ad una riduzione drastica della durata. Durante la riparazione assicurarsi di essere collegati allo stesso potenziale attraverso un bracciale di protezione contro scariche elettrostatiche. Inoltre tenere anche tutti i componenti e gli attrezzi a questo potenziale.

– Apparecchi da riparare bisogna collegarli sempre via un

trasformatore isolante (separatore) alla tensione normale.

– Non scambiare moduli o altri componenti quando l’apparecchio

è in funzione.

– Per l’accordo usare soltanto attrezzi di plastica (non usare

attrezzi metallici). Cosí si evitano cortocircuiti e collegamenti instabili.

Osservazioni

– Misurare le tensioni continue e gli oscillogrammi riferiendosi

alla massa dell’apparecchio. ECCEZIONE Le tensioni continue e gli oscillogrammi dall’alimentatore sono misurati sulla parte primaria contro GND-Live.

– Le tensioni continue e gli oscillogrammi indicati negli schemi di

collegamento devono essere misurati secondo le condizioni seguenti: segnale barre colore, portante dell’immagine su:

503.25 MHz (C25).

– Gli oscillogrammi e le tensioni continue sono misurati in

RECORD o PLAYBACK.

– I componenti indicati nelle liste sono intercambiabili con quelli

nell’apparecchio nonostante l’eventuale denominazione di modelli.

Avisos

– Las instrucciones de seguridad exigen que después de la

reparación el aparato se encuentre en el estado original y que las piezas de repuesto, utilizadas para la reparación, sean idénticas a las originales.

Los componentes de seguridad estan marcados con

– Todos los IC y semiconductores son sensibles a descargas

electrostáticas (ESD). Un tratamiento no conforme a las instrucciones de semiconductores en caso de reparación, podría llevar a la destrucción de estos componentes, o a una reducción drástica de la duración. Tenga cuidado de que, en caso de reparación, estar al mismo potencial que la masa del aparato, por una pulsera con resistencia. Ponga todos los componentes, herramientas y recursos al mismo potencial.

– Para reparar un aparato hay que conectarlo siempre a la

alimentación a traves de un transformador de aislamiento.

– Cuando un aparato está en marcha no pueden ser cambiados

módulos u otras piezas de repuesto.

– Para los ajustes hay que utilizar exclusivamente herramientas

de plástico (nunca herramientas metálicas). Así se evitaran cortocircuitos y circuitos inestables.

Notas

– Hay que medir las tensiones continuas y los oscilogramas

contra la masa del aparato. UITZONDERING: Bij het netgedeelte zijn de gelijkspanningen en oscillogrammen aan de primaire kant tegen Live GND gemeten.

– Las tensiones continuas y los oscilogramas mencionados en

los esquemas tienen que ser medidos de manera siguiente: señal barra de color portadora de imagen en 503.25MHz (C25)

– Los oscilogramas y las tensiones continuas son medidas en

„RECORD“ y „PLAYBACK“

– Los componentes mencionados en las listas se los puede

cambiar por los componentes en el aparato, a pesar de eventuales designaciones de tipos.

1-8

Modifications

Description of the system used for publishing modification data and supplements to the service manual.

All modification data and supplements to the Service Manual are published by means of Service Information bulletins.

Each Service information has a number, for example :

VR 00 - 01 GB

Language Sequence number Y ear Video cassette recorder

A Service Information bulletin concists of a front sheet, as the case may be followed by supplementary and/or replacement sheets.

Replacement sheets serve to replace existing sheets in the Service Manual. These sheets are identified by an additional letter after the page number, for example 5-1a. Page 5-1a then takes the place of page 5-1.

Supplementary sheets are inserted between the existing sheets in the Service Manual. These sheets can be identified by an additional figure following the page number, for example 5-1-1.

Sheet 5-1-1 should be inserted after page 5-1.

Description of the system by means of which modifications are indicated in the recorder.

All important parts of the recorder, such as tape deck, p.c. boards and modules, are provided with a sticker. These stickers specify a number of product data. The meaning of this data will now be explained for the most important sections.

Tape deck

12345678 009271 AT-P2/0 00151 10WD51

Production code Factory indication Production date T ape deck type Factory code number Serial number

Note : The production code and the serial number on the tape deck need

not correspond to the production code and the serial number on the type plate.

Printed panels

The stickers are generally located on the track side of the module. Example :

AVR 01102

12345 KW 015 WD 01 123456

Serial number Production code Production week Printed board name Factory code

Remarks :

The complete recorder

The type plate is located at the back of the recorder, below an example of such a type plate is given.

Type plate :

.FOR BY GEMSTARDEVELOPMENT CORP. P

.GEMSTARDEVELOPMENT CORP.

MADE IN EUROPEMADE IN EUROPE

220-240 V ~220-240 V ~

AAA BBB CCC DDD EEE FFF GGG

MODEL NO:MODEL NO:

PROD.NO:PROD.NO:

VN 37 0015 123456VN 37 123456

50Hz50Hz

VR110/02

Note :

- In the case of an important modification to the recorder the production code on the type plate is increased by one. E.g. 37 becomes 38.

- In the case of an important modification to the service documentation the evolution code on the type plate is increased by one. E.g. AA becomes AB.

Service

Option codes (A-G)

IS M

Evolution code

Type number

UNDER LICENSE FROM

SHOWVIEW IS A TRADEMARK APPLIED

SHOWVIEW SYSTEM IS MANUFACTURED

Serial number Production date

Production center (VN), Production code

The production code number will not always be mentioned. In case of an important modification, the last figure of the factory code

number (point number) is increased by one. E.g. 6635.1 becomes

6635.2.

1-9

GB D

TECHNICAL DATA TECHNISCHE DATEN CARACTERISTIQUES

Mains voltage.................................. Netzspannung ...................................... Tension secteur ............................. 220 - 240 V, +/- 10%

Mains frequency ............................. Netzfrequenz ....................................... Fréquence...................................... 45 - 65 Hz

Power consumption: ...................... Leistungsaufnahme:.............................. Puissance absorbée: ..................... mono 12.5 W during operation

HiFi 16 W during operation

without Low Power Standby...... Standby................................................ mode veille normal ........................ mono 4 W during standby

HiFi 4.4 W during standby

with Low Power Standby ........... Standby mit geringem Verbrauch ........ mode veille faible consommation .. < 4 W standby

Ambient temperature ...................... Raumtemperatur .................................. Température ambiante .................. +10°C to +35°C

Relative humidity ............................ Relative Luftfeuchtigkeit ...................... Humidité relative ............................ 20 - 80 %

Dimensions ..................................... Abmessungen ...................................... Encombrement .............................. 380 x 260 x 94 mm

Weight............................................. Gewicht ................................................ Poids .............................................. 3,7 kg

Fast forward/rewind time (turbo) ... Vor-/Rückspulzeit (turbo) ..................... Temps (re-)bobinage (turbo) ......... typ. 100s (E180 cass.)

Position of use ................................ Betriebslage ......................................... Position d'emploi ........................... horizontally, max. 15°

Video resolution .............................. Video-Auflösung .................................. Puissance absorbée ...................... ≥240 lines

Audio............................................... Audio.................................................... Audio SP: Linear Audio ................. 80Hz - 10kHz (+/−6 dB)

Audio LP: Linear Audio.................. 80Hz - 5kHz (+/−6 dB)

Stereo FM Audio............................ 20Hz - 20kHz (+/−3dB)

NL E I

TECHNISCHE GEGEVENS DATOS TECNICOS DATI TECNICI

Netspanning.................................... Tensión de red ..................................... Tensione di alimentazione............. 220 - 240 V

Netfrequentie .................................. Frecuencia de red ................................ Frequenza di rete .......................... 45 - 65 Hz

Opgenomen vermogen: .................. Consumo de potencia:......................... Potenza assorbita: ......................... mono 12.5 W during operation

HiFi 16 W during operation

zonder Low Power Standby ...... sin standby de bajo consumo .............. in attesa non a basso consumo .... mono 4 W during standby

HiFi 4.4 W during standby

met Low Power Standby ........... con standby de bajo consumo............. in attesa a basso consumo............ < 4 W standby

Omgevingstemperatuur .................. Temperatura ambiente ........................ Temperatura ambiente .................. +10°C to +35°C

Relatieve vochtigheid ..................... Humedad relativa ................................ Umiditá relativa .............................. 20 - 80 %

Afmetingen...................................... Dimensiones ........................................ Dimensioni ..................................... 380 x 260 x 94 mm

Gewicht ........................................... Peso ..................................................... Peso ............................................... 3,7 kg

Vooruit/terugspoeltijd (turbo) .......... tiempo de (re-)bobinado (turbo) .......... Tempo di (ri-)avvolgimento (turbo) typ. 100s (E180 cass.)

Gebruikspositie ............................... Posición de uso ................................... Posizione di funzionamento .......... horizontally, max. 15°

Opplossend vermogen ................... Resolución video ................................. Risoluzione video .......................... ≥240 lines

Audio............................................... Audio.................................................... Audio SP: Linear Audio ................. 80Hz - 10kHz (+/−6 dB)

Audio LP: Linear Audio.................. 80Hz - 5kHz (+/−6 dB)

Stereo FM Audio ............................ 20Hz - 20kHz (+/−3dB)

Euroconnector (AV1) SCART plug 1

Connection to TV, monitor, projection TV ... Pin 1 ARO (audio right out) 500 mV

Pin 2 ARI (audio right in) 0,2 V Pin 3 ALO (audio left out) 500 mV Pin 6 ALI (audio left in) 0,2 V Pin 7 Blue (out) **) Pin 8 Switching output: (with R

low: 2 V

+/- 3 dB R

rms

to 2V

rms

+/- 3 dB R

rms

to 2 V

rms

= 10kOhm, C

load

rms

1 kOhm

out

Rin 10 kOhm

1 kOhm

out

Rin 10 kOhm

< 2nF)

load

high: 9.5 V

rise time: 5 ms Pin 11 Green (out) **) Pin 15 Red (out) **) Pin 16 Blanking (out) **) loop through enabled during

standby, view-mode Pin 19 CVBS II (video out) 1 Vpp +1/-2dB R Pin 20 CVBS I (video in) 1 Vpp +3/-3dB Rin 75 Ohm

75 Ohm

out

**) passive loop through from AV2

Cinch Audio/Video input on front panel (OPTION)

Audio:

AINFR (audio right in) red 0.2 V AINFL (audio left in) white 0.2 V Input impedance 47 kOhm

to 2 V

rms

to 2 V

rms

typ. 500 mV

rms

typ. 500 mV

rms

rms rms

Video:

VFR yellow 1 Vpp + 3 / -3 dB Input impedance 75 Ohm

Cinch Audio Out Rear (OPTION)

AOUT1R (audio right out) red 500 mV AOUT1L (audio left out) white 500 mV

This outputs are in parallel with the corresponding outputs on Euroconnector 1.

+/- 3 dB R

rms

+/- 3 dB R

rms

1 kOhm

out

1 kOhm

out

Euroconnector (AV2) SCART plug 2

Connection to decoder, SAT tuner, video disc, 2nd VCR ....

Pin 1 ARO (audio right out) 500 mV Pin 2 ARI (audio right in) 0,2 V Pin 3 ALO (audio left out) 500 mV Pin 6 ALI (audio left in) 0,2 V Pin 7 Blue (in) *) Pin 8 Switching input only low: 2 V (low) Rin 10 kOhm

high: 4.5 V (high) R Pin 11 Green (in) *) Pin 15 Red (in) *) Pin 16 Blanking (in) *) loop through enabled during

standby, view-mode Pin 19 CVBS II (video out) 1 Vpp +1/- 2dB R Pin 20 CVBS I (video in) 1 Vpp +3/-3 dB Rin 75 Ohm *) passive loop through to Euroconnector AV1

+/- 3 dB R

rms

to 2 V

rms

+/- 3 dB R

rms

to 2 V

rms

rmsRin

1 kOhm

out

10 kOhm

1 kOhm

out

10 kOhm

10kOhm

75 Ohm

out

TUMOD

Modulator:

Frequency range loop through 45 MHz - 860 MHz Gain: ANT IN - TV OUT 2 dB + 3 / -2 dB

ANT IN - TUN OUT 2 dB + 3 / -2 dB Switch for RF input attenuation NO Frequency range out (tuned by IIC bus) Ch 21 - Ch55

Tuner: Frequency range 43 MHz - 860 MHz

for UK 450 MHz - 860MHz

Input voltage max. < 100 dBµV

min. > 60 dBµV

2-1

TOOLS FOR ERROR DIAGNOSIS

Replacement procedure for leadless components (chip)

The following procedures are recommended for replacing leadless components used in this unit.

1. Preparation for replacement

a. Soldering iron

Use a pencil-type soldering iron that uses less than 30W.

b. Solder

Use Eutectic solder (Tin 63%, Lead 37%)

c. Soldering time

Maximum 4 seconds.

Note: a. Leadless components must not be re-used after removal.

b. Excessive mechanical stress and rubbing of the component

electrode must be avoided.

2. Removing the leadless components

Grasp the leadless component body with tweezers and alternately apply heat to both electrodes. When the solder on both electrodes has melted, remove leadless component with a twisting motion.

Note: a. Do not attempt to lift the component off the board until the

component is completely disconnected from the board with a twisting motion.

3. Installation of leadless components

a. Presolder the contact points on the circuit board.

Presolder

Soldering iron

Fig. 2-2

b. Using tweezers press down the part and solder both electrodes as shown below.

Tweezers

Soldering iron

solder

Fig. 2-3

Note:

Do not glue the replacement component to the circuit board.

How to remove/install the FLA T PACK IC

1. How to remove the Flat Pack IC

• Using a hot air Flat Pack IC unsoldering equipment

b. Be careful not to break the copper foil on the printed circuit

board.

Tweezers

Chip

Soldering iron

Fig. 2-1

EXAMPLE

Fig. 2-4

2-2

a. Prepare the hot air Flat Pack IC unsoldering equipment. Then apply hot air to Flat Pack lC for 5 - 8 seconds.

b. Remove the Flat Pack lC with tweezers while applying the hot air.

CAUTION:

To avoid damage, do not apply the hot air to the chip parts around the Flat Pack lC for long periods.

C.B.A.

Masking

tape

Tweezers

Fig. 2-5

Put masking tape around the Flat Pack lC to protect adjacent parts.

2. The Flat Pack IC is fixed to the P.C.B. with glue; therefore take care not to break or damage any foil under the lC or on each pin when removing it.

Hot air Flat Pack

IC unsoldering

equipment

FLAT PACK IC

b. Lift up each lead of the Flat Pack IC individually, using a sharp pin or non-solder wire (iron wire), while heating the pins using a fine tip soldering iron or a hot air blower.

Sharp pin

Soldering iron

Fig. 2-7

• Using iron wire

a. Use unsoldering braid to remove the solder from all pins of the

Flat Pack IC. Apply solder flux to all pins of the Flat Pack IC, to allow easy removal.

b. Affix the wire to workbench or solid mounting point (see Fig. 2-8) c. Pull up the wire as the solder melts in order to lift the IC lead from

the P.C.B. contact pad, while heating the pins using a fine-tip soldering iron or hot air blower.

• Using a soldering iron

a. Use unsoldering braid to remove the solder from all pins of the

Flat Pack IC. Apply solder flux to all pins of the Flat Pack IC, to allow easy removal.

FLA T P ACK

Unsoldering

braid

Soldering iron

Fig. 2-6

Hot air

blower ...

Pull up gently

to remove

Fig. 2-8

Note:

When using a soldering iron care must be taken to ensure that the Flat Pack lC is not held by glue or the P.C.B. may be damaged if force is used. If the IC is glued, heat the IC with hot air to loosen the glue.

Solid mounting

point

Iron wire

... or soldering iron

2-3

2. How to install the FLA T PACK IC

a. Use unsoldering braid to remove the solder from the foil of each

pin of the Flat Pack lC on the P.C.B. in order to install the replacement Flat Pack IC more easily.

b. The “•” mark on the Flat Pack IC indicates pin 1. Make sure this mark matches the 1 on the P.C.B. when positioning for installation. Then pre-solder the four corners of the Flat Pack IC. (see Fig. 2-9).

EXAMPLE

Pin 1 on FLAT PACK IC is marked by a "•".

Fig. 2-9

Presolder

Soldering iron

C.B.A.

FLA T P ACK

V oltage measurements

Color bar signal in SP REC and PB modes.

Note:

Voltage indications for the REC. and PB mode on the schematic diagrams are shown below:

REC. and PLAY mode (Identical voltages for both modes).

PLAY mode REC. mode

Fig. 2-11

How to read wave forms

1 Connecting point 2 Amplitude 3 Time base 4 Operating mode of the VCR

Fig. 2-10

c. Solder all pins of the Flat Pack IC. Make sure that none of the pins have solder bridges between pins on the Flat Pack IC.

Note

All integrated circuits and many other semiconductor devices are electrostatically sensitive and therefore require the special handling techniques described in the “SAFETY INSTRUCTIONS” section of this manual.

Fig. 2-12

Voltage indication of Zener diodes

The Zener voltage of Zener diodes is indicated as such on schematic diagrams:

Example:

BZX79C20............Zener voltage: 20 Volts

2-4

How to identify connectors on schematic diagrams

Each connector is labeled with a connector number and a pin number indicating to what component it is connected; in other words, its counterpart.

Use the Connecting Wiring Diagram to find the connections between associated connectors.

Example:

The connections between C.B.A.s are shown below:

Connector no.

and Pin no.

on PCB

PCB to which this

connector is connected

Test point information

With this model, test pin or components leads are used as contact points for adjustment and checking. In case of other test points with no test pin or components leads, use the foil solder pad to connect the measuring equipment.

Removal or installation of flat cables

a. Removal

Pull out the flat cable, holding it securely to avoid damaging individual wires (see fig. 2-14).

Flat cable

PULL

Connector

Pin 1

Board

Fig. 2-13

Connector no. to which

the left connector is

connected

Fig. 2-14

b. Installation

1. Adjust the position of the flat cable so that the lines on the flat

cable align with the pins X of the trap connector (see fig. 2-14).

2. Align individual wires with its individual trap connector hole. Then insert the flat cable wire into the trap connector.

CAUTION: After installation, inspect the connection to insure that individual wires are not bent or touching other wires.

Dismantling instructions

2-5

General guidelines for dismantling housing components, electronic parts and the drive mechanism

Always disconnect from mains before dismantling or assembly.

Due to the supply voltages (hot circuit) on the primary side of the switched-mode power supply, an isolating transformer is required for the operation of the device.

The drive or the drive/motherboard unit must not be pulled out by the cross struts!

Components placed below the tape deck has to be inserted exactly.

The use of a regulating isolating transformer is recommended for detecting faults around the power supply.

All screws of the video recorder can be removed or tightened with a 10* torx screwdriver .

1. Housing cover (Fig. 1)

- Remove the four screws (A).

- Push catch (S) inwards, lifting lid at the same time to move out of groove.

- Slide housing cover back by approx. 1 cm.

- Push centre of housing cover sides on underside approx. 1 cm outwards and lift up the housing cover.

Assembly

Assemble in reverse order.

Fig. 1

2. Base plate (Fig. 2)

The base plate may not be removed from the frame!

3. Front panel (Fig. 2)

Preparation

Dismantle the housing lid as described in section 1.

- Position the device with the base plate facing upwards.

- Undo the six catches (S) one after the other, starting from the left or the right.

- Remove the front panel by pulling it forwards.

- For devices with shuttle print or socket print, disconnect the cabling to the motherboard.

Assembly

Assemble in reverse order (device in operational position).

Important

- The lift flap lever should be connected to the lift flap guide.

- Check that all catches are engaged.

Fig. 2

* …available from dealers

2-6

4. Dismantling of the motherboard/drive combination (Fig. 3) (Fig. 4)

Preparation

Remove the housing cover as described in section 1. Remove the front panel as described in section 3.

- Move device into operational position (Fig. 3).

- Undo the two screws (B) of the stay and pull it up to remove it.

- Push back the lift by 5 cm after releasing both lift stops.

- Undo and remove the four fastening screws (C) of the drive.

- Detach the Cinch socket cable (K) and ground cable (M) from the socket print (if present).

- Remove the cables (K1; K2; K3) from the guides on the rear of the frame.

- Pull the Cinch socket holder with the socket and print up and out of the frame (if present).

- Position the device with the base plate facing up.

- Undo the 8 catches (S) from the rear right to the rear front and then from the rear left to the front left.

- After the weight of the motherboard/drive unit has released it from the frame, the catch (S) at the mains socket has to be released for a second time.

- The frame can be removed by lifting it off.

- Turn the motherboard/drive unit and move it into the service position (Fig. 5), if necessary. The device is operational in this position

”Eject” must NOT be used !!!

M/K

C K2 K3

C C B

Lift protection

Caution:

Adjustments can not be made in the service position.

”Eject” must NOT be used !!!

Assembly

- Position the frame with the top open onto a level surface.

- Hold the drive on the side at the lift and insert the motherboard/ drive unit into the frame, pushing it down lightly. Observe that the power supply and Scart sockets are positioned in openings.

- Check that all 8 catches (S) are engaged.

- Secure the drive with the four holding screws (C).

- Move the lift into the ”Eject” position.

- Push the stay onto the frame with the chamfered side facing to the rear and secure with both screws (B).

- Insert the Cinch socket into the opening and ensure that it engages.

- Connect the Cinch socket and the ground cable (K ; M) (if present).

- Insert the cables (K1; K2; K3) into the supports provided in

the frame.

- Replace the front panel and the housing cover.

Fig. 3

Fig. 4

5. Dismantling the drive (Fig. 3)(Fig. 5)(Fig. 6)

Preparation

Remove the housing cover as described in section 1. Remove the front panel as described in section 3.

- Undo the two screws (B) of the stay and pull it up to remove it.

- Push back lift by 5 cm after releasing both lift stops.

- Undo and remove the four fastening screws (C) of the drive.

- Undo and remove the ground screw (D) at the rear. (For this purpose, insert the screwdriver through the hole in the back panel).

- Remove the cables from the drive.

- Bend back the guard of the scanner cable.

- Remove the scanner cable from the socket.

- Return the lift into the ”Eject” position.

- Slightly lift the left rear side of the drive to undo the connector to the capstan motor.

- Press both catches (S) together with fine pliers and lift the drive around the snapholders.

- The drive may be separated from the motherboard.

Assembly

Assemble in reverse order.

Important

Observe that the cables (K1; K2; K3) are positioned in the supports on the rear of the frame and that the ground screw (D) is screwed in!

Fig. 6

2-7

Fig. 5

Service position

2-8

Circuit descriptions

1. Switched-mode power supply PS (PS Part) ................................................................................................................................................9

1.1 Technical data:................................................................................................................................................................................................9

1.2 Functional principle: .......................................................................................................................................................................................9

1.3 Supply voltage part.........................................................................................................................................................................................9

1.4 Start-up with Mains-on: ..................................................................................................................................................................................9

1.5 Normal mode: .................................................................................................................................................................................................9

1.6 Overload, power limitation, burst mode: ......................................................................................................................................................10

1.7 Standby mode: .............................................................................................................................................................................................10

2. Operating unit DC (DC part) ........................................................................................................................................................................10

2.1 Evaluation of the keyboard matrix................................................................................................................................................................10

2.2 IR receiver and signal evaluation .................................................................................................................................................................10

2.3 Activation and function of the VFD display ..................................................................................................................................................10

3. Central Control AIO (AIO part) .................................................................................................................................................................... 11

3.1 Analogue interface to the µC:.......................................................................................................................................................................11

3.2 Tape end - LED control : ............................................................................................................................................................................... 11

3.3 CMT detection (video detection with CSYNC) ............................................................................................................................................. 11

3.4 EE-PROM ..................................................................................................................................................................................................... 11

3.5 Easy link (P50) .............................................................................................................................................................................................11

3.6 Shuttle: .........................................................................................................................................................................................................11

3.7 Satmouse...................................................................................................................................................................................................... 11

4. Deck electronics DE (DE part) ....................................................................................................................................................................11

4.1 CTL stage .....................................................................................................................................................................................................11

4.2 Power on reset (POR) generator ................................................................................................................................................................. 12

4.3 The sensor interface :...................................................................................................................................................................................12

4.4 Interface to the head drum motor driver part ............................................................................................................................................... 12

4.5 Interface to the loading motor driver part:....................................................................................................................................................12

4.6 Interface to the capstan motor .....................................................................................................................................................................12

5. Front end FV (FV part) .................................................................................................................................................................................13

5.1 The front end comprises the following parts : ..............................................................................................................................................13

5.2 The front end has been designed to receive the following systems:...........................................................................................................13

5.3 Tuner modulator (TUMOD) ...........................................................................................................................................................................13

5.4 IF selection ...................................................................................................................................................................................................13

5.5 IF demodulator .............................................................................................................................................................................................13

5.6 Audio demodulator .......................................................................................................................................................................................13

6. Video signal processing VS (VS part) ........................................................................................................................................................13

6.1 Switchover functions in the signal electronics IC LA71595M [7004]: ..........................................................................................................13

6.2 Recording : ...................................................................................................................................................................................................14

6.2.1 Luminance .................................................................................................................................................................................................14

6.2.2 Chrominance PAL......................................................................................................................................................................................14

6.2.3 MESECAM ................................................................................................................................................................................................14

6.2.4 SECAM L ...................................................................................................................................................................................................14

6.2.5 FM signal ...................................................................................................................................................................................................14

6.3. Playback: ..................................................................................................................................................................................................... 15

6.3.1 FM signal ...................................................................................................................................................................................................15

6.3.2 Luminance .................................................................................................................................................................................................15

6.3.3 Chroma PAL ..............................................................................................................................................................................................15

6.3.4 Chroma MESECAM...................................................................................................................................................................................15

6.3.5 Chroma SECAM L .....................................................................................................................................................................................15

6.3.6 NTSC .........................................................................................................................................................................................................15

6.3.7 PAL M,N.....................................................................................................................................................................................................15

6.4 General .........................................................................................................................................................................................................15

7. Audio linear (AL part)...................................................................................................................................................................................16

7.1 Audio I/O for the 1-scart version...................................................................................................................................................................16

7.2 Audio I/O for the 2-scart version...................................................................................................................................................................16

7.3 Audio linear recording...................................................................................................................................................................................16

7.4 Audio linear playback....................................................................................................................................................................................16

7.5 Audio linear muting.......................................................................................................................................................................................16

8. Audio HiFi - for stereo units (AF part)........................................................................................................................................................16

8.1 General .........................................................................................................................................................................................................16

8.2 Audio I/O .......................................................................................................................................................................................................16

8.3 Audio HiFi recording .....................................................................................................................................................................................16

8.4 Audio HiFi playback......................................................................................................................................................................................16

8.5 Interface to the audio linear..........................................................................................................................................................................16

9. IN/OUT (IO part) ............................................................................................................................................................................................17

9.1 Video:............................................................................................................................................................................................................17

9.1.1 Audio for the 2-scart version: ....................................................................................................................................................................17

9.2 Decoder mode: (REC or STOP)...................................................................................................................................................................17

9.2.1 Program position with decoder (front end)................................................................................................................................................17

9.2.2 External input with decoder .......................................................................................................................................................................17

10. Follow Me (FOME part) ..............................................................................................................................................................................17

11. VPS/PDC, on-screen display (VPO part) ..................................................................................................................................................17

11.1 VPS/PDC ....................................................................................................................................................................................................17

11.2 OSD-PART..................................................................................................................................................................................................17

2-9

1. Switched-mode power supply PS (PS Part)

1.1 Technical data:

Mains voltage: 195-264 V Maximum output: 15W / 40W (continuous / maximum output) Operating frequency:40 kHz Efficiency: approx. 75 % at maximum output

Six different direct voltages are supplied on the power supply outputs.

1.2 Functional principle:

This power supply functions in a similar way to a blocking oscillator. In the supply voltage part [1300 to 2318], the mains voltage is rectified and buffered in the capacitor [2318]. From this direct voltage [2318] energy is transferred into the transformer [5301, pins 1-3] during the conductive phase of the switching transistor [7302] and is stored there as magnetic energy. This energy is passed to the secondary outputs on the power supply in the in the blocking phase of the switching transistor [7302]. With the switchon time of the switching transistor [7302], the energy transferred in every cycle is regulated in such a way that the output voltages remain constant regardless of changes in the load or input voltages. The power transistor is activated using the integrated switch [7303] Fig.1.

1.3 Supply voltage part

The supply voltage part extends from the mains socket [1300] to the capacitor [2318]. Using the diodes [6310, 6311, 6312 and 6313] the a.c. supply voltage is rectified and buffered using the capacitor [2318]. The line reactor [5305] and capacitor [2316] create a filter to keep interference arising in the power supply away from the mains. Components [1302], [3326] and [3323] protect the power supply against short-term overvoltages in the mains, e.g. caused by indirect effects from lightning.

MC44608

start - up phase

200 µA

ISENSE

start - up management

Vcc management

switching phase

stand - by

200 µA

leading edge blanking

rms

3318

C demag

latched off phase

start up phase

stand - by management

65mV/45mV

PWM comp

DEMAG

current mirror

Fig. 1

OVP - out

1.4 Start-up with Mains-on:

Following connection to the mains, the capacitor [2310] is loaded via the start-up resistor [3318] and a current source between pin 8 and pin 6 on the IC [7303]. Once the voltage on [2310] and therefore the supply voltage Vcc on the IC [7303] has reached approx. 13V, the IC starts up and issues pulses to its output on pin

5. These pulses are used to control the gate on the power transistor [7302] (see Fig.2). The frequency has a fixed setting in the IC (approx. 40 kHz). The current input on the IC is approx. 5 mA in normal mode. If Vcc drops to below approx. 10V (e.g. with power limitation) or if Vcc exceeds around 15V (interruption of the control loop), the output on the IC [7303, pin 5] is blocked. All output voltages on the power supply, and therefore also Vcc, decrease. Once Vcc has dropped to below approx. 6.5V, a new start-up cycle begins. (See also “Overload, Power Limitation, Burst Mode“ section)

1.5 Normal mode:

With the power supply in normal mode, the periodic sequences in the circuit are divided primarily into the conductive and blocking phase of the switching transistor [7302]. During the conductive phase of the switching transistor [7302], current flows from the rectified mains voltage to the capacitor [2318] through the primary coil on the transformer [5301, pins 1-3], the transistor [7302] and resistors [3314, 3331] to earth (see Fig.1). The positive voltage on pin 1 of the transformer [5301] can be assumed to be constant for a switching cycle. The current in the primary coil on the transformer [5301] increases linearly in the pattern of U=L*di/dt. A magnetic field representing a certain volume of the primary current is formed inside the transformer. In this phase, the voltages on the secondary coils are polarised in such a way that the diodes [6300, 6301, 6306, 6308 and 6309] block. From the controller on [7301], a current is supplied to the CTRL input on the IC [pin 3, 7303] via optocoupler [7300]. Once the switch-on time for the switching transistor [7302] has been reached, which corresponds to the current supplied on the CTRL input, the switching transistor is switched off. Once the switching transistor has been switched off, the blocking phase begins. No more energy will be transferred into the transformer. The inductivity of the transformer will still attempt to maintain the current which has flowed through it (U=L*di/dt) at a constant level. As the primary current circuit is interrupted by the shut-off switching transistor [7302], the current will flow through the secondary coils.

current and voltage

quick OVP

PWM latch

stand by

UVL01

references

output

buffer

DRIVER

VCC

GND

CTRL

7300

6307

3314

7302

6304

6305

2310

regulation block

200 µA

thermal shutdown

latch OFF phase

5301

2-10

The polarity of the voltages on the transformer is reversed, which means that the diodes [6300, 6301, 6306, 6308 and 6309] become conductive and current flows into the capacitors [2301, 2305, 2309, 2311 and 2312] and the load. This current is also ramp-shaped (di/ dt negative, therefore decreasing). The control adjustment for the switched-mode power supply is made by changing the conductive phase of the switching transistor (see Fig.2), so that either more or less energy is transferred from the rectified mains voltage to [2318] in the transformer. The control information is provided by the control element [7301]. This element compares the 5V output voltage via the voltage dividers [3300, 3306, 3336] with an internal 2.5V reference voltage. The output voltage from [7301] passes via an optocoupler [7300] (for the metallic isolation of the primary and secondary parts) as the current value to pin 3 on the IC [7303]. The switch-on time for the switching transistor [7302] is inversely proportional to the value of this current.

1.6 Overload, power limitation, burst mode:

With an increasing load on one or more power supply outputs, the switch-on time for the power transistor [7302] also increases, and thus also the peak value of the delta-shaped current through this power transistor. The equivalent voltage circuit for this current profile is passed from resistors [3314] and [3331] via [3312] and [3347] to pin 2 on the IC [7305]. If the voltage on pin 2 reaches 1V in one switching cycle, the conductive phase of the switching transistor is ended immediately. This check is made in each individual switching cycle. This process ensures that no more than approx. 48W can be taken out of the mains ( = power limitation ). If the power supply reaches the power limit, the output voltages and the supply voltage Vcc on pin 6 of the IC [7303] will be reduced following further loading. If Vcc is less than approx. 10V at any point during this process, the output on the IC [7303, pin 5] is blocked. All output voltages and Vcc are reduced. Once Vcc has dropped to below approx. 6.5V, a new start-up cycle begins. If the overload status or short-circuit remains, the power limitation will be activated immediately and the voltages will continue to be reduced, followed by another start-up attempt ( Burst Mode ). The amount of power taken up from the mains in burst mode is low.

1.7 Standby mode:

In the ‘Standby‘ operating mode on the device, the ’STBY‘ control line is used to shut off the output voltages 14AL, 5VA and 5VD on the power supply to minimise the amount of power taken up from the mains. The supply to the display heating can also be switched off using the ‘I1WSTBY‘ control line. The power supply itself will continue to function continuously in the ‘Standby‘ operating mode with a switching frequency of 40kHz.

= UGS

Dmax

point of reversal

UDS

Fig. 2

2. Operating unit DC (DC part)

The microcontroller TMP93CT76F [7899-A] is a 16 bit microcontroller fitted with 128Kb ROM and 2.5Kb RAM. It is the core element of the operating unit, fulfilling the following tasks with the respective functional groups:

• Integrated VFD driver

• Timer

• Evaluation of the keyboard matrix

• Decoding the remote control commands from the infra-red

receiver pos. 6170

• Activation of the display

• Back-up mode

In normal operation, the µP is operated in dual-clock mode, i.e. both quartzes [1170, 1171] oscillate. The time is derived from the slow quartz [1170] (32.768 kHz), and the fast quartz [1171] (16MHz) is used to generate the system clock frequency. In case of a mains failure (back-up mode) the µP is not reset, but instead the mains failure is registered by the IPOR interrupt 3 [7899-B] (pin 67) and the µP is moved into “Sleep mode” (low power consumption). The 16MHz quartz is turned off and the 32kHz quartz is then used as the clock and system clock frequency. The operating voltage for the AIO is buffered by a back-up cell [pos. 2174, 2172]. A diode [6171] prevents this gold capacity from discharging.

2.1 Evaluation of the keyboard matrix

There are 12 different keys. Each key function is assigned a fixed voltage value. This value is decoded using an analogue/digital (A/ D) port (7899-B, pin 56). Each mechanical key position on the printed board can adopt any key function via a coding resistor. Pressing keys simultaneously may lead to undesired functions!

Schematic:

10K

DC-KEY [7899-B, pin56]

100K

2.2 IR receiver and signal evaluation

The IR receiver [6170] includes a selective, controlled amplifier in addition to a photo-diode. The photo-diode changes the received transmission (approx. 940nm) in electrical pulses, which are then amplified and demodulated. On the output of the IR receiver [7220] a level lift 0V/5V pulse sequence, which corresponds to the envelope curve of the received IR remote control command, can be measured. This pulse sequence is input into the controller for further signal evaluation via input IRR [7899-B, pin 46].

2.3 Activation and function of the VFD display

In principle, the VFD display [7170] is a tube triode in which the heating filaments in the tube serve as cathodes (F+,F-). The 7 grids (G1 - G7) are activated via PC2 - PC7, PD0 on the controller, and the 16 anodes (P1 - P16) are controlled via ports PE0 - PE7, PF0 PF7, PC0, PC1 on the controller, each with a positive potential compared to the cathode. The grids and anodes (digits and symbols to be displayed) are activated in the time-multiplex procedure, voltage lift 5V/-18V. A dimmer function is generated using pulse-width modulation of the grid control signals. At maximum display brightness, the pulse width for each grid is 2.16 ms. It can be reduced, controlled using software, which reduces the visual brightness of the VFD display accordingly. A digit or symbol is only illuminated if the corresponding anode and the surrounding grid are switched simultaneously to 5V for a certain time within a scanning period. The electrons emitted from the cathode are accelerated by the positively charged grid and hit the luminous layer of the anode which is also positively charged.

T C

27K

47K

18K

12K

8K2

C JE

R O

5K6

3K9

IT N

1K2

2K2

470E

ILL T S

W O

2-11

During the remainder of the scanning period, the corresponding grid and parts of the anode are at -18V, due to the internal pulldown resistors in the controller. This potential is still lower than the average cathode potential of approx. -15V, prevents the acceleration of electrons, thus causing the relevant grid and anode segments to go dark. The heating direct voltage of the display (U = 3.5V) is supplied from the power supply via lines HELO or HEHI to pins F+ and F- to the VFD display. Resistors [3070] and [3071] restrict F- to approx. 15V.

3. Central Control AIO (AIO part)

The microcontroller (µC) TMP93CT76F [7899-B] includes the following functions:

• PWM outputs

• A/D converters

• Composite sync input

• Special servo inputs for VCR functions

• I²C-BUS interface

• Shuttle evaluation

3.3 CMT detection (video detection with CSYNC)

This has been extended due to identification problems with weak transmission signals and video signals not conforming to the STANDARD (common channel interference). The CSYNC line is supplied to the µP [7899-B] on pin 50. A hardware integration [7807,7808,7809] of the video pulse compensates the interference generated by the common channels and weak signals.

3.4 EE-PROM

The EE-PROM [7818] is a non-volatile memory which can be erased and written to electrically. (Data remains even if the operating voltage fails). Data specific to the device such as the X distance, head changeover position, preset stations, optional bytes etc. is stored in the EE-PROM [7818]. The data is accessed by the µP via the I²C bus.

3.5 Easy link (P50)

For the communication between the TV set, video recorder and the peripheral devices, a bi-directional single-wire bus is used, which runs via pin 10 to scart socket 1. The output signal is generated on pin 84 of the µC [7899-B], pin 68 is the signal input.

3.6 Shuttle:

The shuttle is connected to the motherboard on plug pos.1982. It is a binary coded rotary switch with a rotation angle of +/- 70 degrees and 16 switch positions. These are input and evaluated via four lines (shuttle b1 – shuttle b4) to the input ports P24 – P27 [7899B pins 2-5].

3.1 Analogue interface to the µC:

The following analogue levels are supplied to the µC’s internal analogue/digital (A/D) converter:

• TAE/TAS Tape End / Tape Start Detection

• TRIV Tracking Information Video

• TRIA Tracking Information Audio

• AGC Automatic Gain Control

• AFC Automatic Frequency Control

• 8SC1/2 Pin 8 Scart1 or Scart2 switching voltage

• Key-in Keypad evaluation

3.2 Tape end - LED control :

The LED current is switched using transistor [7804]. The ON time is approx. 1 msec and the OFF time approx. 12 msec during playback and 1msec to 5.5msec during the winding functions. The LED current is typically 150 mA. In order to prevent interference from the relatively high pulsed current ‘spreading’ through the entire unit, the LED is fed from the 14VM1, and filtered by 2 resistors [3800, 3805] with 10R each and a 220µF electrolytic capacitor [2803].

3.7 Satmouse

For activating a sat-receiver via an external infrared electronic transmission unit (Satmouse) a bi-directional data line, a shortcircuit proof +5V and earth are provided via a 3-pin 3.5mm jack [1941]. The +5V is limited to approx. 140 mA using a current limiting switch [7812 and peripherals].

4. Deck electronics DE (DE part)

The deck interface IC MP63100FP [7463] contains the following functional groups:

• CTL stage (tape synchronisation)

• Sensor interface

• Power on reset

• Head drum motor driver

• Loading motor driver

• Capstan motor control

4.1 CTL stage

The IC M63100FP [7463] contains a read/write stage for the CTL track with the option of overwriting an existing CTL track without any interference. The playback stage is fitted with a “digital” fivestage AGC. This logic circuit identifies the size of the output signal supplied by the CTL head, and then selects the best amplification ratio in the playback stage using comparators. The CTL head voltage can therefore vary greatly, if Vmax / Vmin is great. The slowest tape speed is in LP mode. The fastest speed is adjusted during rewind. To ensure that the duty cycle in the tape sync is always reproduced correctly in the conditions mentioned above (important for detecting VISS marks), the amplifier must not be overdriven. The five-stage AGC alone cannot cover the large dynamic range of the input voltage. The amplifier is therefore also equipped with a low pass characteristic (fg = 3kHz typ.; internal).

2-12

In parallel with the CTL head is the RC cell comprising capacitor [2479] and resistor [3471]. The capacitor [2479], together with the CTL head inductivity, causes a resonance step-up at around 10 kHz and the resistor [3471] suppresses this step-up. This creates an aperiodic transient response in the resonance. Beyond the resonance frequency , there is an adjustment in terms of a steep fall in the frequency transmission characteristic. This effectively suppresses high-frequency pick-ups. The CTL head signal amplitude in standard play is around 1mVp (typ.) which means that the amplification for the playback amplifier must be correspondingly high. To avoid offset problems, a 100 µF electrolytic capacitor [2490] is fitted in the negative feedback branch for DC decoupling. The polarity of the playback amplifier can be changed using the Video Index Search System (VISS) voltage. This is the only way in which the µP can write a VISS mark on the tape without spikes. The Write/Read (W/R) signal is used to switch over between record and playback: W = “H“, R = “L“.

4.2 Power on reset (POR) generator

The POR generator contained in the M63100FP [7463] requires only one external capacitor [2477], which specifies the length of the POR pulse. For 33 nF, tPOR is approx. 30ms. The response threshold of the reset circuit is between 4.5 and 4.8 V. Supply fluctuations which are shorter than tPOR/100 area and which do not fall below 4.0 V, do not trigger the POR. The µP is reset using the inverted POR.

4.3 The sensor interface :

The four comparators in the M63100FP [7463] are used to convert sensor signals to the logic level. The outputs are overload protected by a current limiter and thermal overload protection. Only the non-inverting input on each comparator is accessible from the outside. The other inputs are connected to an internal reference of

2.5V. The fixed hysteresis of the comparators of approx. 18 mV is also located internally.

The comparators are connected as follows:

Comparator 1: In = FTA, pin 39; Out = FTAD, pin 34:

FTA

= threading tachometer. This signal comes from a forked light barrier in the deck. An infra-red light beam is interrupted by a 4blade impeller (butterfly). The output amplitude for the light barriers should be less than 2V for the low level and greater than 3V in the high level to ensure a correct evaluation process. An additional hysteresis is created with a resistor [3476]. For unit versions <1W and FOME the external operation amplifier [7530B] is used to reduce the power consumption in <1W mode.

Comparator 2: In = WTR, pin 38; Out = WTRD, pin 33:

WTR

= Winding tachometer right, from a reflection photoelectric

barrier. The level is the same as for the FTA. Comparator 3: In = WTL, pin 37; Out = WTLD, pin 31 :

WTL

= Winding tachometer left, from a reflection photoelectric

barrier. The level is the same as for the FTA. Comparator 4: In = FG, pin 35; Out = FGD, pin 30:

= capstan tachometer. This signal stems from an amplifier for the tachometer hall sensor on the motor unit [1946 pin 4]. The output impedance is 10 kOhm. The amplitude of the virtually sinusoidal signal is normally 1 Vp. It should not fall below 300 mVpp. It is AC-coupled via a capacitor [2485]. In order for a bias current to flow, the input pin 31 must be passed via a resistor [3474] to the reference voltage on pin 4. A capacitor [2480] for filtering out high-frequency interference is arranged in parallel to the bias resistor.

4.4 Interface to the head drum motor driver part

The head drum control voltage (speed and phase control information) is output via a µP-output (7899-B pin 35; PWM 14-bit). This pulse-wide modulated signal is fed to the motor driver IC M63100FP [7463 pin 11] and integrated with the capacitor [2469]. This IC already has a completely integrated ‘start-up’ circuit fitted. For the commutation, the head drum motor driver uses the e.m.f. on the non-current carrying motor coil (transformer principle). The motor speed is also discharged from there at the same time. The phase of the head disc is discharged from a position coil. The speed and phase are multiplexed into one signal [7463 pin 6] and output, which means that the falling edge of the signal is available with a positive edge for the speed (FG/450Hz) and at 25Hz for the position pulse (PG). The motor driver M63100FP [7463] is connected to the head drum motor on the motherboard using plug [1948].

• DRUM is the speed-phase control signal. The resolution is 14 bit.

• PG/FG is the combined POS/tachometer signal from the M63100FP [7463].

4.5 Interface to the loading motor driver part:

The loading motor driver part is constructed for use as a bridged dual power operations amplifier (OPAMP). It can supply max. +/-

0.8A output current. The output current is limited to approx. 0.7A by

the internal resistance of the loading motor (18 Ohm typ.) (start-up or motor is blocked). Between the IC outputs [7463, pins 22 and 24] there is a “Boucherot” circuit [3467] 1E, [2474] 100 nF for suppressing a spurious 3MHz oscillation from the output stage. One half of the bridge is controlled via the TMO line on pin 27 and acts as a comparator. The other half is an amplifier integrator with a 3.9 gain. A change in the input voltage (THIO) of between 0 and 5V on pin 25 results in a change in the output voltage of between 0V and almost Ub. With 50% modulation (THIO = 2.5 V) pin 24 has approx. 7 V. The 100nF capacitor [2473] in the negative feedback of the op-amp filters out the PWM frequency of approx. 39kHz. During POR, the µP issues “L” to the THIO line, whilst TMO is “H”. This ensures that no current flows in the motor for the duration of the POR pulse. This prevents the motor being destroyed in case of prolonged running or blockage. This arrangement also has a disadvantage, however. This is that if the 5 V supply fails (e.g. because the 5V fuse has blown), residual voltages may be passed to the IC inputs via the adjacent 14 V voltages. These residual voltages trigger the comparator and the op-amp in opposite ways, causing a shortcircuit in the blocked loading motor after about a minute. To get around this problem, a separate voltage divider is used internally for the comparator. Both outputs on the M63100FP [7463] are then in “common mode” if this error occurs.

4.6 Interface to the capstan motor

The driver IC on the capstan motor is activated via connector [1946]. CAP is the signal for the capstan speed. This voltage may vary without load between 0 and 5 V. The rotational direction of the motor is determined using CREV (capstan reverse). The maximum current input for the motor is limited to 1A. Typical values in PLAY mode are 0.2 ... 0.3 A.

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5. Front end FV (FV part)

5.1 The front end comprises the following parts :

• TUMOD = Tuner (+ Modulator Option) (+Booster Option) (+Passive Loop Through Option)

• IF amplifier & video demodulator IC TDA 9817, [7705] with FM

- PLL demodulator

• IF amplifier & video demodulator IC TDA 9818, [7705] with FM

- PLL and AM demodulator

• FM stereo decoder TDA 9873 [7760]

• Multi-standard FM stereo, AM, NICAM decoder MSP3415D

[7761]

5.2 The front end has been designed to receive

the following systems:

• PAL B/G with FM stereo

• PAL 1 or PAL BG with NICAM stereo

• PAL BG with NICAM and FM stereo

• PAL BG/I SECAM L/L’ with NICAM and FM stereo

• PAL BG SECAM DK with NICAM and FM stereo

• PAL B/G =/01,/02/16

• PAL I =/05 Pal I with UHF reception

• PAL I Ireland =/07 Pal I with VHF/UHF reception

• SECAM L,L‘, PAL BG/I =/39

• PAL B/G, SECAM DK =/58

The relevant layout is given in the version list on the circuit diagram.

5.3 Tuner modulator (TUMOD)

The tuner and modulator are fitted into the same housing. Both the tuner and the modulator are PLL-controlled. The reception frequency or modulator frequency is set using the IIC bus. The amplification is determined by the AGC voltage at pin 5 [1701] (for operation, see IF demodulator section).

5.4 IF selection

The IF frequency of the video carrier is 38.9 MHz for all systems except SECAM L’ (33.9 MHz). For PAL BG-SECAM DK and for PAL BG/I-SECAM L/L´ a quasisplit audio system is used; i.e. for video and audio carriers, separate surface-wave filters (OFW) are required [1704, 1703]. For all other standards an intercarrier system is used; i.e. a common OFW with audio stair-step can be used [1704] for video and audio carriers. For the PAL BG/I-SECAM L/L’ version, an additional circuit for suppressing the adjacent channel audio carrier is provided, which is set using coil [5704] to maximum suppression at 40.4MHz.

5.5 IF demodulator

TDA 9818

The IF signal from the tuner is processed by another demodulator IC of type TDA 9818 [7705]. The TDA 9818 is used to demodulate pos. or neg. modulated video carriers. It is possible to generate a QSS-audio-IF signal or an intercarrier IF signal for demodulation in the audio demodulator [7761]. For the best possible video signal performance the IF signal is conveyed via an OFW [1704] according to the standard. The audio-IF carrier is selected in the audio OFW [1703] which is switched for SECAM L’. The output signal for this OFW is further processed in the TDA 9818. FM carriers are converted from the IF level into the audio IF position and further processed in the audio demodulator. The AFC coil [5702] on the TDA 9818 is adjusted so that when a frequency of

38.9 MHz is supplied to the IF output of the tuner, the AFC voltage

on pin 17 on the TDA 9818 is 2.5V. The setting of the picture carrier frequency for SECAM L in the TDA 9818 is achieved by connecting pin 7 of the IC via a potentiometer [3730] to earth. The AFC voltage on pin 17 TDA 9818 should then also be 2.5V at 33.9 MHz. The HFAGC is set using the AGC controller [3707] so that with a sufficiently large input signal (74 dBµV), the voltage at the IF output on the tuner [1701, pin 17] is 550 mVpp. The setting must be carried out when the audio carrier is switched off. The demodulated

video signal appears on pin 16 [7705]. The video drop [1705] reduces adjacent channel sound carrier and sound carrier remainders in the video.

TDA 9817

As for TDA9818, without the option for processing AM audio and positive video modulation (SECAM L,L’).

5.6 Audio demodulator

Multi-standard audio processor MSP 3415D

The MSP 3415D [7761] is a multi-standard sound processor which can demodulate FM Mono/Stereo, NICAM and AM signals. The incoming signal is first controlled and then digitised. The digital signal is then demodulated in 2 separate channels. In the first MSP channel, FM and NICAM (B/G/I/D/K) are demodulated, whereas in the second MSP channel, FM and AM is demodulated again (NICAM L corresponds to NICAM B/G). These demodulated signals are selected digitally in the I/O and switched to the D/A converter on the outputs. Amplitude and bandwidth of the demodulated audio signals can be determined in the MSP using the corresponding commands via the I2C bus. This means that the setting required for the best possible performance can be made.

FM stereo audio decoder TDA 9873

The TDA 9873 [7760] is a multi-standard A2 audio processor which can demodulate FM mono/stereo signals. The audio IF SIF2 is passed from pin 3 [7705] to pin 25 [7760]. The demodulated stereo signals AFL and AFR I2C bus are available controlled on pins 1 and

6. Video signal processing VS (VS part)

6.1 Switchover functions in the signal electronics IC LA71595M [7004]:

The signal electronics IC LA71595M [7004] are controlled via the I2C Bus on pins 23 and 24 by the AIO. As groups 5 and 6 can only be transferred with a change in HP1, it must be ensured that during measurements the HP1 line is always connected to the SE IC or replaced by a corresponding signal.

REC/PB via IIC bus

During RECORD pin 30 must be passed via [7009] on 5V (IREV=LOW) to activate the video write current stages. T o keep the transient condition of the write current as short as possible, the signal electronics IC is set to REC via IIC bus before the pin 30 change.

PAL/SECAM/MESECAM/NTSC via IIC bus

SP/LP/SLP via IIC bus

VIDEO INPUT SELECTOR SWITCH via IIC bus

In 1-scart units a distinction is made via the IIC bus between VFV (pin 36 / VID2) and VBS which corresponds to VIN1 (pin 38 / VID1). In 2-scart units the video input selection is made via IIC bus in the STV6401 [7904] and the SE IC is always on VBS (pin 38 / VIN1).

VIDEO ENTRY

The feature frame pulse FFP signal on pin 26 is used to enter the artificial picture pulse for playback features and the test picture for the unit installation procedure:

Loop through < 0.8V Test picture = 1.2 ... 3.8V Artificial picture pulse > 4.2V

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LP/SP head pair switchover

The switchover between the long play LP head pair and the standard play SP head pair is made via the HSC signal (pin 25). 4/x scanner in play back:SP head pair: 0V <= HSC <= 0.8V

LP head pair: 1.2V <= HSC <= 2.8V

2/x scanner in play back: always 3.2V <= HSC <= 5V

Head switchover

The video head switchover is made using the HP1 signal (pin 11). To keep audio linear interference as low as possible, the HP1 polarity should be selected to be inverse and the HP1 level should be the same as the CROT signal on pin 10. PB: SP1 / LP1: 1.2V <= HP1 <= 2.8V

SP2 / LP2: 0V <= HP1 <= 0.8V

Envelope curve comparator

If the ENVC signal (pin 94) is HIGH, the FM envelope curve on the LP head is greater than that on the SP head, and vice versa.

6.2 Recording :

6.2.1 Luminance

The input signal (1-scart: pin 38 = scart , pin 36 = front end; 2-scart: pin 38 = input video selected using STV6401) is connected in the IC [7004] and is available uncontrolled on pin 32 as VREC (SECAM; VPS only unit data slicers). It reaches pin 31 via an electrolytic capacitor [2036]. In the IC [7004] the video signal first goes through an amplification control process (time constants determined by C [2035]). After the AGC the video signal reaches the FBC clamping stage (feed back clamp), then the video signal is divided onto 3 paths:

• Loop-through signal path: The video signal is amplified by 6dB following video entry and is available controlled on pin 29 as a VSB signal (OSD entry, data slicer -> I/O, front end,..).

• Y-REC path: The video signal passes via a 3.5 MHz low pass filter to vertical emphasis comprising the YNR block (part of this circuit block is used in REC for vertical emphasis) and a 1H-CCD delay line integrated into the SE IC [7004-C] and an external emitter follower [7006]. This vertical emphasis can be switched via IIC and is only active in LP. The Y-signal before the 1H-CCD can be measured on pins 43 and 45 on the IC [7004-C] (separated only by a coupling electrolytic capacitor). The Y-signal after the 1H-CCD is passed back from pin 46 IC [7004-C] via the E-follower [7006] on pin 41 IC [7004]. After the vertical emphasis the Y-signal passes via pin 21 [7004], the E-follower [7008] (the filter, on the base of the emitter follower is not active in REC mode (due to the low resistance of the output stage on pin 21 [7004]), via pin 21 [7004] and a clamping stage to the detail enhancer. The Y-signal is then passed to the non-linear emphasis, the linear emphasis (time constant via pin 18, 19 – due to the low resistance of the pin 18 output stage and the transistor [7010] introduced for impedance decoupling, the FM PB all-pass does not influence the linear emphasis) and the white/dark clipping stage. The signal generated in this way then triggers the FM modulator directly. The FM-Y-signal generated in this way is passed via the REC-EQ filter and the REC-FM-AGC1 to the Y-C addition point. The FM-Y-signal can be measured after the REC-EQ filter on pin 12 [7004].

6.2.2 Chrominance PAL

The chroma signal is separated from the video signal after the FBC clamping stage (see “Luminance recording“) by the BPF1 band pass filter and reaches the ACC stage via a delay element (D.E.) and a low pass filter (LPF). The ACC amplifier stage controls the chroma amplitude for the subsequent stages (time constant via capacitor [2038] on pin 14 [7004]). The chroma signal is then conveyed to the main converter (Main Conv.). The main converter mixes the 5.06MHz subcarrier with the 4.43 MHz chroma signal to the 627kHz chroma FM signal. The subcarrier is a mixture of

4.43MHz (the REC APC time constant on pin 65 compares quartz and burst frequency) and (40+ 1/8) fH = 627kHz (produced by 321fH –VCO corresponds to 8(40+1/8)fH, time constant pin 60/62 and phase rotation in accordance with the VHS standard, 10 [7004] (CROT)). Via a low pass filter (C_LPF) and the colour killer stage (KIL), the converted chroma signal reaches pin 72 on the IC [7004], where it is added directly to the Y FM signal IC internally via a capacitor [2007]. The colour killer can either identify the incoming signal itself (PAL yes/no, PAL: chroma signal out, SECAM L: chroma signal killed) or be set via the I2C bus to PAL MESECAM or SECAM L. The quartz oscillation (pin 66) is used for chroma processing, in addition to the reference frequency, and also for generating the pulse frequency for the combined CCD on pin 49 integrated into the IC [7004].

6.2.3 MESECAM

The signal path is virtually identical to the path for PAL.

The differences are:

No phase rotation. The filter characteristic for the chroma band passes becomes wider. Free-running quartz frequency

6.2.4 SECAM L

The video signal (VREC) from the SE IC pin 32 [7004] passes through SECAM L SE IC pin 15 [7072] and a band pass filter (4.3MHz BPF-A) and reaches the cloche filter (CA filter components pin 21) which reverses the Hf pre-emphasis on the sender side. The C-signal is then limited (LIM, time constant pin

18) and divided to ¼ of the frequency in the frequency divider. The C-signal is suppressed in SYNC GATE during the H-sync. period. The harmonics arising in the division into four and the gating are suppressed in the band pass filter (1.1MHz BPF) and then preprocessed in the anti-cloche filter (filter components pin 8) for standard VHS recording. The amplitude on the REC-chrome signal on pin 11 [7072] can be set using the setting resistor [3088] on pin 10 [7072]. This REC-chroma signal is passed via transistor [7077] as a CSRP signal to SE IC pin 72 [7004] following an external drop (3.9MHz, suppression of the 3rd harmonics of the low frequency REC-chroma) and added to the FM-Y-signal in the SE IC. As the SECAM SE IC (LA7339A) has an automatic cloche and anti cloche comparison, only the REC-chroma signal level is required to be set.

6.2.5 FM signal

After the addition of the FM-Y-signal and the C-signal, this FMsignal is adjusted by the REC-FM-AGC2 controlled by the IIC bus to the preset amplitude (reference: pin 74 [7004] resistor [3009]). The head pair is selected using the HSC control line.

• C-REC path: see Chrominance PAL Recording (6.2.2).

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6.3. Playback:

6.3.1 FM signal

The FM signal coming from the scanner is amplified by approx. 60dB. Depending on the level of the HSC and HP1 line, the amplified FM signal is connected to pin 74 [7004]. The envelope curve signal for the head currently active (TRIV) is output on pin 93 [7004]. In addition, the envelope curves for the SP and the LP heads which read from the tape are compared and output as the ENVC signal. The FM signal (FMPV) on pin 74 [7004] is used internally for Y, SECAM, MESECAM and NTSC M/N playback and externally for SECAM playback.

6.3.2 Luminance

The FM playback signal is first adjusted in the AGC stage to a constant level and filtered in the FM processing (PB-EQ). The signal exits the IC [7004] on pin 18, passes via an E-follower [7010] with drop (1.07MHz – only in SECAM units – to suppress additional chroma remainders externally) to a phase shifter [7003] and enters the IC once more on pin 17 [7004]. The FM-Y signal limited using the double limiter is demodulated (FM-DEM) and filtered using a low pass (SUB_LPF). The demodulated Y signal is also affected by the recording-side pre-emphasis. This now removes the linear deemphasis at the base of the emitter follower [7008]. The filter circuit is effective, as pin 21 [7004] becomes an open collector output in playback mode, where the load impedance is determined by the de-emphasis circuit. The Y signal is then clamped after the E-follower on pin 20 [7004], filtered using a low pass, and carried by a vertical noise canceller or dropout compensator (Y.N.R.). To do this the Y-signal exits the IC [7004] (out: pin 43, in: pin 41) and delayed by 1H in the internal CCD. The CCD-1H delay line is effective for the Y signal first as a comb filter (vertical noise suppression) and secondly as a line storage device for the dropout compensation. The subsequent switching stages are: The non-linear de-emphasis (NON_LIN DE_EMP), horizontal noise canceller (N.C.1 / N.C.2) and the picture control switching to the increase in edge steepness (PIC_CTL ANR; sharpness). The luminance signal is then added to the chroma signal (Y/C MIX) and output (pin 29 [7004]) as FBAS signal via a clamp (FBC), the video input (CHARA INSERT) and a 6dB amplifier (6dB_AMO).

6.3.3 Chroma PAL

This is first adjusted in the AGC stage to a constant level and filtered in the FM processing (PB-EQ). The signal exits the IC on pin 18 [7004], and passes via an E-follower [7010] with drop (1.07MHz ). On pin 17, the FMPV signal is carried from the head amplifier to the IC [7007] signal electronics. From the FM playback signal the 627 kHz chroma signal is filtered using the internal low pass (C_LPF). The ACC amplifier amplifies and controls the chroma amplitude. In the main converter (MAIN CONV), the chroma signal is mixed with 5.06 MHz back to the original 4.43 MHz. The 5.06 MHz are produced in playback from the free-running quartz oscillator and from the (40+1/8) fH = 627 kHz frequency derived from the 321fH-VCO. After the main converter the chroma signal is freed as far as possible from crosstalk from additional traces using a 2H comb filter (internal CCD connections: pin 57 -> 54; pin 59 -> 52 and pin 51 -> 61). The chroma signal is then filtered using a low pass (LPF), checked by the colour killer, filtered once again by a band pass, looped through pins 72 and 71 and then added to the Y signal.

6.3.5 Chroma SECAM L

During playback the FM signal is passed from the band on pin 74 [7004] after the E-follower [7002] (FMPV) to pin 13 [7072], where the amplitude is adjusted in the AGC and passed via the same band pass (1.1MHz BPF) as for recording. The NF pre-emphasis for the recording is then reversed using a cloche filter (external filter components on pin 8; the same components as for recording). In the subsequent stages the frequency of the signal is doubled, filtered using a band pass (2.2MHz BPF) and doubled once again. Then follows another band pass (4.3MHz BPF-B), and then the limiter (LIM) already used for recording. The signal is then suppressed again during the H-sync. period and passed through a band pass filter (4.3MHz BPF-A; also used for recording). Before the SECAM-chroma signal exits the IC on pin 17 [7072], an Hf preemphasis is carried out once more (anti-cloche; external filter components on pin 21; the same components as for recording). After pin 17 there is a drop at 2.4MHz which suppresses the 2 harmonic of the chroma from the band, a low pass filter which improves the harmonics of the high frequency chroma and a transistor [7073] which has an emitter connected to pin 72 (CSRP) on the SE IC [7004].

6.3.6 NTSC

During the playback of NTSC signals, the original NTSC chroma is converted into a PAL chroma signal. This requires an internal switchover in the IC in the chroma part:

The internal CCD is switched over on a 1H comb filter to reduce crosstalk. The NAP switchover is activated and translates the 4.43MHz

NTSC chroma signal into a PAL signal. Line and picture frequencies remain unchanged in accordance with the NTSC standard. The result is a 60Hz NTSC Y-signal with a 4.43MHz PAL C-signal.

6.3.7 PAL M,N

As for chroma PAL (6.3.3).

6.4 General

SECAM: Automatic cloche and anti-cloche comparison: During the

vertical blanking gap the external filter components (pin 21 or pin 8) on the cloche or anti-cloche are used to create an oscillator and to divide the resonance frequency produced, and compared with a frequency derived from the 4.43MHz oscillation (reference signal from the SE IC [7004]). Depending on the deviation, more or less internal capacity is connected in parallel to the external cloche and anti-cloche filter components. This process is carried out during each vertical blanking gap and thus also improves the temperature stability.

Chroma selection for REC and PB pin 71 and 72 SE IC [7004]:

Both the PB chroma and the REC chroma in PAL (MESECAM, PAL M/N) and also in SECAM are passed into the SE IC [7004] via pin 71 [7004]. In all PAL and MESECAM modes the DC voltage is on the base of the output emitter follower pin 72 [7004] 3.2V and the both bases of transistors [7077] and [7073] of the SECAM chroma signals are at 0V -> the PAL/MESECAM chroma signal is added to the FM-Y signal or to the PB-Y signal, according to REC or PB. In SECAM PB mode only the transistor [7073] has 2.5V DC voltage on the base. In SECAM REC mode only the transistor [7075] has

2.5V DC voltage on the base.

6.3.4 Chroma MESECAM

The signal path is virtually identical to the path for PAL.

The differences are:

No phase rotation. The comb filter is not active.

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7. Audio linear (AL part)

7.1 Audio I/O for the 1-scart version

The input is selected via the IIC bus control in the IC signal electronics [7004-A]. Either signal AIN1 (pin 76) or AFV (pin 80) is selected. The output signal AMLP (pin 96) is passed to scart 1 and to the HF modulator.

7.2 Audio I/O for the 2-scart version

The input is selected via the IIC bus control in the IC signal electronics [7004-A]. Either signal AIN1 (pin 76), AINF_AIN2 (pin

78) or AFV (pin 80) is selected. The output signal AMLP (pin 96) is always passed to the HF modulator.

7.3 Audio linear recording

The signal inputs for recording or loop-through are pins 76,78 and 80 on the linear audio part of the IC LA71595 [7004-A]. During record and loop-through, the selected signal passes through the linear amplifier and then a mute stage and exits the IC on pin 96. This is the output which leads to the I/O part or the stereo units back to the AF part. The attenuation chain on pin 96 sets the required level for the ALC (Automatic Level Control) detector and the level for the recording amplifier. The time constant for the ALC detector is specified using R3605 and C2602 on pin 77. R3634, R3640, C2626 and C2627 create the frequency response for the recording amplifier. The output for the recording amplifier is pin 7. The recording current is then added to the bias current via resistor R3642 and flows via the audio head to pin 4 where an electronic switch is closed in the IC. In long play mode the frequency characteristic is modified to the RC network R3635, R3641, C2630, C2631 for the recording amplifier. The coil L5600 and the transistor T7608 create the erasing oscillator for the main eraser head and audio track eraser head, and generate the bias current for the audio head. The bias current is set using potentiometer 3625. To prevent spikes, the erasing oscillator is switched on slowly. This is created using the switching stage T7603, C2609, R3611 and R3613.

8. Audio HiFi - for stereo units (AF part)

8.1 General

All audio input and output selection switches, and the hi-fi FM audio signal processing, are located in the TDA9605 [7650]. This IC is controlled solely by the IIC bus. The carrier frequencies and band pass filter for the FM audio part are adjusted by the TDA9605 independently. This adjustment is started via the IIC bus following a mains reset. The RMHI signal is used as a reference for this [7650 Pin 41].

8.2 Audio I/O

The input and output selection switches are controlled exclusively by the IIC bus. Audio signals coming from the receiver part, the two scart sockets and the front sockets pass via pins 2 to 9 to the two input selector switches which select the relevant signals for the FM and the linear audio part. The output selector switch for SCART 1 and SCART 2 (pins 16,17 and 19, 20) select the relevant signal sources, independently from one another. The RFAGC limits the maximum amplitude of the signal to the AMCO modulator (pin 13) to prevent overmodulation.

8.3 Audio HiFi recording

The signal coming from the input selector switch (INPUT SEL) reaches, via a level actuator (VOLUME L//R) and a low pass filter (LPF), the NOISE REDUCTION block, which compresses the dynamics during recording. The compressed signal is passed to both FM modulators (1.4MHz and 1.8MHz carrier frequencies). Both carriers are added and pass to the FM audio head amplifier. Via the recording / playback switch on the head amplifier, which is switched using the control line RMHI, the FM signal reaches the output (pin 35, pin 36, pin 37) on the FM audio processor and then the audio heads via the rotating transformer. The TRIA_ALM line forwards the size of both audio signals (1 VRMS = 2.68 VDC) to the AIO processor [7899-B]. This DC level information is required during recording by the SCART or front cinch socket to prevent overmodulation of the FM carriers. When the audio signal levels are too high, they are attenuated using the VOLUME controller via the I2C bus.

7.4 Audio linear playback

During playback the switch [T7604, T7607] is controlled by pin 99 and is closed. The playback signal from the head is amplified in the equaliser stage (time constant between pin 1 and pin 3) and passed to pin 1. The resistor R3633 and the capacitor C2619 determine the head resonance during playback. In long play mode the frequency characteristic is modified using R3627, C2617 for playback. The output of the playback amplifier (pin 1) is passed via the filter R3632, C2623 to pin 100 where an electronic potentiometer sets the playback level via the 12C bus. Amplifier and head tolerances are compensated here. The amplification can be compensated via software control (12C bus) in service mode.

7.5 Audio linear muting

The mute stage in the linear audio part on the IC LA71595 [7004-A] is controlled by the combination control line MTA_CROT which is connected on pin 10 (VS part). The mute stage is activated in that the CROT control signal (square-wave pulse 1.7 Vss) is moved into the upper direct voltage range ( > 2.2 V ).

MTA

MUTE active

no MUTE

8.4 Audio HiFi playback

The FM signal from the audio heads goes via the rotating transformer to the recording / playback switch (pin 35, pin 36, pin

37) on the head amplifier. After amplification in the head amplifier (66 dB), the FM signal reaches the HF-AGC (Automatic Gain Control), where the tolerances of the tape, the heads and the rotating transformer are balanced. Via the two band pass filter and limiters, the FM signals reach the PLL demodulators. Head change-over interference is suppressed using SAMPLE & HOLD stages (triggered by the RMHI signal). The demodulated signals are then expanded into the NOISE REDUCTION stage. The hi-fi signals are then available at the output selection switches. If there is no audio FM on the tape during playback, the output selector switch is switched over automatically from the IC to linear audio (input pin 22). In playback mode the TRIA_ALM line supplies the level of the FM envelope curve to the AIO processor [IC7899-B]. This level information from the FM envelope curve is used for the hi-fi tracking of the rotating FM audio heads to achieve the best possible playback quality (typically: 3.5 VDC).

8.5 Interface to the audio linear

In recording mode, the input selection switch NORMAL SEL in the TDA9605 [7650] selects the audio source for the linear audio part in the signal electronics IC LA71595 [7004 - A] and passes this signal to pin 21 (AMLR). In stereo sets, the input selection switch on the signal electronics IC LA71595 [7004-A] is always set to IN2 (pin 78). During playback the AMLP signal passes from the linear audio part in the signal electronics IC [7004-A] pin 96 to the linear audio input on pin 22 on the TDA9605 [7650].

A: DC, 1 V/Div, 20ms/Div IC7004-B PIN10 CROT/MTA

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9. IN/OUT (IO part)

9.1 Video:

The entire video-I/O is carried out in 2-scart units using the matrix switch STV6401 [7904), which is controlled by the AIO via the IIC bus (SDA,SCL). To do this, the following signals are connected to STV6401 at the inputs: VFV-pin4, VIN1-pin6, VIN2-pin8, VOUT1)pin10 (1)The VOUT signal is also passed through a voltage divider and a low pass [2906,3934,3928] and passed to the modulator where necessary via the emitter follower [7909]) and VFR-pin12 (front cinch input). The outputs OUT3/pin15 (scart 2) and OUT2/ pin16 (scart 1) in the IC are fitted with a 6dB amplifier and convey the signal to the relevant scart socket. OUT1/pin2 has no amplifier; this signal (VBS) is passed on to the VS circuit parts for further processing: In 1-scart units the SE IC [7004] selects the input video. SE IC original layout: VIN1 (the VBS line is used in the plan) pin 38 , VFV pin 36. The VOUT1 signal (scart 1 video out) is generated using an E-follower [7908] from the VOUT signal.

9.1.1 Audio for the 2-scart version:

The output signal for scart 1 is selected using the switch - IC HEF4053 [7911-C] using the MON control line (pin 9) from AMLP (pin 5) and AINF_AIN2 (pin 3). The output signal for scart 2 is selected using the switch - IC HEF4053 [7911-B] using the DEC control line (pin 10) from AIN1 (pin 2) and AFV (pin 1).

9.2 Decoder mode: (REC or STOP)

9.2.1 Program position with decoder (front end)

The front end signal (VFV or AFV1/2) is passed to the decoder connected to Scart 2 and from there, goes back to the VCR via VIN2 or AIN2L/AIN2R . External input with decoder (9.2.2) is not possible for these program positions.

9.2.2 External input with decoder

The signal from scart 1-in (normally TV set) is passed to the decoder connected to scart 2. For scrambled programs, the decoder switches the pin 8 to high. The VCR then passes the decoded signal from scart 2-in to scart 1-out.

10. Follow Me (FOME part)

This circuit is used to compare the front end video with the video on scart 1 (video from the TV connected) in order to be able to save the stations in the same order as on the TV. The video signals from the front end (VFV) and from the scart socket (VIN1) are “digitised” using filters and comparators [7530-C, 7530-D] and compared with one another [7531, 7532, 7530-A]. Low on the output for the circuit means that the picture contents for the two video signals are identical and that both receiver parts (TV and VCR) therefore have to be adjusted for the same station. Possible errors detected may result with similar signals, e.g. news programmes.

11. VPS/PDC, on-screen display (VPO part)

11.1 VPS/PDC

The VPS and PDC data is either decoded by the VPS-PDC decoder-IC SDA5650 [7502] or by the OSD-IC with integrated VPS, PDC decoder SDA5652 [7502]. Both ICs are compatible in terms of pins, despite any differences in the peripherals. The VPS-PDC data are read from the vertical blanking gap and stored in the internal RAM. This data is read from the µP via the I²C bus. The time can also be read from the TXT header line (required for “Time download“). The date is not called up from the TXT header (various write versions of the preset stations) but only via PDC format-1. In the case of the SDA5650 [7502] the input video signal comes from the signal electronics IC LA71595M [7004-B pin 32] (VREC) via a 470n capacitor [2504] to the data slicer input on the SDA5650 (pin 17). For the SDA5652 the input signal from pin 29 (VSB) on the LA71595M [7004-B] comes via an emitter follower [7501] with a voltage divider to the data slicer input on the SDA5652 (pin1 17).

11.2 OSD-PART

The IC SDA5652 [7502] also allows both the generation of text keyboard matrices into a video signal and the generation of an entire picture (full page) for menu-control or if no background video is available. The video signal (VSB) passes from the signal electronics IC LA71595M [7004-B pin 29] via a resistor [3512] to the input for the OSD-IC [7502 pin 18]. For keyboard matrices in Secam video signals, a bypass between video-in and video-out is activated via a switch inside the IC and a band filter [2507, 5502]. The output signal is available on pin 15. A multiple of the doubled colour subcarrier oscillation from the signal electronics (2FSC/8.86MHz) is used as the system pulse for the IC. It is also used as a reference for generating the various OSD colours. The signal reaches the IC via a coupling capacitor [2509]. For the vertical synchronisation of keyboard matrices, an OSD frame pulse (OFP) is generated by the µP [7899-B pin 36] and passed to the IC [7502] on pin 9. The horizontal sync-pulse is generated using an internal sync-separator and an internal H-PLL from the video signal on pin 17. During full-page OSD (menu or no video) neither a vertical-sync (OFP) nor an H-sync is required, as in this mode, the OSD-IC generates everything from the system clock frequency, i.e. all the necessary pulses are generated internally from the 2FSC signal.

2-18

Simple Blockdiagram

FFP

SYCA Video-Part

Testpict.

Generator

PLAY

REC/EE

293132

VSB

VPO

VSB

7502

SDA5652

Secam

VPO

Bypass

not for VPO

OFP

VOUT

VBS

VOUT1VOUT2

7004-B

LA71595M

IN3

IN2

IN1

VREC

7072

LA7339A

VS_ SEC

VBS

VFVVIN1

21615

x1x2x2

Mute

10k

BUS

7904

STV6401

SCL

SDA

I C-Bus

from AIO1

VIN2

VOUT

VFR

51210864 13

MON

VREC

7502

VS-SECAM

SDA5650

VPS/ PDC

SDA

I C-Bus

VPS/PDC

SCL

from AIO1

FOME

7530

VIN1

LM339D

FOME

VOUT

1701

MODULATOR

VFV

TUMOD

VFV

7899-B

CENTRAL CONTROL

AIO1

IO-Block diagram 2 Scart-Video-Mono&Stereo

not for OSD

FFP OFP

55 32

8SC18SC2

MON

7913

VFR

1954A

Front plug

Video from

Front plug

VOUT2

197201181516101016151911207

1952

Scart2

Video Out

VIN2

Video In

8SC2

Switching

blanking

Blanking

pin10

red

pin10

blue

green

blue

Scart1

1951

blue

red

green

pin10

red

pin10

blanking

Blanking

VOUT1

Video Out

VIN1

Video In

8SC1

Switching

2-19

Audio In 1

Audio Out 1

Front plug

Audio In 2

Audio Out 2

Scart1

1951

Front plug

1954A

Scart2

1952

2+6

1/3

2+6

1/3

AINF

AIN1

AOUT1

AIN2

AOUT2

AFV

AIN1

AIN2 - AINF

AFV

STV6401

7904

SCL SDA

PB-Head

BUS

IS1

MONDEC

IN1

IN2

IN3

PLAY

REC/EE

SYCA Audio-Part

LA71595M

7004-A

AMLP

AIN2

AINF

MON

AMLP

AIN2

DEC

AIN1

AF1

AMLP

MODULATOR

TUMOD

7911

AIN2 - AINF 14

HEF4053

1701

AOUT1

AOUT2

Switching

Video In

Video Out

Audio Out l

Audio In l

Scart 1

1951

MODULATOR

8SC1

VIN1

VOUT

AMLP

1/3

AIN1

2+6

1701

TUMOD

AMLP

VOUT

VFV

AFV

OFP

FFP

36 32

8SC1

AIN1

AFV

IO-Block diagram 2 Scart-Audio-Mono

7004-B LA71595M

AMLP

not for OSD

VREC

VPS/PDC

SYCAVideo-Part

PLAY

REC/EE

Generator

VREC

Testpict.

293132

SDA5650

VPS/PDC

I C-Bus

SCL SDA

VSB

FFP

VSB

not for OSD

VOUT

VS_

SEC

VS-SECAM

VPO

Secam

Bypass

VREC

LA7339A

SDA5652

OSD

70727502

OFP

7502

FOME

VFV

VIN1

VFV

PB-Head

IN1

IN2

IN3

IN1

IN2

IN3

PLAY

REC/EE

SYCA Audio-Part

7004-A

LA71595M

QMB1 IO-Block diagram 1 Scart-Audio-Video-Mono

2-20

Simple Blockdiagram FM Audio / Linear Audio processing

Volume L/R

REC

+15dB

AH2

mute

-48dB

FM Audio

TapeDeck

1965-1 1965-3

EQ-AmpLine

REC

EtoE

APH

AHC

36 10

Processing

Head

AH1

Amplifier

7004-A

AMLR

ARH

ALC Rec-Amp

0dB

+15dB

Level

mute

LA71595M

Mute

Linear-Aud.

Processing

mute

AMLP

TDA 9605H

FM-Audio Processing

LEFT

L+R

L+R x VolumeLR

Lin.Audio Sel

L x Volume

OutputSel

RIGHT

STEREO

NOR+ST

NORMAL

NOR+L

NOR+R

mute

InputSel

7650 AF

ST/NIC

7760/7761

TUNER

CINCH

4/5

2/3

AFL

AFR

Dec.

Stereo

MSP3415

TDA9873

SIF2

EXT1

8/9

6/7

Nicam

EXT2

EXT3

SAP

AINFL

AINFR

AIN1L

AIN1R

EXT2

LineSel

OutSel

AOUT1L

AOUT1R

EXT1

OutSel

TUNER

DecoderSel

201719

AIN2L

AIN2R

Mute

AFC

AOUT2L

mute

AMCO

AOUT2R

OutSel

STEREO

Env-Sel

TRIA/DC

Demod.

TDA 98xx

7721

TUMOD

1701

1954-B

AMCO

Front

CINCH

IO 1956

Rear

CINCH

1951

TVC

7899-B

SCART1

1952

SCART2

DECK-µC

2-21

SERVICE MODES

1. Special functions

1.1 Erasing the EEPROM

- Disconnect from mains

- Push and hold down the Standby key, reconnect to mains and keep the Standby key depressed for a further 3 sec.

All EEPROM data will then be erased and initialised (timer and transmitter channels). The internal processor RAM will also be erased, but the option codes, deck parameters and adjustment values are maintained.

1.2 After changing the EEPROM or Motherboard

the following steps must be carried out:

Step 40: Option code input Step 51: Gap position adjustment Step 52: Studio Picture control adjustment Step 53: Input of clock correction

Step 62: Adjustment of Audio Linear Playback Level

Step 99: Clock frequency output

2. Service test program

2.1 Introduction

The software program for the control, deck and operating microprocessors includes a service test program. It was divided into the following steps, with the following modes:

Step 00: Display of mask version number Step 01: Check of the drive positions Step 02: Display of the deck - error codes Step 03: Deck - sensors and manual tracking Step 04: Display of operating hours counter Step 05: Display of the IIC-Bus Communication Step 10: Operation without drive - dummy mode Step 40: Option code input

Adjustment Steps in the service test program:

Step 51: Gap position adjustment Step 52: ‘Studio Picture control‘ adjustment Step 53: Input of clock correction Step 62: Adjustment of Audio Linear Playback Level Step 98: Display test Step 99: Clock frequency output

In the service test program, all drive functions apart from the channel search and channel change mode can be carried out. The program position set before entering the service test program is maintained.

2.2 Activating the service test program

Press and hold down the STOP key on the remote control. Then press the PLAY key on the recorder and keep it depressed for at least 5 sec. The STOP key on the remote control may be released whilst the PLAY key on the recorder is pressed. The service test program can be selected in any operating mode apart from the channel search, install, clock set-up and cassette length calculation mode. The recorder and all drive functions are fully operational in the service mode.

The display shows, for instance:

By pressing the SELECT key on the remote control, all step modes may be left and the currently selected step number appears and flashes.

Other service steps are selected with the UP and DOWN keys or the numerical remote control keys. By pressing the SELECT key on the remote control whilst the Step is flashing, the respective mode can be entered or left. If a step is selected to which no mode is assigned, the displays shows - - and flashes.

To leave the service program, press the STAND-BY key or disconnect recorder from mains.

2.3 Service mode functions

Endurance test

In the service test program, the recorder can be endurance tested. For this purpose, use a cassette and activate PLAY or REC. The functions are then repeated continuously. In RECORD, the recorder does not move to EJECT at the tape end, but to REWIND, after which it starts to RECORD again. This test serves to detect intermittent faults. The last error is stored in the EEPROM. (The fault remains stored even after a power failure).

The endurance test is ended by pressing STOP or leaving the service test program.

PLAY TAPE END RECORD

TAPE BEGIN REWIND TAPE BEGIN

2.4 Description of steps with modes:

Step 00: Display of mask version number

After activating the service test program, step 00 and the mask version number are automatically displayed.

Central control mask

The mode can be left again by pressing the SELECT key on the remote control. The currently selected position number appears and flashes on the display.

Central control mask

A step between 00 and 99 can now be selected

2-22

Step 01: Checking the drive positions

By pressing the SELECT key whilst Step 01 is flashing, the drive position appears on the display. The FTA signal from the photoelectric barriers which controls the revolutions of the loading motor is used to check the drive condition. The drive position is shown as a 3-digit decimal number by counting the FTA pulses on the display.

(e.g. 213 = Play)

Table of drive positions:

Status Position

(FTA dec) Eject 007 +2/-2 Index 191 +0/-2 Stop 200 +4/-4 Play 213 +4/-4 Reverse 237 +2/-0

Function of the Init switch:

The diagram shows the function of the Init switch, depending on the position of the deck. The number of FTA pulses is important for the position of the drive.

A:DC,2V/Div,0.5s/Div B:DC,2V/Div,0.5s/Div

Stopping of head drum motor

This is monitored with the PG/FG signal. The signal is discharged from the e.m.f. of the non-conducting spools of the head cylinder motor, showing the position of the head cylinder.

Capstan motor fault

This is monitored with the FGD signal.

If one of the above sensor signals is not available, the recorder tries to put the lift into the EJECT position.

Explanation of deck error codes and deck error status

The last error code is stored and remains in the EEPROM, even if the recorder is disconnected from the mains. The error code can be erased by pushing the CLEAR button on the remote control.

The display shows, for instance:

The left digit shows the error: (e.g.: Error 2 = Capstan error)

Error table:

no error

threading error

no capstan pulses

tape broken

no pulses left reel

no pulses right reel

head motor error

Eject

Play

Init switch

FTA pulses

Index/

Cass down

wind-rewind

Reverse

Step 02: Display of the deck error codes

By pressing the SELECT key whilst Step 02 is flashing, the deck error code is shown on the display.

Checking the drive function Loading and unloading time

The signal (FTA) of the photoelectric barrier which controls the revolutions of the loading motor is used as a reference for the loading and unloading time.

The 3 digits on the right represent the deck error condition: (e.g.: 053 = during Play )

Functiontable:

012

Standby 114 VISS write 211 Slowmotion 1/24 014 Autotracking 115 Viss erase 212 " " 1/14 031 Play-3 125 Tuner - Stopout 215 " " 1/7 034 Slow_reverse 126 Auto Remain Funct. 216 " " 1/2 041 Still Picture 130 ATTS Fun c tion 217 " " -1/24 042 Fast 168 Frame+ 218 " " -1/14 044 Play-9 169 Frame- 219 " " -1/7 045 Eject 170 Play-11 220 " " -1/2 046 Play9 171 Play-7 222 Edit Record 047 Play-1 172 Play-5 223 Align of Gap 048 Pause 173 Play5 238 Pause 050 Rewind 174 Play7 239 SPC align 052 Wind 175 Play11 246 Edit Pause 053 Play 196 Tuner - Eject 247 Slow motion 1/10 054 Stop out 197 Standby Eject 248 " " 1/18 055 Record 199 Audio Dubbing 249 " " -1/10 112 Index next 202 Audio Dubb. Pause 250 " " -1/18 113 Index previous 206 Reset Tapecounter 253 Key Released

Stopping of supply or take-up reels

The tacho signals of the left (WTL) and right (WTR) winding disks are used as control reference.

The error code can be reset in this step with the CLEAR key.

2-23

Step 03: Deck sensors and manual tracking

By pressing the SELECT key whilst step 03 is flashing, the deck sensors will be displayed in one digit as either 1 or 0.

nl z A are used to display the deck status. START init switch (INIT) END record protection (RECP) DEC Loading pulses (FTA)

In the service test program, the tracking is always in the centre position. Only in this step can the value for the required tape running setting be changed, manually in the PLAY function with the UP / DOWN keys. After leaving the mode with the SELECT key, the tracking value always resets itself to the centre position and cannot be changed.

Step 04: Display of the operating hours counter:

By pressing the SELECT key whilst step 04 is flashing, the operating hours counter shows how many hours the head disk has turned. The hours are displayed as a 4-digit decimal number.

Step 10: Operation without drive - dummy mode

Before activating this mode with the SELECT key, the recorder must be in the EJECT position.

Enter the mode by pressing the SELECT key . The motors are then switched off and the sensors will be ignored by the deck microprocessor. The drive can now be dismantled from the motherboard (see dismantling instructions). Only install drive if recorder is disconnected from mains. For signal tracking, the recorder can be set to all drive conditions, i.e. signal electronics, audio and IO processing are switched to the respective operating mode.

nl z A are used to show the deck status START init switch (INIT) END record protection (RECP) DEC loading pulses (FTA)

Step 40: Option code input

If a new EEPROM is installed in the course of repairs, it must be initialised. By pressing the SELECT key whilst step 40 is flashing, the decimal option A appears in the display.

Step 05: Display of the IIC - Bus Communication:

By pressing the SELECT key whilst step 05 is flashing, the available IIC- components will be displayed with symbols.

Symbol Description Component Position

VPS or VPO IC SDA5650 or SDA5652 7502

FM ST / NIC IC MSP 3415D 7761

DEC

FM St IC TDA 9873 7760

Video switch IC STV 6401 7904

FM Audio IC TDA 9605H 7650

Tuner Philips TP9xx 1701

Tuner Alps TMRxx/TCBZ4 1701 Modulator Phil TP9xx 1701

Modulator Alps TMRxx/TCBZ4 1701

Signal electr. IC LA71595M 7004

The following errors are visible in the display when the start up routine of the set isn’t working properly.

E000 IIC-Data line is low E001 IIC-Clock line is low E002 EEPROM give no acknowlegement

By entering a 3-digit decimal code, the correct features are set.

These codes are shown on the type-plate of the recorder.

After pressing the OK key on the remote control, the entered code is saved. The display shows OK for approx. 3 sec. and then the stored value in decimal format.

By pressing the UP and DOWN keys, the available options (A to G) can be selected. The display shows the last stored value in decimal format.

In case of an invalid entry (value >255) the activation of the OK key causes the content of the last stored option to be displayed and OK does not appear in the display.

Depending on the model, some bits are software or default protected and cannot be changed by an entry. In this case, the display shows OK, but the display returns to the default value.

Step 98: Display Test

By pressing the SELECT key whilst step 98 is flashing, all segments of the display are illuminated.

The step is exited by pressing SELECT again.

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