HITACHI HM514260C User Manual

HM514260C

HM514260C Series

HM51S4260C Series

262,144-word × 16-bit Dynamic Random Access Memory

ADE-203-260A (Z)

Rev. 1.0

Jun. 12, 1995

Description

The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51(S)4260C has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4260C offers fast page mode as a high speed access mode. Multiplexed address input permits the HM51(S)4260C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4260C self refresh operation.

Features

•Single 5 V (±10%) (HM51(S)4260C-6/7/8)

(±5%) (HM51(S)4260C-6R)

•High speed

—Access time: 60 ns/70 ns/80 ns (max)

•Low power dissipation

—Active mode: 825 mW/788 mW/770 mW/688 mW (max)

—Standby mode: 11 mW (max) (HM51(S)4260C-6/7/8)

10.5mW (max) (HM51(S)4260C-6R)

1.1 mW (max) (L-version) (HM51(S)4260C-6/7/8)

1.05mW (max) (L-version) (HM51(S)4260C-6R)

•Fast page mode capability

•512 refresh cycles: 8 ms

128 ms (L-version)

•2 CAS-byte control

•2 variations of refresh

—RAS-only refresh

—CAS-before-RAS refresh

•Battery backup operation (L-version)

•Self refresh operation (HM51S4260C)

HM514260C, HM51S4260C Series

Ordering Information

Type No.

Access Time

Package

HM514260CJ-6

60 ns

400-mill 40-pin plastic SOJ (CP-40DA)

HM514260CJ-6R

60 ns

HM514260CJ-7

70 ns

HM514260CJ-8

80 ns

HM514260CLJ-6

60 ns

HM514260CLJ-6R

60 ns

HM514260CLJ-7

70 ns

HM514260CLJ-8

80 ns

HM51S4260CJ-6

60 ns

HM51S4260CJ-6R

60 ns

HM51S4260CJ-7

70 ns

HM51S4260CJ-8

80 ns

HM51S4260CLJ-6

60 ns

HM51S4260CLJ-6R

60 ns

HM51S4260CLJ-7

70 ns

HM51S4260CLJ-8

80 ns

HM514260CTT-6

60 ns

400-mill 44-pin plastic TSOP II (TTP-44/40DB)

HM514260CTT-6R

60 ns

HM514260CTT-7

70 ns

HM514260CTT-8

80 ns

HM514260CLTT-6

60 ns

HM514260CLTT-6R

60 ns

HM514260CLTT-7

70 ns

HM514260CLTT-8

80 ns

HM51S4260CTT-6

60 ns

HM51S4260CTT-6R

60 ns

HM51S4260CTT-7

70 ns

HM51S4260CTT-8

80 ns

HM51S4260CLTT-6

60 ns

HM51S4260CLTT-6R

60 ns

HM51S4260CLTT-7

70 ns

HM51S4260CLTT-8

80 ns

HM514260C, HM51S4260C Series

Pin Arrangement

HM514260CJ/CLJ Series					HM514260CTT/CLTT Series
HM51S4260CJ/CLJ Series					HM51S4260CTT/CLTT Series

				VSS		VCC	1	44	VSS
	VCC	1	40			I/O0	2	43	I/O15
	VCC	1	40			I/O0	2	43	I/O15
	I/O0	2	39	I/O15		I/O1	3	42	I/O14


	I/O1	3	38	I/O14
	I/O1	3	38	I/O14		I/O2	4	41	I/O13
	I/O2	4	37	I/O13		I/O2	4	41	I/O13
	I/O2	4	37	I/O13		I/O3	5	40	I/O12
	I/O3	5	36	I/O12		I/O3	5	40	I/O12
	VCC	6	35	VSS		VCC	6	39	VSS
	VCC	6	35	VSS		I/O4	7	38	I/O11
	I/O4	7	34	I/O11		I/O5	8	37	I/O10
	I/O4	7	34	I/O11
	I/O5	8	33	I/O10
	I/O6	9	32	I/O9		I/O6	9	36	I/O9
	I/O7	10	31	I/O8		I/O7	10	35	I/O8
	I/O7	10	31	I/O8
	NC	11	30	NC
	NC	11	30	NC

	NC	12	29	LCAS		NC	13	32	NC

			28	UCAS
	WE	13	28	UCAS
						NC	14	31	LCAS
	RAS	14	27	OE		NC	14	31	LCAS
	NC	15	26	A8		WE	15	30	UCAS
								29
						RAS	16	29	OE
	A0	16	25	A7		NC	17	28	A8
	A1	17	24	A6		NC	17	28	A8
	A2	18	23	A5		A0	18	27	A7
	A3	19	22	A4		A1	19	26	A6
	VCC	20	21	VSS		A2	20	25	A5
						A3	21	24	A4

		(Top view)
		(Top view)				VCC	22	23	VSS
							(Top view)

Pin Description

Pin Name

Function

A0 to A8

Address input

–Row address

A0 to A8

–Column address

A0 to A8

–Refresh address

A0 to A8

I/O0 to I/O15

Data-in/data-out

RAS

Row address strobe

UCAS, LCAS

Column address strobe

Read/write enable

Output enable

VCC

Power (+5 V)

VSS

Ground

No connection

HM514260C, HM51S4260C Series

Block Diagram

256 k Memory Array Mat

I/O Bus & Column Decoder

256 k Memory Array Mat

I/O Bus & Column Decoder

256 k Memory Array Mat

Peripheral Circuit

256 k Memory Array Mat

I/O Bus & Column Decoder

256 k Memory Array Mat

I/O Bus & Column Decoder

256 k Memory Array Mat

Row

Decoder

Decoder Decoder

Decoder

Decoder Decoder

Decoder

Selector

I/O4

I/O3

I/O2

I/O1

I/O0

I/O15

I/O14

I/O13

I/O12

I/O11

Buffer

I/O3

I/O2

I/O1

I/O0

I/O15

I/O14

I/O13

I/O12

I/O5

Buffer

I/O10

Buffer

I/O6

I/O9

Buffer

I/O7

I/O8

Buffer

Peripheral Circuit

LCAS

UCAS

RAS

Address

A0,A1,A2,A3

Address A4,A5

A6,A7,A8

Selector

Row	Row	Row	Row	Row	Row	Row	Row
Decoder	Decoder Decoder		Decoder	Decoder	Decoder Decoder		Decoder

256 k Memory Array Mat

I/O Bus & Column Decoder

256 k Memory Array Mat

I/O Bus & Column Decoder

256 k Memory Array Mat

Peripheral Circuit

256 k Memory Array Mat

I/O Bus & Column Decoder

256 k Memory Array Mat

I/O Bus & Column Decoder

256 k Memory Array Mat

HM514260C, HM51S4260C Series

Operation Mode

The HM51(S)4260C series has the following 11 operation modes.

1.Read cycle

2.Early write cycle

3.Delayed write cycle

4.Read- modify-write cycle

5.RAS-only refresh cycle

6.CAS-before-RAS refresh cycle

7.Self refresh cycle(HM51S4260C)

8.Fast page mode read cycle

9.Fast page mode early write cycle

10.Fast page mode delayed write cycle

11.Fast page mode read- modify-write cycle

Inputs

RAS	LCAS	UCAS		WE	OE	Output	Operation

H	H	H		D	D	Open	Standby
H	L	L		H	L	Valid	Standby
L	L	L		H	L	Valid	Read cycle
L	L	L		L*2	D	Open	Early write cycle
L	L	L		L*2	H	Undefined	Delayed write cycle
L	L	L		H to L	L to H	Valid	Read-modify-write cycle
L	H	H		D	D	Open	RAS-only refresh cycle
H to L	H	L		D	D	Open	CAS-before-RAS refresh cycle

	L	H					Self refresh cycle (HM51S4260C)
	L	L
	L	L
L	H to L	H to L		H	L	Valid	Fast page mode read cycle
L	H to L	H to L		L*2	D	Open	Fast page mode early write cycle
L	H to L	H to L		L*2	H	Undefined	Fast page mode delayed write cycle
L	H to L	H to L		H to L	L to H	Valid	Fast page mode read-modify-write cycle
L	L	L		H	H	Open	Read cycle (Output disabled)

Notes: 1.	H: High(inactive) L: Low(active) D: H or L
2.	tWCS ≥ 0 ns		Early write cycle
	tWCS < 0 ns		Delayed write cycle

3.Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS.

ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.

HM514260C, HM51S4260C Series

Absolute Maximum Ratings

Parameter	Symbol	Value	Unit
Voltage on any pin relative to VSS	VT	–1.0 to +7.0	V
Supply voltage relative to VSS	VCC	–1.0 to +7.0	V
Short circuit output current	Iout	50	mA
Power dissipation	PT	1.0	W
Operating temperature	Topr	0 to +70	°C
Storage temperature	Tstg	–55 to +125	°C

Recommended DC Operating Conditions (Ta = 0 to +70°C)*2

Parameter	Symbol	Min	Typ	Max	Unit	Notes
Supply voltage	VSS	0	0	0	V	2
	VCC (HM51(S)4260C-6/7/8)	4.5	5.0	5.5	V	1, 2
	VCC (HM51(S)4260C-6R)	4.75	5.0	5.25	V	1, 2
	VCC (HM51(S)4260C-6R)	4.75	5.0	5.25	V	1, 2
Input high voltage	VIH	2.4	—	6.5	V	1
Input low voltage	VIL	–1.0	—	0.8	V	1

Notes: 1. All voltage referred to VSS.

2.The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.

HM514260C, HM51S4260C Series

DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V) (HM51(S)4260C-6R)

(Ta = 0 to 70°C, VCC = 5 V ±10%, VSS = 0 V) (HM51(S)4260C-6/7/8)

HM514260C, HM51S4260C

			-6/-6R		-7		-8
Parameter	Symbol		Min	Max	Min	Max		Min		Max	Unit	Test Conditions

Operating	ICC1		—	150	—	140		—	125		mA	RAS, UCAS or LCAS cycling
current1, 2												tRC = min
Standby current	ICC2		—	2	—	2		—	2		mA	TTL interface
												RAS, UCAS, LCAS = VIH
												Dout = High-Z
			—	1	—	1		—	1		mA	CMOS interface
			—	1	—	1		—	1		mA	CMOS interface
												RAS, UCAS, LCAS, WE,
												OE ≥ VCC – 0.2 V
												Dout = High-Z
Standby current	ICC2		—	200	—	200		—	200		A	CMOS interface
(L-version)												RAS, UCAS, LCAS, OE,
												WE ≥ VCC – 0.2 V
												Dout = High-Z
RAS-only refresh	ICC3		—	140	—	130		—	110		mA	tRC = min
current*2
Standby current*1	I	CC5	—	5	—	5		—	5		mA	RAS = V , UCAS or LCAS = V	IL
		CC5										IH	IL
												Dout = enable
CAS-before-RAS ICC6			—	140	—	130		—	110		mA	tRC = min
refresh current*2
Fast page mode	ICC7		—	150	—	130		—	120		mA	tPC = min
current1, 3
Battery backup	ICC10		—	300	—	300		—	300		A	Standby: CMOS interface
current*4 (Standby												Dout = High-Z
with CBR refresh)												CBR refresh: tRC = 250 s
(L-version)												tRAS ≤ 1 s, UCAS, LCAS = VIL
												WE, OE = VIH
Self-refresh mode	ICC11		—	1	—	1		—	1		mA	CMOS interface
current												RAS, UCAS, LCAS ≤ 0.2 V,
(HM51S4260C)												Dout = High-Z
Self-refresh mode	ICC11		—	200	—	200		—	200		A	CMOS interface
current												RAS, UCAS, LCAS ≤ 0.2 V,
(HM51S4260CL)												Dout = High-Z

HM514260C, HM51S4260C Series

DC Characteristics (Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V) (HM51(S)4260C-6R)

(Ta = 0 to 70°C, VCC = 5 V ±10%, VSS = 0 V) (HM51(S)4260C-6/7/8) (cont)

HM514260C, HM51S4260C

		-6/-6R		-7		-8
Parameter	Symbol	Min	Max	Min	Max	Min	Max	Unit	Test Conditions

Input leakage	ILI	–10	10	–10	10	–10	10	A	0	V ≤ Vin ≤ 6.5 V
current
Output leakage	ILO	–10	10	–10	10	–10	10	A	0	V ≤ Vout ≤ 6.5 V, Dout = disable
current
Output high voltage	VOH	2.4	VCC	2.4	VCC	2.4	VCC	V	High Iout = –5.0 mA
Output low voltage	VOL	0	0.4	0	0.4	0	0.4	V	Low Iout = 4.2 mA

Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition.

2.Address can be changed once or less while RAS = VIL.

3.Address can be changed once or less while UCAS and LCAS = VIH.

4.VIH ≥ VCC – 0.2 V, 0 ≤ VIL ≤ 0.2 V, Address can be changed once or less while RAS = VIL

5.All the VCC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage.

Capacitance (Ta = +25°C, VCC = 5 V ±5%) (HM51(S)4260C-6R)
(Ta = +25°C, VCC = 5 V ±10%) (HM51(S)4260C-6/7/8)
Parameter	Symbol	Typ	Max	Unit	Notes

Input capacitance (Address)	CI1	—	5	pF	1
Input capacitance (Clocks)	CI2	—	7	pF	1
Output capacitance (Data-in, Data-out)	CI/O	—	10	pF	1, 2

Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable Dout

HM514260C, HM51S4260C Series

AC Characteristics (Ta = 0 to 70°C, VCC = 5 V ±5%, VSS = 0 V)

(HM51(S)4260C-6R)*1, *14, *15, *17, *18

(Ta = 0 to 70°C, VCC = 5 V ±10%, VSS = 0 V) (HM51(S)4260C-6/7/8)*1, *14, *15, *17, *18

Test Conditions

•Input rise and fall time: 5 ns

•Input timing reference levels: 0.8 V, 2.4 V

•Input levels: 0 V, 3 V

Output load: 2 TTL gate + CL (50 pF) (HM51(S)4260C-6R) (Including scope and jig) 2 TTL gate + CL (100 pF) (HM51(S)4260-6/7/8) (Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

HM514260C, HM51S4260C

			-6/-6R		-7		-8
Parameter	Symbol		Min	Max	Min	Max	Min	Max	Unit	Notes

Random read or write cycle time	tRC	110		—	130	—	150	—	ns
RAS precharge time	tRP	40		—	50	—	60	—	ns
RAS pulse width	tRAS	60		10000	70	10000	80	10000	ns
CAS pulse width	tCAS	15		10000	20	10000	20	10000	ns	23
Row address setup time	tASR	0		—	0	—	0	—	ns
Row address hold time	tRAH	10		—	10	—	10	—	ns
Column address setup time	tASC	0		—	0	—	0	—	ns	19
Column address hold time	tCAH	15		—	15	—	15	—	ns	19
RAS to CAS delay time	tRCD	20		45	20	50	20	60	ns	8
RAS to column address delay time	tRAD	15		30	15	35	15	40	ns	9
RAS hold time	tRSH	15		—	20	—	20	—	ns
CAS hold time	tCSH	60		—	70	—	80	—	ns
CAS to RAS precharge time	tCRP	10		—	15	—	15	—	ns	20
OE to Din delay time	tODD	15		—	20	—	20	—	ns
OE delay time from Din	tDZO	0		—	0	—	0	—	ns
CAS setup time from Din	tDZC	0		—	0	—	0	—	ns
Transition time (rise and fall)	tT	3		50	3	50	3	50	ns	7
Refresh period	tREF		—	8	—	8	—	8	ms
Refresh period (L-version)	tREF		—	128	—	128	—	128	ms

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