Page 1
Hard Disk Drive Specification
Deskstar 7K80
3.5 inch Ultra ATA/133 hard disk drive
Models:
HDS728040PLAT20
HDS728080PLAT20
Version 1.6 12 September 2006
Page 2
Page 3
Hard Disk Drive Specification
Deskstar 7K80
3.5 inch Ultra ATA/133 hard disk drive
Models:
HDS728040PLAT20
HDS728080PLAT20
Version 1.6 12 September 2006
Page 4
1st Edition (Revision 1.3) (22 September 2005) Revised
2nd Edition (Revision 1.4)(16 December 2005) Revised
3rd Edition (Revision 1.5)(05 May 2006) Revised
4th Edition (Revision 1.6)(12 September 2006) Final
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Page 5
Table Of Contents
1.0 General................................................................................................................11
1.1 Introduction..............................................................................................11
1.2 References................................................................................................11
1.3 Abbreviations...........................................................................................11
1.4 Caution.....................................................................................................13
2.0 General features of the drive ............................................................................15
3.0 Fixed-disk subsystem description.....................................................................19
3.1 Control electronics...................................................................................19
3.2 Head disk assembly ................................................................................19
3.3 Actuator ...................................................................................................19
4.0 Drive characteristics..........................................................................................21
4.1 Default logical drive parameters..............................................................21
4.2 Data sheet.................................................................................................22
4.3 World Wide Name Assignment...............................................................22
4.4 Drive organization ...................................................................................22
4.4.1 Drive format....................................................................................22
4.4.2 Cylinder allocation..........................................................................23
4.5 Performance characteristics.....................................................................24
4.5.1 Command overhead........................................................................24
4.5.2 Mechanical positioning...................................................................24
4.5.3 Drive ready time .............................................................................26
4.5.4 Data transfer speed..........................................................................27
4.5.5 Throughput......................................................................................28
4.5.6 Operating modes.............................................................................29
5.0 Defect flagging strategy.....................................................................................31
6.0 Electrical interface specification.......................................................................33
6.1 Connector location...................................................................................33
6.1.1 DC power connector.......................................................................33
6.1.2 AT signal connector........................................................................33
6.2 Signal definitions.....................................................................................34
6.3 Signal descriptions...................................................................................35
6.4 Interface logic signal levels .....................................................................38
6.5 Reset timings............................................................................................38
6.6 PIO timings..............................................................................................39
6.6.1 Write DRQ interval time.................................................................39
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6.6.2 Read DRQ interval time .................................................................39
6.7 Multi-word DMA timings........................................................................41
6.8 Ultra DMA timings..................................................................................42
6.8.1 Initiating Read DMA ......................................................................42
6.8.2 Host Pausing Read DMA................................................................43
6.8.3 Host Terminating Read DMA.........................................................44
6.8.4 Device Terminating Read DMA.....................................................45
6.8.5 Initiating Write DMA .....................................................................46
6.8.6 Device Pausing Write DMA...........................................................47
6.8.7 Device Terminating Write DMA....................................................48
6.8.8 Host Terminating Write DMA........................................................49
6.9 Addressing of registers ............................................................................50
6.9.1 Cabling............................................................................................50
7.0 Specification .......................................................................................................53
7.1 Jumper settings ........................................................................................53
7.1.1 Jumper pin location.........................................................................53
7.1.2 Jumper pin identification ................................................................53
7.1.3 Jumper pin assignment....................................................................54
7.1.4 Jumper positions .............................................................................54
7.2 Environment.............................................................................................58
7.2.1 Temperature and humidity..............................................................58
7.2.2 Corrosion test..................................................................................59
7.3 DC power requirements...........................................................................59
7.3.1 Input voltage ...................................................................................59
7.3.2 Power supply current (typical)........................................................60
7.3.3 Power supply generated ripple at drive power connector...............60
7.4 Reliability.................................................................................................61
7.4.1 Data integrity ..................................................................................61
7.4.2 Cable noise interference..................................................................61
7.4.3 Start/stop cycles..............................................................................61
7.4.4 Preventive maintenance..................................................................61
7.4.5 Data reliability ................................................................................61
7.4.6 Required power-off sequence.........................................................61
7.5 Mechanical specifications........................................................................62
7.5.1 Physical dimensions and weight.....................................................62
7.5.2 Mounting hole locations .................................................................63
7.5.3 Connector locations ........................................................................63
7.5.4 Drive mounting...............................................................................64
7.5.5 Heads unload and actuator lock......................................................64
7.6 Vibration and shock.................................................................................65
7.6.1 Operating vibration.........................................................................65
7.6.2 Nonoperating vibration...................................................................65
7.6.3 Operating shock..............................................................................66
7.6.4 Nonoperating shock........................................................................66
7.6.5 Nonoperating rotational shock........................................................67
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7.7 Acoustics..................................................................................................68
7.8 Identification labels..................................................................................68
7.9 Safety .......................................................................................................69
7.9.1 UL and CSA approval.....................................................................69
7.9.2 German safety mark........................................................................69
7.9.3 Flammability...................................................................................69
7.9.4 Safe handling ..................................................................................69
7.9.5 Environment....................................................................................69
7.9.6 Secondary circuit protection...........................................................69
7.10 Electromagnetic compatibility...............................................................70
7.10.1 C-TICK mark................................................................................70
7.10.2 BSMI mark ...................................................................................70
7.11 Packaging...............................................................................................70
8.0 General................................................................................................................71
8.1 Introduction..............................................................................................71
8.2 Terminology.............................................................................................71
8.3 Deviations from standard.........................................................................71
9.0 Registers..............................................................................................................73
9.1 Register set...............................................................................................73
9.2 Alternate Status Register .........................................................................74
9.3 Command Register ..................................................................................74
9.4 Cylinder High Register............................................................................74
9.5 Cylinder Low Register.............................................................................74
9.6 Data Register............................................................................................75
9.7 Device Control Register..........................................................................75
9.8 Drive Address Register............................................................................76
9.9 Device/Head Register ..............................................................................76
9.10 Error Register.........................................................................................77
9.11 Features Register....................................................................................77
9.12 Sector Count Register............................................................................77
9.13 Sector Number Register.........................................................................78
9.14 Status Register .......................................................................................78
10.0 General operation............................................................................................81
10.1 Reset response........................................................................................81
10.2 Register initialization.............................................................................82
10.3 Diagnostic and Reset considerations .....................................................83
10.4 Sector Addressing Mode........................................................................84
10.4.1 Logical CHS addressing mode .....................................................84
10.4.2 LBA addressing mode ..................................................................84
10.5 Power management features..................................................................85
10.5.1 Power mode ..................................................................................85
10.5.2 Power management commands ....................................................85
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10.5.3 Standby timer................................................................................85
10.5.4 Interface capability for power modes ...........................................86
10.6 S.M.A.R.T. Function .............................................................................87
10.6.1 Attributes ......................................................................................87
10.6.2 Attribute values.............................................................................87
10.6.3 Attribute thresholds.......................................................................87
10.6.4 Threshold exceeded condition ......................................................87
10.6.5 S.M.A.R.T. commands .................................................................87
10.6.6 Off-line read scanning ..................................................................87
10.6.7 Error log........................................................................................88
10.6.8 Self-test.........................................................................................88
10.7 Security Mode Feature Set.....................................................................89
10.7.1 Security mode ...............................................................................89
10.7.2 Security level ................................................................................89
10.7.3 Passwords......................................................................................90
10.7.4 Operation example........................................................................90
10.7.5 Command table.............................................................................94
10.8 Host Protected Area Feature..................................................................96
10.8.1 Example for operation (In LBA Mode)........................................96
10.8.2 Security extensions .......................................................................97
10.9 Seek overlap...........................................................................................98
10.10 Write cache function............................................................................99
10.11 Reassign function.................................................................................100
10.11.1 Auto Reassign function...............................................................100
10.12 Power-Up in Standby feature set .........................................................101
10.13 Advanced Power Management feature set (APM) ..............................102
10.14 Automatic Acoustic Management feature set (AAM).........................103
10.15 Address Offset Feature ........................................................................104
10.15.1 Enable/Disable Address Offset Mode.........................................104
10.15.2 Identify Device Data...................................................................105
10.15.3 Exceptions in Address Offset Mode..........................................105
10.16 48-bit Address Feature Set...................................................................106
10.17 Streaming feature Set...........................................................................106
10.17.1 Streaming commands..................................................................107
10.17.2 Urgent bit....................................................................................107
10.17.3 Flush to Disk bit..........................................................................107
10.17.4 Not Sequential bit .......................................................................108
10.17.5 Read Continuous bit....................................................................108
10.17.6 Write Continuous bit...................................................................108
10.17.7 Handle Streaming Error bit.........................................................108
10.17.8 Streaming Logs...........................................................................108
11.0 Command protocol ..........................................................................................109
11.1 PIO Data In commands..........................................................................109
11.2 PIO Data Out Commands ......................................................................110
11.3 Non-data commands .............................................................................112
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11.4 DMA commands....................................................................................113
12.0 Command descriptions....................................................................................115
12.1 Check Power Mode (E5h/98h) ..............................................................120
12.2 Configure Stream (51h) .........................................................................121
12.3 Device Configuration Overlay (B1h) ....................................................123
12.3.1 DEVICE CONFIGURATION RESTORE (Subcommand C0h).123
12.3.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)123
12.3.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h).124
12.3.4 DEVICE CONFIGURATION SET (subcommand C3h).............124
12.4 Download Microcode (92h)...................................................................127
12.5 Execute Device Diagnostic (90h) ..........................................................129
12.6 Flush Cache (E7h) .................................................................................130
12.7 Flush Cache Ext (EAh)..........................................................................131
12.8 Format Track (50h)................................................................................132
12.9 Format Unit (F7h)..................................................................................134
12.10 Identify Device (ECh)..........................................................................135
12.11 Idle (E3h/97h).....................................................................................143
12.12 Idle Immediate (E1h/95h)....................................................................144
12.13 Initialize Device Parameters (91h) ......................................................145
12.14 Read Buffer (E4h)................................................................................146
12.15 Read DMA (C8h/C9h).........................................................................147
12.16 Read DMA Ext (25h)...........................................................................149
12.17 Read Log Ext (2Fh) .............................................................................151
12.17.1 General Purpose Log Directory..................................................153
12.17.2 Extended Comprehensive SMART Error Log............................154
12.17.3 Extended Self-test log sector ......................................................156
12.17.4 Read Stream Error Log...............................................................157
12.17.5 Write Stream Error Log..............................................................158
12.17.6 Streaming Performance Log.......................................................159
12.18 Read Long (22h/23h)...........................................................................161
12.19 Read Multiple (C4h)............................................................................163
12.20 Read Multiple Ext (29h) ......................................................................164
12.21 Read Native Max ADDRESS (F8h)....................................................166
12.22 Read Native Max Address Ext (27h)...................................................167
12.23 Read Sectors (20h/21h)........................................................................168
12.24 Read Sector(s) Ext (24h)......................................................................170
12.25 Read Stream DMA (2Ah)....................................................................172
12.26 Read Stream PIO (2Bh).......................................................................176
12.27 Read Verify Sectors (40h/41h) ............................................................179
12.28 Read Verify Sectors Ext (42h).............................................................181
12.29 Recalibrate (1xh)..................................................................................183
12.30 Security Disable Password (F6h).........................................................184
12.31 Security Erase Prepare.........................................................................185
12.32 Security Erase Unit (F4h) ....................................................................186
12.33 Security Freeze Lock (F5h) .................................................................188
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12.34 Security Set Password (F1h)................................................................189
12.35 Security Unlock (F2h) .........................................................................191
12.36 Seek (7xh)...........................................................................................193
12.37 Set Features (EFh) ...............................................................................194
12.37.1 Set Transfer mode.......................................................................195
12.37.2 Write Cache ................................................................................195
12.37.3 Advanced Power Management...................................................195
12.37.4 Automatic Acoustic Management ..............................................197
12.38 Set Max ADDRESS (F9h)...................................................................198
12.38.1 Set Max Set Password (Feature=01h).........................................200
12.38.2 Set Max Lock (Feature=02h)......................................................201
12.38.3 Set Max Unlock (Feature = 03h) ................................................202
12.38.4 Set Max Freeze Lock (Feature = 04h) ........................................203
12.39 Set Max Address Ext (37h)..................................................................204
12.40 Set Multiple (C6h) ...............................................................................206
12.41 Sleep (E6h/99h) ...................................................................................207
12.42 S.M.A.R.T. Function Set (B0h)...........................................................208
12.42.1 S.M.A.R.T. Function Subcommands.........................................209
12.42.2 Device Attribute Data Structure .................................................213
12.42.3 Device Attribute Thresholds data structure ................................216
12.42.4 S.M.A.R.T. Log Directory..........................................................218
12.42.5 S.M.A.R.T. summary error log sector ........................................218
12.42.6 Self-test log data structure .........................................................220
12.42.7 Error reporting ............................................................................221
12.43 Standby (E2h/96h)...............................................................................222
12.44 Standby Immediate (E0h/94h).............................................................224
12.45 Write Buffer (E8h)...............................................................................225
12.46 Write DMA (CAh/CBh) ......................................................................226
12.47 Write DMA Ext (35h)..........................................................................228
12.48 Write Log Ext (3Fh) ............................................................................230
12.49 Write Long (32h/33h)..........................................................................231
12.50 Write Multiple (C5h) ...........................................................................233
12.51 Write Multiple Ext (39h) .....................................................................235
12.52 Write Sectors (30h/31h).......................................................................237
12.53 Write Sectors Ext.................................................................................239
12.54 Write Stream DMA (3Ah)...................................................................241
12.55 Write Stream PIO (3Bh) ......................................................................243
13.0 Timings .............................................................................................................247
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List of Tables
Table 1.Formatted capacities.....................................................................................21
Table 2.Mechanical positioning performance ...........................................................22
Table 3.Word Wide Name Assignment.....................................................................22
Table 4.Cylinder allocation........................................................................................23
Table 5.Command overhead......................................................................................24
Table 6.Mechanical positioning performance ...........................................................24
Table 7.Full stroke seek time.....................................................................................25
Table 8.Head switch time ..........................................................................................25
Table 9.Single track seek time...................................................................................26
Table 10.Latency Time..............................................................................................26
Table 11.Drive ready time .........................................................................................26
Table 12.Data transfer speed .....................................................................................27
Table 13.Simple Sequential Access performance......................................................28
Table 14.Random Access Performance.....................................................................28
Table 15.Description of operating modes..................................................................29
Table 16.Mode transition times .................................................................................29
Table 17.PATA Plist physical format........................................................................31
Table 18.Signal definitions........................................................................................34
Table 19.Special signal definitions for Ultra DMA...................................................35
Table 20.System reset timing chart............................................................................38
Table 21.System reset timing.....................................................................................38
Table 22.PIO cycle timings chart ..............................................................................39
Table 23.Multiword DMA cycle timing chart...........................................................41
Table 24.Multiword DMA cycle timings ..................................................................41
Table 25.Ultra DMA cycle timings (Initiating Read)................................................42
Table 26.Ultra DMA cycle timing chart (Host pausing Read)..................................43
Table 27.Ultra DMA cycle timings (Host pausing Read) .........................................43
Table 28.Ultra DMA cycle timing chart (Host pausing Read)..................................44
Table 29.Ultra DMA cycle timings (Host pausing Read) .........................................44
Table 30.Ultra DMA cycle timing chart (Host pausing Read)..................................45
Table 31.Ultra DMA cycle timings (Device Terminating Read) ..............................45
Table 32.Ultra DMA cycle timing chart (Initiating Write) .......................................46
Table 33.Ultra DMA cycle timing chart (Device Pausing Write).............................47
Table 34.Ultra DMA cycle timings (Device Pausing Write).....................................47
Table 35.Ultra DMA cycle timing chart (Device Terminating Write)......................48
Table 36.Ultra DMA cycle timings (Device TerminatingWrite)...............................48
Table 37.Ultra DMA cycle timing chart (Host Terminating Write)..........................49
Table 38.Ultra DMA cycle timings (Host Terminating Write) .................................49
Table 39.I/O address map..........................................................................................50
Table 40.Jumper positions for capacity clip to 32GB ...............................................56
Table 41.Jumper settings for Disabling Auto Spin....................................................56
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Table 42.Temperature and humidity..........................................................................58
Table 43.Limits of temperature and humidity ...........................................................59
Table 44.Input voltage...............................................................................................59
Table 45.Power supply current of 80GB and 40GB models .....................................60
Table 46.Power supply generated ripple at drive power connector...........................60
Table 47.Random vibration PSD...............................................................................65
Table 48.Random vibration PSD profile break points (operating)............................65
Table 49.Random Vibration PSD profile breakpoints (nonoperating)......................65
Table 50.Sinusoidal shock wave................................................................................67
Table 51.Rotational shock .......................................................................................67
Table 52.Sound power levels.....................................................................................68
Table 53.Register Set.................................................................................................73
Table 54.Alternate Status Register ............................................................................74
Table 55.Device Control Register .............................................................................75
Table 56.Drive Address Register...............................................................................76
Table 57.Device Head/Register.................................................................................76
Table 58.Error Register..............................................................................................77
Table 59.Status Register ............................................................................................78
Table 60.Reset response table....................................................................................81
Table 61.Default Register Values..............................................................................82
Table 62.Diagnostic codes.........................................................................................82
Table 63.Reset error register values ..........................................................................83
Table 64.Power conditions ........................................................................................86
Table 65.Initial setting...............................................................................................91
Table 66.Usual operation for POR ............................................................................92
Table 67.Password lost ..............................................................................................93
Table 68.Seek overlap................................................................................................98
Table 69.Device address map before and after Set Feature.......................................104
Table 70.Command Set..............................................................................................115
Table 71.Command Set (subcommand).....................................................................118
Table 72.Check Power Mode command (E5h/98h)...................................................120
Table 73.Configure Stream (51h)..............................................................................121
Table 74.Check Power Mode Command (E5h/98h)..................................................123
Table 75.Device Configuration Overlay Features register values.............................123
Table 76.Device Configuration Overlay Data structure............................................125
Table 77.DCO error information definition...............................................................126
Table 78.Downlad Microcode Command (92h)........................................................127
Table 79.Execute Device Diagnostic command (90h) ..............................................129
Table 80.Flush Cache command (E7h)......................................................................130
Table 81.Flush Cache Ext Command (EAh) .............................................................131
Table 82.Format Track command (50h)....................................................................132
Table 83.Format Unit command (F7h)......................................................................134
Table 84.Identify Device command (ECh)................................................................135
Table 85.Identify device information (Part 1 of 7)....................................................136
Table 86.Identify device information (Part 2 of 7)...................................................137
Table 87.Identify device information (Part 3 of 7)....................................................138
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Table 88.Identify device information (Part 4 of 7)....................................................139
Table 89.Identify device information (Part 5 of 7)....................................................140
Table 90.Identify device information (Part 6 of 7)....................................................141
Table 91.Identify device information (Part 7 of 7)....................................................142
Table 92.Idle command (E3h/97h)............................................................................143
Table 93.Idle Immediate command (E1h/95h)..........................................................144
Table 94.Initialize Device Parameters command (91h).............................................145
Table 95.Read Buffer (E4h).......................................................................................146
Table 96.Read DMA command (C8h/C9h)...............................................................147
Table 97.Read DMA Ext Command (25h)................................................................149
Table 98.Read Log Ext Command (2Fh)...................................................................151
Table 99.Log Address Definition ..............................................................................152
Table 100.General Purpose Log Directory................................................................153
Table 101.Extended Comprehensive SMART Error Log .........................................154
Table 102.Extended Error log data structure.............................................................154
Table 103.Command data structure...........................................................................155
Table 104.Error data structure ...................................................................................155
Table 105.Read Stream Error Log.............................................................................157
Table 106.Stream Error Log entry.............................................................................158
Table 107.Write Stream Error Log............................................................................159
Table 108.Streaming Performance Parameters log....................................................160
Table 109.Sector Time Array Entry (Linearly Interpolated).....................................160
Table 110.Access Time Array Entry (Linearly Interpolated)....................................160
Table 111.Read Long (22h/23h)................................................................................161
Table 112.Read Multiple (C4h).................................................................................163
Table 113.Read DMA Ext Command (25h)..............................................................164
Table 114.Read Native Max ADDRESS (F8h).........................................................166
Table 115.Read Native Max Address Ext command (27h).......................................167
Table 116.Read Sectors Command (20h/21h)...........................................................168
Table 117.Read Sector(s) Ext command (24h).........................................................170
Table 118.Read Stream DMA Command (2Ah) .......................................................172
Table 119.Read Stream PIO (2Bh)............................................................................176
Table 120.Read Verify Sectors (40h/41h).................................................................179
Table 121.Read Verify Sectors Ext command (42h).................................................181
Table 122.Recalibrate (1xh) ......................................................................................183
Table 123.Security Disable Password (F6h)..............................................................184
Table 124.Password Information for Security Disable Password command.............184
Table 125.Security Disable Password (F3h)..............................................................185
Table 126.Security Erase Unit (F4h).........................................................................186
Table 127.Erase Unit information .............................................................................186
Table 128.Security Freeze Lock command (F5h) .....................................................188
Table 129.Security Set Password command (F1h)....................................................189
Table 130.Security Set Password Information ..........................................................189
Table 131.Security Unlock command (F2h)..............................................................191
Table 132.Seek command (7xh)................................................................................193
Table 133.Set Features command (EFh)....................................................................194
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Table 134.Set Max ADDRESS command (F9h).......................................................198
Table 135.Set Max Set Password command..............................................................200
Table 136.Set Max Set Password data contents ........................................................200
Table 137.Set Max Lock command...........................................................................201
Table 138.Set Max Unlock command (F9h) .............................................................202
Table 139.Set Max Freeze Lock (F9h)......................................................................203
Table 140.Set Max Address Ext command (37h)......................................................204
Table 141.Set Multiple command (C6h) ...................................................................206
Table 142.Sleep command (E6h/99h) .......................................................................207
Table 143.S.M.A.R.T. Function Set command (B0h)...............................................208
Table 144.Device Attribute Data Structure ...............................................................213
Table 145.Individual Attribute Data Structure ..........................................................213
Table 146.Device Attribute Thresholds Data Structure.............................................217
Table 147.Individual Threshold Data Structure ........................................................217
Table 148.S.M.A.R.T. Log Directory........................................................................218
Table 149.S.M.A.R.T. summary error log sector ....................................................218
Table 150.Error log data structure............................................................................219
Table 151.Command data structure...........................................................................219
Table 152.Error data structure ...................................................................................219
Table 153.Self-test log data structure ........................................................................220
Table 154.S.M.A.R.T. Error Codes...........................................................................221
Table 155.Standby (E2h/96h)....................................................................................222
Table 156.Standby Immediate (E0h/94h)..................................................................224
Table 157.Write Buffer (E8h)....................................................................................225
Table 158.Write DMA (CAh/CBh) ...........................................................................226
Table 159.Write DMA Ext Command (35h)............................................................228
Table 160.Write Log Ext Command (3Fh)...............................................................230
Table 161.Write Long (32h/33h)...............................................................................231
Table 162.Write Multiple (C5h)................................................................................233
Table 163.WriteMultiple Ext Command (39h)..........................................................235
Table 164.Write Sectors command (30h/31h)...........................................................237
Table 165.Write Sectors Ext......................................................................................239
Table 166.Write Stream DMA Command (3Ah) ......................................................241
Table 167.Write Stream PIO Command (3Bh) .........................................................243
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1.0 General
1.1 Introduction
This document describes the specifications of the Deskstar 7K80, a 3.5-inch hard disk drive with A TA interface and
a rotational speed of 7200 RPM.
HDS728040PLAT20 41.1GB
HDS728080PLAT20 82.3GB
For Serial ATA function specification, please refer to ’Serial ATA function - Addendum.’
These specifications are subject to change without notice.
1.2 References
• Information Technology - AT Attachment with Packet Interface-7.
1.3 Abbreviations
Abbreviation Meaning
AAmpere
AC alternating current
AT Advanced Technology
ATA Advanced Technology Attachment
BIOS Basic Input/Output System
C Celsius
CSA Canadian Standards Association
C-UL Canadian-Underwriters Laborato ry
Cyl cylinder
DC Direct Current
DFT Drive Fitness Test
DMA Direct Memory Access
ECC error correction code
EEC European Economic Community
EMC electromagnetic compatibility
ERP Error Recovery Procedure
ESD E lectrostatic Discharge
FCC Federal Com munications Commission
FRU field replacement unit
G gravity (a unit of force)
2
G
/Hz (32 ft/sec)2 per Hertz
Gb 1,000,000,000 bits
GB 1,000,000,000 bytes
Deskstar 7K80 Hard Disk Drive Specification
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GND ground
h hexadecimal
HDD hard disk drive
Hz Hertz
I Input
ILS integrated lead suspension
I/O Input/Output
ISO International Standards Organization
KB 1,000 bytes
Kbpi 1000 bits per inch
kgf-cm kilogram (force)-centimeter
KHz kilohertz
LBA logical block addressing
Lw unit of A-weighted sound power
mmeter
max maximum
MB 1,000,000 bytes
Mbps 1,000,000 bits per second
MHz megahertz
MLC Machine Level Control
mm millimeter
ms millisecond
us, ms microsecond
OOutput
OD Open Drain Programmed Input/Output
POH power on hours
Pop population
P/N part number
p-p peak-to-peak
PSD power spectral density
RES radiated electromagnetic susceptibility
RFI radio frequency interference
RH relative humidity
RMS root mea n square
RPM revolu t ions per minute
RST reset
R/W read/write
sec second
SELV secondary low voltage
S.M.A.R.TSelf-Monitoring, Analysis, and Reporting Technology
TPI tracks per inch
Trk track
TTL transistor-transistor logic
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UL Underwriters Laboratory
Vvolt
VDE Verband Deutscher Electrotechniker
Wwatt
3-state transistor-transistor tristate logic
1.4 Caution
• Do not apply force to the top cover.
• Do not cover the breathing hole on the top cover.
• Do not touch the interface connector pins or the surface of the printed circuit board
• This drive can be damaged by electrostatic discharge (ESD). Any damages incurred to the drive after its
removal from the shipping package and the ESD protective bag are the responsibility of the user.
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2.0 General features of the drive
• Formatted capacities of 40 GB and 80 GB
• Spindle speeds of 7200 RPM
• Fluid Dynamic Bearing motor
• Enhanced IDE interface
• Sector format of 512 bytes/sector
• Closed-loop actuator servo
• Load/Unload mechanism, non head disk contact start/stop
• Automatic Actuator lock
• Interleave factor 1:1
• Seek time of 8.8 ms in Read Operation. 8.5 ms typical without Command Overhead
• Sector Buffer size of 2048 K (Upper 270 KB is used for firmware)
• Ring buffer implementation
• Write Cache
• Advanced ECC On The Fly (EOF)
• Automatic Error Recovery procedures for read and write commands
• Self Diagnostics on Power on and resident diagnostics
• PIO Data Transfer Mode 4 (16.6 MB/s)
• DMA Data Transfer
• Multiword mode Mode 2 (16.6 MB/s)
• Ultra DMA Mode 6 (133 MB/s)
• CHS and LBA mode
• Power saving modes/Low RPM idle mode (APM)
• S.M.A.R.T. (Self Monitoring and Analysis Reporting Technology)
• Support security feature
• Quiet Seek mode (AAM)
• 48-bit addressing feature
• Adaptive BPI
• ATA -7 co mpliant
• UDMA 133 support
• Streaming feature set support
• World Wide Name
Note: For serial ATA model, please refer "Serial ATA Function Specification - Addendum."
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Part 1. Functional specification
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3.0 Fixed-disk subsystem description
3.1 Control electronics
The drive is electronically controlled by a microprocessor, several logic modules, digital/analog modules, and various drivers and receivers. The control electronics performs the following major functions:
• Controls and interprets all interface signals between the host controller and the drive.
• Controls read write accessing of the disk media, including defect management and error
recovery.
• Controls starting, stopping, and monitoring of the spindle.
• Conducts a power-up sequence and calibrates the servo.
• Analyzes servo signals to provide closed loop control. These include position error signal and
estimated velocity.
• Monitors the actuator position and determines the target track for a seek operation.
• Controls the voice coil motor driver to align the actuator in a desired position.
• Constantly monitors error conditions of the servo and takes corresponding action if an error
occurs.
• Monitors various timers such as head settle and servo failure.
• Performs self-checkout (diagnostics).
3.2 Head disk assembly
The head disk assembly (HDA) is assembled in a clean room environment and contains the disks and actuator
assembly. Air is constantly circulated and filtered when the drive is operational. Venting of the HDA is accomplished via a breather filter.
The spindle is driven directly by an in-hub, brushless, sensorless DC drive motor. Dynamic braking is used to
quickly stop the spindle.
3.3 Actuator
The read/write heads are mounted in the actuator. The actuator is a swing-arm assembly driven by a voice coil
motor . A closed-loop position ing servo controls the movement of the actuator. An embedded servo pattern supplies
feedback to the positioning servo to keep the read/write heads centered over the desired track.
The actuator assembly is balanced to allow vertical or horizontal mounting without adjustment.
When the drive is powered off, the actuator automatically moves the head to the actuator ramp outside of the disk
where it parks.
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4.0 Drive characteristics
4.1 Default logical drive parameters
Table 1: Formatted capacities
HDS728040PLAT20 HDS728080PLAT20
Physical Layout
Label capacity (GB) 40 80
Bytes per sector 512 512
Sectors per track 567-1170 567-1170
Number of heads 1 2
Number of disks 1 1
Data sectors per cylinder 567-1170 1134-2340
Data cylinders per zone 1444-4501 1444-4501
Logical layout
Number of heads 16 16
Number of Sectors per track 63 63
Number of Cylinders
Number of sectors 80,418,240 160,836,480
Total logical data bytes 41,174,138,880 82,348,277,760
Notes:
1.
Number of cylinders: For drives with capacities greater than 8.45 GB the Identify Device information word 01
limits the number of cylinders to 16, 383 per the ATA specification.
1
2
16,383 16,383
2.
Logical layout: Logical layout is an imaginary drive parameter (that is, the number of heads) which is used to
access the drive from the system interface. The logical layout to Physical layout (that is, the actual Head and Sectors ) translation is done automatically in the drive. The default setting can be obtained by issuing an IDENTIFY
DEVICE command.
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4.2 Data sheet
Table 2: Mechanical positioning performance
Data transfer rates (Mbps) 757
Interface transfer rates (Mb/s) 133
Data buffer size
Rotational speed (RPM) 7200
Number of buffer segments (read) up to 128
Number of buffer segments (write) up to 63
Recording density - max (Kbpi) 689
Track density [TPI] 87 / 90 / 93
Areal density - max (Gbits/in
Number of data bands 30
1
(KB)
2
)
2048
62
4.3 World Wide Name Assignment
Tabl e 3: Word Wide Name Assignment
Description
Organization Hitachi GST Hitachi GST
Manufacturing Site Sriracha Plant, Thailand China
Product Deskstar 7K80 Deskstar 7K80
OUI 000CCAh 000CCAh
SHBU Block Assignment 201h 300h
Port/Node ID 11b 11b
4.4 Drive organization
4.4.1 Drive format
Upon shipment from manufacturing the drive satisfies the sector continuity in the physical format by means of the
defect flagging strategy described in Section 5.0, “Defect flagging strategy” on page 21 in order to provide the
maximum performance to users.
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4.4.2 Cylinder allocation
Table 4: Cylinder allocation
Data Zone Physical Cylinders Blk/Trk
0 1,444 1,170
1 3,095 1,147
2 3,095 1,147
3 3,389 1,134
4 3,043 1,125
5 3,845 1,080
6 3,946 1,080
7 4,501 1,026
8 4,001 1,026
9 3,232 1,012
10 3,726 990
11 3,193 972
12 4,286 945
13 3,120 918
14 3,093 900
15 3,106 877
16 4,037 855
17 4,073 810
18 3,573 810
19 3,276 742
20 2,675 742
21 2,408 720
22 1,960 702
23 1,568 675
24 1,568 675
25 2,082 630
26 2,157 630
27 1,700 607
28 1,570 594
29 1,521 567
Physical cylinder is calculated from the starting data track of 0. It is not relevant to logical CHS. Depending on the
capacity some of the inner zone cylinders are not allocated.
Data cylinder
This cylinder contains the user data which can be sent and retrieved via read/write commands and a spare area for
reassigned data.
Spare cylinder
The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a
defect location.
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4.5 Performance characteristics
Drive performance is characterized by the following parameters:
• Command overhead
• Mechanical head positioning
- Seek time
- Latency
• Data transfer speed
• Buffering operation (Look ahead/Write cache)
All the above parameters contribute to drive performance. There are other parameters that contribute to the performance of the actual system. This specification tries to define the bare drive characteristics, not system throughput,
which depends on the system and the application.
4.5.1 Command overhead
Command overhead is defined as the time required from the time the command is written into the command register by a host to the assertion of DRQ for the first data byte of a READ command when the requested data is not in
the buffer excluding Physical seek time and Latency.
The table below gives average command overhead.
Table 5: Command overhead
Command type (Drive is in quiescent state) Time (typical)
(ms)
Read (cache not hit) (from Command Write to Seek Start)
Read (cache hit) (from Command Write to DRQ)
Write (from Command Write to DRQ)
Seek (from Command Write to Seek Start)
0.3 0.3
0.1 0.1
0.015 0.05
0.3 not applicable
Time (typical) for
queued command
(ms)
4.5.2 Mechanical positioning
4.5.2.1 Average seek time (without command overhead, including settling)
Table 6: Mechanical positioning performance
Command type Typical (ms) Max (ms)
Read 40-80GB 8.5 9.5
Write 40-80GB 9.5 10.5
Read (Quiet Seek mode) 19.5 20.5
Write (Quiet Seek mode) 20.5 21.5
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The terms “Typical” and “Max” are used throughout this document and are defined as follows:
Typical The average of the drive population tested at nominal environmental and voltage conditions.
Max Maximum value measured on any one drive over the full range of the environmental and voltage
conditions. The seek time is measured from the start of the actuator’s motion to the start of a reliable read or write operation. A reliable read or write implies that error correction or recovery is not
used to correct arrival problems. The average seek time is measured as the weighted average of all
possible seek combinations.
max
Σ (m10 n)(Tnin + Tnout)
n=1
Weighted Average = ––––––––––––––––––––––––––––
(max + 1)(max)
where
max = Maximum seek length
n= Seek length (1 to max)
Tnin = Inward measured seek time for an n track seek
Tnout = Outward measured seek time for an n track seek
4.5.2.2 Full stroke seek time (without command overhead, including settling)
Table 7: Full stroke seek time
Function Ty pical (ms) Max (ms)
Read 40-80GB 15.1 18.1
Write 40-80GB 16.1 19.1
Read (Quiet Seek mode) 32.5 35.5
Write (Quiet Seek mode) 33.5 36.5
Full stroke seek is measured as the average of 1,000 full stroke seeks with a random head switch from both directions (inward and outward).
4.5.2.3 Head switch time (head skew)
Table 8: Head switch time
Head switch time-typical (ms)
90 kTPI 1.4
Head switch time is defined as the amount of time required by the fixed disk to complete a seek of the next sequential track after reading the last sector in the current track
The measuring method is given in 4.5.5, “Throughput” on page 28.
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4.5.2.4 Cylinder switch time (cylinder skew)
Cylinder switch time - typical (ms)
1.6
Cylinder switch time is defined as the amount of time required by the fixed disk to access the next sequential block
after reading the last sector in the current cylinder.
The measuring method is given in Section 4.5.5, “Throughput” on page 28.
4.5.2.5 Single track seek time (without command overhead, including settling)
Tabl e 9: Single track seek time
Function Typical (ms) Max (ms)
Read 0.8 1.5
Write 1.3 2.0
Read (Quiet Seek mode) 0.8 1.5
Write (Quiet Seek mode) 1.3 2.0
Single track seek is measured as the average of one (1) single track seek from every track in both directions
(inward and outward).
4.5.2.6 Average latency
Table 10: Latency Time
Rotational speed
(RPM)
Time for one
revolution (ms)
Average latency
(ms)
7200 RPM 8.3 4.17
4.5.3 Drive ready time
Table 11: Drive ready time
Power on to ready Typical (sec) Maximum (sec)
620
Ready The condition in which the drive is able to perform a media access command (for exam-
ple- read, write) immediately.
Power on This includes the time required for the internal self diagnostics.
Note: Max Power On to ready time is the maximum time period that Device 0 waits for Device 1 to assert PDIAG.
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4.5.4 Data transfer speed
Table 12: Data transfer speed
Data transfer speed
Disk-Buffer transfer (Zone 0)
Instantaneous - typical 66
Sustained - read typical 61.1
Disk-Buffer transfer (Zone 29)
Instantaneous - typical 34.5
Sustained - read typical 29.6
Buffer - host (max) 133
(Mbytes/sec)
• Instantaneous disk-buffer transfer rate (Mbyte/s) is derived by the following formula:
512 (Number of sectors on a track) (revolutions per second)
Note: The number of sectors per track will vary because of the linear density recording.
• Sustained disk-buffer transfer rate (Mbyte/s) is defined by considering head/cylinder change time
for read operation. This gives a local average data transfer rate. It is derived by the following formula:
(Sustained Transfer Rate) = A/(B+C+D)
where
A = 512 (number of data sectors per cylinder)
B = (number of Surfaces per cylinder – 1) (head switch time)
C = cylinder change time
D = (number of surfaces) (time for one revolution)
• Instantaneous buffer-host transfer rate (Mbyte/s) defines the maximum data transfer rate on the
AT Bus. It also depends on the speed of the host.
The method of measurement is given in 4.5.5, “Throughput” on page 28.
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4.5.5 Throughput
4.5.5.1 Simple sequential access
The following table illustrates simple sequential access for the enclosure.
Table 13: Simple Sequential Access performance
Operation Typical (sec) Max (sec)
Sequential Read (Zone 0) 0.3 0.32
Sequential Read (Zone 29) 0.61 0.63
The above table gives the time required to read a total of 8000h consecutive blocks (16,777,216 bytes) accessed by
128 read commands. Typical and Max values are given by 105% and 110% of T respectively throughout following
performance description.
T = A + B + C + 16,777,216/D + 512/E (READ)
where
T = Calculated time (sec)
A = Command process time (Command overhead) (sec)
B = Average seek time (sec)
C = Average latency (sec)
D = Sustained disk-buffer transfer rate (byte/sec)
E = Buffer-host transfer rate (byte/sec)
Note: It is assumed that a host system responds instantaneously and host data transfer is faster than sustained data
rate.
4.5.5.2 Random access
The following table illustrates simple sequential access for enclosure.
Table 14: Random Access Performance
Operation Typical (sec) Max (sec)
Random Read 55.9 58.6
The above table gives the time required to execute a total of 1000h read commands which access a single random
LBA. Typical and Max values are given by 105% and 110% of T respectively throughout following performance
description.
T = 4096(A + B + C+ 512/D + 512/E) (READ)
where
T = Calculated time (sec)
A = Command process time (Command overhead) (sec)
B = Average seek time (sec)
C = Latency
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D = Average sustained disk-buffer transfer rate (byte/s)
E = Buffer-host transfer rate (byte/s)
4.5.6 Operating modes
4.5.6.1 Description of operating modes
Table 15: Description of operating modes
Operating mode Description
Spin-up
Seek
Write
Read
Unload Idle
Idle
Standby
Sleep
Start up time period from spindle stop or power down.
Seek operation mode
Write operation mode
Read operation mode
Spindle rotation at 7200 RPM with heads unloaded.
Spindle motor and servo system are working normally. Commands can be received and processed immediately.
Actuator is unloaded and spindle motor is stopped. Commands can be received immediately.
TActuator is unloaded and spindle motor is stopped. Only soft reset or hard reset can change
the mode to standby.
Note: Upon power down or spindle stop a head locking mechanism will secure the heads in the OD parking position.
4.5.6.2 Mode transition time
Table 16: Mode transition times
From To RPM
Standby Idle 0 ---> 7200 6 20
Idle Standby 7200 ---> 0 Immediately Immediately
Standby Sleep 0 Immediately Immediately
Sleep Standby 0 Immediately Immediately
Unload idle Idle 7200 0.7 20
Idle Unload idle 7 200 0.7 20
Low RPM Idle Idle 4500 ---> 7200 3 20
Transition time (sec)
Typical Maximum
Note: The command is processed immediately (within 1ms) but there will be an actual spin down time reflecting
the seconds passed until the spindle motor stops.
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5.0 Defect flagging strategy
Media defects are remapped to the next available sector during the Format Process in manufacturing. The
mapping from LBA to the physical locations is calculated by an internally maintained table.
Shipped format
• Data areas are optimally used.
• No extra sector is wasted as a spare throughout user data areas.
• All pushes generated by defects are absorbed by the spare tracks of the inner zone.
Table 17: P ATA Plist physical format
NN+1 N+2 N+3
Defects are skipped without any constraint, such as track or cylinder boundary.
defect defect
skip
skip
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6.0 Electrical interface specification
6.1 Connector location
Refer to the following illustration to see the location of the connectors
Figure 1 : Connector location
6.1.1 DC power connector
The DC power connector is designed to mate with AMP part number 1-480424-0 using AMP pins part number
350078-4 (strip), part number 61173-4 (loose piece), or their equivalents. Pin assignments are shown in the figure
below.
Pin Voltage
4 3 2 1
1+12 V
2GND
3GND
4+5V
6.1.2 AT signal connector
The AT signal connector is a 40-pin connector.
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6.2 Signal definitions
The pin assignments of interface signals are listed as follows:
Table 18: Signal definitions
PIN SIGNAL I/O Type PIN SIGNAL I/O Type
01 RESET- I TTL
03 DD7 I/O 3–state
05 DD6 I/O 3–state
07 DD5 I/O 3–state
09 DD4 I/O 3–state
11 DD3 I/O 3–state
13 DD2 I/O 3–state
15 DD1 I/O 3–state
17 DD0 I/O 3–state
19 GND
21 DMARQ O 3–state
23 DIOW-(*) I TTL
25 DIOR-(*) I TTL
27 IORDY-(*) O 3–state
29 DMACK- I TTL
31 INTRQ O 3–state
33 DA1 I TTL
35 DA0 I TTL
37 CS0- I TTL
02 GND
04 DD08 I/O 3–state
06 DD09 I/O 3–state
08 DD10 I/O 3–state
10 DD11 I/O 3–state
12 DD12 I/O 3–state
14 DD13 I/O 3–state
16 DD14 I/O 3–state
18 DD15 I/O 3–state
(20) Key
22 GND
24 GND
26 GND
28 CSEL I TTL
30 GND
32
34 PDIAG- I/O OD
36 DA02 I TTL
38 CS1- I TTL
39 DASP- I/O OD
40 GND
Notes:
O designates an output from the drive
I desi gnates an input to the drive
I/O designates an input/outp ut common
OD designates an Open-Drain output
The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special functions. These
lines change from the conventional to special definitions at the moment the host decides to allow a DMA burst, if
the Ultra DMA transfer mode was previously ch os e n vi a Set Features. The drive becomes aware of this change
upon assertion of the DMACK- line. These lines revert back to their original definitions upon the deassertion of
DMACK- at the termination of the DMA burst.
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6.3 Signal descriptions
Table 19: Special signal definitions for Ultra DMA
Special Definition
(for Ultra DMA)
Conventional
Definition
DDMARDY- IORDY
Write Operation
HSTROBE DIORSTOP DIOWHDMARDY- DIOR-
Read Operation
DSTROBE IORDY
STOP DIOW-
DD00–DD15
A 16-bit bi-directional data bus between the host and the drive. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00–15, are used for data transfer. These are 3-state lines with 24 mA current sink capability.
DA00–DA02
These are addresses used to select the individual register in the drive.
CS0-
The chip select signal generated from the Host address bus. When active, one of the Command Block Registers
[Data, Error (Features when written), Sector Count, Sector Number, Cylinder Low , Cylinder High, Drive/Head
and Status (Command when written) register] can be selected. (See Table 39: “I/O address map” on page 50.)
CS1-
The chip select signal generated from the Host address bus. When active, one of the Control Block Registers
[Alternate Status (Device Control when written) and Drive Address register] can be selected. (See Table 39: “I/
O address map” on page 50.)
RESET-
This line is used to reset the drive. It shall be kept at a Low logic state during power up and kept High thereafter.
DIOW-
The rising edge of this signal holds data from the data bus to a register or data register of the drive.
DIOR-
When this signal is low , it enables data from a register or data register of the drive onto the data bus. The data on
the bus shall be latched on the rising edge of DIOR-
INTRQ
The interrupt is enabled only when the drive is selected and the host activates the IEN- bit in the Device Control
Register. Otherwise, this signal is in high impedance state regardless of the state of the IRQ bit. The interrupt is
set when the IRQ bit is set by the drive CPU. The IRQ is reset to zero by a host read of the status register or a
write to the Command Register. This signal is a 3-state line with 24mA of sink capability.
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DASP-
This is a time-multiplexed signal which indicates that a drive is active or that device 1 is present. This signal is
driven by an Open-Drain driver and internally pulled up to 5 volts through a 10 kW resistor. During a Power-On
initialization or after RESET- is negated, DASP- shall be asserted by Device 1 within 400 ms to indicate that
device 1 is present. Device 0 shall allow up to 450 ms for device 1 to assert DASP-. If device 1 is not present,
device 0 may assert DASP- to drive an LED indicator. The DASP- signal shall be negated following acceptance
of the first valid command by device 1. Anytime after negation of DASP-, either drive may assert DASP- to
indicate that a drive is active.
During Power-On initialization or after RESET- is negated, DASP- shall be asserted by Device 1 within 400 ms
to indicate that device 1 is present. Device 0 shall allow up to 450ms for device 1 to assert DASP-. If device 1 is
not present, device 0 may assert DASP- to drive a LED indicator.
DASP- shall be negated following acceptance of the first valid command by device 1. At anytime after negation of DASP-, either drive may assert DASP- to indicate that a drive is active.
PDIAG-
This signal shall be asserted by device 1 to indicate to device 0 that it has completed the diagnostics. This line is
pulled up to 5 volts in the drive through a 10 kΩ resistor.
Following a Power On Reset, software reset, or RESET-, drive 1 shall negate PDIAG- within 1 ms (to indicate
to device 0 that it is busy). Drive 1 shall then assert PDIAG- within 30 seconds to indicate that it is no longer
busy and is able to provide status.
Following the receipt of a valid Execute Drive Diagnostics command, device 1 shall negate PDIAG- within 1
ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics. If device 1 is present then
device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1
to assert PDIAG-. Device 1 should clear BSY before asserting PDIAG-, as PDIAG- is used to indicate that
device 1 has passed its diagnostics and is ready to post status.
If device 1 did not assert DASP- during reset initialization, device 0 shall post its own status immediately after
it completes diagnostics and clear the device 1 Status register to 00h. Device 0 may be unable to accept commands until it has finished its reset procedure and is ready (DRDY=1).
Device 1 shall release PDIAG-/CBLID- no later than after the first command following a power on or hardware
reset sequence so that the host may sample PDIAG-/CBLID- in order to detect the presence or absence of an 80conductor cable assembly.
CSEL (Cable Select)
The drive is configured as either Device 0 or 1 depending upon the value of CSEL.
• If CSEL is grounded, the device address is 0
• If CSEL is open, the device address is 1
KEY
Pin position 20 has no connection pin. It is recommended to close the respective position of the cable connector
in order to avoid incorrect insertion.
IORDY
This signal is negated to extend the host transfer cycle when a drive is not ready to respond to a data transfer
request and may be negated when the host transfer cycle is less than 240 ns for PIO data transfer. This signal is
an open-drain output with 24 mA sink capability and an external resistor is needed to pull this line to 5 volts.
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DMACK-
This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted,
or that data is available.
This signal is internally pulled up to 5 Volt through a 15kΩ resistor with a resistor tolerance value of –50% to
+100%.
DMARQ
This signal is used for DMA data transfers between the host and drive. It shall be asserted by the drive when it
is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR- and DIOWsignals. This signal is used in a handshake mode with DMACK-. This signal is a 3-state line with 24 mA sink
capability and internally pulled down to GND through a 10 kΩ resistor.
HDMARDY- (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive. The signal HDMARDY- is a flow
control signal for Ultra DMA data in bursts. This signal is held asserted by the host to indicate to the device that
the host is ready to receive Ultra DMA data in transfers. The host may negate HDMARDY- to pause an Ultra
DMA data in transfer.
HSTROBE (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive.
The signal HSTROBE is the data out strobe signal from the host for an Ultra DMA data out transfer. Both the
rising and falling edge of HSTROBE latch the data from DD (15:0) into the device. The host may stop toggling
HSTROBE to pause an Ultra DMA data out transfer.
STOP (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive.
The STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst. A STOP shall be
negated by the host before data is transferred in an Ultra DMA burst. Assertion of STOP by the host during or
after data transfer in an Ultra DMA mode signals the termination of the burst.
DDMARDY- (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive.
The signal DDMARDY- is a flow control signal for Ultra DMA data out bursts. This signal is held asserted by
the device to indicate to the host that the device is ready to receive Ultra DMA data out transfers. The device
may negate DDMARDY- to pause an Ultra DMA data out transfer.
DSTROBE (Ultra DMA)
This signal is used only for Ultra DMA data transfers between host and drive.
The signal DSTROBE is the data in strobe signal from the device for an Ultra DMA data in transfer. Both the
rising and the falling edge of DSTROBE latch the data from DD (15:0) into the host. The device may stop toggling DSTROBE to pause an Ultra DMA data in transfer.
Device termination
The termination resistors on the device side are implemented on the drive side as follows:
•33 Ω for DD0 through DD15, DMARQ, INTRQ
•82 Ω for CS0-, CS1-, DA0, DA1, DA2, DIOR-, DIOW-, DMACK-
•22 Ω for IORDY
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6.4 Interface logic signal levels
The interface logic signals have the following electrical specifications:
Inputs
Outputs:
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
6.5 Reset timings
Table 20: System reset timing chart
RESET-
BUSY
Table 21: System reset timing
2.0 V min
0.8 V max.
2.4 V min.
0.5 V max.
t10
t14
PARAMETER DESCRIPTION Min (µs) Max (µs)
t10 RESET low width
t14 RESET high to not BUSY
25 -
-31
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6.6 PIO timings
The PIO cycle timings meet Mode 4 of the ATA/ATAPI-6 description.
Table 22: PIO cycle timings chart
PARAMETER DESCRIPTION MIN (ns) MAX (ns)
t0 Cycle time
t1 Address valid to DIOR-/DIOW- setup
t2 DIOR-/DIOW- pulse width
t2i DIOR-/DIOW- recovery time
t3 DIOW- data setup
t4 DIOW- data hold
t5 DI OR- data setup
t6 DIOR- data hold
t9 DIOR-/DIOW- to address valid hold
tA IORDY setup width
tB IORDY pulse width
120 –
25 –
70 –
25 –
20 –
10 –
20 –
5–
10 –
–35
–1250
6.6.1 Write DRQ interval time
For write sectors and write multiple operations 3.8 ms is inserted from the end of negation of the DRQ bit until setting of the next DRQ bit.
6.6.2 Read DRQ interval time
For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of
the next DRQ bit is as follows:
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• In the event that a host reads the status register only before the sector or block transfer DRQ interval, the
DRQ interval 4.2 µs
• In the event that a host reads the status register after or both before and after the sector or block transfer, the
DRQ interval is 11.5 µs
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6.7 Multi-word DMA timings
The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-6 description.
Table 23: Multiword DMA cycle timing chart
CS0-/CS1-
DMARQ
DMACK-
DIOR-/DIOW-
READ DATA
WRITE DATA
Table 24: Multiword DMA cycle timings
PARAMETER DESCRIPTION
t0 Cycle time
tD DIOR-/DIOW- asserted pulse width
tE DIOR- data access
tF DIOR- data hold
tG DIOR-/DIOW- data setup
tH DIOW- data hold
tI DMACK- to -DIOR-/DIOW- setup
tJ DIOR-/DIOW- to DMACK- hold
tKR/tKW DIOR-/DIOW- negated pulse width
tLR/tLW DIOR-/DIOW- to DMARQ- delay
tM CS (1:0) valid to DIOR-/DIOWtN CS (1:0)
tZ DMACK- to read data released
tM
tI tD
tE
tG
t0
tFtG
tH
tN
tLR/tLW
tJ
tKR/tKW
tZ
MIN (ns) MAX (ns)
120 –
70 –
–50
5–
20 –
10 –
0–
5–
25 –
–35
25 10 -
–25
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6.8 Ultra DMA timings
The Ultra DMA timings meet Mode 0, 1, 2, and 4, 5 and 6 of the Ultra DMA Protocol.
6.8.1 Initiating Read DMA
DMARQ
tUI
DMACK-
tA CK tEN V
STOP
tA CK tENV
HDMARDY-
DSTROBE
DD(15:0)
tZI O RDY
tA Z
xxxxxxxxxxxxxxxxxxxxxxxxxxx
Host drives DD
tFS tC Y C
tZAD
xxx xxxx xxx
RD Data RD Data
Device drives DD
t2C Y C
tC Y C
tDS
tDH
RD Data
Table 25: Ultra DMA cycle timings (Initiating Read)
PARAMETER
DESCRIPTION
(all values in ns)
tUI Unlimited interlock time0–0–000–0–0–0–
tACKSetup time for DMACK-20–20–20–20–20–20–20–
tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 50 20 50
tZIORDY
tFS First DSTROBE time 02300200017001300120– 90 0 80
tCYCCycle time 112–73–54–39–25–17–13–
t2CYC Two cycle time
tAZ Maximum time allowed
tZAD Drivers to assert
tDS Data setup time at host
tDH Data hold time at host
tDZFS Time from data ouput
Minimum time before
driving IORDY
for output drivers to
release
released-to-driving until
the first transition of crit-
ical timing
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
0–0–0–0–0–0–0–
230–154–115–86–57–38
–10–10–10–10–10 10
0–0–0–0–0–0–0
15–10–7–7–5–4.8–2.6
5–5–5–5–5–4.8–3.5
70–48–31–20–6.7–25–17.5
–
29 –
–
10
–
–
–
–
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6.8.2 Host Pausing Read DMA
Table 26: Ultra DMA cycle timing chart (Host pausing Read)
DMARQ
DMACK-
STOP
tSR
HDMARDY-
tRFS
DSTROBE
Table 27: Ultra DMA cycle timings (Host pausing Read)
PARAMETER
DESCRIPTION
(all values in ns)
tSR DSTROBE to
HDMARDY- time
tRFS HDMARDY- to final
DSTROBE time
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
–50–30–20––––––––
–75–70–60–60–60–50–50
Note: When a host does not satisfy tSR timing, it should be ready to receive two more data words after HDMARDY
- is negated.
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6.8.3 Host Terminating Read DMA
Table 28: Ultra DMA cycle timing chart (Host pausing Read)
DMARQ
tLI
DMACK-
tRP
STOP
tMLI
tACK
tACK
HDMARDY-
DSTROBE
DD(15:0)
tRFS
tLI tIORDYZ
tCH
xxx
tCS
CRC
tAZ
xxx RD Data xxxxxxxxxxx
xxxxxxxxxxxxxxxxxx
tZAH
Device drives DD
Host drives DD
Table 29: Ultra DMA cycle timings (Host pausing Read)
PARAMETER DESCRIPTION
(all values in ns)
tRFS HDMARDY- to final
DSTROBE time
tRP Ready to pause time 160 – 125 – 100 – 100 – 100 – 85 – 85 –
tLI Limited interlock time 0 150 0 150 0 15 0 0 100 0 100 0 75 0 60
tAZ Maximum time allowed for
output drivers to release
tZAH Minimum delay time
required for output
tMLIInterlock time with minimum20–20–20–20–20–20–20–
tCS CRC word setup time at
device
tCH CRC word hold time at
device
tACKHold time for DMACK- 20–20–20–20–20–20–20–
tIO-
Maximum time before
RDYZ
releasing IORDY
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
–75–70–60–60–60–50–50
–10–10–10–10–10–10–10
20–20–20–20–20–20–20–
15–10–7–7–5–5–5–
5–5–5–5–5–5–5–
–20–20–20–20–20–20–20
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6.8.4 Device Terminating Read DMA
Table 30: Ultra DMA cycle timing chart (Host pausing Read)
DMARQ
tSS
tMLI
DMACK-
tLI
tACK
STOP
tLI
tACK
HDMARDY-
tLI
tIORDYZ
DSTROBE
tCH
tCS
CRC
DD(15:0)
tAZ
xxxxxx xxxxxxxxxx
xxxxxxxxxxxxxxxxxx
tZAH
Device drives DD
Host drives DD
Table 31: Ultra DMA cycle timings (Device Terminating Read)
PARAMETER DESCRIPTION
(all values in ns)
tSS Time from DSTROBE edge
to negation of DMARQ
tLI Limited interlock time 015001500150010001000 75 0 60
tAZ Maximum time allowed for
output drivers to release
tZAH Maximum delay time
required for output
tMLI Interlock time with minimum20–20–20–20–20–20–20–
tCS CRC word setup time at
device
tCH CRC word hold time at
device
tACK Hold time for DMACK- 20–20–20–20–20–20–20–
tIORDYZ Maximum time before
releasing IORDY
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
50–50–50–50–50–50–50–
–10–10–10–10–10–10–10
20–20–20–20–20–20–20–
15–10–7–7–5–5–5–
5–5–5–5–5–5–5–
–20–20–20–20–20–20–20
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6.8.5 Initiating Write DMA
Table 32: Ultra DMA cycle timing chart (Initiating Write)
DMARQ
tUI
DMACK-
tACK
STOP
tENV
tZIORDY
DDMARDY-
tA CK
tLI
tUI tCY C
t2CYC
tCYC
HSTROBE
tDH
tDS
DD(15:0)
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
WT Data
WT Data
xxx xxx
WT Data
Host drives DD
PARAMETER
DESCRIPTION
(all values in ns)
tUI Unlimited interlock time0–0–0–0–0–0–0–
tACK Setup time for DMACK- 20 – 20 – 20 – 20 – 20 – 20 – 20 –
tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 55 20 50
tZIORDY Minimum time before
driving IORDY
tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60
tCYC Cycle time 112 – 73 – 54 – 39 – 25 – 16.8 – 13.0 –
t2CYC Two cycle time 230 – 154 – 115 – 86 – 57 – 38 – 29 –
tDS Data setup time at
device
tDH Data Hold time at device5–5–5–5–5–4.6–3.5–
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
0–0–0–0–0–0–0–
15–10–7–7–5–4–2.6–
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6.8.6 Device Pausing Write DMA
Table 33: Ultra DMA cycle timing chart (Device Pausing Write)
DMARQ
DMACK-
STOP
tSR
DDMARDY-
tRFS
HSTROBE
Table 34: Ultra DMA cycle timings (Device Pausing Write)
PARAMETER
DESCRIPTION
(all values in ns)
tSR HSTROBE to DDMARDY-
time
tRFS DDMARDY- to final
HSTROBE time
MODE 0MODE 1MODE 2MODE 3MODE 4MODE 5MODE 6
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
–50–30–20––––––––
–75–70–60–60–60–50–50
Note: When a device does not satisfy the tSR timing, it shall be ready to receive two more strobes after
DDMARDY– is negated.
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6.8.7 Device Terminating Write DMA
Table 35: Ultra DMA cycle timing chart (Device Terminating Write)
DMARQ
tRP
tLI
tMLI
DMACK-
tACK
STOP
tIORDY Z
DDMARDY-
tRFS
tLI
tACK
HSTROBE
tCH
tCS
DD(15:0)
xxx WT Data xxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxx
CRC
Host drives DD
PARAMETER
DESCRIPTION
(all values in ns)
tRFS DDMARDY- to final
HSTROBE time
tRP Rea dy to pause time 160 – 125 – 100 – 100 – 100 – 85 – 85 –
tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60
tMLI Interlocking time with
minimum
tCS CRC word setup time at
device
tCH CRC word hold time at
device
tACK Hold time for DMACK-
negation
tIORDYZ Maximum time before
releasing IORDY
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
–75–70–60–60–60–50–50
20 – 20 – 20 – 20 – 20 – 20 – 20 –
15–10–7–7–5–5–5–
5–5–5–5–5–5–5–
20 – 20 – 20 – 20 – 20 – 20 – 20 –
–20–20–20–20–20–20–20
Table 36: Ultra DMA cycle timings (Device TerminatingWrite)
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6.8.8 Host Terminating Write DMA
Table 37: Ultra DMA cycle timing chart (Host Terminating Write)
DMARQ
tLI
tM L I
DMACK-
tSS
tACK
STOP
tLI
tIORDYZ
DDMARDY-
tLI
tACK
HSTROBE
tC H
tCS
DD(15:0)
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
CRC
xxxxxxxxxx
Host drives DD
Table 38: Ultra DMA cycle timings (Host Terminating Write)
PARAMETER
DESCRIPTION
(all values in ns)
tSS Time from HSTROBE edge
to assertion of STOP
tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 0 60
tMLI Interlock time with mini-
mum
tCS CRC word setup time at
device
tCH CRC word hold time at
device
tACKHold time for DMACK- 20–20–20–20–20–20–20–
tIO-
Maximum time before
RDYZ
releasing IORDY
MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
50–50–50–50–50–50–50–
20–20–20–20–20–20–20–
15–10–7–7–5–5–5–
5–5–5–5–5–5–5–
–20–20–20–20–20–20–20
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6.9 Addressing of registers
The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's
I/O space. Two chip select lines (CS0– and CS1–) and three address lines (DA0–2) are used to select one of these
registers, while a DIOR– or DIOW– is provided at the specified time.
The chip select line CS0- is used to address the Command Block registers while the CS1– is used to address Control Block registers.
The following table shows the I/ O address map.
Table 39: I/O address map
CS0– CS1–
01
01
01
01
01
01
01
01
10
DA2 DA1 DA0 DIOR– = 0 (Read) DIOW– = 0 (Write)
Command Block Registers
0 0 0 Data Reg. Data Reg.
0 0 1 Error Reg. Features Reg.
0 1 0 Sector count Reg. Sector count Reg.
0 1 1 Sector number Reg. Sector number Reg.
1 0 0 Cylinder low Reg. Cylinder low Reg.
1 0 1 Cylinder high Reg. Cylinder high Reg.
1 1 0 Drive/Head Reg. Drive/Head Reg.
1 1 1 Status Reg. Command Reg.
Control Block Registers
1 1 0 Alt. Status Reg. Device control Reg.
Note: "Addr" field is shown as an example.
During DMA operation (from writing to the command register until an interrupt) not all registers are accessible.
For example, the host is not supposed to read status register contents before interrupt (the value is invalid).
6.9.1 Cabling
The maximum cable length from the host sys tem to the drive pl us circuit patter n length in the host system shall not
exceed 18 inches.
For higher data transfer application (>8.3 MB/s) a modification in the system design is recommended to reduce
cable noise and cross-talk, such as a shorter cable, bus termination, or a shielded cable.
For systems operating with Ultra DMA mode 3, 4, and 5, 80-conductor ATA cable assembly shall be used.
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Part 2. Interface specification
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7.0 Specification
7.1 Jumper settings
7.1.1 Jumper pin location
Jumper pinsJumper pins
7.1.2 Jumper pin identification
Pin I
Pin A
DERA001.prz
Pin B
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7.1.3 Jumper pin assignment
There are four jumper settings as shown in the following sections:
• 16 logical head default (normal use)
• 15 logical head default
• 32 GB clip
• Power up in standby
Within each of these four jumper settings the pin assignment selects Device 0, Device 1, Cable Selection, or Device
1 Slave Present as shown in the following figures.
The Device 0 setting automatically recognizes device 1 if it is present.
The Device 1 Slave Present setting is for a slave device that does not comply with the ATA specification.
Note: In conventional terminology "Device 0" designates a Master and "Device 1" designates a Slave.
RSV
GND
GND GND RSV
IGECA
H
DS
CS/SP
D
GND
7.1.4 Jumper positions
7.1.4.1 16 logical head default (normal use)
The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device1
(Slave) Present.
I
I
ECA
G
HFDB
G
ECA
HFDB
DEVICE 0 (Master)
DEVICE 1 (Slave)
BF
RS V
I
I
I
G
ECA
HFDB
G
ECA
HFDB
ECA
G
HFDB
CABLE SEL
DEVICE 1 (Slave) Present
Shipping Default Condition
(DEVICE 0)
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Notes:
1. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL
mode the drive address is determined by AT interface signal #28 CSEL as follows:
• When CSEL is grounded or at a low level, the drive address is 0 (Device 0).
• When CSEL is open or at a high level, the drive address is 1 (Device 1).
2. In CSEL mode, installing or removing the jumper blocks at A-B or C-D position does not affect any selection of Device or Cable Selection mode.
3. The shipping default position is the Device 0 position.
7.1.4.2 15 logical head default
The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device1
(Slave) Present setting 15 logical heads instead of default 16 logical head models.
I
I
I
I
ECA
G
HFDB
G
ECA
HFDB
ECA
G
HFDB
G
ECA
HFDB
DEVICE 0 (Master)
DEV ICE 1 (Slave )
CABLE SEL
DEVICE 1 (Slave) Present
Notes:
1. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL
mode the drive address is determined by AT interface signal #28 CSEL as follows:
• When CSEL is grounded or at a low level, the drive address is 0 (Device 0).
• When CSEL is open or at a high level, the drive address is 1 (Device 1).
2. In CSEL mode, installing or removing the jumper blocks at A-B or C-D position does not affect any selection of Device or Cable Selection mode.
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7.1.4.3 Capacity clip to 32GB
The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device1
(Slave) Present while setting the drive capacity down to 32 GB for the purpose of compatibility.
Table 40: Jumper positions for capacity clip to 32GB
I
I
I
I
ECA
G
HFDB
G
ECA
HFDB
G
ECA
HFDB
ECA
G
HFDB
DEVICE 0 (Master)
DEVICE 1 (Slave)
CABLE SEL
DEVICE 1 (Slave) Present
Note: The jumper setting acts as a 32GB clip which clips the LBA to 66055248. The CHS is unchanged from the
factory default of 16383/16/63.
7.1.4.4 Power up in Standby
The figure below shows the jumper positions used to select Device 0, Device 1, Cable Selection, or Device1
(Slave) Present to enable Power Up In Standby.
Table 41: Jumper settings for Disabling Auto Spin
I
G
ECA
HFDB
I
ECA
G
HFDB
I
ECA
G
HFDB
I
ECA
G
HFDB
Deskstar 7K80 Hard Disk Drive Specification
D EVICE 0 (Mas ter)
DEVICE 1 (Slave)
CABLE SEL
DEVICE 1 (Slave) Present
56
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Notes:
1. These jumper settings are used for limiting power supply current when multiple drives are used.
2. Command to spin up is SET FEATURES (subcommand 07h). Refer to 12.28 Set Features.
3. To enable the CSEL mode (Cable Selection mode) the jumper block must be installed at E-F. In the CSEL
mode the drive address is determined by AT interface signal #28 CSEL as follows:
• When CSEL is grounded or at a low level, the drive address is 0 (Device 0).
• When CSEL is open or at a high level, the drive address is 1 (Device 1).
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7.2 Environment
7.2.1 Temperature and humidity
Table 42: Temperature and humidity
Operating conditions
Temperature 5C to 55ºC (See note below)
Relative humidity 8 to 90%, non-condensing
Maximum wet bulb temperature 29.4ºC, non-condensing
Maximum temperature gradient 15ºC/hour
Altitude –300 to 3,048 m
Non-operating conditions
Temperature –40C to 65ºC
Relative humidity 5 to 95%, non-condensing
Maximum wet bulb temperature 35ºC, non-condensing
Altitude –300 to 12,000 m
Notes:
• The system is responsible for providing sufficient ventilation to maintain a surface temperature below
60°C at the center of the top cover of the drive.
• Noncondensing conditions should be maintained at any time.
• Maximum storage period within shipping package is one year.
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Tabl e 43: Limi ts of temperature and humidity
100
90
80
31'C/90%
36'C /95%
W etBuib=35.0'C
70
60
50
40
Relative Humidity (%)
30
20
10
0
-45-35-25-15-5 5 152535455565
Non-operating
Operating
Temp erature ('C)
W etBuib=29.4'C
65'C /14%
55'C/15%
Note: Storage temperature range is 0° to 65°.
7.2.2 Corrosion test
The drive shows no sign of corrosion inside and outside of the hard disk assembly and is functional after being subjected to seven days at 50°C with 90% relative humidity.
7.3 DC power requirements
The following voltage specifications apply at the power connector of the drive. Damage to the drive electronics
may result if the power supply cable is connected or disconnected while power is being applied to the drive (no hot
plug/unplug is allowed). Connections to the drive should be made in a low voltage, isolated secondary circuit
(SELV). There is no special power on/off sequencing required.
7.3.1 Input voltage
Table 44: Input voltage
Input voltage supply
+5 V 5 V ± 5% –0.3 to 7 V 0 to 5 sec
+12 V 12 V + 10% –8% –0.3 to 15 V 0 to 5 sec
1
To avoid damage to the drive electronics, power supply voltage spikes must not exceed specifications.
2
+12V should be applied within 60 seconds after +5V is applied to the drive.
2
During run and spin up Absolute max spike voltage1Supply rise time
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7.3.2 Power supply current (typical)
Table 45: Power supply current of 80GB and 40GB models
Power supply current of 40 GB
and 80 GB models(PATA)
(values in milliamps. RMS) Pop Mean Std Dev Pop Mean Std Dev
Idle average
Idle ripple (peak-to-peak)
Low RPM idle
Low RPM idle ripple
Unload idle average
Unload idle ripple
Random R/W average1
Random R/W peak
Silent R/W average
Silent R/W peak
Start up (max)
Standby average
Sleep average
+5 Volts [mA] +12 Volts [mA]
275 14 275 24
230 40 290 20
160 6 140 7
220 20 250 20
160 6 270 6
220 20 400 20
490 7 600 12
1200 30 1700 50
500 6 360 8
1200 30 1000 40
840 50 1830 50
150 9 15 2 0.9
100 10 15 2 0.7
7.3.3 Power supply generated ripple at drive power connector
Total
[W]
4.7
2.5
4.0
9.7
6.8
Table 46: Power supply generated ripple at drive power connector
Maximum (mV pp) MHz
+5 V dc 100 0-10
+12 V dc 150 0-10
During drive start up and seeking 12-volt ripple is generated by the drive (referred to as dynamic loading). If the
power of several drives is daisy chained together, the power supply ripple plus the dynamic loading of the other
drives must remain within the above regulation tolerance. A common supply with separate power leads to each
drive is a more desirable method of power distribution.
To prevent external electrical noise from interfering with the performance of the drive, the drive must be held by
four screws in a user system frame which has no electrical level difference at the four screws position and has less
than ±300 millivolts peak to peak level difference to the ground of the drive power connector.
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7.4 Reliability
7.4.1 Data integrity
No more than one sector is lost at Power loss condition during the write operation when the write cache option is
disabled. If the write cache option is active, the data in write cache will be lost. To prevent the loss of customer
data, it is recommended that the last write access before power off be issued after setting the write cache off.
7.4.2 Cable noise interference
To avoid any degradation of performance throughput or error rate when the interface cable is routed on top or
comes in contact with the HDA assembly, the drive must be grounded electrically to the system frame by four
screws. The common mode noise or voltage level difference between the system frame and power cable ground or
AT interface cable ground should be in the allowable level specified in the power requirement section.
7.4.3 Start/stop cycles
The drive withstands a minimum of 50,000 start/stop cycles in a 40° C environment and a minimum of 10,000
start/stop cycles in extreme temperature or humidity within the operating range. See Table 42: “Temperature and
humidity” on page 58 and Figure 9: “Limits of temperature and humidity” on page 48.
7.4.4 Preventive maintenance
None
7.4.5 Data reliability
Probability of not recovering data is 1 in 1014 bits read
ECC On The Fly correction
• 1 Symbol : 10 bits
• 1 Interleave
• 36 ECCs are embedded into each interleave
• This implementation always recovers 16 random burst errors and a 151-bit continuous burst error
7.4.6 Required power-off sequence
The required BIOS sequence for removing power from the drive is as follows:
Step 1: Issue one of the following commands.
Standby
Standby immediate
Sleep
Note: Do not use the Flush Cache command for the power off sequence because this command does not
invoke Unload
Step 2: Wait until the Command Complete status is returned. In a typical case 350 ms are required for the command to finish completion; however, the BIOS time out value needs to be 30 seconds considering error recovery
time. Refer to section13.0 “Timings” on page 247.
Step 3: Terminate power to HDD.
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7.5 Mechanical specifications
7.5.1 Physical dimensions and weight
BREATHER HOLE
All dimensions in the above figure are in millimeters.
The breather hole must be kept uncovered in order to keep the air pressure inside of the disk enclosure equal to
external air pressure.
The following table lists the dimensions of the drive.
Tabl e 47: P hysical dimensions and weight
Height [mm] 24.3±0.3
Width [mm] 101.6±0.4
Length [mm] 146.0±0.6
Weight [grams - maximum] 560
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7.5.2 Mounting hole locations
The mounting hole locations and size of the drive are shown below. All dimensions are in mm.
(6X) Max. penetration 4.5 mm
(4)
Side View
(5)(6) (7)
I/F Connector
Bottom View
(3)
(4X) Max. penetration 4.0 mm
(1)(2)
Thread(1)(2)(3)(4)(5)(6)(7)
6-32 UNC 41.28±0.5 44.45±0.2 95.25±0.2 6.35±0.2 28.5±0.5 60.0±0.2 41.6±0.2
7.5.3 Connector locations
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7.5.4 Drive mounting
The drive will operate in all axes (6 directions). Performance and error rate will stay within specification limits if
the drive is operated in the other orientations from which it was formatted.
For reliable operation, the drive must be mounted in the system securely enough to prevent excessive motion or
vibration of the drive during seek operation or spindle rotation, using appropriate screws or equivalent mounting
hardware.
The recommended mounting screw torque is 0.6 - 1.0 Nm (6-10 Kgf.cm).
The recommended mounting screw depth is 4 mm maximum for bottom and 4.5 mm maximum for horizontal
mounting.
Drive level vibration test and shock test are to be conducted with the drive mounted to the table using the bottom
four screws.
7.5.5 Heads unload and actuator lock
The head load/unload mechanism is provided to protect the disk data during shipping, movement, or storage. Upon
power down, the heads are automatically unload from the disk area and the locking mechanism of the head actuator
will secure the heads in unload position.
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7.6 Vibration and shock
All vibration and shock measurements recorded in this section are made with a drive that has no mounting attachments for the systems. The input power for the measurements is applied to the normal drive mounting points.
7.6.1 Operating vibration
7.6.1.1 Random vibration
The test is 30 minutes of random vibration using the power spectral density (PSD) levels shown below in each of
three mutually perpendicular axes. The disk drive will operate without non-recoverable errors when subjected to
the above random vibration levels.
The overall RMS (root mean square) level is 0.67 G for horizontal vibration and 0.56 G for vertical.
Table 48: Random vibration PSD
Table 49: Random vibration PSD profile break points (operating)
Direction
Horizontal x10–3
[G2/Hz
Vertical x10–3
[G2/Hz]
The overall RMS (root mean square) level is 0.67 G for horizontal vibration and 0.56 G for vertical.
5Hz 17Hz 45Hz 48Hz 62Hz 65Hz 150Hz 200Hz 500Hz
0.02 1.1 1.1 8.0 8.0 1.0 1.0 0.5 0.5 0.67
0.02 1.1 1.1 8.0 8.0 1.0 1.0 0.08 0.08 0.56
RMS
(G)
7.6.1.2 Swept sine vibration
The drive will meet the criteria shown below while operating in the specified conditions:
• No errors occur with 0.5 G 0 to peak, 5 to 300 to 5 Hz sine wave, 0.5 oct/min sweep rate with 3-minute
dwells at two major resonances
• No data loss occurs with 1 G 0 to peak, 5 to 300 to 5 Hz sine wave, 0.5 oct/min sweep rate with 3-minute
dwells at two major resonances
7.6.2 Nonoperating vibration
The drive does not sustain permanent damage or loss of previously recorded data after being subjected to the environment described below
7.6.2.1 Random vibration
The test consists of a random vibration applied in each of three mutually perpendicular axes for a duration of 10
minutes per axis. The PSD levels for the test simulate the shipping and relocation environment shown below.
Table 50: Random Vibration PSD profile breakpoints (nonoperating)
Frequency 2Hz 4Hz 8Hz 40Hz 55Hz 70Hz 200Hz
G2/Hz 0.001 0.03 0.03 0.003 0.01 0.01 0.001
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The overall RMS (root mean square) level of vibration is 1.04 G.
7.6.2.2 Swept sine vibration
• 2 G (zero-to-peak), 5 to 500 to 5 Hz sine wave
• 0.5 oct/min sweep rate
• 3 minutes dwell at two major resonances
7.6.3 Operating shock
The drive meets the following criteria while operating in the conditions described below . The shock test consists of
10 shock inputs in each axis and direction for total of 60. There must be a delay between shock pulses long enough
to allow the drive to complete all necessary error recovery procedures.
• No error occurs with a 10 G half-sine shock pulse of 11 ms duration in all models.
• No data loss occurs with a 30 G half-sine shock pulse of 4 ms duration in all models.
• No data loss occurs with a 55 G half-sine shock pulse of 2 ms duration in all models.
7.6.4 Nonoperating shock
The drive will operate with no degradation of performance after being subjected to shock pulses with the following
characteristics.
7.6.4.1 Trapezoidal shock wave
• Approximate square (trape zoidal) pulse shape
• Approximate rise and fall time of pulse is 1 ms
• Average acceleration level is 50 G. (Average response curve value during the time following the 1 ms rise
time and before the 1 ms fall with a time "duration of 11 ms")
• Minimum velocity change is 4.23 meters per second
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7.6.4.2 Sinusoidal shock wave
The shape is approximately half-sine pulse. The figure below shows the maximum acceleration level and duration.
Table 51: Sinusoidal shock wave
Acceleration level (G) Duration (ms)
350 2
150 11
7.6.5 Nonoperating rotational shock
All shock inputs shall be applied around the actuator pivot axis.
Table 52: Rotational shock
Duration Rad/s
1 ms 30,000
2 ms 20,000
2
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7.7 Acoustics
The upper limit criteria of the octave sound power levels are given in Bels relative to one picowatt and
are shown in the following table. The sound power emission levels are measured in accordance with
ISO7779.
Table 53: Sound power levels
Mode Typical/Max
Idle 2.6 / 3.0
Operating Performance seek mode 3.4 / 3.7
Quiet seek mode 2.8 / 3.2
Mode definitions
•I
dle mode:
respond to control line commands.
•
Operating mode:
dwell time at each cylinder. The seek rate for the drive is calculated with the following formula:
• Dwell time = 0.5 x 60/RPM
• Seek rate = 0.4 / (average seek time + dwell time)
The drive is powered on, disks spinning, track following, unit is ready to receive and
Continuous random cylinder selection and seek operation of the actuator with a
7.8 Identification labels
The following labels are affixed to every drive:
• A label containing the Hitachi logo, the Hitachi Global Storage Technologies part number and the
statement " Made by Hitachi Global Storage Technologies Inc." or Hitachi Global Storage Technologies approved equivalent.
• A label containing the drive model number, the manufacturing date code, the formatted capacity,
the place of manufacture, UL/CSA/TUV/CE/C-Tick mark logos
• A bar code label containing the drive serial number
• A label containing jumper pin description
• A user designed label per agreement
The above labels may be integrated with other labels
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7.9 Safety
7.9.1 UL and CSA approval
The product is qualified per UL (Underwriters Laboratory) 1950 Third Edition and CAN/CSA C22.2 No.950-M95
Third Edition, for use in Information Technology Equipment, including Electric Business Equipment. The UL Recognition or the CSA certification is maintained for the product life. The UL and C-UL recognition mark or the CSA
monogram for CSA certification appears on the drive.
7.9.2 German safety mark
All models are approved by TUV on T est Requirement: EN60950:1 992+A1-4, but the GS mark is not applicable to
internal devices such as this product.
7.9.3 Flammability
The printed circuit boards used in this drive are made of material with a UL recognized flammability rating of V-1
or better. The flammability rating is marked or etched on the board. All other parts not considered electrical components are made of material with a UL recognized flammability rating of V-1 or better. However, small mechanical
parts such as cable ties, washers, screws, and PC board mounts may be made of material with a UL recognized
flammability rating of V-2.
7.9.4 Safe handling
The product is conditioned for safe handling in regards to sharp edges and corners.
7.9.5 Environment
The product does not contain any known or suspected carcinogens.
Environmental controls meet or exceed all applicable government regulations in the country of origin. Safe chemi-
cal usage and manufacturing control are used to protect the environment. An environmental impact assessment has
been done on the manufacturing process used to build the drive, the drive itself and the disposal of the drive at the
end of its life.
Production also meets the requirements of the international treaty on chlorofluorocarbon (CFC) control known as
the United Nations Environment Program Montreal Protocol, and as ratified by the member nations. Material to be
controlled include CFC-11, CFC-12, CFC-113, CFC-114, CFC-115, Halon 1211, Halon 1301 and Halon 2402.
Although not specified by the Protocol, CFC-112 is also controlled. In addition to the Protocol Hitachi Global Storage Technologies requires the following:
• that no packaging used for the shipment of the product use controlled CFCs in the manufacturing process.
• that no manufacturing processes for parts or assemblies include printed circuit boards use controlled CFC
materials.
7.9.6 Secondary circuit protection
Spindle/VCM driver module includes 12 V over current protection circuit
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7.10 Electromagnetic compatibility
The drive, when installed in a suitable enclosure and exercised with a random accessing routine at maximum data
rate meets the worldwide EMC requirements listed below:
• United States Federal Communications Commission (FCC) Rules and Regulations (Class B), Part 15. (A 6
dB buffer shall be maintained on the emission requirements).
• European Economic Community (EEC) directive number 76/889 related to the control of radio frequency
interference and the Verband Deutscher Elektrotechniker (VDE) requirements of Germany (GOP). Spectrum Management Agency (SMA) EMC requirements of Australia. The SMA has pproved two forms of CTick Marking for Hitachi Global Storage Technologies.
The product is declared to be in conformity with requirements of the following EC directives under the sole
responsibility of Hitachi Global Storage Technologies Japan Ltd:
Council Directive 89/336/EEC on the approximation of laws of the Member States relating to electromagnetic
compatibility.
7.10.1 C-TICK mark
The product complies with the following Australian EMC standard:
Limits and methods of measurement of radio disturbance characteristics of information technology, AS/NZS 3548
:1995 Class B.
7.10.2 BSMI mark
The product complies with the Taiwan EMC standard"Limits and methods of measurement of radio disturbance
characteristics of information technology equipment, CNS 13438 Class B."
7.11 Packaging
Drives are packed in ESD protective bags and shipped in appropriate containers.
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8.0 General
8.1 Introduction
This specification describes the host interface of the HDS7280x0PLATy0 hard disk drive.
The interface conforms to the Working Document of Information technology, AT Attachment with Packet Interface
Extension (ATA/ATAPI-7) Revision 4, dated 23 December 2003, with certain limitations described in Section 8.3
below.
8.2 Terminology
Device Device indicates HDS7280x0PLATy0
Host Host indicates the system that the device is attached to
8.3 Deviations from standard
The device conforms to the referenced specifications with the following deviations:
Check Power Mode Check Power Mode command returns FFh to Sector Count Register when
the device is in Idle mode. This command does not support 80h as the
return value.
Hard Reset Hard reset response is not the same as that of power on reset. Refer to
section 10.1, “Reset response” on page 81 for details.
Download Download command is aborted when teh device is in security locked
mode.
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9.0 Registers
9.1 Register set
Table 54: Register Set
Addresses Functions
CS0- CS1- DA2 DA1 DA0 READ (DIOR-) WRITE (DIOW-)
N N x x x Data bus high impedance Not used
Control block registers
N A 0 x x Data bus high impedance Not used
N A 1 0 x Data bus high impedance Not used
N A 1 1 0 Alternate Status Device Control
N A 1 1 1 Device Address Not used
Command block registers
A N 0 0 0 Data Data
A N 0 0 1 Error Register Features
A N 0 1 0 Sector Count Sector Count
A N 0 1 1 Sector Number Sector Number
A N 0 1 1 * LBA bits 0-7 * LBA bits 0-7
A N 1 0 0 Cylinder Low Cylinder Low
A N 1 0 0 * LBA bits 8-15 * LBA bits 8-15
A N 1 0 1 Cylinder High Cylinder High
A N 1 0 1 * LBA bits 16-23 * LBA bits 16-23
A N 1 1 0 Device/Head. Device/Head
A N 1 1 0 * LBA bits 24-27 * LBA bits 24-27
A N 1 1 1 Status Command
A A x x x Invalid address Invalid address
Logic conventions: A = signal asserted
N = signal not asserted
x = either A or N
* = Mapping of registers in LBA mode
Communication to or from the device is through an I/O Register that routes the input or output data to or from the
registers addressed by the signals from the host(CS0-, CS1-, DA2, DA1, DA0, DIOR- and DIOW-).
The Command Block Registers are used for sending commands to the device or posting status from the device.
The Control Block Registers are used for device control and to post alternate status.
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9.2 Alternate Status Register
Table 55: Alternate Status Register
76543210
BSY RDY DF
This register contains the same information as the Status Register. The only difference between this register and the
Status Register is that reading the Alternate Status Register does not imply an interrupt acknowledge or a clear of a
pending interrupt. See section 9.14 ‘Status Register” on page 78 for the definition of the bits in this register.
DSC/
SERV
DRQ COR IDX ERR
9.3 Command Register
This register contains the command code being sent to the device. Command execution begins immediately after
this register is written. The command set is shown in Table 71: ‘Command Set” on page 115 and Table
74: ‘Command Set (2 of 2)” on page 106. All other registers required for the command must be set up before writing to the Command Register.
9.4 Cylinder High Register
This register contains the high order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 16–23. At the end of the command, this register is updated to reflect the
current LBA Bits 16–23.
The cylinder number may be from zero to the number of cylinders minus one.
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 16-23 and the
"previous content" contains Bits 40-47. The 48-bit Address feature set is described in Section 9.16, "48-Bit
Address Feature Set" on page 93.
9.5 Cylinder Low Register
This register contains the low order 8 bits of the starting cylinder address for any disk access. At the end of the
command, this register is updated to reflect the current cylinder number.
In LBA Mode this register contains Bits 8–15. At the end of the command, this register is updated to reflect the
current LBA Bits 8–15.
The cylinder number may be from zero to the number of cylinders minus one (1).
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 8-15 and the
"previous content" contains Bits 32-39.
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9.6 Data Register
This register is used to transfer data blocks between the device data buffer and the host. It is also the register
through which sector information is transferred on a Format Track command and the configuration information is
transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO
only.
The register contains valid data only when DRQ = 1 is in the Status Register.
9.7 Device Control Register
Table 56: Device Control Register
76543210
HOB---1SRST -IEN 0
Bit Definitions
HOB
SRST Software Reset. The device is held at reset when RST = 1. Setting RST = 0 again enables the
-IEN Interrupt Enable. When IEN = 0, and the device is selected, the device interrupts to the host will
HOB (high order byte) is defined by the 48-bit Address feature set. A write to any Command
Register shall clear the HOB bit to zero.
device. To ensure that the device recognizes the reset, the host must set RST = 1 and wait for at
least 5 ms before setting RST = 0.
be enabled. When IEN = 1, or the device is not selected, the device interrupts to the host will be
disabled.
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9.8 Drive Address Register
Table 57: Drive Address Register
76543210
HIZ -WTG -H3 -H2 -H1 -H0 -DS1 -DS0
This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions
HIZ High Impedance. This bit is not a device and will always be in a high impedance state.
-WTG Write Gate. This bit is 0 when writing to the disk device is in progress.
-H3, -H2,H1,-H0-
-Head Select. These four bits are the one's complement of the binary coded address of the currently selected head. Bit -H0 is the least significant.
-DS1 Drive Select 1. The Drive Select bit for device 1 is active low. DS1 = 0 when device 1 (slave) is
selected and active.
-DS0 Drive Select 0. The Drive Select bit for device 0 is active low. DS0 = 0 when device 0 (master) is
selected and active.
9.9 Device/Head Register
Table 58: Device Head/Register
76543210
1 L 1 DRV HS3 HS2 HS1 HS0
This register contains the device and head numbers.
Bit Definitions
L Binary encoded address mode select. When L = 0, addressing is by CHS mode. When L = 1,
addressing is by LBA mode.
DRV Device. When DRV = 0, device 0 (master) is selected. When DRV = 1, device 1 (Slave) is
selected.
HS3, HS2,
HS1, HS0
Head Select. These four bits indicate the binary encoded address of the head. Bit HS0 is the least
significant bit. At command completion, these bits are updated to reflect the currently selected
head. The head number may be from zero to the number of heads minus one. In LBA mode, HS3
through HS0 contain bits 24–27 of the LBA. At command completion these bits are updated to
reflect the current LBA bits 24–27.
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9.10 Error Register
Table 59: Error Register
76543210
CRC UNC 0 IDNF 0 ABRT TK0NF AMNF
This register contains the statu s from the la st command e xecuted by the device or a diagnostic code. At the completion of any command, except Execute Device Diagnostic, the contents of this register are always valid even if
ERR = 0 is in the Status Register.
Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register contains a
diagnostic code. See Table 63: ‘Diagnostic codes” on page 82 for the definitions.
Bit Definitions
ICRCE
(CRC)
UNC Uncorrectable Data Error. When UNC = 1 it indicates that an uncorrectable data error has been
IDNF
(IDN)
ABRT
(ABT)
TK0NF
(T0N)
AMNF
(AMN)
Interface CRC Error. When CRC = 1, it indicates that a CRC error has occurred on the data bus
during a Ultra DMA transfer.
encountered.
ID Not Found. When IDN = 1, it indicates that the requested sector's ID field could not be found.
Aborted Command. When ABT = 1, it indicates that the requested command has been aborted
due to a device status error or an invalid parameter in an output register.
Track 0 Not Found. When T0N = 1, it indicates that track 0 was not found during a Recallibrate
command.
Address Mark Not Found. When AMN = 1, it indicates that the data address mark has not been
found after finding the correct ID field for the requested sector.
9.11 Features Register
This register is command specific. It is used with the Set Features command, the S.M.A.R.T. Function Set command, and the Format Unit command.
9.12 Sector Count Register
This register contains the number of sectors of data requested to be transferred on a read or write operation between
the host and the device. If the value in the register is set to 0, a count of 256 secto rs (in 28-bit addressing) or 65,53 6
sectors (in 48-bit addressing) is specified.
If the register is zero at command completion, the command was successful. If it is not successfully completed, the
register contains the number of sectors which need to be transferred in order to complete the request.
The contents of the register are defined otherwise on some commands. These definitions are given in the command
descriptions.
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9.13 Sector Number Register
This register contains the starting sector number for any disk data access for the subsequent command. The sector
number is from one to the maximum number of sectors per track.
In LBA mode, this register contains Bits 0–7. At the end of the command this register is updated to reflect the current LBA Bits 0–7.
When 48-bit commands are used, the "most recently written" content contains LBA Bits 0-7 and the "previous content" contains Bits 24-31.
9.14 Status Register
Table 60: Status Register
76543210
BSY DRDY DF
DSC/
SERV
DRQ CORR IDX ERR
This register contains the device status. The contents of this register are updated whenever an error occurs and at
the completion of each command.
If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any
pending interrupt is cleared whenever this register is read.
If BSY=1, no other bits in the register are valid.
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Bit Definitions
BSY Busy. Bit BSY=1 whenever the device is accessing the registers. The host should not read or write
any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status
Register will be returned.
DRDY
(RDY)
Device Ready. RDY=1 indicates that the device is capable of responding to a command. RDY
will be set to zero during power on until the device is ready to accept a command. If the device
detects an error while processing a command, RDY is set to zero until the Status Register is read
by the host, at which time RDY is set back to one.
DF Device Fault. This product does not support DF bit. DF is always zero.
DSC Device Seek Complete. If DSC=1, it indicates that a Seek has completed and the device head is
settled over a track. Bit DSC is set to 0 by the device just before a Seek begins. When an error
occurs, this bit is not changed until the Status Register is read by the host at which time the bit
again indicates the current Seek complete status. When the device enters into or is in Standby
mode or Sleep mode, this bit is set by the device in spite of the drive not spinning up.
DRQ Data Request. Bit DRQ=1 indicates that the device is ready to transfer a word or byte of data
between the host and the device. The host should not write the Command register when DRQ=1.
CORR
Corrected Data. Always 0
(COR)
IDX Index. IDX=1 once per revolution. Because IDX=1 only for a very short time during each revolu-
tion, the host may not see it set to 1 even if the host is continuously reading the Status Register.
Therefore the host should not attempt to use IDX for timing purposes.
ERR Error. ERR=1 indicates that an error occurred during execution of the previous command. The
Error Register should be read to determine the error type. The device sets bit ERR=0 when the
next command is received from the host.
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10.0 General operation
10.1 Reset response
ATA has the following three types of resets:
Power On Reset (POR)
The device executes a series of electrical circuitry diagnostics, spins up the
head disk assembly, tests speed and other mechanical parametric, and sets
default values.
Hard Reset (Hardware Reset)
The RESET- signal is negated in the ATA Bus. The device resets the interface
circuitry and sets the default values.
Soft Reset (Software Reset)
The SRST bit in the Device Control Register is set and then is reset. The device
resets the interface circuitry according to the Set Features requirement.
The actions of each reset are shown in the table below.
Table 61: Reset response table
Aborting Host interface
Aborting Device operation
Initialization of hardware
Internal diagnostic
Spinning spindle
Initialization of registers (*2)
DASP handshake
PDIAG handshake
Reverting programmed parameters to default
Number of CHS (set by Initialize
Device Parameters)
Multiple mode
Write Cache
Read look-ahead
ECC bytes
Power mode
Disable Standby timer(*5)
POR hard reset soft reset
-OO
- (*1) (*1)
OXX
OXX
OXX
OOO
OOX
OOO
O (*3) (*3)
(*5) (*4) (*4)
OXX
O – execute X – does not execute
Notes:
(*1) Execute after the data in write cache has been written.
(*2) The default value on POR is shown in Table 62: “Default Register Values” on page 82.
(*3) The Set Features command with Feature register = CCh enables the device to revert these parameters to the
power on defaults.
(*4) In the case of Sleep mode, the device goes to Standby mode. In other cases, the device does not change current
mode.
(*5) Idle when Power-Up in Standby feature set is disabled. Standby when Power-Up in Standby feature set is
enabled.
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10.2 Register initialization
After a power on, a hard reset, or a software reset, the register values are initialized as shown in the table below.
Table 62: Default Register Values
Register Default Value
Error Diagnostic Code
Sector Count 01h
Sector Number 01h
Cylinder Low 00h
Cylinder High 00h
Device/Head A0h
Status 50h
Alternate Status 50h
The meaning of the Error Register diagnostic codes resulting from power on, hard reset, or the Execute Device
Diagnostic command is shown in the figure below.
Table 63: Diagnostic code s
Code Description
01h No error detected
02h Formatter device error
03h Sector buffer error
04h ECC circuitry error
05h Controller microprocessor error
8xh Device 1 failed
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10.3 Diagnostic and Reset considerations
For each Reset and Execute Device Diagnostic, the diagnostic is done as follows:
Power On Reset DASP– is read by Device 0 to determine if Device 1 is present. If Device 1 is present,
Device 0 shall read PDIAG– to determine when it is valid to clear the BSY bit and
whether Device 1 has powered on or reset without error, otherwise Device 0 clears the
BSY bit whenever it is ready to accept commands. Device 0 may assert DASP– to
indicate device activity.
Hard Reset,
Soft Reset
Execute Device
Diagnostic
In each case – Power On Reset [Hard Reset], Soft Reset, and the Execute Device Diagnostic command – the
Device 0 Error register value is interpreted using the table below.
Table 64: Reset error register values
If Device 1 is present, Device 0 shall read PDIAG– to determine when it is valid to clear
the BSY bit and whether Device 1 has reset without any errors; otherwise, Device 0 shall
simply reset and clear the BSY bit. DASP– is asserted by Device 0 (and Device 1 if it is
present) in order to indicate device active.
If Device 1 is present, Device 0 shall read PDIAG– to determine when it is valid to clear
the BSY bit and if Device 1 passed or failed the EXECUTE DEVICE DIAGNOSTIC
command; otherwise, Device 0 shall simply execute its diagnostics and then clear the
BSY bit. DASP– is asserted by Device 0 (and Device 1 if it is present) in order to
indicate that the device is active.
Device 1 present? PDIAG- Asserted? Device 0 Passed Error Register
Yes Yes Yes 01h
Yes Yes No 0xh
Yes No Yes 81h
Yes No No 8xh
No (not read) Yes 01h
No (not read) No 0xh
The "x" indicates the appropriate Diagnostic Code for the Power on, RESET-, Soft Reset, or Device Diagnostic
error.
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10.4 Sector Addressing Mode
All addressing of data sectors recorded on the device's media is done by a logical sector address. The logical CHS
address for HDS7280x0PLATy0 is different from the actual physical CHS location of the data sector on the disk
media.
HDS7280x0PLATy0 supports both Logical CHS Addressing Mode and LBA Addressing Mode as the sector
addressing mode.
The host system may select either the currently selected CHS translation addressing or LBA addressing on a
command-by-command basis by using the L bit in the DEVICE/HEAD register. A host system must set the L bit to
1 if the host uses LBA Addressing mode.
10.4.1 Logical CHS addressing mode
The logical CHS addressing is made up of three fields: the cylinder number, the head number, and the sector number.
Sectors are numbered from 1 to the maximum value allowed by the current CHS translation mode but cannot exceed
255 (0FFh). Heads are numbered from 0 to the maximum value allowed by the current CHS translation mode but
cannot exceed 15 (0Fh). Cylinders are numbered from 0 to the maximum value allowed by the current CHS
translation mode but cannot exceed 65535 (0FFFFh).
When the host selects a CHS translation mode using the INITIAL IZE DEVICE PARAMETERS command, the host
requests the number of sectors per logical track and the number of heads per logical cylinder. The device then
computes the number of logical cylinders available in requested mode.
The default CHS translation mode is described in the Identify Device Information. The current CHS translation
mode also is described in the Identify Device Information.
10.4.2 LBA addressing mode
Logical sectors on the device shall be linearly mapped with the first LBA addressed sector (sector 0) being the same
sector as the first logical CHS addressed sector (cylinder 0, head 0, sector 1). Irrespective of the logical CHS
translation mode currently in effect, the LBA address of a given logical sector does not change. The following
formula is always true:
LBA = ((cylinder x heads_per_cylinder + heads) x sectors_per_track) + sector - 1
where heads_per_cylinder and sectors_per_track are the current translation mode values.
On LBA addressing mode the LBA value is set to the following register:
Device/Head <- - - LBA bits 27–24
Cylinder High <- - - LBA bits 23–16
Cylinder Low <- - - LBA bits 15–8
Sector Number <- - - LBA bits 7–0
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10.5 Power management features
The power management feature set permits a host to modify the behavior in a manner which reduces the power
required to operate. The power management feature set provides a set of commands and a timer that enables a device
to implement low power consumption modes.
HDS7280x0PLATy0 implements the following set of functions:
• A Standby timer
• Idle command
• Idle Immediate command
• Sleep command
• Standby command
• Standby Immediate command
10.5.1 Power mode
Sleep Mode The lowest power consumption when the device is powered on occurs in Sleep Mode. When
in Sleep Mode, the device requires a reset to be activated.
Standby
Mode
Idle Mode In Idle Mode the device is capable of responding immediately to media access requests.
Active Mode The device is executing a command or accessing the disk media with the read look-ahead
The device interface is capable of accepting commands, but since the media may not be
immediately accessible, there is a delay while waiting for the spindle to reach operating
speed.
function or the write cache function.
10.5.2 Power management commands
Check Power
Mode
Idle, Idle
Immediate
Sleep Moves a device to sleep mode. The device's interface becomes inactive at the completion of the
Standby,
Standby
Immediate
Allows a host to determine if a device is currently in, going to, or leaving standby mode.
Move a device to idle mode immediately from the active or standby modes. The idle command
also sets the standby timer count and starts the standby timer.
sleep command. A reset is required to move a device out of sleep mode. When a device exits
sleep mode it will enter standby mode.
Move a device to standby mode immediately from the active or idle modes. The standby
command also sets the standby timer count.
10.5.3 Standby timer
The standby timer provides a method for the device to automatically enter standby mode from either active or idle
mode following a host programmed period of inactivity. If the device is in the active or idle mode, the device waits
for the specified time period and, if no command is received, the device automatically enters the standby mode.
If the value of the SECTOR COUNT register on Idle command or Standby command is set to 00h, the standby timer
is disabled.
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10.5.4 Interface capability for power modes
Each power mode affects the physical interface as defined in the following table:
Table 65: Power con di tions
Mode BSY RDY Interface active Media
Active x x Yes Active
Idle o 1 Yes Active
Standby o 1 Yes Inactive
Sleep x x No Inactive
Ready (RDY) is not a power condition. A device may post ready at the interface even though the media may not be
accessible.
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10.6 S.M.A.R.T. Function
The intent of Self-monitoring, analysis, and reporting technology (S.M.A.R.T.) is to protect user data and prevent
unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By
monitoring and storing critical performance and calibration parameters, S.M.A.R.T. devices employ sophisticated
data analysis algorithms to predict the likelihood of near-term degradation or fault condition. By alerting the host
system of a negative reliability status condition, the host system can warn the user of the impending risk of a data
loss and advise the user of appropriate action.
10.6.1 Attributes
Attributes are the specific performance or calibration parameters that are used in analyzing the status of the device.
Attributes are selected by the device manufacturer based on that attribute's ability to contribute to the prediction of
degrading or faulty conditions for that particular device. The specific set of attributes being used and the identity of
these attributes is vendor specific and proprietary.
10.6.2 Attribute values
Attribute values are used to represent the relative reliability of individual performance or calibration attributes. The
valid range of attribute values is from 1 to 253 decimal. Higher attribute values indicate that the analysis algorithms
being used by the device are predicting a lower probability of a degrading or faulty condition existing. Accordingly,
lower attribute values indicate that the analysis algorithms being used by the device are predicting a higher
probability of a degrading or faulty condition.
10.6.3 Attribute thresholds
Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute
value to indicate the existence of a degrading or faulty condition. The numerical value of the attribute thresholds are
determined by the device manufacturer through design and reliability testing and analysis. Each attribute threshold
represents the lowest limit to which its corresponding attribute value can be equal while still retaining a positive
reliability status. Attribute thresholds are set at the device manufacturer's factory and cannot be changed in the field.
The valid range for attribute thresholds is from 1 through 253 decimal.
10.6.4 Threshold exceeded condition
If one or more attribute values, whose Pre-failure bit of their status flag is set, are less than or equal to their
corresponding attribute thresholds, the device reliability status is negative, indicating an impending degrading or
faulty condition.
10.6.5 S.M.A.R.T. commands
The S.M.A.R.T. commands provide access to attribute values, attribute thresholds, and other logging and reporting
information.
10.6.6 Off-line read scanning
The device provides the off-line read scanning feature with reallocation. This is the extension of the off- line data
collection capability. The device performs the entire read scan with reallocation of the marginal sectors to prevent
loss of user data.
If interrupted by the host during the read scanning, the device services the host command.
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10.6.7 Error log
Logging of reported errors is supported. The device provides information on the last five errors that the device
reported as described in the SMART error log sector. The device may also provide additional vendor specific
information on these reported errors. The error log is not disabled when SMART is disabled. Disabling SMART
disables the delivering of error log information via the SMART READ LOG SECTOR command.
If a device receives a firmware modification, all error log data is discarded and the device error count for the life of
the device is reset to zero.
10.6.8 Self-test
The device provides the self-test features which are initiated by SMART Execute Off-line Immediate
command. The self-test checks the fault of the device, reports the test status in Device Attributes Data, and stores
the test result in the SMART self-test log sector as described in the SMART self-test log data structure. All SMART
attributes are updated accordingly during the execution of self-test.
If it is interrupted by the host during the self-tests, the device services the host command.
If the device receives a firmware modification, all self-test log data is discarded
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10.7 Security Mode Feature Set
Security Mode Feature Set is a powerful security feature. With a device lock password, a user can prevent
unauthorized access to a device even if it is removed from the computer.
New commands are supported for this feature as listed below:
Security Set Password ('F1'h)
Security Unlock ('F2'h)
Security Erase Prepare ('F3'h)
Security Erase Unit ('F4'h)
Security Freeze Lock ('F5'h)
Security Disable Password ('F6'h)
10.7.1 Security mode
The following security modes are provided:
Device Locked
Mode
Device Unlocked
Mode
Device Frozen Mode The device enables all commands except those which can update the device lock
The device disables media access commands after power on. Media access
commands are enabled by either a Security Unlock command or a Security Erase
Unit command.
The device enables all commands. If a password is not set this mode is entered after
power on, otherwise it is entered by a Security Unlock or a Security Erase Unit
command.
function, set/change password. The device enters this mode via a Security Freeze
Lock command. It cannot quit this mode until power off.
10.7.2 Security level
The following security levels are provided:
High level security When the device lock function is enabled and the User Password is forgotten, the
device can be unlocked via a Master Password.
Maximum level
security
When the device lock function is enabled and the User Password is forgotten,
only the Master Password with a Security Erase Unit command can unlock the
device. User data is then erased.
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10.7.3 Passwords
This function can have two types of passwords as described b elow.
Master Password When the Master Password is set, the device does NOT enable the Device Lock
Function, and the device CANNOT be locked with the Master Password, but the
Master Password can be used for unlocking the locked device.
Identify Device Information word 92 contains the value of the Master Password
Revision Code set when the Master Password was last changed. Valid values are
0001h through FFFEh.
User Password The User Password should be given or changed by a system user. When the User
Password is set, the device enables the Device Lock Function, and the device is
then locked on the next power on reset or hard reset.
The system manufacturer or dealer who intends to enable the device lock function for end users must set the master
password even if only single level password protection is required.
10.7.4 Operation example
10.7.4.1 Master Password setting
The system manufacturer or dealer can set a new Master Password from default Master Password using the Security
Set Password command without enabling the Device Lock Function.
The Master Password Revision Code is set to FFFEh as shipping default by the drive manufacturer.
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10.7.4.2 User Password setting
When a User Password is set, the device will automatically enter lock mode the next time the device is powered on.
Table 66: Initial setting
< Setting password >
POR
Set Password with User Password
Normal operation
Power off
POR
Device locked mode
< No setting password >
POR
Normal operation
Power off
POR
Device unlocked mode
10.7.4.3 Operation from POR after user password is set
When Device Lock Function is enabled, the device rejects media access command until a Security Unlock command
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is successfully completed.
POR
Device Locked mode
Unlock CMD
Password
Match ?
N
Enter Device
Unlock mode
Y
Enter Device Frozen mode
Normal Operation expect Set Password,
Disable Password, Erase Unit, Unlock commands.
Table 67: Usual operation for POR
Erase Prepare
Erase Unit
Password
Match ?
Y
Complete
Erase Unit
Lock function
Disable
Normal operation : All commands are available
Freeze Lock command
N
Media Access
Command (*1) Command (*1)
Reject
Non-media Access
Complete
(*1) — refer to the commands in Figure 10.7.5, “Command table” on page 84.
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10.7.4.4 User Password lost
If the User Password is forgotten and High level security is set, the system user cannot access any data. However
the device can be unlocked using the Master Password.
If a system user forgets the User Password and Maximum security level is set, data access is impossible. However
the device can be unlocked using the Security Erase Unit command to unlock the device and erase all user data with
the Master Password.
User Password L ost
LEVEL ? High
Maximum
Erase Prepare Command
Erase Unit Command
with Master Password
Normal operatio n but data lost
Table 68: Password lost
Unlock CMD with Master Password
Normal operation
10.7.4.5 Attempt limit for the SECURITY UNLOCK command
The SECURITY UNLOCK command has an attempt limit, the purpose of which is to prevent attempts to unlock
the drive with various passwords numerous times.
The device counts the password mismatch. If the password does not match, the device counts it without
distinguishing the Master password and the User password. If the count reaches 5, EXPIRE bit (bit 4) of Word 128
in Identify Device information is set, and then the SECURITY ERASE UNIT command and the SECURITY
UNLOCK command are aborted until a hard reset or a power off. The count and EXPIRE bit are cleared after a
power on reset or a hard reset.
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10.7.5 Command table
This table shows the device's response to commands when the Security Mode Feature Set (Device lock function) is
enabled.
Command Locked Mode Unlocked Mode Frozen Mode
Check Power Mode Executable Executable Executable
Configure Stream Command aborted Executable Executable
Execute Device
Diagnostic
Device Configuration
Restore
Device Configuration
Freeze Lock
Device Configuration
Identify
Device Configuration
Set
Download Microcode Command aborted Executable Executable
Flush Cache Command aborted Executable Executable
Flush Cache Ext Command aborted Executable Executable
Format Track Command aborted Executable Executable
Identify Device Executable Executable Executable
Idle Executable Executable Executable
Idle Immediate Executable Executable Executable
Initialize Device
Parameters
Read Buffer Executable Executable Executable
Read DMA Command aborted Executable Executable
Read DMA Ext Command aborted Executable Executable
Read Log Ext Command aborted Executable Executable
Read Long Command aborted Executable Executable
Read Multiple Command aborted Executable Executable
Read Multiple Ext Command aborted Executable Executable
Read Native Max Address Executable Executable Executable
Read Native Max Ext Executable Executable Executable
Read Sector(s) Command aborted Executable Executable
Read Sector(s) Ext Command aborted Executable Executable
Read Stream DMA Command aborted Executable Executable
Read Stream PIO Command aborted Executable Executable
Read Verify Sector(s) Command aborted Executable Executable
Read Verify Sector(s)
Ext
Recalibrate Executable Executable Executable
Security Disable
Password
Executable Executable Executable
Command aborted Executable Executable
Executable Executable Executable
Executable Executable Executable
Command aborted Executable Executable
Executable Executable Executable
Command aborted Executable Executable
Command aborted Executable Command aborted
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Security Erase Prepare Executable Executable Command aborted
Security Erase Unit Executable Executable Command aborted
Security Freeze Lock Command aborted Executable Executable
Security Set Password Command aborted Executable Command aborted
Security Unlock Executable Executable Command aborted
Seek Executable Executable Executable
Set Features Executable Executable Executable
Set Max Address Command aborted Executable Executable
Set Max Address Ext Command aborted Executable Executable
Set Multiple Mode Executable Executable Executable
Sleep Executable Executable Executable
SMART Disable
Executable Executable Executable
Operations
SMART Enable/Disable
Executable Executable Executable
Attributes Autosave
SMART Enable Operations Executable Executable Executable
SMART Execute Off-line
Executable Executable Executable
Immediate
SMART Read Attribute
Executable Executable Executable
Values
SMART Read Attribute
Executable Executable Executable
Thresholds
SMART Return Status Executable Executable Executable
SMART Save Attribute
Executable Executable Executable
Values
SMART Read Log Sector Executable Executable Executable
SMART Write Log Sector Executable Executable Executable
SMART Enable/Disable
Executable Executable Executable
Automatic Off-Line
Standby Executable Executable Executable
Standby Immediate Executable Executable Executable
Write Buffer Executable Executable Executable
Write DMA Command aborted Executable Executable
Write DMA Ext Command aborted Executable Executable
Write Log Ext Command aborted Executable Executable
Write Long Command aborted Executable Executable
Write Multiple Command aborted Executable Executable
Write Multiple Ext Command aborted Executable Executable
Write Sector(s) Command aborted Executable Executable
Write Sector(s) Ext Command aborted Executable Executable
Write Stream DMA Command aborted Executable Executable
Write Stream PIO Command aborted Executable Executable
o - executable x - command aborted
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10.8 Host Protected Area Feature
Host Protected Area Feature provides a protected area which cannot be accessed via conventional methods. This
protected area is used to contain critical system data such as BIOS or system management information. The contents
of the main memory of the entire system may also be dumped into the protected area to resume after a system power
off.
The following set of commands changes the LBA/CYL, which affects the Identify Device Information:
• Read Native Max ADDRESS ('F8'h)
• Set Max ADDRESS ('F9'h)
10.8.1 Example for operation (In LBA Mode)
The following example uses hypothetical values.
Capacity (native) 6,498,680,832 byte (6.4 GB)
Max LBA (native) 12,692,735 (0FFFFFh)
Required size for protected area 206,438,400 bytes
Required blocks for protected area 403,200 (062700h)
Customer usable device size 6,292,242,432 byte (6.2 GB)
Customer usable sector count 12,289,536 (BB8600h)
LBA range for protected area BB8600h to C1ACFFh
1. Shipping of drives from the drive manufacturer
When the drive is shipped from the manufacturer, the device has been tested to have a capacity of 6.4 GB
besides flagged media defects not visible by the system.
2. Preparation of drives by the system manufacturer
Special utility software is required to define the size of the protected area and to store the data in it. The sequence is
as follows:
i. Issue a Read Native Max ADDRESS command to get the real device maximum LBA. Returned value
shows that native device maximum LBA is 12,692,735 (C1ACFFh) regardless of the current setting.
ii. Make the entire device accessible, including the protected area, by setting the device maximum LBA to
12,692,735 (C1ACFFh) via Set Max ADDRESS command. The option may be either nonvolatile or
volatile.
iii. Test the sectors for protected area (LBA > = 12,289,536 (BB8600h)) if required.
iv. Write information data such as BIOS code within the protected area.
v. Change maximum LBA using Set Max ADDRESS command to 12,289,535 (BB85FFh) with nonvolatile
option.
vi. From this point the protected area cannot be accessed until next Set Max ADDRESS command is issued.
Since the device functions in the same manner as a 6.2 GB device, any BIOS, device driver, or
application software will access the drive as if it were a 6.2 GB device.
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