Hitachi H8/3152, H8/3153, HD6483152, HD6483155, HD6483153 Hardware Manual

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Page 1

Hitachi Single-Chip Microcomputer

H8/3150 Series

H8/3152

HD6483152

H8/3153

HD6483153

H8/3155

HD6483155

H8/3156

ADE-602-182 Rev. 1.0 3/11/99 Hitachi, Ltd.

HD6483156

H8/3158

HD6483158

Hardware Manual

Page 2

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

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Preface

The H8/3150 series is a single-chip microcomputer built around a high-speed H8/300 CPU core. On-chip facilities include an EEPROM, a ROM, a RAM, two I/O ports, a random number generator (RNG), and a watchdog timer (WDT).

On-chip EEPROM makes the H8/3150 series ideal for applications requiring nonvolatile data storage, including smart cards and portable data banks. Security functions protect data in the internal memory against illegal external reading and writing.

This manual describes the H8/3150 series hardware. For details of the instruction set, refer to the H8/300 Series Programming Manual.

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Contents

Section 1 Overview.......................................................................................... 1

1.1 Overview............................................................................................................................ 1

1.2 Block Diagram................................................................................................................... 4

1.3 Pin Arrangement and Functions........................................................................................ 5

1.3.1 Pin Arrangement .................................................................................................. 5

1.3.2 Pin Functions........................................................................................................ 7

Section 2 CPU.................................................................................................. 9

2.1 Overview............................................................................................................................ 9

2.1.1 Features ................................................................................................................ 9

2.1.2 CPU Registers ...................................................................................................... 11

2.2 Register Descriptions......................................................................................................... 12

2.2.1 General Registers.................................................................................................. 12

2.2.2 Control Registers.................................................................................................. 12

2.2.3 Initial Register Values.......................................................................................... 14

2.3 Data Formats...................................................................................................................... 14

2.3.1 Data Formats in General Registers....................................................................... 15

2.3.2 Memory Data Formats.......................................................................................... 16

2.4 Addressing Modes.............................................................................................................17

2.4.1 Addressing Modes................................................................................................ 17

2.4.2 Effective Address Calculation.............................................................................. 19

2.5 Instruction Set.................................................................................................................... 22

2.5.1 Data Transfer Instructions.................................................................................... 24

2.5.2 Arithmetic Operations.......................................................................................... 26

2.5.3 Logic Operations.................................................................................................. 27

2.5.4 Shift Operations.................................................................................................... 27

2.5.5 Bit Manipulations................................................................................................. 29

2.5.6 Branching Instructions.......................................................................................... 33

2.5.7 System Control Instructions................................................................................. 35

2.5.8 EEPROM Write Instruction ................................................................................. 36

2.6 Operating States................................................................................................................. 37

2.6.1 Overview.............................................................................................................. 37

2.6.2 Program Execution State...................................................................................... 38

2.6.3 Exception-Handling State .................................................................................... 38

2.6.4 Power-Down State................................................................................................ 38

2.7 Exception Handling...........................................................................................................39

2.7.1 Overview.............................................................................................................. 39

2.7.2 Reset..................................................................................................................... 40

2.7.3 Interrupts .............................................................................................................. 40

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2.7.4 Reset Start Timing................................................................................................ 41

2.8 Power-Down State.............................................................................................................42

2.8.1 Overview.............................................................................................................. 42

2.8.2 Transition to Sleep Mode ..................................................................................... 42

2.8.3 Exit from Sleep Mode .......................................................................................... 43

Section 3 Memory Maps.................................................................................. 45

Section 4 Random Number Generator (RNG)................................................. 51

4.1 Overview............................................................................................................................ 51

4.1.1 Features ................................................................................................................ 51

4.1.2 Register Configuration ......................................................................................... 51

4.2 Register Descriptions......................................................................................................... 52

4.2.1 RNG Control Status Register (RCSR) ................................................................. 52

4.2.2 RNG Result Register (RNRR).............................................................................. 53

4.3 Operation........................................................................................................................... 54

4.4 Notes on Usage.................................................................................................................. 55

Section 5 Watchdog Timer (WDT)................................................................. 57

5.1 Overview............................................................................................................................ 57

5.1.1 Features ................................................................................................................ 57

5.1.2 Block Diagram...................................................................................................... 58

5.1.3 Register Configuration ......................................................................................... 58

5.1.4 Vector Configuration............................................................................................ 59

5.2 Register Descriptions......................................................................................................... 59

5.2.1 Timer Counter (TCNT)........................................................................................ 59

5.2.2 Timer Control/Status Register (TCSR)................................................................ 60

5.2.3 Timer Counter Write Address (TCWA)............................................................... 61

5.3 Operation........................................................................................................................... 63

5.3.1 Checking Application Program Execution Area.................................................. 63

5.3.2 Checking the Procedure for Writing to EEPROM............................................... 65

5.3.3 Reloading TCNT by TCWA Function................................................................. 67

5.3.4 Initializing WDT .................................................................................................. 69

5.4 Notes on Usage.................................................................................................................. 70

Section 6 RAM................................................................................................ 71

6.1 Overview............................................................................................................................ 71

6.1.1 Block Diagram...................................................................................................... 71

Section 7 ROM................................................................................................ 73

7.1 Overview............................................................................................................................ 73

7.1.1 Block Diagram...................................................................................................... 73

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Section 8 EEPROM ......................................................................................... 77

8.1 Overview............................................................................................................................ 77

8.1.1 Features ................................................................................................................ 77

8.1.2 Block Diagram...................................................................................................... 78

8.1.3 Memory Organization .......................................................................................... 79

8.1.4 Register Configuration ......................................................................................... 81

8.2 Register Descriptions......................................................................................................... 82

8.2.1 EEPROM Control Register (ECR)....................................................................... 82

8.2.2 EEPROM Protection Register (EPR)................................................................... 83

8.3 EEPROM Read Operation ................................................................................................ 83

8.4 EEPROM Write and Erase Operations.............................................................................. 84

8.4.1 Write/Erase Sequence .......................................................................................... 84

8.4.2 Rewrite ................................................................................................................. 86

8.4.3 Erase..................................................................................................................... 87

8.4.4 Overwrite.............................................................................................................. 87

8.5 Write/Erase Protection.......................................................................................................88

8.5.1 Protect Bits ........................................................................................................... 88

8.5.2 Protection Procedure ............................................................................................ 89

8.5.3 Reading the Protect Bits....................................................................................... 91

8.6 Notes on Usage.................................................................................................................. 92

8.7 Notes on Usage of H8/3153 .............................................................................................. 94

Section 9 I/O Ports........................................................................................... 97

9.1 Overview............................................................................................................................ 97

9.1.1 Block Diagram...................................................................................................... 97

9.1.2 Register Configuration ......................................................................................... 99

9.2 Register Descriptions......................................................................................................... 99

9.2.1 Data Register (DR)............................................................................................... 99

9.2.2 Data Direction Register (DDR)............................................................................ 100

9.3 Pin Functions..................................................................................................................... 100

Section 10 Clock Pulse Generator .....................................................................103

10.1 Overview............................................................................................................................ 103

10.2 System Control Register.................................................................................................... 104

Section 11 Security............................................................................................105

11.1 Overview............................................................................................................................ 105

11.2 Error Detection in Sleep Mode.......................................................................................... 105

Section 12 Electrical Characteristics..................................................................107

12.1 Absolute Maximum Ratings.............................................................................................. 107

12.2 Electrical Characteristics ................................................................................................... 108

12.2.1 DC Characteristics (5 V, CPU operates at half of the external clock frequency) 109

iii

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12.2.2 AC Characteristics (5 V, CPU operates at half of the external clock frequency) 110

12.2.3 DC Characteristics (5 V, CPU operates at the external clock frequency)............ 111

12.2.4 AC Characteristics (5 V, CPU operates at the external clock frequency)............ 112

12.2.5 DC Characteristics (3 V, CPU operates at half of the external clock frequency) 114

12.2.6 AC Characteristics (3 V, CPU operates at half of the external clock frequency) 115

12.2.7 DC Characteristics (3 V, CPU operates at the external clock frequency)............ 116

12.2.8 AC Characteristics (3 V, CPU operates at the external clock frequency)............ 117

Appendix A Instruction Set...............................................................................119

Appendix B Operation Code Map.....................................................................127

Appendix C Register Field................................................................................129

C.1 Register Field (1)............................................................................................................... 129

C.2 Register Field (2)............................................................................................................... 130

Appendix D Comparison with H8/3102, H8/3103............................................135

Appendix E H8/3150 Series DP-64S Pin Arrangement....................................138

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Section 1 Overview

1.1 Overview

The H8/3150 series is a single-chip microcomputer unit (MCU) built around a high-speed H8/300 CPU core. An EEPROM, a ROM, a RAM, two I/O ports, a random number generator (RNG), and a watchdog timer (WDT) are integrated onto the H8/3150 series chip.

Operating at a maximum 5-MHz internal clock rate at 5 V, the H8/300 CPU rapidly executes bitmanipulation instructions, arithmetic and logic instructions, and data transfer instructions.

Table 1.1 lists the features of the H8/3150 series.

Table 1.1 Features

Item Specification

CPU H8/300 CPU

Two-way general register configuration

• Sixteen 8-bit registers, or

• Eight 16-bit registers

High-speed operation

• Maximum clock rate: internal clock 5 MHz (at 5 V)

• Add/subtract: 0.4 µs

• Multiply/divide: 2.8 µs

Streamlined, concise instruction set

• Instruction length: 2 or 4 bytes

• Register-register arithmetic and logic operations

• MOV instruction for data transfer between registers and memory

Instruction set features

• Multiply instruction (8 bits × 8 bits)

• Divide instruction (16 bits ÷ 8 bits)

• Bit-accumulator instructions  Register-indirect specification of bit positions

• EEPROM write instruction (EEPMOV instruction)

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Table 1.1 Features (cont)

Item Specification

On-chip memory EEPROM

H8/3152: 8 kbytes + 256 bytes (32 bytes x (256 + 8) pages) H8/3153: 16 kbytes + 512 bytes (64 bytes x (256 + 8) pages) H8/3155: 1 kbyte + 128 bytes (16 bytes x (64 + 8) pages) H8/3156: 2 kbyte + 128 bytes (16 bytes x (128 + 8) pages) H8/3158: 16 kbytes + 512 bytes (64 bytes x (256 + 8) pages)

• Written by a special block data transfer instruction

• Page write (1 byte to page capacity) and erase

• Protected against accidental writing and erasing

• On-chip voltage pumping circuit

• Built-in oscillator and timer

• Write/erase time (max.): 10 ms (rewrite), 5 ms (erase, overwrite)

• Rewrite endurance: 10

• Data retention time: 10 years

times

ROM

H8/3152: 24 kbytes H8/3153: 32 kbytes H8/3155: 16 kbytes H8/3156: 16 kbytes H8/3158: 46 kbytes

RAM

H8/3152: 512 bytes H8/3153: 1 kbyte H8/3155: 512 bytes H8/3156: 512 bytes H8/3158: 1 kbyte

I/O ports Two general-purpose input/output ports (Also used for interrupts)

Note: When writing to the DDR7 and DDR6 bits, use the MOV instruction instead of the bit manipulation instruction.

Random number

Generates 16-bit random numbers.

generator (RNG)

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Table 1.1 Features (cont)

Item Specification

Watchdog timer (WDT) (option)

• Issues a UDF interrupt at a required interval.

• Issues an EWE interrupt before an EEPMOV instruction is executed.

• Stops the on-chip functions when the halt flag is set.

• One of four counter clock sources can be selected.

Note: Specify whether to operate or stop the WDT for each ROM code. If specifying that the WDT stops, do not access WDT control registers.

Interrupts Two external interrupt pins: I/O-1/IRQ and I/O-2/IRQ

• Used for interrupt input in sleep mode

• Same exception handling vector is assigned to both interrupts

Two internal interrupts: EWE and UDF from WDT Note: When sleep mode is entered, set DDR to 0 to use the pins as I/O input

ports before executing a SLEEP instruction. When writing to the DDR7 and DDR6 bits, use the MOV instruction instead of the bit manipulation instruction.

Power Single-voltage power supply

• 4.5 V to 5.5 V

• 2.7 V to 3.3 V

Clock frequency range

When the CPU operates at the external clock frequency (CPUCS0 = 1):

• f

= 1 MHz to 5 MHz (VCC = 4.5 V to 5.5 V)

CLK

= 1 MHz to 4 MHz (VCC = 2.7 V to 3.3 V)

CLK

When the CPU operates at half of the external clock frequency (CPUCS0 = 0):

= 1 MHz to 10 MHz (VCC = 4.5 V to 5.5 V) *

CLK

= 1 MHz to 5 MHz (VCC = 2.7 V to 3.3 V) *

CLK

: External clock frequency)

CLK

= 1 MHz to 5 MHz (VCC = 4.5 V to 5.5 V), and

CLK

= 1 MHz to 4 MHz (VCC = 2.7 V to 3.3 V).

Operating

• f

(f Note*: For H8/3153, f f

CLK

–25 to +85°C

temperature Power-down state Sleep mode (The sleep mode is entered by the SLEEP instruction) Security • High frequency detector

• High voltage detector

• Low frequency detector

• Low voltage detector

• Illegal access detector

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1.2 Block Diagram

Figure 1.1 shows an internal block diagram of the H8/3150 series.

CLK

RES

Clock divider

Address bus

H8/300 CPU

System control logic

Security logic

ROM

RAM

EEPROM

RNG

I/O port

WDT

I/O-1/IRQ I/O-2/IRQ

Data bus

Figure 1.1 Block Diagram

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1.3 Pin Arrangement and Functions

1.3.1 Pin Arrangement

Figure 1.2 shows the standard COT (chip on tape) pattern of the H8/3150 series. Figure 1.3 shows the bonding pad arrangement of the wafer product. The COT is mounted on a tape.

RES

CLK

I/O-1/IRQ

Figure 1.2 Standard COT Pattern (Electrode Surface)

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CLK

I/O-1/IRQ

Note:

RES

I/O-2/IRQ

User PAD

This figure shows the relative locations of the bonding pads on the chip. For accurate locations and chip dimensions, refer to the separately supplied specifications.

Figure 1.3 Bonding Pad Arrangement

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1.3.2 Pin Functions

Table 1.2 lists the functions of the H8/3150 series pins.

Table 1.2 Pin Functions

Type Symbol I/O Name and Description

Power supply V

I Power supply: 4.5 V to 5.5 V or 2.7 V to 3.3 V

I Ground: 0 V Clock CLK I Clock: External clock input Reset RES* Ports I/O-1/IRQ*

I Reset: Low input resets the chip.

I/O I/O port 1: One-bit data input/output port. Software can

select input or output.

Interrupt: In sleep mode, this port can receive interrupt

input.

I/O-2/IRQ*

I/O I/O port 2: One-bit data input/output port. Software can

select input or output.

Interrupt: In sleep mode, this port can receive interrupt

input.

Notes: 1. An input pull-up MOS is connected to the RES pin as shown in figure 1.4.

Input pull-up MOS

RES

Input buffer

Internal RES signal

Figure 1.4 Block Diagram of RES Pin

2. The I/O-1/IRQ and I/O-2/IRQ pins can be used as I/O ports and interrupt input pins. When these pins are not used, they must be left open.

Input pull-up MOS's are connected to these pins. See section 9, I/O Ports, for I/O-1/IRQ and I/O-2/IRQ specification details.

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Section 2 CPU

2.1 Overview

The H8/3150 series has an H8/300 CPU: an 8-bit central processing unit with a speed-oriented architecture featuring sixteen 8-bit general registers (or eight 16-bit general registers). This section describes the CPU features and functions, including a concise description of the addressing modes and instruction set. For further details on the instructions, see the H8/300 Series Programming

Manual.

2.1.1 Features

The main features of the H8/300 CPU are listed below.

• Two-way register configuration  Sixteen 8-bit general registers, or  Eight 16-bit general registers

• Instruction set with 55 basic instructions*, including:  Multiply and divide instructions  Powerful bit-manipulation instructions  EEPROM write instruction

• Eight addressing modes  Register direct: Rn  Register indirect: @Rn  Register indirect with displacement: @(d:16, Rn)  Register indirect with post-increment or pre-decrement: @Rn+ or @–Rn  Absolute address: @aa:8 or @aa:16  Immediate: #xx:8 or #xx:16  Program-counter relative: @(d:8, PC)  Memory indirect: @@aa:8

• 64-kbyte address space

Note: * The H8/300 CPU has 57 basic instructions, but the H8/3150 series uses only 55 of them.

The MOVFPE and MOVTPE instructions are not used.

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• High-speed operation  Every frequently-used instruction is executed in two to four states  Maximum clock rate is 5-MHz internal clock (at 5 V)

• 8- or 16-bit register-register add or subtract: 0.4 µs

• 8 × 8-bit multiply: 2.8 µs

• 16 ÷ 8-bit divide: 2.8 µs

• Power-down states  Entered by the SLEEP instruction

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2.1.2 CPU Registers

Figure 2.1 shows the register structure of the H8/300 CPU. There are two groups of registers: general registers and control registers.

General registers (Rn)

0707

Control registers (CR)

15 0

R0H R1H R2H R3H R4H R5H R6H R7H

R0L R1L R2L R3L R4L R5L R6L

(SP)

76543210

I UHUNZVCCCR

R7L

Legend: SP:

PC: CCR: I: U: H: N: Z: V: C:

Stack pointer Program counter Condition code register Interrupt mask bit User bit Half-carry flag Negative flag Zero flag Overflow flag Carry flag

Figure 2.1 CPU Registers

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2.2 Register Descriptions

2.2.1 General Registers

All the general registers can be used as both data registers and address registers.

When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.

When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).

Registers R4L, R5, and R6 have special functions when the EEPMOV (EEPROM write) instruction is executed.

R7 also functions as the stack pointer, used implicitly by hardware in exception handling and subroutine calls. In assembly-language coding, R7 can also be denoted by the symbol SP. As indicated in figure 2.2, SP (R7) points to the top of the stack.

Free area

SP (R7)

Stack area

Figure 2.2 Stack Pointer

2.2.2 Control Registers

The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR).

(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of PC is ignored (always regarded as 0).

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(2) Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts when set to 1. This bit is set to 1 at the beginning of exception handling.

Bit 6—User Bit (U): Can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions).

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise.

The H flag is used implicitly by the DAA and DAS instructions.

When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software for its own purposes (using the LDC, STC, ANDC, ORC, and XORC instructions).

Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to store the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave some or all of the flag bits unchanged. The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions.

Refer to the H8/300 Series Programming Manual for the action of each instruction on the flag bits.

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2.2.3 Initial Register Values

When the CPU is reset, the program counter (PC) is loaded from the vector table and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. To prevent program crashes, the stack pointer should be initialized by software, by the first instruction executed after a reset.

2.3 Data Formats

The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data.

• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand.

• All arithmetic instructions except ADDS and SUBS can operate on byte data.

• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions operate on word data.

• The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in

packed BCD form. Each nibble of the byte is treated as a decimal digit.

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2.3.1 Data Formats in General Registers

Data of all the sizes above can be stored in general registers as shown in figure 2.3.

1-bit data

Byte data

Word data

RnH

RnL

RnH

RnL

7 76543210

Don't care

MSB LSB

Don’t care

15 0

MSB LSB

7430

Don’t care

70 76543210

Don’t care

MSB LSB

4-bit BCD data

Legend: RnH: General register (high byte)

RnL: General register (low byte) MSB: Most significant bit LSB: Least significant bit

RnH

RnL

Figure 2.3 Register Data Formats

Don’t care

Don’t careLower digitUpper digit

7430

Upper digit Lower digit

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2.3.2 Memory Data Formats

Figure 2.4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, no address error occurs but the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching.

AddressData type Data format

1-bit data

Byte data

Word data

Byte data (CCR) on stack

Word data on stack

Address n

Even address Odd address

76543210

MSB LSB

MSB

MSB MSB

MSB

Upper 8 bits Lower 8 bits

CCR CCR*

LSB

LSB LSB

LSB

Legend: CCR: Condition code register

Note: * Ignored on return.

Figure 2.4 Memory Data Formats

When the stack is accessed using R7 as an address register, word access should always be performed. When CCR is pushed on the stack, two identical copies of CCR are pushed to make a complete word. When they are restored, the lower byte is ignored.

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2.4 Addressing Modes

2.4.1 Addressing Modes

The H8/300 CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes.

Table 2.1 Addressing Modes

No. Addressing Mode Symbol

(1) Register direct Rn (2) Register indirect @Rn (3) Register indirect with displacement @(d:16, Rn) (4) Register indirect with post-increment @Rn+

Register indirect with pre-decrement @–Rn (5) Absolute address @aa:8 or @aa:16 (6) Immediate #xx:8 or #xx:16 (7) Program-counter relative @(d:8, PC) (8) Memory indirect @@aa:8

(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand.

Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.

(2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand.

(3) Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address.

This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even.

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(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:

• Register indirect with post-increment— @Rn+

The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of

the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.

• Register indirect with pre-decrement— @–Rn

The @–Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by

1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.

(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory.

The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.

For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535).

(6) Immediate— #xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values.

The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number.

(7) Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address. The displacement should be an even number.

Page 25

(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address.

The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that addresses H'0000 to H'000D (0 to 13) are located in the vector table.

If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information.

2.4.2 Effective Address Calculation

Table 2.2 shows how effective addresses are calculated in each of the addressing modes.

Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).

Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8).

Bit manipulation instructions use register direct (1), register indirect (2), or absolute (5) addressing to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position.

Page 26

Table 2.2 Effective Address Calculation

No.

Addressing Mode, Instruction Format

op regm regn

op reg

reg

Effective Address Calculation Effective Address

030347815

regm

Operands are contained in registers m and n

015

16-bit register contents

0346715

015

16-bit register contents

0346715

16-bit register contents

regn

015

disp

op reg

16-bit register contents

0346715

16-bit register contents

0346715

* 1 for a byte operand,

2 for a word operand

1 or 2

015

Page 27

Table 2.2 Effective Address Calculation (cont)

No.

Addressing Mode, Instruction Format

Absolute address @aa:8

Absolute address @aa:16

abs

Immediate #xx:8

Immediate #xx:16

IMM

abs

IMM

Effective Address Calculation Effective Address

078

015

07815

Operand is 1-byte immediate data

015

Operand is 2-byte immediate data

H'FF

07815

015

PC-relative @(d:8, PC)

Memory indirect @@aa:8

op abs

disp

07815

16-bit memory contents

Legend: reg, regm, regn: General registers

op: Operation field

PC contents

H'00

015

dispSign extension

015 87

015

disp: Displacement IMM: Immediate data abs: Absolute address

Page 28

2.5 Instruction Set

The H8/3150 series can use a total of 55 instructions, shown grouped by function in table 2.3.

Note: The H8/300 CPU has 57 basic instructions, but the H8/3150 series uses only 55 of them.

The MOVFPE and MOVTPE instructions are not used.

Table 2.3 Instruction Set

Function Instructions Types

Data transfer MOV, PUSH*

, POP*

Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,

DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

ROTXR Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,

BXOR, BIXOR, BLD, BILD, BST, BIST Branch Bcc*2, JMP, BSR, JSR, RTS 5 System control SLEEP, LDC, STC, ANDC, ORC, XORC, NOP, RTE 8 EEPROM write EEPMOV 1

Total 55

Notes: 1. POP Rn is identical to MOV.W @SP+, Rn. PUSH Rn is identical to MOV.W Rn, @–SP.

2. Bcc is a conditional branch instruction in which cc represents a condition code.

Page 29

Tables 2.4 to 2.11 give a concise summary of the instructions in each functional group. The following notation is used in these tables to describe the operations performed.

Operation Notation

Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) bit of CCR Z Z (zero) bit of CCR V V (overflow) bit of CCR C C (carry) bit of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction

× Multiplication ÷ Division ∧ AND logical ∨ OR logical ⊕ Exclusive OR logical → Move

~ Not :3, :8, :16 3-, 8-, or 16-bit length

Page 30

2.5.1 Data Transfer Instructions

Table 2.4 describes the data transfer instructions.

Table 2.4 Data Transfer Instructions

Instruction Size* Function

MOV B/W (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+ addressing modes are available for byte or word data. The #xx:8 and @aa:8 addressing modes are available for byte data only. Specify word-size operands for @–R7 and @R7+.

POP W @SP+ → Rn

Pops a 16-bit general register from the stack. Identical to MOV.W @SP+, Rn.

PUSH W Rn → @–SP

Pushes a 16-bit general register onto the stack. Identical to MOV.W Rn, @–SP.

Note: * Size: Operand size

B: Byte W: Word

Page 31

Figure 2.5 shows the object code formats of the data transfer instructions.

15 8 7 0

rnrm

15 8 7 0

rnrm

15 8 7 0

rnrm

disp

15 8 7 0

rnrm

15 8 7 0

rnop

abs

15 8 7 0

abs

MOV

Rm → Rn

@Rm ← → Rn

@(d:16, Rm) ← → Rn

@Rm+ → Rn, Rn → @–Rm

@aa:8 ← → Rn

@aa:16 ← → Rn

15 8 7 0

rnop

IMM

15 8 7 0

IMM

15 8 7 0

Legend: op: Operation field

rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data

Figure 2.5 Data Transfer Instruction Object Code Formats

#xx8 → Rn

#xx16 → Rn

POP, PUSH

Page 32

2.5.2 Arithmetic Operations

Table 2.5 describes the arithmetic instructions.

Table 2.5 Arithmetic Instructions

Instruction Size* Function

ADD SUB

ADDX SUBX

INC DEC

ADDS SUBS

DAA DAS

B/W Rd ± Rs → Rd, Rd + #IMM → Rd

Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers.

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register.

B Rd ± 1 → Rd

Increments or decrements a general register.

W Rd ± 1 → Rd, Rd ± 2 → Rd

Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2.

B Rd decimal adjust → Rd

Decimal-adjusts 4-bit BCD data in a general register by referring to CCR.

MULXU B Rd × Rs → Rd

Performs 8-bit × 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result.

DIVXU B Rd ÷ Rs → Rd

Performs 16-bit ÷ 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder.

CMP B/W Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register or with immediate data, and sets CCR according to the result. Word data can be compared only between two general registers.

NEG B 0 – Rd → Rd

Obtains the two's complement (arithmetic complement) of data in a general register.

Note: * Size: Operand size

B: Byte W: Word

Page 33

2.5.3 Logic Operations

Table 2.6 describes the instructions that perform logic operations.

Table 2.6 Logic Operation Instructions

Instruction Size* Function

AND B Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another general register or immediate data.

OR B Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another general register or immediate data.

XOR B Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and another general register or immediate data.

NOT B ~ Rd → Rd

Obtains the one's complement (logical complement) of general register contents.

Note: * Size: Operand size

B: Byte

2.5.4 Shift Operations

Table 2.7 describes the shift instructions.

Table 2.7 Shift Instructions

Instruction Size* Function

SHAL SHAR

SHLL SHLR

B Rd shift → Rd

Performs an arithmetic shift operation on general register contents.

B Rd shift → Rd

Performs a logical shift operation on general register contents.

ROTL ROTR

ROTXL ROTXR Note: * Size: Operand size

B Rd rotate → Rd

B Rd rotate through carry → Rd

B: Byte

Rotates general register contents.

Rotates general register contents through the C (carry) bit.

Page 34

Figure 2.6 shows the object code formats of the arithmetic, logic, and shift instructions.

15 8 7 0

rnrm

15 8 7 0

ADD, SUB, CMP, ADDX, SUBX (Rm)

ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT

rnrm

15 8 7 0

rnop

IMM

15 8 7 0

rnrm

15 8 7 0

IMM

15 8 7 0

Legend: op: Operation field

rm, rn: Register field IMM: Immediate data

MULXU, DIVXU

ADD, ADDX, SUBX, CMP (#xx:8)

AND, OR, XOR (Rm)

AND, OR, XOR (#xx:8)

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR

Figure 2.6 Arithmetic, Logic, and Shift Instruction Object Code Formats

Page 35

2.5.5 Bit Manipulations

Table 2.8 describes the bit-manipulation instructions.

Table 2.8 Bit-Manipulation Instructions

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BTST B ~ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the C flag with a specified bit in a general register or memory and stores the result in the C flag.

BIAND B C ∧ [~ (<bit-No.> of <EAd>)] → C

ANDs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the C flag. The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the C flag with a specified bit in a general register or memory and stores the result in the C flag.

BIOR B C ∨ [~ (<bit-No.> of <EAd>)] → C

ORs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the C flag. The bit number is specified by 3-bit immediate data.

Note: * Size: Operand size

B: Byte

Page 36

Table 2.8 Bit-Manipulation Instructions (cont)

Instruction Size* Function

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the C flag with a specified bit in a general register or memory and stores the result in the C flag.

BIXOR B C ⊕ [~ (<bit-No.> of <EAd>)] → C

Exclusive-ORs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the C flag. The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory to the C flag.

BILD B ~ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory to the C flag. The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the C flag value to a specified bit in a general register or memory.

BIST B ~ C → (<bit-No.> of <EAd>)

Transfers the inverse of the C flag value to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data.

Note: * Size: Operand size

B: Byte

Note on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modifywrite instructions. They read a byte of data, modify one bit in the byte, then write the modified byte back to the same address.

Step Operation

1 Read Read data (1 byte) at a specified address 2 Modify Modify one specified bit in the read data 3 Write Write the modified data back to the specified address

Page 37

Figure 2.7 shows the object code formats of the bit manipulation instructions.

15 8 7 0

op op

15 8 7 0

IMM

rn IMMop

abs

IMM

rnrm

0 0000

0000 0000

0000

BSET, BCLR, BNOT, BTST

Operand: register direct (Rn) Bit No.: immediate (#xx:3)

Operand: register direct (Rn) Bit No.: register direct (Rm)

Operand: register indirect (@Rn)

000

Bit No.: immediate (#xx:3)

Operand: register indirect (@Rn) Bit No.: register direct (Rm)

Operand: absolute (@aa:8) Bit No.: immediate (#xx:3)

15 8 7 0

op op

15 8 7 0

Legend: op: Operation field

rm, rn: Register field abs: Absolute address IMM: Immediate data

IMM

IMM 0000

abs

0000

0000 0000

abs

Operand: absolute(@aa:8) Bit No.: register direct (Rm)

BAND, BOR, BXOR, BLD, BST

Operand: register direct (Rn) Bit No.: immediate (#xx:3)

Operand: register indirect (@Rn) Bit No.: immediate (#xx:3)

Operand: absolute(@aa:8) Bit No.: immediate (#xx:3)

Figure 2.7 Bit Manipulation Instruction Object Code Formats

Page 38

15 8 7 0

IMM

BIAND, BIOR, BIXOR, BILD, BIST

Operand: register direct (Rn) Bit No.: immediate (#xx:3)

15 8 7 0

Legend: op: Operation field

rm, rn: Register field abs: Absolute address IMM: Immediate data

IMM

abs

IMM 0000

0000 0000

Figure 2.7 Bit Manipulation Instruction Object Code Formats (cont)

Operand: register indirect (@Rn) Bit No.: immediate (#xx:3)

Operand: absolute(@aa:8) Bit No.: immediate (#xx:3)

Page 39

2.5.6 Branching Instructions

Table 2.9 describes the branching instructions.

Table 2.9 Branching Instructions

Instruction Size Function

Bcc — Branches to a specified address if condition cc is true.

The branching conditions are listed below.

Mnemonic Description Condition

BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 BCC (BHS) Carry clear

(high or same) BCS (BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP — Branches unconditionally to a specified address.

C = 0

BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine.

Page 40

Figure 2.8 shows the object code formats of the branching instructions.

15 8 7 0

op dispcc

15 8 7 0

0000JMP (@Rm)

15 8 7 0

abs

15 8 7 0

op abs

15 8 7 0

op disp

15 8 7 0

op 0000rm

Bcc

JMP (@aa:16)

JMP (@@aa:8)

BSR

JSR (@Rm)

15 8 7 0

abs

15 8 7 0

op abs

15 8 7 0

Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address

Figure 2.8 Branching Instruction Object Code Formats

JSR (@aa:16)

JSR (@@aa:8)

RTS

Page 41

2.5.7 System Control Instructions

Table 2.10 describes the system control instructions.

Table 2.10 System Control Instructions

Instruction Size* Function

RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to the power-down state. LDC B Rs → CCR, #IMM → CCR

Moves immediate data or general register contents to the condition code register.

STC B CCR → Rd

Copies the condition code register to a specified general register.

ANDC B CCR ∧ #IMM → CCR

Logically ANDs the condition code register with immediate data.

ORC B CCR ∨ #IMM → CCR

Logically ORs the condition code register with immediate data.

XORC B CCR ⊕ #IMM → CCR

Logically exclusive-ORs the condition code register with immediate data.

NOP — PC + 2 → PC

Only increments the program counter.

Note: * Size: Operand size

B: Byte

Page 42

Figure 2.9 shows the object code formats of the system control instructions.

15 8 7 0

op rn

15 8 7 0

Legend: op: Operation field rn: Register field IMM: Immediate data

IMM

Figure 2.9 System Control Instruction Object Code Formats

2.5.8 EEPROM Write Instruction

RTE, SLEEP, NOP

LDC, STC (Rn)

ANDC, ORC, XORC, LDC (#xx:8)

Table 2.11 describes the EEPROM write instruction.

Table 2.11 EEPROM Write Instruction

Instruction Size Function

EEPMOV — If R4L ≠ 0 then

repeat @R5+ → @R6+, R4L – 1 → R4L until R4L = 0 else next; Transfers a data block to EEPROM according to parameters set in

general registers R4L, R5, and R6. R4L: size of block (bytes)

R5: starting source address R6: starting destination address

Execution of the next instruction begins as soon as the EEPROM write operation is completed. The transfer cannot cross an EEPROM page boundary.

Page 43

Figure 2.10 shows the object code format of the EEPROM write instruction.

15 8 7 0

op op

Legend: op: Operation field

EEPMOV

Figure 2.10 EEPROM Write Instruction Object Code Format

2.6 Operating States

2.6.1 Overview

The CPU operates in three states: the program execution state, exception-handling state, and power-down state. Figure 2.11 summarizes these states. Figure 2.12 shows the state transitions.

Chip state Program execution state

CPU executes program

Exception-handling state

Transitory state that changes CPU execution flow at a reset or interrupt

Power-down state

CPU halts to conserve power

Figure 2.11 Operating States

Sleep mode

Page 44

Program execution state

End of exception handling

Exception-handling state

RES = 0

I/O-1/IRQ = 0 or I/O-2/IRQ

RES = 0RES = 1

Reset state

Figure 2.12 State Transitions

2.6.2 Program Execution State

In this state the CPU executes program instructions in normal sequence.

2.6.3 Exception-Handling State

SLEEP instruction

Sleep mode

Power-down state

This is a transitory state entered in response to a reset or interrupt. In interrupt exception handling, the stack pointer is referenced and the program counter and condition code register are saved.

2.6.4 Power-Down State

The power-down state consists of a sleep mode.

Sleep mode is entered from the program execution state when the SLEEP instruction is executed. Operation of the CPU, clocks, and all other on-chip peripheral modules is halted. The on-chip peripheral modules enter the reset state, but the contents of CPU registers and on-chip RAM are retained as long as the specified voltage is supplied. The I/O port DR and DDR values are also retained.

Sleep mode is cleared by a low input to the RES, I/O-1/IRQ, or I/O-2/IRQ pin.

Page 45

2.7 Exception Handling

2.7.1 Overview

In the H8/3150 series, exception handling is performed in response to a reset or interrupt. Table

2.12 summarizes the exception handling priority order and timing. Table 2.13 describes the exception vector table.

Table 2.12 Exception Handling Priority Order and Timing

Priority Cause Detection Timing

High Reset Synchronized with

clock

UDF Interrupt signal level

is detected

EWE Interrupt signal level

is detected

Low External

interrupt (IRQ)

Falling edge is detected

Table 2.13 Exception Vector Table

Start of Exception Handling Sequence

Instruction execution stops and reset processing starts immediately.

Interrupt exception handling starts when the current instruction execution is completed.

Interrupt exception handling starts when the execution of the instruction following the EWE write instruction is executed.

Interrupt exception handling starts immediately when an falling edge is detected on the I/O-1/IRQ or I/O-2/IRQ pin in sleep mode.

Vector Address

Mask by I Bit

Cannot be masked

Can be masked

Description Vector Number PC (High) PC (Low)

Reset 0 H'0000 H'0001 Reserved for system use* 1 H'0002 H'0003 Reserved for system use* 2 H'0004 H'0005 External interrupt (IRQ) 3 H'0006 H'0007 Reserved for system use* 4 H'0008 H'0009 EWE interrupt 5 H'000A H'000B UDF interrupt 6 H'000C H'000D

Note: * Software must not access these addresses.

Page 46

2.7.2 Reset

The H8/3150 series begins reset exception handling when the RES input changes from low to high.

RES must also be low whenever power is switched on or off. At power-up, RES must be held low for at least 20 external clock cycles after the input clock signal (CLK) stabilizes. Similarly, when the chip is reset during operation, RES must be held low for at least 20 external clock cycles.

When a low-to-high transition of RES is detected, the CPU begins reset exception handling in the following steps:

1. The low-to-high transition of the RES input is detected.

2. The internal status of the CPU and the registers of the on-chip peripheral modules are initialized. In CCR, the I bit is set to 1 but other bits are left unchanged.

3. The reset vector is read from addresses H'0000 to H'0001 in the vector table and loaded into the program counter. Program execution then starts from the loaded address (start address).

2.7.3 Interrupts

The H8/3150 series has two types of interrupt sources: external interrupts (IRQ interrupts) and internal interrupts (UDF and EWE interrupts of WDT).

In sleep mode only, the I/O-1/IRQ and I/O-2/IRQ pins function as interrupt pins, and are capable of input. The IRQ interrupt uses falling edge detection, and an interrupt request is accepted if the I bit in CCR is cleared to 0.

See section 9, I/O Ports, for I/O-1/IRQ and I/O-2/IRQ specification details, and section 5, Watchdog Timer, for UDF and EWE interrupt details.

The interrupt sequence consists of the following steps.

1. When the interrupt request is accepted, a transition takes place from sleep mode to the exception-handling state. The program counter and condition code register are saved on the stack as shown in figure 2.13. The program counter address saved on the stack is the address of the first instruction that will be executed after the return from the interrupt-handling routine.

2. The I bit in the condition code register is set to 1.

3. The address of the interrupt-handling routine is read from the vector table entry corresponding to the interrupt vector and loaded into the program counter, and execution of the interrupthandling routine begins.

The maximum number of clocks from interrupt request acceptance to the start of the interrupthandling routine is 35 external clocks.

Page 47

SP–4

SP (R7)

CCR SP–3 SP–2

SP–1 SP (R7)

SP+1 SP+2

SP+3 SP+4

Stack area

CCR*

Even address

Before After

Save on stack

Legend: PC

: Upper 8 bits of program counter (PC)

: Lower 8 bits of program counter (PC)

CCR: Condition code register SP: Stack pointer

Notes: 1. The program counter indicates the address of the first instruction that will be

executed after the return.

2. Registers must be saved and restored by word access starting at an even address. * Ignored on return.

Figure 2.13 Stack before and after Interrupt Exception-Handling Sequence

2.7.4 Reset Start Timing

The reset start timing of the H8/3150 series, that is, the number of clock cycles between the rising edge of RES and the reset vector fetch cycle, is a maximum of 200 external clock cycles.

Page 48

2.8 Power-Down State

2.8.1 Overview

The H8/3150 series has a sleep mode, a power-down state in which CPU functions are halted to conserve power.

Table 2.14 summarizes the conditions for transition to sleep mode, the state of the CPU and onchip peripheral modules in sleep mode, and the conditions for exit from sleep mode.

Table 2.14 Power-Down State

States

Transition

Mode

Sleep mode

Mode

Sleep mode

Note: * For details on t

Condition CLK

Execute SLEEP instruction

States WDT Clock

and WDT WDT Reg's RAM

Stop Retained Retained Retained Interrupt

0 MHz to t

, see figures 12.1 and 12.5 in section 12, Electrical Characteristics.

cyc

2.8.2 Transition to Sleep Mode

CPU Clock and CPU CPU Reg's

* Stop Retained Stop Retained

cyc

DR and DDR I/O Ports

input

RNG Clock and RNG RNG Reg's

ECR and EPR

Initial values

Exiting Methods

Reset or external interrupt

Sleep mode is entered by executing the SLEEP instruction.

In sleep mode the CPU, clock, and on-chip functions halt, reducing power dissipation. As long as the necessary voltage is supplied, however, the contents of CPU registers, RNG registers, WDT registers, RAM, and I/O port registers (DR and DDR) are retained. The ECR and EPR in the EEPROM are initialized. I/O-1/IRQ and I/O-2/IRQ become interrupt input pins. The I/O-1/IRQ, I/O-2/IRQ, and RES signals must be kept high during sleep mode. If either one of I/O-1/IRQ and I/O-2/IRQ is not used, the unused pin must be left as an input pin and left open (unconnected).

When the I/O-1/IRQ and I/O-2/IRQ are used as output pins, change them into input pins by writing 0 to the DDR7 and DDR6 bits before executing the SLEEP instruction.

Figure 2.14 shows the sequence for transition to sleep mode.

Page 49

DDR7 ← 0 DDR6 ← 0

CCR(I) ← 0

Execute SLEEP instruction

Sleep mode

Program execution state (EN = 0)

Figure 2.14 Transition to Sleep Mode

Note: When sleep mode is entered, set DDR to 0 to use the pins as I/O input ports before

executing a SLEEP instruction. When writing to the DDR7 and DDR6 bits, use the MOV instruction instead of the bit manipulation instruction.

2.8.3 Exit from Sleep Mode

Sleep mode is cleared by an input to the I/O-1/IRQ, I/O-2/IRQ, or RES pin.

1. Exit by interrupt In sleep mode, the I/O-1/IRQ and I/O-2/IRQ pins can receive interrupt signals. When a high-

to-low transition occurs in the input, the external clock is supplied to the CPU and on-chip modules, sleep mode is cleared, and interrupt exception handling starts. The external clock must be stable when the interrupt signal goes low. Figure 2.15 shows the transition sequence from sleep mode to interrupt handling. Figure 2.16 shows the timing of an interrupt in sleep mode.

2. Exit by reset If the RES input goes low during sleep mode, the external clock is supplied to the CPU and on-

chip peripheral modules. After that, when the RES input goes high, the CPU begins reset exception handling. The RES input must be held low for at least 20 stable external clock cycles.

Page 50

Sleep mode

I/O-1/IRQ = low

I/O-2/IRQ = low

Execution of interrupt-

handling routine

RTE instruction

Figure 2.15 Recovery from Sleep Mode

Note: The RES, I/O-1/IRQ, and I/O-2/IRQ signals must be held high during sleep mode.

CLK

CCR I bit

I/O-1/IRQ or I/O-2/IRQ

State

CCR I bit cleared to 0

Operating state

SLEEP instruction

CLK = 0 MHz to t

Power-down state

Sleep mode

cyc

IRQ

Operating state

Interrupt exception handling

Figure 2.16 Interrupt Timing in Sleep Mode

Page 51

Section 3 Memory Maps

Figures 3.1 to 3.5 show memory maps of the H8/3150 series.

Address

H'0000

Exception vectors

ROM

(24 kbytes)

Reset

IRQ

EWE interrupt

UDF interrupt

Address

H'0000/H'0001 H'0002/H'0003 H'0004/H'0005 H'0006/H'0007 H'0008/H'0009 H'000A/H'000B H'000C/H'000D

Access

Word Byte

(Read

only)

(Read

only)

H'5FFF H'6000

H'7FFF H'80FF

H'FDC0

H'FFBF

H'FFF0 H'FFF2

H'FFF3 H'FFF4

H'FFF5

EEPROM data area

(8 kbytes)

(256 bytes)

RAM

(512 bytes)

RCSR

RNRR

SYSCR

TCWA

Switched by EPR (PBM bit)

EEPROM

protection area

PBM = 1 PBM = 0

Registers for RNG

(Read

only)

xx x

H'FFF8 H'FFF9 H'FFFA H'FFFB H'FFFC H'FFFD

H'FFFE H'FFFF

Note:

ECR

EPR

TCSR TCNT

DDR

Shaded areas are unavailable to the user. User programs must not access these areas.

Registers for EEPROM

Registers for WDT Registers for I/O port

Figure 3.1 H8/3152 Memory Map

: Access possible : Access not possible

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Address

H'0000

Exception vectors

ROM

(32 kbytes)

Reset

IRQ

EWE interrupt

UDF interrupt

Address

H'0000/H'0001 H'0002/H'0003 H'0004/H'0005 H'0006/H'0007 H'0008/H'0009 H'000A/H'000B H'000C/H'000D

Access

Word Byte

(Read

only)

(Read

only)

H'7FFF H'8000

H'BFFF H'C1FF

H'FBC0

H'FFBF

H'FFF0 H'FFF2

H'FFF3 H'FFF4

H'FFF5

EEPROM

data area

(16 kbytes)

(512 bytes)

RAM

(1024 bytes)

RCSR

RNRR

SYSCR

TCWA

Switched by EPR (PBM bit)

EEPROM

protection area

PBM = 1 PBM = 0

Registers for RNG

(Read

only)

xx x

H'FFF8 H'FFF9 H'FFFA H'FFFB H'FFFC H'FFFD

H'FFFE H'FFFF

Note:

ECR EPR

TCSR TCNT

DDR

Shaded areas are unavailable to the user. User programs must not access these areas.

Registers for EEPROM

Registers for WDT Registers for I/O port

: Access possible : Access not possible

Figure 3.2 H8/3153 Memory Map

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Address

H'0000

H'3FFF

Exception vectors

ROM

(16 kbytes)

Reset

IRQ

EWE interrupt

UDF interrupt

Address

H'0000/H'0001 H'0002/H'0003 H'0004/H'0005 H'0006/H'0007

H'0008/H'0009 H'000A/H'000B H'000C/H'000D

Access

Word Byte

(Read

only)

(Read

only)

H'6000

H'63FF H'647F

H'FDC0

H'FFBF

H'FFF0

H'FFF2

H'FFF3 H'FFF4

H'FFF5

EEPROM data area

(1 kbyte)

(128 bytes)

RAM

(512 bytes)

RCSR

RNRR

SYSCR

TCWA

Switched by EPR (PBM bit)

PBM = 1 PBM = 0

Registers for RNG

EEPROM

protection area

(Read

only)

H'FFF8 H'FFF9

H'FFFC H'FFFD

H'FFFE H'FFFF

Note: Shaded areas are unavailable to the user. User programs must not access these areas.

ECR

EPR

TCSR TCNT

DDR

Registers for EEPROM

Registers for WDT

Registers for I/O port

Figure 3.3 H8/3155 Memory Map

: Access possible : Access not possible

Page 54

Address

H'0000

H'3FFF

Exception vectors

ROM

(16 kbytes)

Reset

IRQ

EWE interrupt

UDF interrupt

Address

H'0000/H'0001 H'0002/H'0003 H'0004/H'0005 H'0006/H'0007

H'0008/H'0009 H'000A/H'000B H'000C/H'000D

Access

Word Byte

(Read

only)

(Read

only)

H'6000

H'67FF H'687F

H'FDC0

H'FFBF

H'FFF0

H'FFF2

H'FFF3 H'FFF4

H'FFF5

EEPROM

data area

(2 kbytes)

(128 bytes)

RAM

(512 bytes)

RCSR

RNRR

SYSCR

TCWA

Switched by EPR (PBM bit)

PBM = 1 PBM = 0

Registers for RNG

EEPROM

protection area

(Read

only)

H'FFF8 H'FFF9

H'FFFC H'FFFD

H'FFFE H'FFFF

Note: Shaded areas are unavailable to the user. User programs must not access these areas.

ECR

EPR

TCSR

TCNT

DDR

Registers for EEPROM

Registers for WDT Registers for I/O port

Figure 3.4 H8/3156 Memory Map

: Access possible : Access not possible

Page 55

Address

H'0000

Exception vectors

ROM

(46 kbytes)

Reset

IRQ

EWE interrupt

UDF interrupt

Address

H'0000/H'0001 H'0002/H'0003 H'0004/H'0005 H'0006/H'0007 H'0008/H'0009 H'000A/H'000B H'000C/H'000D

Access

Word Byte

(Read

only)

(Read

only)

H'B7FF H'B800

H'F7FF H'F9FF

H'FBC0

H'FFBF

H'FFF0 H'FFF2

H'FFF3 H'FFF4

H'FFF5

EEPROM data area

(16 kbytes)

(512 bytes)

RAM

(1024 bytes)

RCSR RNRR

SYSCR

TCWA

Switched by EPR (PBM bit)

EEPROM

protection area

PBM = 1 PBM = 0

Registers for RNG

(Read

only)

xx x

H'FFF8 H'FFF9 H'FFFA H'FFFB H'FFFC H'FFFD

H'FFFE H'FFFF

Note:

ECR

EPR

TCSR TCNT

DDR

Shaded areas are unavailable to the user. User programs must not access these areas.

Registers for EEPROM

Registers for WDT Registers for I/O port

: Access possible : Access not possible

Figure 3.5 H8/3158 Memory Map

Page 56

Section 4 Random Number Generator (RNG)

4.1 Overview

The H8/3150 series has a random number generator (RNG) which generates 16-bit random numbers. A random number generated by the RNG is written to a 16-bit register. Using the RNG enables a unique value to be generated inside the chip, which improves the system security.

4.1.1 Features

• 16-bit random number generation

• High-speed random number generation

Generates a 16-bit random number in 3.2 ms (typical value). Generation time does not depend on external clocks.

• Continuous random number generation Generates a new random number automatically when the register that holds a random number

is read.

4.1.2 Register Configuration

Table 4.1 shows the RNG registers.

Table 4.1 RNG Registers

Name Abbreviation R/W Initial Value Address

RNG control status register RCSR R/W* H'3F H'FFF0 RNG result register RNRR R Undefined H'FFF2 — H'FFF3

Note: Data can be written only to bit 6 to set or clear the flag.

Page 57

4.2 Register Descriptions

4.2.1 RNG Control Status Register (RCSR)

RCSR is an 8-bit register whose bit 6 is readable and writable while the other bits are read-only. RCSR has a GE bit and an RRDY bit; the GE bit controls the RNG operation and the RRDY bit indicates whether a random number has been written to RNRR. The initial RCSR value is H'3F.

Bit: 7 6 5 4 3 2 1 0

RRDY GE — — — — — —

Initial value: 0 0 1 1 1 1 1 1

Read/Write: R R/W R R R R R R

Bit 7—Random Number Ready (RRDY): Indicates whether a random number generated by the RNG has been written to RNRR. This bit is read-only and cannot be written to.

Writing 0 to the GE bit clears the RRDY bit to 0, and the RRDY bit holds the value.

Writing 1 to the GE bit starts random number generation in the RNG, and when the generated random number is written to RNRR, the RRDY bit is set to 1.

Reading RNRR while the RNG is active (GE = 1) starts generating and writing a new random number to RNRR; therefore, the RRDY bit is cleared to 0.

Bit 7: RRDY Description

0 [Clearing condition]

• When 0 is written to the GE bit

• When RNRR is read while the GE bit is 1 (Initial value)

1 [Setting condition]

When a generated random number is written to RNRR

Bit 6—Generation Enabled (GE): Enables or disables the RNG operation.

Writing 1 to the GE bit starts the RNG operation, and the generated 16-bit random number is written to RNRR.

Writing 0 to the GE bit stops the RNG operation. The data read from RNRR after the GE bit is cleared to 0 must not be used as a random number.

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Bit 6: GE Description

0 Stops the RNG operation (Initial value) 1 Starts the RNG operation

Bits 5 to 0—Reserved: Always read as 1 and cannot be written to.

Although not used at present, the reserved bits may be used in the future. When writing to RCSR, write 0 to these bits.

4.2.2 RNG Result Register (RNRR)

RNRR is a 16-bit read-only register and cannot be written to. RNRR must always be read in word size. The initial value is undefined.

The random number generated in the RNG is written to RNRR. Reading RNRR while the RNG is active (GE = 1) clears the RRDY to 0, then automatically generates and writes a new random number to RNRR.

Bit: 15 14 13 12 11 10 9 8 76543210

Initial value: — — — —————————————

Read/Write: R R R RRRRRRRRRRRRR

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4.3 Operation

A 16-bit uniform random number can be generated by the following steps:

• Write 1 to the GE bit.

• Read RNRR while the GE bit is 1.

Figure 4.1 shows the procedure for writing the required length of a random number to the RAM.

Start

Write 1 to GE

RRDY = 1 ?

YES

Read RNRR in word size

and write the data to RAM

RRDY = 0

Required length of data ?

YES

Write 0 to GE

Figure 4.1 Random Data Writing Procedure Using RNG

To generate a random number, first write 1 to the GE bit to start the RNG. When a random number is generated, the 16-bit random number is written to RNRR and the RRDY bit is set to 1. Reading the random number from RNRR in this state clears the RRDY bit to 0, and a new 16-bit random number is generated and written to RNRR. Repeat these steps until the required length of random number is obtained. In this procedure, check whether RNRR holds a valid data by referring to the RRDY bit status each time before reading RNRR.

End

Page 60

The following shows a coding example of 80-bit random-number generation.

--- Coding example of random-number generation (80-bit random number) --RNGstart:

MOV.W #RNSA,R0 ;Random number store address (bottom) MOV.B #5,R1L ;R1L = 80 (bit length) / 16 MOV.B #H'40,R2L MOV.B R2L,@RCSR ;GE <- 1

RRDYwait: BTST #7,@RCSR

BEQ RRDYwait MOV.W @RNRR,R3 ;Word size read MOV.W R3,@R0 SUBS #2,R0 DEC R1L BNE RRDYwait MOV.B #H'00,R2L MOV.B R2L,@RCSR ;GE <- 0

--- End of the program ---

The performance of random number generation for this program is shown in table 4.2.

Table 4.2 Random-Number Generation Performance (reference values)

Data Length

Performance 16 Bits 80 Bits 128 Bits 160 Bits 192 Bits 256 Bits 288 Bits 384 Bits 512 Bits

Execution time

3.2 ms 16 ms 26 ms 32 ms 39 ms 53 ms 58 ms 77 ms 103 ms

4.4 Notes on Usage

1. Check that the RRDY bit is 1 before reading the data from RNRR. If read while the RRDY bit is 0, the RNRR data must not be used as a random number.

RNRR must always be read in word size. If read in byte size, the RNRR data must not be used as a random number.

2. If read after the GE bit is cleared to 0, the RNRR data must not be used as a random number.

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Section 5 Watchdog Timer (WDT)

5.1 Overview

Specify whether to operate or stop the WDT for each ROM code. When stopped, the WDT does not issue interrupts.

The H8/3150 series has a single-channel watchdog timer (WDT) for monitoring system operations; that is, monitoring whether the application program is properly executed and whether the EEPROM is correctly written to.

The WDT issues a UDF interrupt at a required interval. The UDF interrupt routine can monitor the PC in the stack area to check whether the application program was executed in the defined area. The WDT also issues an EWE interrupt before an EEPMOV instruction is executed. The EWE interrupt routine can monitor the instructions in the area pointed to by the PC that is saved in the stack area, to check whether an EEPMOV instruction will be executed in the correct procedure and with the correct data. UDF and EWE interrupts are not masked by the I bit setting in the CCR. Setting the halt flag after the above checking is completed stops all the on-chip functions. To exit from this state and enter the reset state, input a low-level signal to the RES pin.

5.1.1 Features

• Reloads the counter value when the write instruction at the defined area is executed.

• Issues a UDF interrupt at a required interval.

• Issues an EWE interrupt before an EEPMOV instruction is executed.

• Stops the on-chip functions (enters reset state) when the halt flag is set.

• One of four counter clock sources can be selected.

Note: When the WDT stops, do not access WDT control registers.

Page 62

5.1.2 Block Diagram

Figure 5.1 shows a block diagram of the WDT.

CLK/32

control

UDF interruptInterrupt EWE interrupt

CLK/64 CLK/128 CLK/256

TCNT: Timer counter TCSR: Timer control/status register TCWA: Timer control write address

Selector

TCSR TCNT TCWA

Reset control

Internal data bus (upper eight bits)

Internal reset

ECR controller

Figure 5.1 WDT Block Diagram

5.1.3 Register Configuration

Table 5.1 lists the WDT registers.

Table 5.1 WDT Registers

Name Abbr. R/W Initial Value Address

Timer counter write address TCWA R/W H'FF H'FFF5 Timer control/status register TCSR R/W * H'2C H'FFFC Timer counter TCNT R/W H'FF H'FFFD

Note: Only 1 can be written to bit 6 to set the flag.

Page 63

5.1.4 Vector Configuration

Figure 5.2 shows the memory map of the WDT vector area.

Address

EWE interrupt vector UDF interrupt vector

H'000A/H'000B H'000C/H'000D

Figure 5.2 WDT Vectors

5.2 Register Descriptions

5.2.1 Timer Counter (TCNT)

Bit: 7 6 5 4 3 2 1 0

Initial value: 1 1 1 1 1 1 1 1

Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W

TCNT is an 8-bit readable and writable down-counter. Before TCSR is written to after reset, TCNT decrements the value by counting internal clocks for the CPU regardless of the CS1 and CS0 bit settings in TCSR. Therefore, if the WDT is not initialized within 512 external clock cycles from the rising edge of the RES signal when the CPUCS0 bit of SYSCR is 0 or within 256 external clock cycles from the rising edge of the RES signal when the CPUCS0 bit of SYSCR is 1, a TCNT underflow (H'00 → H'FF) occurs. When TCSR is written to after reset, TCNT starts decrementing the value by counting pulses of the internal clock selected by the CS1 and CS0 bits in TCSR. The number of clock cycles before TCNT underflows depends on the CS1 and CS0 bit settings. When a TCNT underflow occurs, the UDF bit in TCSR is set to 1, then a UDF interrupt is issued; TCNT starts decrementing from the initially written value.

TCNT is initialized to H'FF at reset or when the CS1 and CS0 bits in TCSR are written to. TCNT can be written to only once after TCSR is written to after reset. TCNT decrementation starts from the written value.

When the WAD bit in TCWA is 1, if once written, TCNT cannot be written to again until the chip is reset by a low-level input to the RES pin.

When the WAD bit is 0, the initially written data can be reloaded to TCNT at any time even if it has already been once written. To reload the initially written data, place an instruction for writing

Page 64

to TCNT in the 4-kbyte area defined by TCWA. Any value can be specified as an operand (write data) of the reloading instruction; the initially written data is always reloaded to TCNT.

In sleep mode, or during EEPMOV instruction execution, TCNT suspends counting without being initialized.

5.2.2 Timer Control/Status Register (TCSR)

TCSR is an 8-bit readable and writable register that controls the WDT, for example, when selecting the clock input to TCNT.

TCSR is initialized to H'2C at reset, but not reset in sleep mode. The CS1 and CS0 bits can be written to only once after reset. Once written to, they cannot be written to again until the chip is reset by a low-level input to the RES pin.

Bit: 7 6 5 4 3 2 1 0

UDF EWE — HLT — — CS1 CS0

Initial value: 0 0 1 0 1 1 0 0

Read/Write: R R/W* R R/W R R R/W R/W

Note: Only 1 can be written to bit 6 to set the flag.

Bit 7—Underflow Flag (UDF): Indicates that a UDF interrupt was issued due to TCNT underflow (H'00 → H'FF).

Bit 7: UDF Description

0 [Clearing condition]

When RTE instruction is executed while UDF = 1 (Initial value)

1 [Setting condition]

When TCNT underflow occurs (H'00 → H'FF)

Bit 6—ECR Write Enable (EWE): Enables writing to ECR before writing to EEPROM. An EWE interrupt is issued when 1 is written to this bit. When the EWE bit is 0, writing to ECR is ignored. Regardless of the EWE bit setting, ECR can always be read.

Bit 6: EWE Description

0 [Clearing condition]

When EEPMOV instruction execution ends (Initial value)

1 [Setting condition]

When 1 is written to this bit while it is 0

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Bit 5—Reserved: Always read as 1 and cannot be written to. Although not used at present, the reserved bit may be used in the future. When writing to TCSR, write 0 into bit 5.

Bit 4—Halt Flag (HLT): Controls operation of all the on-chip functions. When the HLT bit is set to 1, all the on-chip functions stop. The HLT bit is set to 1 when a TCNT underflow occurs while UDF = 1, or 1 is written to the EWE bit while UDF = 1, or 1 is written to the EWE bit while EWE = 1.

Bit 4: HLT Description

0 Normal operation (Initial value) 1 All the on-chip functions stop operating. Operation returns from halt state when

a low-level signal is input to the RES pin.

Bits 3 and 2—Reserved: Always read as 1 and cannot be written to. Although not used at present, the reserved bits may be used in the future. When writing to TCSR, write 0 into bits 3 and

Bits 1 and 0—Clock Select 1 and 0 (CS1 and CS0): Select one from four clock sources obtained by dividing the CLK pin input, as the input to TCNT.

Bit 1: CS1 Bit 0: CS0 Description

0 0 CLK/32 (Initial value)

1 CLK/64

1 0 CLK/128

1 CLK/256

5.2.3 Timer Counter Write Address (TCWA)

TCWA has four address bits and one control bit, which are readable and writable. Bits 3 to 1 cannot be written to.

TCWA is initialized to H'FF at reset, but not reset in sleep mode. TCWA can be written to only once when 0 is written to the WAD bit at the same time, and before TCSR is written to. Once written to, TCWA cannot be written to again until the chip is reset by a low-level input to the RES pin.

Bit: 7 6 5 4 3 2 1 0

IA15 IA14 IA13 IA12 — — — WAD

Initial value: 1 1 1 1 1 1 1 1

Read/Write: R/W R/W R/W R/W R R R R/W

Page 66

Bits 7 to 4—Instruction Address (IA15 to IA12): These bits specify the high-order four bits (bits 15 to 12) of the address pointing to the area storing the write instruction for reloading the TCNT value. When specifying the IA15 to IA12 bits, set the WAD bit to 0 at the same time. For example, when H'X is specified in the IA15 to IA12 bits, the write instruction for reloading TCNT must be placed in the 4-kbyte area ranging from address H'X000 to address H'XFF7 in the ROM area; a write instruction placed outside the area cannot reload TCNT. Any value can be specified as an operand (write data) of the write instruction for reloading TCNT; the initially written value is always reloaded to TCNT.

Bits 3 to 1—Reserved: Always read as 1 and cannot be written to.

Bit 0—Write Address Disable (WAD): Enables or disables TCWA. When WAD = 1, TCWA

does not operate. When writing data to IA15 to IA12 in TCWA, set the WAD bit to 0 at the same time; the TCWA data becomes valid only after TCWA is written to. If 1 is written to the WAD bit at the same time as a write address is written to IA15 to IA12, the write address becomes invalid. The TCWA data can always be read regardless of the WAD bit setting.

Bit 0: WAD Description

0 TCWA operates. The TCWA data is valid. 1 TCWA does not operate. The TCWA data is invalid. (Initial value)

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5.3 Operation

5.3.1 Checking Application Program Execution Area

As shown in figure 5.3, when the counter underflows, the WDT sets the UDF bit to 1 and issues a UDF interrupt. Since the TCNT initial value cannot be changed, a UDF interrupt is issued at regular intervals until reset. UDF interrupt vector addresses are H'000C to H'000D. The UDF interrupt routine can monitor the PC in the stack area to check whether application program was executed in the defined area. Figure 5.4 shows memory contents in this status.

TCNT value

H'FF

Set value

H'00

Time

TCSR and TCNT write

UDF interrupt

Figure 5.3 WDT Operation

IRQ requests are masked from the UDF interrupt acceptance until RTE instruction completion. Here, the IRQ requests include external IRQ pin inputs. The WDT sets the HLT bit to 1 when the counter value underflows again between the UDF interrupt acceptance and RTE instruction completion. The WDT sets the HLT bit to 1 also when 1 is written to the EWE bit between the UDF interrupt acceptance and RTE instruction completion.

Figure 5.4 shows an example of checking the application execution area by using the UDF interrupt routine. In this example, addresses H'1000 to H'1FFF are defined as a correct application area. When a UDF interrupt is issued immediately after the MOV instruction is executed, the stack contents that can be referred to from the UDF interrupt routine are as shown on the right in figure

5.4. The PC marked by *1 points to the address marked by *2. The UDF interrupt routine checks

whether this PC is in the defined area. If it is not in the defined area, the application program may have run out of control or the application program may have been executed in an undefined area.

Page 68

In this case, system operation can be stopped by writing 1 to the HLT flag, or the external systems can be notified of the abnormal execution by outputting a signal to an I/O pin.

--- Example of program in UDF interrupt routine --UDFentry:

BTST #7,@TCSR ; reconfirmation BEQ ERROR MOV.W @(2,SP), R0 MOV.W #H'1000, R1 MOV.W #H'1FFF, R2 CMP.W R0, R1 ; if (H'1000<=PC<=H'1FFF) then PASS BHS ERROR CMP.W R0, R2 BLO ERROR RTE

ERROR:

MOV.B #H'FF, R0L MOV.B R0L, @TCSR ; system halt

--- End ---

H'1000

MOV

H'1FFF

ADD

Application program area

UDF interrupt

PC marked with *1 points to address marked with *2

SP SP+1

SP+2 SP+3

CCR (CCR)

PCH *1 PCL *1

Stack area

Figure 5.4 Memory Contents for Checking Application Execution

Page 69

5.3.2 Checking the Procedure for Writing to EEPROM

The WDT issues an EWE interrupt when 1 is written to the EWE bit. The EWE interrupt is accepted at the end of the instruction following the instruction in which 1 is written to the EWE bit. Figure 5.5 shows the timing of the EWE interrupt. EWE interrupt vector addresses are H'000A to H'000B. The EWE interrupt routine can monitor the instructions in the area pointed to by the PC stored in the stack, to check whether or not the EEPMOV instruction was executed by the correct procedure and with correct data, that is, the routine can check whether EEPROM was correctly written to. Figure 5.6 shows memory contents at this time.

MOV fetch

EWE interrupt

MOV.W #4000,R0 MOV.B R0H,@TCSR ;Writes 1 to the EWE bit. MOV.B R0L,@ECR EEPMOV

EWE write MOV fetch ECR write EEPMOV

RTE

EWE interrupt routine

Figure 5.5 Timing for EWE Interrupt Acceptance by EWE Write

IRQ requests are masked from the EWE interrupt acceptance until EEPMOV instruction completion. Here, the IRQ requests include external IRQ pin inputs. When a TCNT underflow and a write to EWE occur at the same time, an exception by the EWE interrupt is processed, then an exception by the TCNT underflow is processed. The WDT sets the UDF bit to 1 and issues a UDF interrupt when the counter value underflows in the EWE interrupt routine. The WDT sets the HLT bit is set to 1 when 1 is written to the EWE bit again between the EWE interrupt acceptance and EEPMOV instruction completion.

Figure 5.6 shows an example of checking the EEPROM writing operation by using the EWE interrupt routine. In the program shown on the left in figure 5.6, an EWE interrupt is issued between the MOV instruction to ECR and the EEPMOV instruction. At this time, the stack contents that can be referred to from the EWE interrupt routine are as shown on the right in figure

5.6. The PC marked by *1 points to the start address marked by *2 of the EEPMOV instruction.

The EWE interrupt routine checks whether the instructions before and after this PC are correct. If they are not correct, EEPROM will be incorrectly written to due to the invalid procedure. The EWE interrupt routine also checks whether the R4 to R6 contents used for the EEPMOV

Page 70

instruction are correct. If they are not correct, EEPROM will be incorrectly written to due to invalid register settings.

In this case, system operation can be stopped by writing 1 to the HLT flag, or the external systems can be notified of the abnormal operation by outputting a signal to an I/O pin.

--- Example of program in EWE interrupt routine --EWEentry:

BTST #6, @TCSR ; reconfirmation BEQ ERROR MOV.W @(2,SP), R0 MOV.W #H'7B5C, R1 MOV.W #H'598F, R2 MOV.W @R0, R3 CMP.W R1, R3 ; EEPMOV instruction line check BNE ERROR MOV.W @(2,R0), R3 CMP.W R2, R3 BNE ERROR MOV.W @(-18,R0), R2 CMP.W R2,R5 ; R5 set value check BNE ERROR RTE

ERROR:

MOV.B #H'FF, R0L MOV.B R0L, @TCSR ; system halt

--- End ---

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Opcode Mnemonic FC20 MOV.B #H'20, R4L

7905FF00 MOV.W #H'FF00, R5 79066010 MOV.W #H'6010, R6

790040FC MOV.W #H'40FC, R0 6A88FFFC MOV.B R0H, @TCSR 6A80FFF8 MOV.B R0L, @ECR

7B5C598F EEPMOV

Application program area

SP SP+1

EWE interrupt

PC marked with *1 points to address marked with *2

SP+2 SP+3

CCR (CCR)

PCH *1 PCL *1

Stack area

Figure 5.6 Memory Contents for Checking EEPROM Writing Procedure

5.3.3 Reloading TCNT by TCWA Function

When the operation timing is controlled by software, for example, in a serial transfer routine using I/O ports, the operation timing may be shifted by UDF interrupts. To avoid this, either confirm that the TCNT value is not in the neighborhood of H'00 before executing such a routine or reload the initial value to TCNT using the TCWA function. In the latter case, the UDF interrupt interval can be extended to a specified time. Figure 5.7 shows the TCNT reloading operation.

TCNT value

H'FF

Set value

H'00

TCWA, TCSR, and TCNT write

UDF interrupt

TCNT reloading

UDF interrupt

Figure 5.7 TCNT Reloading

Time

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To reload the initial value to TCNT using the TCWA function, an instruction that writes to TCNT is used. Specify, in TCWA, the address where the instruction that writes to TCNT is stored, before initializing TCSR and TCNT in the WDT initializing routine. At the same time, set the WAD bit in TCWA to 0. When the write instruction stored in the address specified in TCWA is executed, the value initially set to TCNT in the WDT initializing routine is reloaded to TCNT. With this write instruction, any value can be specified as a write data but the initial value is written to TCNT regardless of the specified write data. The write instruction for reloading must be stored in the ROM area pointed to by the specified address; if it is stored outside the specified ROM area, TCNT will not be reloaded. Figure 5.8 shows the memory contents when TCNT reloading is specified.

--- Example of program in TCNT reloading --CPUinit:

MOV.B #H'00, R0L ; CPU speed = CLK/2 MOV.B R0L, @SYSCR

WDTinit:

MOV.B #H'10, R0L ; WAD = 0, enable address = H'1000–H'1FF7 MOV.B R0L, @TCWA MOV.B #H'2F, R0L ; CS = CLK/256 MOV.B R0L, @TCSR MOV.B #H'FF, R0L ; UDF interval MOV.B R0L, @TCNT

--------------.org H'1000

TCNTreload:

MOV.B R0L, @TCNT ; TCNT reload

--- End ---

H'1000

MOV.B R0L, @TCNT

TCNT reloading enabled

H'2000

MOV.B R0L, @TCNT

Figure 5.8 Memory Contents for Reloading TCNT

TCNT reloading disabled

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5.3.4 Initializing WDT

The WDT initialization procedure is described below. Figure 5.9 shows the initialization flow.

(1) Set CPUCS0 bit of SYSCR to select the CPU operating clock. (2) Set TCWA to specify the allocation address of the reloading instruction. (3) Set CS1 and CS0 to select the clock to be input to TCNT. (4) Set TCNT to specify the initial value.

START

Cancel reset

Set the CPUCS0 bit of SYSCR

Set TCWA

Set CS1 and CS0 of TCSR

Set TCNT

END

Figure 5.9 WDT Initialization Flow

If the WDT is not initialized within 512 external clock cycles from reset when the CPUCS0 bit of SYSCR is set to 0 or within 256 external clock cycles from reset when the CPUCS0 bit is set to 1, TCNT will underflow and an UDF interrupt will occur. In this case, if register R7 (SP) has not been set to the correct value, an illegal address will be accessed during the UDF interrupt exception handling, and the chip enters the reset state by the security function.

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5.4 Notes on Usage

1. When a SLEEP instruction is executed in the UDF interrupt routine, the sleep mode cannot be canceled. Also when a SLEEP instruction is executed between an EWE interrupt acceptance and an EEPMOV instruction execution, the sleep mode cannot be canceled. In sleep mode, the WDT suspends operation. Therefore, the sleep mode will not be canceled by an EWE interrupt or a UDF interrupt. The sleep mode can be canceled only by a low-level input to the RES pin.

2. Before the serial transfer routine using I/O ports is started, confirm that TCNT is not in the neighborhood of H'00. When a UDF interrupt occurs during one frame of serial transfer, the serial transfer timing shifts by the number of clock cycles required for the UDF interrupt handling. The UDF interrupt response time (the interval between an interrupt acceptance and the first instruction execution in the interrupt routine) is 14 CPU clock cycles. In the program execution state, the number of cycles required until the current instruction execution is completed is added.

3. Table 5.2 shows the state transitions with WDT.

Table 5.2 State Transitions with WDT

Current State

Next Event Normal

During EEPMOV

Sleep Mode IRQ Routine EWE Routine UDF Routine

None Normal EEPMOV Sleep IRQ EWE UDF EEPMOV

EEPMOV — — EEPMOV EEPMOV EEPMOV

instruction SLEEP

Sleep — — Sleep *

Sleep *

instruction IRQ IRQ — Cleared IRQ masked IRQ masked IRQ masked

EWE EWE — * UDF UDF — *

— * — *

EWE Halt Halt UDF UDF Halt

Notes: 1. WDT suspends operation without being initialized. EWE or UDF event does not occur.

2. IRQ interrupts are masked. The sleep mode can be canceled by a low-level input to the RES pin.

4. The write instruction that reloads the initial value to TCNT must not be stored in the last eight bytes (H'XFF8 to H'XFFF) of the area specified in TCWA. Otherwise, TCNT reloading may fail.

5. The CS1 and CS0 bits in TCSR can be written to only once after reset. To set these bits, use the MOV instruction; they cannot be set by executing the BSET instruction twice. Any bit manipulation instruction, such as the BSET instruction, accesses the memory space in byte units, and therefore, the MCU regards the first BSET instruction as setting these two bits together.

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Section 6 RAM

6.1 Overview

The H8/3150 series has an on-chip static RAM (H8/3152, H8/3155, and H8/3156: 512 bytes; H8/3153 and H8/3158: 1024 bytes).

The RAM is connected to the CPU by a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer.

If word access is performed at an odd address in RAM, the word at the preceding even address is accessed. Normally an even address should be specified for word data.

6.1.1 Block Diagram

Figures 6.1 and 6.2 show block diagrams of the RAM.

H'FDC0 H'FDC1 H'FDC2 H'FDC3

On-chip RAM

(512 bytes)

H'FFBE H'FFBF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Even addresses Odd addresses

Figure 6.1 RAM Block Diagram (H8/3152, H8/3155, and H8/3156)

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H'FBC0 H'FBC1 H'FBC2 H'FBC3

On-chip RAM

(1024 bytes)

H'FFBE H'FFBF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Even addresses Odd addresses

Figure 6.2 RAM Block Diagram (H8/3153 and H8/3158)

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Section 7 ROM

7.1 Overview

The H8/3150 series has an on-chip ROM (H8/3152: 24 kbytes; H8/3153: 32 kbytes; H8/3155 and H8/3156: 16 kbytes; H8/3158: 46 kbytes). The ROM is connected to the CPU by a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer.

If word access is performed at an odd address in ROM, the word at the preceding even address is accessed. Normally an even address should be specified for word data.

7.1.1 Block Diagram

Figures 7.1 to 7.4 show block diagrams of the ROM.

Internal data bus (upper 8 bits)

H'0000 H'0001 H'0002 H'0003

On-chip ROM

(24 kbytes)

H'5FFE H'5FFF

Even addresses Odd addresses

Figure 7.1 ROM Block Diagram (H8/3152)

Internal data bus (lower 8 bits)

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H'0000 H'0001 H'0002 H'0003

On-chip ROM

(32 kbytes)

H'7FFE H'7FFF

Even addresses Odd addresses

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Figure 7.2 ROM Block Diagram (H8/3153)

H'0000 H'0001 H'0002 H'0003

On-chip ROM

(16 kbytes)

H'3FFE H'3FFF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Even addresses Odd addresses

Figure 7.3 ROM Block Diagram (H8/3155 and H8/3156)

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H'0000 H'0001 H'0002 H'0003

On-chip ROM

(46 kbytes)

H'B7FE H'B7FF

Even addresses Odd addresses

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Figure 7.4 ROM Block Diagram (H8/3158)

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Section 8 EEPROM

8.1 Overview

The H8/3150 series has an electrically writable and erasable EEPROM on-chip. Both data and program code can be stored in the EEPROM.

8.1.1 Features

The features of the EEPROM are listed below.

• Configuration: Allocated on the CPU address space

Product EEPROM Capacity Page Size Number of Pages

H8/3152 8 kbytes + 256 bytes 32 bytes 256 + 8 pages H8/3153 16 kbytes + 512 bytes 64 bytes 256 + 8 pages H8/3155 1 kbyte + 128 bytes 16 bytes 64 + 8 pages H8/3156 2 kbyte + 128 bytes 16 bytes 128 + 8 pages H8/3158 16 kbytes + 512 bytes 64 bytes 256 + 8 pages

• Written by a special block data transfer instruction

EEPMOV instruction: rewrites or overwrites a block of data (1 byte to the maximum number of bytes in a page), or erases a page (16, 32, or 64 bytes) at a time.

• Protection features prevent accidental writing and erasing  Write/erase protection can be designated by protect bits.  Control registers prevent inadvertent writing and erasing.

• On-chip voltage pumping circuit

Generates the high voltage required for writing and erasing

• Built-in oscillator and timer The write/erase sequence is controlled using an independent oscillator. EEPROM write/erase

timing does not depend on the external clock.

• Write/erase time (max.): 10 ms (rewrite), 5 ms (erase, overwrite)

• Rewrite endurance: 105 times

• Data retention time: 10 years

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8.1.2 Block Diagram

Figure 8.1 shows a block diagram of the EEPROM.

The built-in timer generates the write/erase sequence. The clock pulses for this timer are obtained from an on-chip oscillator and are independent of the CPU clock. Changing the CPU clock rate (external clock) does not affect the EEPROM write/erase timing.

The voltage pumping circuit generates the high voltages needed for writing and erasing. No external high-voltage power supply is required.

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

EPR ECR EEPROM

Figure 8.1 EEPROM Block Diagram

Voltage pumping circuit

Timer

Oscillator

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8.1.3 Memory Organization

Figures 8.2 to 8.5 show configurations of the EEPROM.

32 bytes

Page 0 Page 1

Page 263 H'80E1 H'80FE H'80FF

H'6000 H'6001 H'601E H'601F H'6020 H'6021 H'603E H'603F

H'80E0

Selector

Data

Figure 8.2 EEPROM Memory Organization (H8/3152)

64 bytes

Page 0 Page 1

Page 263 H'C1C1 H'C1FE H'C1FF

H'8000 H'8001 H'803E H'803F H'8040 H'8041 H'807E H'807F

H'C1C0

Selector

Data

Figure 8.3 EEPROM Memory Organization (H8/3153)

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16 bytes

Page 0 Page 1

Page 71 H'6471 H'647E H'647F

H'6000 H'6001 H'600E H'600F H'6010 H'6011 H'601E H'601F

H'6470

Selector

Data

Figure 8.4 EEPROM Memory Organization (H8/3155)

16 bytes

Page 0 Page 1

Page 135 H'6871 H'687E H'687F

H'6000 H'6001 H'600E H'600F H'6010 H'6011 H'601E H'601F

H'6870

Selector

Data

Figure 8.5 EEPROM Memory Organization (H8/3156)

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64 bytes

Page 0 Page 1

Page 263 H'F9C1 H'F9FE H'F9FF

H'B800 H'B801 H'B83E H'B83F H'B840 H'B841 H'B87E H'B87F

H'F9C0

Selector

Data

Figure 8.6 EEPROM Memory Organization (H8/3158)

8.1.4 Register Configuration

Writing and erasing of the EEPROM are controlled by the registers listed in table 8.1.

Table 8.1 EEPROM Registers

EEPROM control register ECR R/W H'FF H'FFF8 EEPROM protection register EPR R/W H'FF H'FFF9

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8.2 Register Descriptions

8.2.1 EEPROM Control Register (ECR)

ECR is an 8-bit register that controls the type of write or erase operation performed on the EEPROM.

Bit: 7 6 5 4 3 2 1 0

——————OC1OC0

Initial value: 1 1 1 1 1 1 1 1

Read/Write: R R R R R R R/W R/W

Bits 7 to 2—Reserved: Always read as 1 and cannot be written to.

Although not used at present, reserved bits may be used in the future. When writing to ECR, write 0 to these bits.

Bits 1 and 0—Operation Control 1 and 0 (OC1 and OC0): These bits select the type of EEPROM write/erase operation.

Four operations can be selected by OC1 and OC0 as follows.

Bit 1: OC1 Bit 0: OC0 Description

0 0 Rewrite

1 Overwrite

1 0 Page erase

1 Write/erase disabled (Initial value)

To prevent unintended writing and erasing, the OC1 and OC0 bits are both set to 1 automatically at a reset, in sleep mode, and at the end of a write or erase operation. It is accordingly necessary to clear one or both of these bits before every write or erase operation.

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8.2.2 EEPROM Protection Register (EPR)

Bit: 7 6 5 4 3 2 1 0

PBM ———————

Initial value: 1 1 1 1 1 1 1 1

Read/Write: R/W R R R R R R R

EPR is an 8-bit register that enables the writing of EEPROM write/erase protect bits.

Bit 7—Protect Bit Mode (PBM): This bit selects the EEPROM data area or protection area.

The protection area is selected when the PBM bit is cleared to 0. The data area is selected when the PBM bit is set to 1.

Writing the PBM bit automatically sets both the OC1 and OC0 bits in ECR to 1, disabling writing or erasing of the EEPROM. At the end of a write or erase operation in the protection area, the PBM bit itself is automatically set to 1, selecting the data area.

The protect bits are allocated at the same addresses as the first bytes of the pages in the EEPROM data area. Each page of the EEPROM can be protected individually.

See section 8.5, Write/Erase Protection, for further information on the protection area and data area.

Bit 7: PBM Description

0 Protection area is selected 1 Data area is selected (Initial value)

Bits 6 to 0—Reserved: Always read as 1 and cannot be written to.

Although not used at present, reserved bits may be used in the future. When writing to EPR, write 0 to these bits.

ECR and EPR are initialized by the SLEEP instruction. After clearing sleep mode, software must set up these registers again before writing to EEPROM.

8.3 EEPROM Read Operation

The EEPROM is read directly by the CPU, using the same instructions as for reading ROM or RAM. The read data is sent to the CPU via a 16-bit bus. If word access is performed at an odd address, the word at the preceding even address is read.

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8.4 EEPROM Write and Erase Operations

8.4.1 Write/Erase Sequence

The EEPROM is written or erased using the EEPMOV block data transfer instruction. The EEPMOV instruction transfers a block of data stored in RAM to a single page in EEPROM. The data transfer from RAM to EEPROM is controlled by parameters set in CPU registers R4L, R5, and R6 as shown in figure 8.7. The transfer is made by first setting parameters in registers R4L, R5, and R6 and control bits in EPR and ECR, then executing the EEPMOV instruction.

RAM

R5 R5 + R4L – 1

Transfer

EEPROM

R6 R6 + R4L – 1

Figure 8.7 Block Transfer to EEPROM

Figure 8.8 indicates the contents of the three parameter registers used by the EEPMOV instruction. Table 8.2 describes the parameters and their valid ranges of values.

Byte counter

15 0

RAM address register

R4L

15 0

Figure 8.8 EEPMOV Instruction Parameters

EEPROM address register

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Table 8.2 EEPMOV Instruction Parameters and Their Valid Ranges

R4L Byte counter Byte length of block to be

written in EEPROM

R5 RAM address

R6 EEPROM address

Notes: 1. The valid range is for the H8/3153.

2. When an EEPROM write operation ends at the last address on a page, the EEPROM address register (R6) reverts to the first address on that page.

Example: If R6 = H'8000 and R4L = H'40, the final value of R6 is H'8000.

If R6 = H'807F and R4L = H'01, the final value of R6 is H'8040.

Starting address of source block in RAM

Starting address of destination block in EEPROM

1 to 64 (H'01 to H'40)

H'FBC0 to H'FFBF R5 + R4L

H'8000 to H'C1FF R6 + R4L*

Final Value

H'00

If the parameters are set to values outside the valid ranges in table 8.2 when the EEPMOV instruction is executed, or if the byte counter (R4L) and EEPROM address register (R6) are set so as to cross a page boundary, the write or erase operation may not be performed as intended. In addition, the final values left in the registers after instruction execution may not be the values indicated in table 8.2.

Figure 8.9 shows the sequence to be performed by software for writing to or erasing the EEPROM.

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START

Store write data in RAM

Set parameters in CPU registers (R4L, R5, R6)

Notes:

Set EWE in WDT to 1*

Set EPR*

Set ECR

Execute EEPROM write/erase instruction (EEPMOV)

END

1. EWE does not need to be set when the WDT is disabled.

2. EPR does not need to be set when writing to or erasing the data area of the EEPROM

Figure 8.9 EEPROM Write/Erase Sequence

When the WDT is disabled, EWE does not need to be set.

After an EEPMOV instruction, the CPU does not execute the next instruction until the writing or erasing of EEPROM data has ended.

EEPROM data cannot be written or erased by instructions other than EEPMOV.

8.4.2 Rewrite

A single rewrite operation can modify contiguous bytes located in the same EEPROM page; 1 to 32 contiguous bytes in the H8/3152, 1 to 64 contiguous bytes in the H8/3153 and H8/3158, and 1 to 16 contiguous bytes in the H8/3155 and H8/3156 can be modified.

A rewrite operation is restricted to a single page. The byte counter (R4L) and EEPROM address register (R6) must be set so that the operation does not cross a page boundary.

To perform a rewrite operation, clear both OC1 and OC0 to 0.

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8.4.3 Erase

When the EEPMOV instruction is executed with OC1 = 1 and OC0 = 0, the relevant EEPROM page is erased.

The entire page containing the byte addressed by the EEPROM address register (R6) is erased. All data in the page is changed to 1 when erased. The byte counter (R4L) and RAM address register (R5) can be set to any valid values.

EEPROM

Page N + 2 Page N + 1

Page N

1 Page Erased

Page N + 2

Page N + 1

Page N

Figure 8.10 EEPROM Erase Operation

8.4.4 Overwrite

When the EEPMOV instruction is executed with OC1 = 0 and OC0 = 1, the transferred data is overwritten on the old data.

After an overwrite operation, the EEPROM contains the logical AND of the old data and the overwritten data.

10010110Old data

. . . . . . . . . . . . . . . . . .

11100100

Overwritten data

10001111

10000110Resulting data 10100100

Figure 8.11 Results of Overwrite Operations (Examples)

. . . . . . . . . . . . . . . . . .

10100111

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8.5 Write/Erase Protection

8.5.1 Protect Bits

EEPROM data can be protected from accidental writing and erasing. Each page can be protected individually.

Each page has its own protect bits. Write/erase protection is conferred by writing a protection code (H'78) to the protect bits.

Once a page is protected, the protection cannot be canceled.

The protect bits for a page have the same address as the first data byte in the page. The PBM bit in EPR selects either the protection or data area. The protection area is selected when PBM = 0; the data area is selected when PBM = 1.

Figure 8.12 shows how the protect bits are allocated to pages. Figure 8.13 shows an example of write/erase protection.

H'8000

16 kbytes + 512 bytes

H'C1FF

64 bytes

Page 0 Protect 0

. . .

Page 263 Protect 263

PBM = 1 EEPROM Data area

1 byte

. . .

PBM = 0 EEPROM Protection area

Figure 8.12 Allocation of Protect Bits (H8/3153)

264 pages

Page 92

Data area Protection area

Page 0 Page 1 Page 2

. . .

Page 263

: Write/erase-protected pages

H'FF H'FC H'FF

. . .

H'FC

Can be written only once

Figure 8.13 Example of Write/Erase Protection (H8/3153)

8.5.2 Protection Procedure

To protect a page, software must set the EPR and ECR registers, then write the protection code (H'78) to the protect bits.

The protection procedure is given next. Figure 8.14 shows a flowchart.

1. Set the EWE bit in TCSR of WDT to 1 to enable EPR and ECR writing.

2. Clear the PBM bit in EPR to 0 to select the protection area. The OC1 and OC0 bits in ECR will then be automatically set to 1, disabling EEPROM writing and erasing.

3. Clear the OC1 bit in ECR to 0. The OC0 bit may be set to either 1 or 0.

4. Execute the EEPMOV instruction to write the protection code, H'78, to the protect bits. The address of the protect bits is the same as the top byte address in the page to be protected.

After the protection code has been written, EPR automatically reverts to select the data area, and ECR is set to the write/erase-disabled state (OC1 = OC0 = 1).

Steps 1 to 4 must be carried out in that order for each page protected.

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START

EWE ← 1*

PBM ← 0

OC1 ← 0

Protect bits ← H'78

END

Note: EWE does not need to be set when the WDT is disabled.

Figure 8.14 Protection Flowchart

Note that the EWE bit in TCSR must be set to 1 before the PBM bit in EPR is cleared to 0. However, when the WDT is disabled, the EWE does not need to be set.

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8.5.3 Reading the Protect Bits

After the EWE bit in TCSR is set to 1 and the PBM bit in EPR is cleared to 0, the protect bits can be read. The EWE bit continues holding 1 until the EEPMOV instruction is completed. To clear the EWE bit, execute the EEPMOV instruction at OC1 = OC0 = 1. Note that setting the EWE bit to 1 at EWE = 1 sets the HLT bit in TCSR to 1. The EWE bit does not need to be set when the WDT is disabled.

The protect bits for a protected page are read as H'FC. The protect bits for an unprotected page are read as H'FF. Figure 8.15 shows a flowchart for protect bit read.

START

EWE ← 1 *

PBM ← 0

Read the protect bits

OC1, OC0 ← 0 *

Execute EEPMOV *

END

Note *: Does not need when the WDT is disabled.

(Clear the EWE bit)

Figure 8.15 Protect Bit Read Flowchart

Page 95

8.6 Notes on Usage

When using the EEPROM, note the following points.

(1) Write/Erase Abort: If an external reset is input during write or erase operation, the write or erase operation in progress is aborted and the control registers are initialized. In this case, data written to the EEPROM is not guaranteed.

(2) EEPMOV Instruction Execution with Invalid Register Settings: If registers R4L and R6 are set so as to cross a page boundary, the EEPROM write or erase operation is performed within the page including the initial address in R6.

Example: In the H8/3153, if:

R4L = H'40 R5 = H'FF00 R6 = H'8030

Then the block data transfer is performed as follows:

RAM addresses H'FF00 to H'FF0F → EEPROM addresses H'8030 to H'803F RAM addresses H'FF10 to H'FF3F → EEPROM addresses H'8000 to H'802F

(3) Rewrite/Overwrite Operations: Rewrite/overwrite operations can be specified in 1-byte units, but are executed in 8-byte units depending on the address and the number of bytes to be written into the EEPROM. Figure 8.16 shows the rewrite/overwrite operation areas (for H8/3153).

Case 1: Rewrite/overwrite to the first one byte in a page

If the rewrite/overwrite address specifies the first one byte in a page, only the first 8-byte area is rewritten/overwritten. The remaining area in the page is not rewritten/overwritten.

Case 2: Rewrite/overwrite to the first nine bytes in a page

If the rewrite/overwrite address specifies the first nine bytes in a page, only the first 16byte area is rewritten/overwritten. The remaining area in the page is not rewritten/overwritten.

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88888888

Page NCase 1

88888888

: Rewrite/overwrite execution area : Rewrite/overwrite operations are not executed in this area

Page NCase 2

Figure 8.16 Rewrite/Overwrite Operations (for H8/3153)

(4) Use the EEPMOV Instruction: When writing to the EEPROM, use the EEPMOV instruction.

Do not use the MOV instruction for writing.

(5) Setting the EPR registers: When using the EEPROM as a program area, fix the PBM bit of the EPR register to 1.

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8.7 Notes on Usage of H8/3153

The H8/3153 has several usage restrictions. Note that when developing software, a violation of these restrictions cannot be detected by the emulator.

(1) Target Users: users that specify the ROM code to operate the WDT for the H8/3153.

(2) Usage Restrictions:

1. In the EEPROM write procedure, do not locate the instruction string from the EWE setting instruction to the ECR setting instruction for the WDT in the EEPROM area. The following three MOV.B instructions must not be located in the EEPROM area.

MOV.B R0L,@EWE MOV.B R0H,@EPR MOV.B R1H,@ECR EEPMOV

2. Do not locate the EWE or UDF interrupt routine for the WDT in the EEPROM area.

3. Use EEPMOV for writing to EEPROM (do not use a write instruction, such as MOV).

(3) Effect of Violating Usage Restrictions: writing to EEPROM may fail.

(4) Detection by Emulator: The emulator cannot detect a violation of these restrictions.

Therefore, if the EWE setting instruction is located in EEPROM, in violation of the usage restrictions, the software cannot operate with the product chip although it can operate with the emulator.

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Section 9 I/O Ports

9.1 Overview

The H8/3150 series has two I/O ports. Software can select whether to use each I/O bit for data input or output.

The I/O ports have a data register (DR) for latching output data, and a data direction register (DDR) for specifying input or output.

9.1.1 Block Diagram

Figure 9.1 shows an I/O port block diagram. DR and DDR can be accessed only by byte access.

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Sleep mode

Internal data bus

DDR7

I/O-1/

IRQ

Input pull-up MOS (always switched-on)

Input buffer

Output buffer

Falling edge

detector

DDR write

DR7 QD

DR write

DR read

Sleep mode

External interrupt request (to CPU)

I/O-2/

IRQ

Input pull-up MOS (always switched-on)

Input buffer

Sleep mode

DDR6 QD

DDR write

DR6 QD

Output buffer

DR write

DR read

Figure 9.1 I/O Port Block Diagram

Page 100

9.1.2 Register Configuration

Table 9.1 lists the I/O port registers.

Table 9.1 I/O Port Registers

Name Abbr. R/W Address

Data register DR R/W H'FFFE Data direction register DDR W H'FFFF

9.2 Register Descriptions

9.2.1 Data Register (DR)

Bit: 7 6 5 4 3 2 1 0

DR7 DR6 — — — — — —

Initial value: — — — — — — — —

Read/Write: R/W R/W — — — — — —

The data register latches the output data.

Bit 7—Data Register Bit 7 (DR7): Latches I/O port output data. When DDR7 = 1 (selecting output), the value of the DR7 bit is output on the I/O-1 pin.

When DR is read, if DDR7 = 0 (input), the logic level of the I/O-1 signal is read directly. If DDR7 = 1 (output), the value in the DR7 latch is read.

The value of DR7 after a reset is undetermined.

Bit 6—Data Register Bit 6 (DR6): Latches I/O port output data. When DDR6 = 1 (selecting output), the value of the DR6 bit is output on the I/O-2 pin.

When DR is read, if DDR6 = 0 (input), the logic level of the I/O-2 signal is read directly. If DDR6 = 1 (output), the value in the DR6 latch is read.

The value of DR6 after a reset is undetermined.

Bits 5 to 0—Reserved: Always read as undetermined and cannot be written to.

Although not used at present, reserved bits may be used in the future. When writing to DR, write 0 to these bits.