Hitachi H8S/2633, HD6432633, HD6432631, H8S/2633 F-ZTAT, HD64F2633 Hardware Manual

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H8S/2633 Series

H8S/2633

HD6432633

H8S/2632

HD6432632

H8S/2631

HD6432631

H8S/2633 F-ZTAT™

ADE-602-165A Rev. 2.0 4/14/00 Hitachi, Ltd.

HD64F2633

Hardware Manual

Cautions

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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

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Preface

The H8S/2633 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting functions required for system configuration.

The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently.

The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily.

Single-power-supply flash memory (F-ZTAT™*1), PROM (ZTAT™*2), and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through fullscale volume production, even for applications with frequently changing specifications.

On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, 14-bit PWM timer (PWM), watchdog timer (WDT), serial communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also possible to incorporate an on-chip PC bus interface (IIC) as an option.

In addition, DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling high-speed data transfer without CPU intervention.

Use of the H8S/2633 Series enables easy implementation of compact, high-performance systems capable of processing large volumes of data.

This manual describes the hardware of the H8S/2633 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set.

Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

Main Revisions and Additions in this Edition

Revisions

Page Item

2 1.1 Overview Table 1-1 Overview

9 1.3.2 Pin Functions in Each Operating Mode Table 1-2 Pin Functions in Each

14 1.3.3 Pin Functions Table 1-3 Pin Functions amended 38 2.6.1 Overview Table 2-1 Instruction Classification

39 2.6.2 Instructions and Addressing Modes Table 2-2 Combinations of

43, 47 2.6.3 Table of Instructions Classified by Function Table 2-3 Instructions classified by

(See Manual for Details)

Input clock frequency amended

Operating Mode amended

Notes on TAS Instruction added

Instructions and Addressing Modes Notes on TAS Instruction added

Function

Notes on TAS Instruction added 66 2.10 Usage Note Added 68 3.2.1 Mode Control Register (MDCR) Bit 7 description amended 75 3.4 Pin Functions in Each Operating Mode Table 3-3 Pin Functions in Each

Mode amended 76 to 78 3.5 Address Map in Each Operating Mode Figure 3-1 Memory Map in Each

Operating Mode in the H8S/2633

Note 2 added

Figure 3-2 Memory Map in Each

Operating Mode in the H8S/2632

Note 2 added

Figure 3-3 Memory Map in Each

Operating Mode in the H8S/2631

Note 2 added, amended 84, 85 4.2.3 Reset Sequence Figure 4-2 Reset Sequence

(Modes 4 and 5) amended

87 4.4 Interrupts Figure 4-4 Interrupt Sources and

Figure 4-3 Reset Sequence

(Modes 6 and 7) added

Number of Interrupts amended

Revisions

Page Item

(See Manual for Details)

101 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 Interrupt Sources, Vector

Addresses, and Interrupt Priorities 8-bit timer channel names amended

109 5.4.2 Interrupt Control Mode 0 Figure 5-5 Flowchart of Procedure

Up to Interrupt Acceptance in Interrupt Control Mode 0 amended

189 7.6.1 DDS=1 Figure 7-30 DACK Output Timing

when DDS=1 (Example Showing DRAM Access)

Note added

190 7.6.2 DDS=0 Figure 7-31 DACK Output Timing

when DDS=0 (Example Showing DRAM Access)

Note added

202 7.10.4 Transition Timing Figure 7-39 Bus-Released State

Transition Timing amended

209, 210 8.1.3 Overview of Functions Table 8-1 Overview of DMAC

Functions SCI transfer source names

amended

290, 291 8.7 Usage Notes DMAC Register Access during

Operation added Figure 8-40 and figure 8-41 added

296 9.1.2 Block Diagram Figure 9-1 Block Diagram of DTC

amended

310, 311 9.3.3 DTC Vector Table Table 9-4 Interrupt Sources, DTC

Vector Addresses, and Corresponding DTCEs

8-bit timer channel names amended 327 10.1 Overview Capacitance load value amended 328 to

331 350 to

352

10.3.3 Pin Functions Table 10-5 Port 3 Pin Functions

Table 10-1 Port Functions

amended

amended 363 10.7.1 Overview Figure 10-6 Port A Pin Functions

369 10.8.1 Overview Figure 10-9 Port B Pin Functions

amended

Revisions

Page Item

(See Manual for Details)

396 10.12.3 Pin Functions Table 10-21 Port F Pin Functions

PF3 description amended

522 13.1.2 Block Diagram Figure 13-1 Block Diagram of 8-Bit

Timer amended

523 13.1.3 Pin Configuration Table 13-1 Pin Configuration

amended 563 15.1 Overview Amended 566 15.1.4 Register Configuration Table 15-2 WDT Registers

amended 570, 571 15.2.2 Timer Control/Status Register (TCSR) Bits 2 to 0 (overflow period)

amended 573 15.2.4 Pin Function Control Register (PFCR) Amended 587, 588 16.1.4 Register Configuration Table 16-2 SCI Registers

Note 3 amended 597 16.2.6 Serial Control Register (SCR) Description of bits 1 and 0 amended 646 16.3.5 IrDA Operation Figure 16-22 IrDA Transmit and

Receive Operations amended 653 to

658

16.5 Usage Notes Operation in Case of Mode Transition added

Switching from SCK Pin Function to Port Pin Function added

18.1.1 Features Formatless description deleted

692, 693 18.1.2 Block Diagram Description amended

Figure 18-1 Block Diagram of I

Bus Interface Dedicated formatless clock deleted

694 18.1.3 Input/Output Pins Table 18-1 I2C Bus Interface Pins

SYNCI pin deleted

699, 700 18.2.2 Slave Address Register (SAR) Bit 0 description amended 701 18.2.3 Second Slave Address Register (SARX) Bit 0 description amended 703 18.2.4 I2C Bus Mode Register (ICMR) Description of bits 5 to 3

705, 708,

18.2.5 I2C Bus Control Register (ICCR) Bit 7 description added

709

ø = 25 MHz added to transfer rates

Bit 1 description amended

Revisions

Page Item

(See Manual for Details)

717 18.2.8 DDC Switch Register (DDCSWR) Description of bits 7 to 4 amended

Bits 3 to 0 amended and Note 2 added

Description of CLR3-0 added

719 18.3.1 I2C Bus Data Format Description amended

Figure 18-3 I

C Bus Formats)

C Bus Data Formats

Formatless description deleted

720 to

18.3.2 Master Transmit Operation Description amended

722 722 to

724

18.3.3 Master Receive Operation Description amended Figure 18-8 Example of Master

Receive Mode Operation Timing (MLS = WAIT = ACKB = 0) amended

731, 732 18.3.9 Sample Flowcharts Figure 18-14 Flowchart for Master

Transmit Mode (Example) amended Figure 18-15 Flowchart for Master

Receive Mode (Example) amended

734 to

18.3.10 Initialization of Internal State Added

736 736, 737,

739, 740

18.4 Usage Notes Table 18-6 I2C Bus Timing (SCL and SDA Output) amended

Table 18-7 Permissible SCL Rise Time (t

) Values ø = 25 MHz added

to time indication

Table 18-8 I Maximum Influence of t

C Bus Timing (with

)

Sr/tSf

amended

740 to 743

745 19.1.1 Features Conversion time amended 753 19.2.3 A/D Control Register (ADCR) Bit 3 and 2 (conversion time)

Note on ICDR Read at End of Master Reception added

Notes on Start Condition Issuance for Retransmission added

Notes on I

C Bus Interface Stop Condition Instruction Issuance added

amended

Revisions

Page Item

(See Manual for Details)

760 19.4.3 Input Sampling and A/D Conversion Time Conversion time amended 761 Table 19-4 A/D Conversion Time

(Single Mode) amended

766 19.6 Usage Notes Permissible Signal Source

Impedance amended

771 20.1.4 Register Configuration Table 20-2 D/A Converter

Registers amended

778 21.2.1 System Control Register (SYSCR) Description of bit 0

Note added 779 21.4 Usage Notes Reserved Areas amended 781 22.1 Features Programming/Erasing amended 792, 793 22.5.2 Flash Memory Control Register 2

Amended

(FLMCR2) 797, 798 22.5.7 Serial Control Register X (SCRX) Amended 801 22.6.1 Boot Mode Automatic SCI Bit Rate Adjustment

Bit rate amended 803, 804 22.6.2 User Program Mode Description amended 805 to

22.7 Programming/Erasing Flash Memory Completely revised

812 821 22.11.1 Socket Adapter Pin Correspondence

Diagram

Figure 22-17 Socket Adapter Pin

Correspondence Diagram amended 822 22.11.2 Programmer Mode Operation Table 22-11 Settings for Various

Operating Modes In Programmer

Mode amended 834 to

838 839 22.14 Note on Switching from F-ZTAT Version to

22.13 Flash Memory Programming and Erasing Precautions

Added

Mask ROM Version 842 23.2.1 System Clock Control Register (SCKCR) Description amended 843, 844 23.2.2 Low-Power Control Register (LPWRCR) Amended 844 23.3 Oscillator Amended

Revisions

Page Item

(See Manual for Details)

844, 845 23.3.1 Connecting a Crystal Resonator Table 23-2 Damping Resistance

Value 25 MHz added Crystal Resonator amended

845, 846 Table 23-3 Crystal Resonator

Parameters 25 MHz added Figure 23-5 Points for Attention

when Using PLL Oscillation Circuit amended

848 23.3.2 External Clock Input External Clock

Description amended Table 23-4 External Clock Input

Conditions amended 849 23.4 PLL Circuit Amended 854 24.1 Overview Table 24-1 LSI Internal States in

Each Mode

WDT module stop mode description

amended 860, 861 24.2.2 System Clock Control Register (SCKCR) Description amended 871 24.6.3 Setting Oscillation Stabilization Time after

Clearing Software Standby Mode

Table 24-5 Oscillation Stabilization

Time Settings

25 MHz added

880 to

25.2 Power supply voltage and operating frequency range

25.2 DC Characteristics Amended

Deleted

Following item numbers amended

887 888 25.3 AC Characteristics Figure 25-1 Output Load Circuit

amended 889 25.3.1 Clock Timing Table 25-5 Clock Timing amended 893, 894,

901

25.3.3 Bus Timing Table 25-7 Bus Timing amended Figure 25-15 External Bus Request

Output Timing added

902 25.3.4 DMAC Timing Table 25-8 DMAC Timing amended

Page Item

Revisions (See Manual for Details)

906 to 908

25.3.5 Timing of On-Chip Supporting Modules Table 25-9 Timing of On-Chip Supporting Modules

Note added Figure 25-21 PPG Output Timing

amended

914 25.4 A/D Conversion Characteristics Table 25-11 A/D Conversion

Characteristics Conditions amended

915 25.5 D/A Conversion Characteristics Table 25-12 D/A Conversion

Characteristics Conditions amended

916 25.6 Flash Memory Characteristics Added 925, 927,

942

A.1 Instruction List Table A-1 Instruction Set

Notes on TAS Instruction added MULXU and MULXS instruction

execution states amended

956, 957 A.2 Instruction Codes Table A-2 Instruction Codes

Notes on TAS Instruction added

974, 975 A.4 Number of States Required for Instruction

Execution

Table A-5 Number of Cycles in Instruction Execution

Notes on TAS Instruction added

988, 989 A.5 Bus States During Instruction Execution Table A-6 Instruction Execution

Cycles Notes on TAS Instruction added

996 to

B.1 Addresses Completely revised

1005 1006 to

B.2 Functions Completely revised

1103

Contents

Section 1 Overview............................................................................................................ 1

1.1 Overview............................................................................................................................ 1

1.2 Internal Block Diagram...................................................................................................... 6

1.3 Pin Description................................................................................................................... 7

1.3.1 Pin Arrangement................................................................................................... 7

1.3.2 Pin Functions in Each Operating Mode................................................................ 9

1.3.3 Pin Functions........................................................................................................ 14

Section 2 CPU..................................................................................................................... 21

2.1 Overview............................................................................................................................ 21

2.1.1 Features................................................................................................................. 21

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU................................... 22

2.1.3 Differences from H8/300 CPU ............................................................................. 23

2.1.4 Differences from H8/300H CPU.......................................................................... 23

2.2 CPU Operating Modes....................................................................................................... 24

2.3 Address Space.................................................................................................................... 29

2.4 Register Configuration.......................................................................................................30

2.4.1 Overview............................................................................................................... 30

2.4.2 General Registers.................................................................................................. 31

2.4.3 Control Registers.................................................................................................. 32

2.4.4 Initial Register Values .......................................................................................... 34

2.5 Data Formats...................................................................................................................... 35

2.5.1 General Register Data Formats............................................................................. 35

2.5.2 Memory Data Formats.......................................................................................... 37

2.6 Instruction Set.................................................................................................................... 38

2.6.1 Overview............................................................................................................... 38

2.6.2 Instructions and Addressing Modes...................................................................... 39

2.6.3 Table of Instructions Classified by Function....................................................... 41

2.6.4 Basic Instruction Formats..................................................................................... 48

2.7 Addressing Modes and Effective Address Calculation...................................................... 50

2.7.1 Addressing Mode.................................................................................................. 50

2.7.2 Effective Address Calculation.............................................................................. 53

2.8 Processing States................................................................................................................ 57

2.8.1 Overview............................................................................................................... 57

2.8.2 Reset State ............................................................................................................ 58

2.8.3 Exception-Handling State..................................................................................... 59

2.8.4 Program Execution State ...................................................................................... 62

2.8.5 Bus-Released State................................................................................................ 62

2.8.6 Power-Down State................................................................................................ 62

2.9 Basic Timing...................................................................................................................... 63

2.9.1 Overview............................................................................................................... 63

2.9.2 On-Chip Memory (ROM, RAM).......................................................................... 63

2.9.3 On-Chip Supporting Module Access Timing....................................................... 65

2.9.4 External Address Space Access Timing............................................................... 66

2.10 Usage Note......................................................................................................................... 66

2.10.1 TAS Instruction .................................................................................................... 66

Section 3 MCU Operating Modes................................................................................. 67

3.1 Overview............................................................................................................................ 67

3.1.1 Operating Mode Selection.................................................................................... 67

3.1.2 Register Configuration.......................................................................................... 68

3.2 Register Descriptions......................................................................................................... 68

3.2.1 Mode Control Register (MDCR).......................................................................... 68

3.2.2 System Control Register (SYSCR)....................................................................... 69

3.2.3 Pin Function Control Register (PFCR)................................................................. 71

3.3 Operating Mode Descriptions............................................................................................ 74

3.3.1 Mode 4.................................................................................................................. 74

3.3.2 Mode 5 ................................................................................................................. 74

3.3.3 Mode 6.................................................................................................................. 74

3.3.4 Mode 7.................................................................................................................. 74

3.4 Pin Functions in Each Operating Mode............................................................................. 75

3.5 Address Map in Each Operating Mode.............................................................................. 75

Section 4 Exception Handling........................................................................................ 79

4.1 Overview............................................................................................................................ 79

4.1.1 Exception Handling Types and Priority................................................................ 79

4.1.2 Exception Handling Operation ............................................................................. 80

4.1.3 Exception Vector Table........................................................................................ 80

4.2 Reset................................................................................................................................... 82

4.2.1 Overview............................................................................................................... 82

4.2.2 Types of Reset ...................................................................................................... 82

4.2.3 Reset Sequence ..................................................................................................... 83

4.2.4 Interrupts after Reset............................................................................................. 85

4.2.5 State of On-Chip Supporting Modules after Reset Release.................................. 85

4.3 Traces................................................................................................................................. 86

4.4 Interrupts............................................................................................................................ 87

4.5 Trap Instruction.................................................................................................................. 88

4.6 Stack Status after Exception Handling.............................................................................. 89

4.7 Notes on Use of the Stack.................................................................................................. 90

Section 5 Interrupt Controller......................................................................................... 91

5.1 Overview............................................................................................................................ 91

5.1.1 Features................................................................................................................. 91

5.1.2 Block Diagram...................................................................................................... 92

5.1.3 Pin Configuration.................................................................................................. 93

5.1.4 Register Configuration.......................................................................................... 93

5.2 Register Descriptions......................................................................................................... 94

5.2.1 System Control Register (SYSCR)....................................................................... 94

5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) ............................. 95

5.2.3 IRQ Enable Register (IER)................................................................................... 96

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 97

5.2.5 IRQ Status Register (ISR) .................................................................................... 98

5.3 Interrupt Sources................................................................................................................ 99

5.3.1 External Interrupts................................................................................................ 99

5.3.2 Internal Interrupts.................................................................................................. 100

5.3.3 Interrupt Exception Handling Vector Table ......................................................... 100

5.4 Interrupt Operation............................................................................................................. 105

5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 105

5.4.2 Interrupt Control Mode 0...................................................................................... 108

5.4.3 Interrupt Control Mode 2...................................................................................... 110

5.4.4 Interrupt Exception Handling Sequence............................................................... 112

5.4.5 Interrupt Response Times..................................................................................... 113

5.5 Usage Notes....................................................................................................................... 114

5.5.1 Contention between Interrupt Generation and Disabling ..................................... 114

5.5.2 Instructions that Disable Interrupts....................................................................... 115

5.5.3 Times when Interrupts are Disabled .................................................................... 115

5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 116

5.6 DTC and DMAC Activation by Interrupt.......................................................................... 116

5.6.1 Overview............................................................................................................... 116

5.6.2 Block Diagram...................................................................................................... 116

5.6.3 Operation .............................................................................................................. 117

Section 6 PC Break Controller (PBC).......................................................................... 119

6.1 Overview............................................................................................................................ 119

6.1.1 Features................................................................................................................. 119

6.1.2 Block Diagram...................................................................................................... 120

6.1.3 Register Configuration.......................................................................................... 121

6.2 Register Descriptions......................................................................................................... 121

6.2.1 Break Address Register A (BARA)...................................................................... 121

6.2.2 Break Address Register B (BARB)...................................................................... 122

6.2.3 Break Control Register A (BCRA)....................................................................... 122

6.2.4 Break Control Register B (BCRB) ....................................................................... 124

6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 124

6.3 Operation............................................................................................................................ 125

6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 125

6.3.2 PC Break Interrupt Due to Data Access ............................................................... 125

6.3.3 Notes on PC Break Interrupt Handling................................................................. 126

iii

6.3.4 Operation in Transitions to Power-Down Modes................................................. 126

6.3.5 PC Break Operation in Continuous Data Transfer ............................................... 127

6.3.6 When Instruction Execution is Delayed by One State.......................................... 128

6.3.7 Additional Notes................................................................................................... 129

Section 7 Bus Controller.................................................................................................. 131

7.1 Overview............................................................................................................................ 131

7.1.1 Features................................................................................................................. 131

7.1.2 Block Diagram...................................................................................................... 133

7.1.3 Pin Configuration.................................................................................................. 134

7.1.4 Register Configuration.......................................................................................... 135

7.2 Register Descriptions......................................................................................................... 136

7.2.1 Bus Width Control Register (ABWCR) ............................................................... 136

7.2.2 Access State Control Register (ASTCR).............................................................. 137

7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 138

7.2.4 Bus Control Register H (BCRH).......................................................................... 142

7.2.5 Bus Control Register L (BCRL)........................................................................... 144

7.2.6 Pin Function Control Register (PFCR)................................................................. 146

7.2.7 Memory Control Register (MCR) ........................................................................ 149

7.2.8 DRAM Control Register (DRAMCR).................................................................. 151

7.2.9 Refresh Timer Counter (RTCNT) ........................................................................ 153

7.2.10 Refresh Time Constant Register (RTCOR).......................................................... 153

7.3 Overview of Bus Control................................................................................................... 154

7.3.1 Area Partitioning................................................................................................... 154

7.3.2 Bus Specifications ................................................................................................ 155

7.3.3 Memory Interfaces................................................................................................ 156

7.3.4 Interface Specifications for Each Area................................................................. 157

7.3.5 Chip Select Signals............................................................................................... 158

7.4 Basic Bus Interface............................................................................................................ 159

7.4.1 Overview............................................................................................................... 159

7.4.2 Data Size and Data Alignment.............................................................................. 159

7.4.3 Valid Strobes ........................................................................................................ 161

7.4.4 Basic Timing......................................................................................................... 162

7.4.5 Wait Control.......................................................................................................... 170

7.5 DRAM Interface................................................................................................................ 172

7.5.1 Overview............................................................................................................... 172

7.5.2 Setting up DRAM Space ...................................................................................... 172

7.5.3 Address Multiplexing............................................................................................ 173

7.5.4 Data Bus................................................................................................................ 173

7.5.5 DRAM Interface Pins ........................................................................................... 174

7.5.6 Basic Timing......................................................................................................... 174

7.5.7 Precharge State Control........................................................................................ 176

7.5.8 Wait Control.......................................................................................................... 177

7.5.9 Byte Access Control ............................................................................................. 179

7.5.10 Burst Operation..................................................................................................... 181

7.5.11 Refresh Control..................................................................................................... 185

7.6 DMAC Single Address Mode and DRAM Interface......................................................... 189

7.6.1 DDS=1.................................................................................................................. 189

7.6.2 DDS=0.................................................................................................................. 190

7.7 Burst ROM Interface.......................................................................................................... 191

7.7.1 Overview............................................................................................................... 191

7.7.2 Basic Timing......................................................................................................... 191

7.7.3 Wait Control.......................................................................................................... 193

7.8 Idle Cycle........................................................................................................................... 194

7.8.1 Operation .............................................................................................................. 194

7.8.2 Pin States in Idle Cycle......................................................................................... 198

7.9 Write Data Buffer Function............................................................................................... 199

7.10 Bus Release........................................................................................................................ 200

7.10.1 Overview............................................................................................................... 200

7.10.2 Operation .............................................................................................................. 200

7.10.3 Pin States in External Bus Released State............................................................ 201

7.10.4 Transition Timing ................................................................................................. 202

7.10.5 Notes..................................................................................................................... 203

7.11 Bus Arbitration................................................................................................................... 204

7.11.1 Overview............................................................................................................... 204

7.11.2 Operation .............................................................................................................. 204

7.11.3 Bus Transfer Timing............................................................................................. 205

7.12 Resets and the Bus Controller............................................................................................ 205

Section 8 DMA Controller.............................................................................................. 207

8.1 Overview............................................................................................................................ 207

8.1.1 Features................................................................................................................. 207

8.1.2 Block Diagram...................................................................................................... 208

8.1.3 Overview of Functions.......................................................................................... 209

8.1.4 Pin Configuration.................................................................................................. 211

8.1.5 Register Configuration.......................................................................................... 212

8.2 Register Descriptions (1) (Short Address Mode)............................................................... 213

8.2.1 Memory Address Registers (MAR)...................................................................... 214

8.2.2 I/O Address Register (IOAR) ............................................................................... 215

8.2.3 Execute Transfer Count Register (ETCR)............................................................ 215

8.2.4 DMA Control Register (DMACR) ....................................................................... 216

8.2.5 DMA Band Control Register (DMABCR)........................................................... 220

8.3 Register Descriptions (2) (Full Address Mode)................................................................. 225

8.3.1 Memory Address Register (MAR)........................................................................ 225

8.3.2 I/O Address Register (IOAR) ............................................................................... 225

8.3.3 Execute Transfer Count Register (ETCR)............................................................ 226

8.3.4 DMA Control Register (DMACR) ....................................................................... 227

8.3.5 DMA Band Control Register (DMABCR)........................................................... 231

8.4 Register Descriptions (3) ................................................................................................... 236

8.4.1 DMA Write Enable Register (DMAWER)........................................................... 236

8.4.2 DMA Terminal Control Register (DMATCR)..................................................... 238

8.4.3 Module Stop Control Register (MSTPCR)........................................................... 239

8.5 Operation............................................................................................................................ 240

8.5.1 Transfer Modes..................................................................................................... 240

8.5.2 Sequential Mode ................................................................................................... 242

8.5.3 Idle Mode.............................................................................................................. 245

8.5.4 Repeat Mode......................................................................................................... 248

8.5.5 Single Address Mode............................................................................................ 252

8.5.6 Normal Mode........................................................................................................ 255

8.5.7 Block Transfer Mode............................................................................................ 258

8.5.8 DMAC Activation Sources................................................................................... 264

8.5.9 Basic DMAC Bus Cycles...................................................................................... 267

8.5.10 DMAC Bus Cycles (Dual Address Mode)............................................................ 268

8.5.11 DMAC Bus Cycles (Single Address Mode)......................................................... 276

8.5.12 Write Data Buffer Function.................................................................................. 282

8.5.13 DMAC Multi-Channel Operation......................................................................... 283

8.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC,

and the DMAC...................................................................................................... 285

8.5.15 NMI Interrupts and DMAC.................................................................................. 286

8.5.16 Forced Termination of DMAC Operation............................................................ 287

8.5.17 Clearing Full Address Mode................................................................................. 288

8.6 Interrupts............................................................................................................................ 289

8.7 Usage Notes....................................................................................................................... 290

Section 9 Data Transfer Controller (DTC)................................................................. 295

9.1 Overview............................................................................................................................ 295

9.1.1 Features................................................................................................................. 295

9.1.2 Block Diagram...................................................................................................... 296

9.1.3 Register Configuration.......................................................................................... 297

9.2 Register Descriptions......................................................................................................... 298

9.2.1 DTC Mode Register A (MRA)............................................................................. 298

9.2.2 DTC Mode Register B (MRB).............................................................................. 300

9.2.3 DTC Source Address Register (SAR) .................................................................. 301

9.2.4 DTC Destination Address Register (DAR) .......................................................... 301

9.2.5 DTC Transfer Count Register A (CRA)............................................................... 301

9.2.6 DTC Transfer Count Register B (CRB)................................................................ 302

9.2.7 DTC Enable Registers (DTCER).......................................................................... 302

9.2.8 DTC Vector Register (DTVECR) ........................................................................ 303

9.2.9 Module Stop Control Register A (MSTPCRA).................................................... 304

9.3 Operation............................................................................................................................ 305

9.3.1 Overview............................................................................................................... 305

9.3.2 Activation Sources................................................................................................ 307

9.3.3 DTC Vector Table ................................................................................................ 308

9.3.4 Location of Register Information in Address Space............................................. 312

9.3.5 Normal Mode........................................................................................................ 313

9.3.6 Repeat Mode......................................................................................................... 314

9.3.7 Block Transfer Mode............................................................................................ 315

9.3.8 Chain Transfer...................................................................................................... 317

9.3.9 Operation Timing.................................................................................................. 318

9.3.10 Number of DTC Execution States........................................................................ 319

9.3.11 Procedures for Using DTC.................................................................................... 321

9.3.12 Examples of Use of the DTC................................................................................ 322

9.4 Interrupts............................................................................................................................ 325

9.5 Usage Notes........................................................................................................................ 325

Section 10 I/O Ports............................................................................................................. 327

10.1 Overview............................................................................................................................ 327

10.2 Port 1.................................................................................................................................. 332

10.2.1 Overview............................................................................................................... 332

10.2.2 Register Configuration.......................................................................................... 333

10.2.3 Pin Functions........................................................................................................ 335

10.3 Port 3.................................................................................................................................. 347

10.3.1 Overview............................................................................................................... 347

10.3.2 Register Configuration.......................................................................................... 347

10.3.3 Pin Functions........................................................................................................ 350

10.4 Port 4.................................................................................................................................. 353

10.4.1 Overview............................................................................................................... 353

10.4.2 Register Configuration.......................................................................................... 354

10.4.3 Pin Functions........................................................................................................ 354

10.5 Port 7.................................................................................................................................. 355

10.5.1 Overview............................................................................................................... 355

10.5.2 Register Configuration.......................................................................................... 356

10.5.3 Pin Functions........................................................................................................ 358

10.6 Port 9.................................................................................................................................. 361

10.6.1 Overview............................................................................................................... 361

10.6.2 Register Configuration.......................................................................................... 362

10.6.3 Pin Functions........................................................................................................ 362

10.7 Port A................................................................................................................................. 363

10.7.1 Overview............................................................................................................... 363

10.7.2 Register Configuration.......................................................................................... 364

10.7.3 Pin Functions........................................................................................................ 367

10.7.4 MOS Input Pull-Up Function................................................................................ 367

vii

10.8 Port B ................................................................................................................................. 369

10.8.1 Overview............................................................................................................... 369

10.8.2 Register Configuration.......................................................................................... 370

10.8.3 Pin Functions........................................................................................................ 373

10.8.4 MOS Input Pull-Up Function................................................................................ 374

10.9 Port C ................................................................................................................................. 375

10.9.1 Overview............................................................................................................... 375

10.9.2 Register Configuration.......................................................................................... 376

10.9.3 Pin Functions for Each Mode ............................................................................... 379

10.9.4 MOS Input Pull-Up Function................................................................................ 381

10.10 Port D ................................................................................................................................. 382

10.10.1 Overview............................................................................................................... 382

10.10.2 Register Configuration.......................................................................................... 383

10.10.3 Pin Functions........................................................................................................ 385

10.10.4 MOS Input Pull-Up Function................................................................................ 386

10.11 Port E.................................................................................................................................. 387

10.11.1 Overview............................................................................................................... 387

10.11.2 Register Configuration.......................................................................................... 388

10.11.3 Pin Functions........................................................................................................ 390

10.11.4 MOS Input Pull-Up Function................................................................................ 391

10.12 Port F.................................................................................................................................. 392

10.12.1 Overview............................................................................................................... 392

10.12.2 Register Configuration.......................................................................................... 393

10.12.3 Pin Functions........................................................................................................ 395

10.13 Port G ................................................................................................................................. 397

10.13.1 Overview............................................................................................................... 397

10.13.2 Register Configuration.......................................................................................... 398

10.13.3 Pin Functions........................................................................................................ 400

Section 11 16-Bit Timer Pulse Unit (TPU) .................................................................. 403

11.1 Overview............................................................................................................................ 403

11.1.1 Features................................................................................................................. 403

11.1.2 Block Diagram...................................................................................................... 407

11.1.3 Pin Configuration.................................................................................................. 408

11.1.4 Register Configuration.......................................................................................... 410

11.2 Register Descriptions......................................................................................................... 412

11.2.1 Timer Control Register (TCR).............................................................................. 412

11.2.2 Timer Mode Register (TMDR)............................................................................. 417

11.2.3 Timer I/O Control Register (TIOR)...................................................................... 419

11.2.4 Timer Interrupt Enable Register (TIER)............................................................... 432

11.2.5 Timer Status Register (TSR) ................................................................................ 435

11.2.6 Timer Counter (TCNT)......................................................................................... 439

11.2.7 Timer General Register (TGR)............................................................................. 440

viii

11.2.8 Timer Start Register (TSTR)................................................................................ 441

11.2.9 Timer Synchro Register (TSYR).......................................................................... 442

11.2.10 Module Stop Control Register A (MSTPCRA).................................................... 443

11.3 Interface to Bus Master...................................................................................................... 444

11.3.1 16-Bit Registers.................................................................................................... 444

11.3.2 8-Bit Registers...................................................................................................... 444

11.4 Operation............................................................................................................................ 446

11.4.1 Overview............................................................................................................... 446

11.4.2 Basic Functions..................................................................................................... 447

11.4.3 Synchronous Operation ........................................................................................ 453

11.4.4 Buffer Operation................................................................................................... 455

11.4.5 Cascaded Operation.............................................................................................. 459

11.4.6 PWM Modes......................................................................................................... 461

11.4.7 Phase Counting Mode........................................................................................... 466

11.5 Interrupts............................................................................................................................ 473

11.5.1 Interrupt Sources and Priorities............................................................................ 473

11.5.2 DTC/DMAC Activation........................................................................................ 475

11.5.3 A/D Converter Activation..................................................................................... 475

11.6 Operation Timing............................................................................................................... 476

11.6.1 Input/Output Timing............................................................................................. 476

11.6.2 Interrupt Signal Timing ........................................................................................ 480

11.7 Usage Notes ....................................................................................................................... 484

Section 12 Programmable Pulse Generator (PPG)..................................................... 495

12.1 Overview............................................................................................................................ 495

12.1.1 Features................................................................................................................. 495

12.1.2 Block Diagram...................................................................................................... 496

12.1.3 Pin Configuration.................................................................................................. 497

12.1.4 Registers................................................................................................................ 498

12.2 Register Descriptions......................................................................................................... 499

12.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 499

12.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 500

12.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 501

12.2.4 Notes on NDR Access.......................................................................................... 501

12.2.5 PPG Output Control Register (PCR).................................................................... 503

12.2.6 PPG Output Mode Register (PMR)...................................................................... 505

12.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 508

12.2.8 Module Stop Control Register A (MSTPCRA).................................................... 508

12.3 Operation............................................................................................................................ 509

12.3.1 Overview............................................................................................................... 509

12.3.2 Output Timing ...................................................................................................... 510

12.3.3 Normal Pulse Output ............................................................................................ 511

12.3.4 Non-Overlapping Pulse Output ............................................................................ 513

12.3.5 Inverted Pulse Output ........................................................................................... 516

12.3.6 Pulse Output Triggered by Input Capture............................................................. 517

12.4 Usage Notes ...................................................................................................................... 518

Section 13 8-Bit Timers (TMR)....................................................................................... 521

13.1 Overview............................................................................................................................ 521

13.1.1 Features................................................................................................................. 521

13.1.2 Block Diagram...................................................................................................... 522

13.1.3 Pin Configuration.................................................................................................. 523

13.1.4 Register Configuration.......................................................................................... 524

13.2 Register Descriptions......................................................................................................... 525

13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3).......................................................... 525

13.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3)............................... 525

13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3)................................ 526

13.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3)................................................. 526

13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3).................................. 529

13.2.6 Module Stop Control Register A (MSTPCRA).................................................... 532

13.3 Operation............................................................................................................................ 533

13.3.1 TCNT Incrementation Timing.............................................................................. 533

13.3.2 Compare Match Timing........................................................................................ 534

13.3.3 Timing of External RESET on TCNT.................................................................. 536

13.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 536

13.3.5 Operation with Cascaded Connection .................................................................. 537

13.4 Interrupts............................................................................................................................ 538

13.4.1 Interrupt Sources and DTC Activation................................................................. 538

13.4.2 A/D Converter Activation..................................................................................... 538

13.5 Sample Application............................................................................................................ 539

13.6 Usage Notes ....................................................................................................................... 540

13.6.1 Contention between TCNT Write and Clear........................................................ 540

13.6.2 Contention between TCNT Write and Increment................................................. 541

13.6.3 Contention between TCOR Write and Compare Match....................................... 542

13.6.4 Contention between Compare Matches A and B.................................................. 543

13.6.5 Switching of Internal Clocks and TCNT Operation............................................ 543

13.6.6 Interrupts and Module Stop Mode........................................................................ 545

Section 14 14-Bit PWM D/A............................................................................................ 547

14.1 Overview............................................................................................................................ 547

14.1.1 Features................................................................................................................. 547

14.1.2 Block Diagram...................................................................................................... 548

14.1.3 Pin Configuration.................................................................................................. 549

14.1.4 Register Configuration.......................................................................................... 549

14.2 Register Descriptions......................................................................................................... 550

14.2.1 PWM D/A Counter (DACNT).............................................................................. 550

14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB) .............................. 551

14.2.3 PWM D/A Control Register (DACR)................................................................... 552

14.2.4 Module Stop Control Register B (MSTPCRB).................................................... 554

14.3 Bus Master Interface.......................................................................................................... 555

14.4 Operation............................................................................................................................ 558

Section 15 Watchdog Timer.............................................................................................. 563

15.1 Overview............................................................................................................................ 563

15.1.1 Features................................................................................................................. 563

15.1.2 Block Diagram...................................................................................................... 564

15.1.3 Pin Configuration.................................................................................................. 566

15.1.4 Register Configuration.......................................................................................... 566

15.2 Register Descriptions......................................................................................................... 567

15.2.1 Timer Counter (TCNT)......................................................................................... 567

15.2.2 Timer Control/Status Register (TCSR) ................................................................ 567

15.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 572

15.2.4 Pin Function Control Register (PFCR)................................................................. 573

15.2.5 Notes on Register Access ..................................................................................... 574

15.3 Operation............................................................................................................................ 576

15.3.1 Watchdog Timer Operation.................................................................................. 576

15.3.2 Interval Timer Operation...................................................................................... 578

15.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 578

15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 579

15.4 Interrupts............................................................................................................................ 580

15.5 Usage Notes ....................................................................................................................... 580

15.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 580

15.5.2 Changing Value of CKS2 to CKS0...................................................................... 581

15.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 581

15.5.4 System Reset by WDTOVF Signal ...................................................................... 581

15.5.5 Internal Reset in Watchdog Timer Mode.............................................................. 581

Section 16 Serial Communication Interface (SCI, IrDA) ........................................ 583

16.1 Overview............................................................................................................................ 583

16.1.1 Features................................................................................................................. 583

16.1.2 Block Diagram...................................................................................................... 586

16.1.3 Pin Configuration.................................................................................................. 586

16.1.4 Register Configuration.......................................................................................... 587

16.2 Register Descriptions......................................................................................................... 589

16.2.1 Receive Shift Register (RSR) ............................................................................... 589

16.2.2 Receive Data Register (RDR)............................................................................... 589

16.2.3 Transmit Shift Register (TSR).............................................................................. 590

16.2.4 Transmit Data Register (TDR).............................................................................. 590

16.2.5 Serial Mode Register (SMR)................................................................................ 591

16.2.6 Serial Control Register (SCR).............................................................................. 594

16.2.7 Serial Status Register (SSR) ................................................................................. 598

16.2.8 Bit Rate Register (BRR) ....................................................................................... 602

16.2.9 Smart Card Mode Register (SCMR)..................................................................... 611

16.2.10 IrDA Control Register (IrCR)............................................................................... 612

16.2.11 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC).................... 613

16.3 Operation............................................................................................................................ 615

16.3.1 Overview............................................................................................................... 615

16.3.2 Operation in Asynchronous Mode........................................................................ 618

16.3.3 Multiprocessor Communication Function............................................................ 629

16.3.4 Operation in Clocked Synchronous Mode............................................................ 637

16.3.5 IrDA Operation..................................................................................................... 645

16.4 SCI Interrupts..................................................................................................................... 648

16.5 Usage Notes ....................................................................................................................... 650

Section 17 Smart Card Interface...................................................................................... 659

17.1 Overview............................................................................................................................ 659

17.1.1 Features................................................................................................................. 659

17.1.2 Block Diagram...................................................................................................... 660

17.1.3 Pin Configuration.................................................................................................. 661

17.1.4 Register Configuration.......................................................................................... 662

17.2 Register Descriptions......................................................................................................... 664

17.2.1 Smart Card Mode Register (SCMR)..................................................................... 664

17.2.2 Serial Status Register (SSR) ................................................................................. 666

17.2.3 Serial Mode Register (SMR)................................................................................ 668

17.2.4 Serial Control Register (SCR).............................................................................. 670

17.3 Operation............................................................................................................................ 671

17.3.1 Overview............................................................................................................... 671

17.3.2 Pin Connections.................................................................................................... 671

17.3.3 Data Format.......................................................................................................... 673

17.3.4 Register Settings ................................................................................................... 675

17.3.5 Clock..................................................................................................................... 677

17.3.6 Data Transfer Operations...................................................................................... 679

17.3.7 Operation in GSM Mode...................................................................................... 686

17.3.8 Operation in Block Transfer Mode....................................................................... 687

17.4 Usage Notes ....................................................................................................................... 688

Section 18 I2C Bus Interface [Option] ........................................................................... 691

18.1 Overview............................................................................................................................ 691

18.1.1 Features................................................................................................................. 691

18.1.2 Block Diagram...................................................................................................... 692

18.1.3 Input/Output Pins.................................................................................................. 694

18.1.4 Register Configuration.......................................................................................... 695

xii

18.2 Register Descriptions......................................................................................................... 696

18.2.1 I2C Bus Data Register (ICDR).............................................................................. 696

18.2.2 Slave Address Register (SAR).............................................................................. 699

18.2.3 Second Slave Address Register (SARX).............................................................. 700

18.2.4 I2C Bus Mode Register (ICMR)............................................................................ 701

18.2.5 I2C Bus Control Register (ICCR).......................................................................... 704

18.2.6 I2C Bus Status Register (ICSR)............................................................................ 711

18.2.7 Serial Control Register X (SCRX)........................................................................ 716

18.2.8 DDC Switch Register (DDCSWR)....................................................................... 717

18.2.9 Module Stop Control Register B (MSTPCRB).................................................... 718

18.3 Operation............................................................................................................................ 719

18.3.1 I2C Bus Data Format............................................................................................. 719

18.3.2 Master Transmit Operation................................................................................... 720

18.3.3 Master Receive Operation .................................................................................... 722

18.3.4 Slave Receive Operation....................................................................................... 724

18.3.5 Slave Transmit Operation..................................................................................... 726

18.3.6 IRIC Setting Timing and SCL Control................................................................. 728

18.3.7 Operation Using the DTC..................................................................................... 729

18.3.8 Noise Canceler...................................................................................................... 730

18.3.9 Sample Flowcharts................................................................................................ 730

18.3.10 Initialization of Internal State ............................................................................... 734

18.4 Usage Notes ....................................................................................................................... 736

Section 19 A/D Converter.................................................................................................. 745

19.1 Overview............................................................................................................................ 745

19.1.1 Features................................................................................................................. 745

19.1.2 Block Diagram...................................................................................................... 746

19.1.3 Pin Configuration.................................................................................................. 747

19.1.4 Register Configuration.......................................................................................... 748

19.2 Register Descriptions......................................................................................................... 749

19.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 749

19.2.2 A/D Control/Status Register (ADCSR)................................................................ 750

19.2.3 A/D Control Register (ADCR) ............................................................................. 753

19.2.4 Module Stop Control Register A (MSTPCRA).................................................... 754

19.3 Interface to Bus Master...................................................................................................... 755

19.4 Operation............................................................................................................................ 756

19.4.1 Single Mode (SCAN = 0) ..................................................................................... 756

19.4.2 Scan Mode (SCAN = 1)........................................................................................ 758

19.4.3 Input Sampling and A/D Conversion Time.......................................................... 760

19.4.4 External Trigger Input Timing.............................................................................. 761

19.5 Interrupts............................................................................................................................ 762

19.6 Usage Notes ....................................................................................................................... 762

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Section 20 D/A Converter.................................................................................................. 769

20.1 Overview............................................................................................................................ 769

20.1.1 Features................................................................................................................. 769

20.1.2 Block Diagram...................................................................................................... 769

20.1.3 Input and Output Pins ........................................................................................... 771

20.1.4 Register Configuration.......................................................................................... 771

20.2 Register Descriptions......................................................................................................... 772

20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3).................................................. 772

20.2.2 D/A Control Register 01 and 23 (DACR01 and DACR23).................................. 772

20.2.3 Module Stop Control Register A and C (MSTPCRA and MSTPCRC) ............... 774

20.3 Operation............................................................................................................................ 776

Section 21 RAM.................................................................................................................... 777

21.1 Overview............................................................................................................................ 777

21.1.1 Block Diagram...................................................................................................... 777

21.1.2 Register Configuration.......................................................................................... 778

21.2 Register Descriptions......................................................................................................... 778

21.2.1 System Control Register (SYSCR)....................................................................... 778

21.3 Operation............................................................................................................................ 779

21.4 Usage Notes ....................................................................................................................... 779

Section 22 ROM.................................................................................................................... 781

22.1 Features.............................................................................................................................. 781

22.2 Overview............................................................................................................................ 782

22.2.1 Block Diagram...................................................................................................... 782

22.2.2 Mode Transitions.................................................................................................. 783

22.2.3 On-Board Programming Modes............................................................................ 784

22.2.4 Flash Memory Emulation in RAM....................................................................... 786

22.2.5 Differences between Boot Mode and User Program Mode.................................. 787

22.2.6 Block Configuration.............................................................................................. 788

22.3 Pin Configuration............................................................................................................... 788

22.4 Register Configuration....................................................................................................... 789

22.5 Register Descriptions......................................................................................................... 789

22.5.1 Flash Memory Control Register 1 (FLMCR1) ..................................................... 789

22.5.2 Flash Memory Control Register 2 (FLMCR2) ..................................................... 792

22.5.3 Erase Block Register 1 (EBR1)............................................................................ 793

22.5.4 Erase Block Register 2 (EBR2)............................................................................ 794

22.5.5 RAM Emulation Register (RAMER).................................................................... 795

22.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 797

22.5.7 Serial Control Register X (SCRX)........................................................................ 797

22.6 On-Board Programming Modes......................................................................................... 798

22.6.1 Boot Mode............................................................................................................ 798

xiv

22.6.2 User Program Mode.............................................................................................. 803

22.7 Programming/Erasing Flash Memory................................................................................ 805

22.7.1 Program Mode...................................................................................................... 806

22.7.2 Program-Verify Mode .......................................................................................... 807

22.7.3 Erase Mode ........................................................................................................... 811

22.7.4 Erase-Verify Mode................................................................................................ 811

22.8 Protection ........................................................................................................................... 813

22.8.1 Hardware Protection ............................................................................................. 813

22.8.2 Software Protection .............................................................................................. 814

22.8.3 Error Protection .................................................................................................... 815

22.9 Flash Memory Emulation in RAM .................................................................................... 817

22.10 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 819

22.11 Flash Memory Programmer Mode..................................................................................... 819

22.11.1 Socket Adapter Pin Correspondence Diagram ..................................................... 820

22.11.2 Programmer Mode Operation ............................................................................... 822

22.11.3 Memory Read Mode ............................................................................................. 823

22.11.4 Auto-Program Mode ............................................................................................. 826

22.11.5 Auto-Erase Mode.................................................................................................. 828

22.11.6 Status Read Mode ................................................................................................. 830

22.11.7 Status Polling ........................................................................................................ 831

22.11.8 Programmer Mode Transition Time ..................................................................... 831

22.11.9 Notes on Memory Programming .......................................................................... 832

22.12 Flash Memory and Power-Down States ............................................................................ 833

22.12.1 Note on Power-Down States................................................................................. 833

22.13 Flash Memory Programming and Erasing Precautions...................................................... 834

22.14 Note on Switching from F-ZTAT Version to Mask ROM Version................................... 839

Section 23 Clock Pulse Generator................................................................................... 841

23.1 Overview............................................................................................................................ 841

23.1.1 Block Diagram...................................................................................................... 841

23.1.2 Register Configuration.......................................................................................... 842

23.2 Register Descriptions......................................................................................................... 842

23.2.1 System Clock Control Register (SCKCR)............................................................ 842

23.2.2 Low-Power Control Register (LPWRCR)............................................................ 843

23.3 Oscillator............................................................................................................................ 844

23.3.1 Connecting a Crystal Resonator............................................................................ 844

23.3.2 External Clock Input............................................................................................. 847

23.4 PLL Circuit ........................................................................................................................ 849

23.5 Medium-Speed Clock Divider ........................................................................................... 849

23.6 Bus Master Clock Selection Circuit................................................................................... 849

23.7 Subclock Oscillator............................................................................................................ 850

23.8 Subclock Waveform Shaping Circuit ................................................................................ 851

23.9 Note on Crystal Resonator................................................................................................. 851

Section 24 Power-Down Modes ...................................................................................... 853

24.1 Overview............................................................................................................................ 853

24.1.1 Register Configuration.......................................................................................... 857

24.2 Register Descriptions......................................................................................................... 858

24.2.1 Standby Control Register (SBYCR)..................................................................... 858

24.2.2 System Clock Control Register (SCKCR)............................................................ 860

24.2.3 Low-Power Control Register (LPWRCR)............................................................ 861

24.2.4 Timer Control/Status Register (TCSR) ................................................................ 864

24.2.5 Module Stop Control Register (MSTPCR)........................................................... 865

24.3 Medium-Speed Mode......................................................................................................... 866

24.4 Sleep Mode ........................................................................................................................ 867

24.4.1 Sleep Mode ........................................................................................................... 867

24.4.2 Exiting Sleep Mode .............................................................................................. 867

24.5 Module Stop Mode ............................................................................................................ 868

24.5.1 Module Stop Mode ............................................................................................... 868

24.5.2 Usage Notes.......................................................................................................... 870

24.6 Software Standby Mode..................................................................................................... 870

24.6.1 Software Standby Mode........................................................................................ 870

24.6.2 Clearing Software Standby Mode......................................................................... 870

24.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 871

24.6.4 Software Standby Mode Application Example .................................................... 872

24.6.5 Usage Notes.......................................................................................................... 873

24.7 Hardware Standby Mode ................................................................................................... 873

24.7.1 Hardware Standby Mode...................................................................................... 873

24.7.2 Hardware Standby Mode Timing.......................................................................... 874

24.8 Watch Mode....................................................................................................................... 874

24.8.1 Watch Mode.......................................................................................................... 874

24.8.2 Exiting Watch Mode............................................................................................. 875

24.8.3 Notes..................................................................................................................... 875

24.9 Sub-Sleep Mode................................................................................................................. 876

24.9.1 Sub-Sleep Mode.................................................................................................... 876

24.9.2 Exiting Sub-Sleep Mode....................................................................................... 876

24.10 Sub-Active Mode ............................................................................................................... 877

24.10.1 Sub-Active Mode.................................................................................................. 877

24.10.2 Exiting Sub-Active Mode..................................................................................... 877

24.11 Direct Transitions............................................................................................................... 878

24.11.1 Overview of Direct Transitions............................................................................ 878

24.12 ø Clock Output Disabling Function ................................................................................... 878

Section 25 Electrical Characteristics.............................................................................. 879

25.1 Absolute Maximum Ratings.............................................................................................. 879

25.2 DC Characteristics ............................................................................................................. 880

25.3 AC Characteristics ............................................................................................................. 888

xvi

25.3.1 Clock Timing........................................................................................................ 889

25.3.2 Control Signal Timing.......................................................................................... 891

25.3.3 Bus Timing ........................................................................................................... 893

25.3.4 DMAC Timing...................................................................................................... 902

25.3.5 Timing of On-Chip Supporting Modules.............................................................. 906

25.4 A/D Conversion Characteristics ........................................................................................ 914

25.5 D/A Conversion Characteristics ........................................................................................ 915

25.6 Flash Memory Characteristics ........................................................................................... 916

25.7 Usage Note......................................................................................................................... 917

Appendix A Instruction Set............................................................................................... 919

A.1 Instruction List................................................................................................................... 919

A.2 Instruction Codes ............................................................................................................... 943

A.3 Operation Code Map.......................................................................................................... 958

A.4 Number of States Required for Instruction Execution....................................................... 962

A.5 Bus States During Instruction Execution........................................................................... 976

A.6 Condition Code Modification............................................................................................ 990

Appendix B Internal I/O Register.................................................................................... 996

B.1 Addresses ........................................................................................................................... 996

B.2 Functions.......................................................................................................................... 1006

Appendix C I/O Port Block Diagrams ......................................................................... 1104

C.1 Port 1 Block Diagram ...................................................................................................... 1104

C.2 Port 3 Block Diagram ...................................................................................................... 1110

C.3 Port 4 Block Diagram ...................................................................................................... 1118

C.4 Port 7 Block Diagram ...................................................................................................... 1119

C.5 Port 9 Block Diagram ...................................................................................................... 1126

C.6 Port A Block Diagram...................................................................................................... 1127

C.7 Port B Block Diagram...................................................................................................... 1131

C.8 Port C Block Diagram...................................................................................................... 1132

C.9 Port D Block Diagram...................................................................................................... 1134

C.10 Port E Block Diagram...................................................................................................... 1135

C.11 Port E Block Diagram...................................................................................................... 1136

C.12 Port G Block Diagram...................................................................................................... 1144

Appendix D Pin States...................................................................................................... 1148

D.1 Port States in Each Mode................................................................................................. 1148

Appendix E Timing of Transition to and Recovery from

Hardware Standby Mode

Appendix F Product Code Lineup................................................................................. 1153

............................................................................ 1152

xvii

Appendix G Package Dimensions................................................................................. 1154

xviii

Section 1 Overview

1.1 Overview

The H8S/2633 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip.

The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include DMA controller (DMAC), data transfer controller (DTC) bus masters, ROM and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), 8-bit timer, 14-bit PWM timer (PWM) watchdog timer (WDT), serial communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also possible to incorporate an on-chip PC bus interface (IIC) as an option.

On-chip ROM is available as 256-kbyte flash memory (F-ZTAT™ version)* or as 256-, 128-, or 64-kbyte mask ROM. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode.

The features of the H8S/2633 Series are shown in table 1-1.

Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.

Table 1-1 Overview

Item Specification

CPU

• General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers

or eight 32-bit registers)

• High-speed operation suitable for realtime control  Maximum clock rate: 25 MHz  High-speed arithmetic operations

8/16/32-bit register-register add/subtract : 40 ns 16 × 16-bit register-register multiply : 160 ns 16 × 16 + 42-bit multiply and accumulate : 160 ns 32 ÷ 16-bit register-register divide : 800 ns

• Instruction set suitable for high-speed operation  Sixty-nine basic instructions  8/16/32-bit move/arithmetic and logic instructions  Unsigned/signed multiply and divide instructions  Multiply-and accumulate instruction  Powerful bit-manipulation instructions

• Two CPU operating modes  Normal mode: 64-kbyte address space

(cannot be used in the H8S/2633 Series)

 Advanced mode: 16-Mbyte address space

Bus controller

PC break controller

DMA controller (DMAC)

• Address space divided into 8 areas, with bus specifications settable independently for each area

• Choice of 8-bit or 16-bit access space for each area

• 2-state or 3-state access space can be designated for each area

• Number of program wait states can be set for each area

• Burst ROM directly connectable

• Possible to connect a maximum of 8 MB of DRAM (alternatively, it is also

possible to use an interval timer)

• External bus release function

• Supports debugging functions by means of PC break interrupts

• Two break channels

• Short address mode and full address mode selectable

• Short address mode: 4 channels

Full address mode: 2 channels

• Transfer possible in repeat mode/block transfer mode Transfer possible in single address mode

• Activation by internal interrupt possible

+ 1138 hidden pages

Hitachi H8S/2633, HD6432633, HD6432631, H8S/2633 F-ZTAT, HD64F2633 Hardware Manual

Specifications and Main Features

Frequently Asked Questions

User Manual