Hitachi H8S/2633, HD6432633, HD6432631, H8S/2633 F-ZTAT, HD64F2633 Hardware Manual

H8S/2633 Series

H8S/2633

HD6432633

H8S/2632

HD6432632

H8S/2631

HD6432631

H8S/2633 F-ZTAT™

ADE-602-165A
Rev. 2.0
4/14/00
Hitachi, Ltd.

HD64F2633

Hardware Manual

Cautions

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life support.

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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Preface

The H8S/2633 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600
CPU core, and a set of on-chip supporting functions required for system configuration.

The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.

The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.

Single-power-supply flash memory (F-ZTAT™*1), PROM (ZTAT™*2), and mask ROM versions
are available, providing a quick and flexible response to conditions from ramp-up through full­scale volume production, even for applications with frequently changing specifications.

On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timer, 14-bit PWM timer (PWM), watchdog timer (WDT), serial
communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O ports. It is also
possible to incorporate an on-chip PC bus interface (IIC) as an option.

In addition, DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling
high-speed data transfer without CPU intervention.

Use of the H8S/2633 Series enables easy implementation of compact, high-performance systems
capable of processing large volumes of data.

This manual describes the hardware of the H8S/2633 Series. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.

Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

Main Revisions and Additions in this Edition

Revisions

Page Item

2 1.1 Overview Table 1-1 Overview

9 1.3.2 Pin Functions in Each Operating Mode Table 1-2 Pin Functions in Each

14 1.3.3 Pin Functions Table 1-3 Pin Functions amended
38 2.6.1 Overview Table 2-1 Instruction Classification

39 2.6.2 Instructions and Addressing Modes Table 2-2 Combinations of

43, 47 2.6.3 Table of Instructions Classified by Function Table 2-3 Instructions classified by

(See Manual for Details)

Input clock frequency amended

Operating Mode amended

Notes on TAS Instruction added

Instructions and Addressing Modes
Notes on TAS Instruction added

Function

Notes on TAS Instruction added
66 2.10 Usage Note Added
68 3.2.1 Mode Control Register (MDCR) Bit 7 description amended
75 3.4 Pin Functions in Each Operating Mode Table 3-3 Pin Functions in Each

Mode amended
76 to 78 3.5 Address Map in Each Operating Mode Figure 3-1 Memory Map in Each

Operating Mode in the H8S/2633

Note 2 added

Figure 3-2 Memory Map in Each

Operating Mode in the H8S/2632

Note 2 added

Figure 3-3 Memory Map in Each

Operating Mode in the H8S/2631

Note 2 added, amended
84, 85 4.2.3 Reset Sequence Figure 4-2 Reset Sequence

(Modes 4 and 5) amended

87 4.4 Interrupts Figure 4-4 Interrupt Sources and

Figure 4-3 Reset Sequence

(Modes 6 and 7) added

Number of Interrupts amended

Revisions

Page Item

(See Manual for Details)

101 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 Interrupt Sources, Vector

Addresses, and Interrupt Priorities
8-bit timer channel names amended

109 5.4.2 Interrupt Control Mode 0 Figure 5-5 Flowchart of Procedure

Up to Interrupt Acceptance in
Interrupt Control Mode 0 amended

189 7.6.1 DDS=1 Figure 7-30 DACK Output Timing

when DDS=1 (Example Showing
DRAM Access)

Note added

190 7.6.2 DDS=0 Figure 7-31 DACK Output Timing

when DDS=0 (Example Showing
DRAM Access)

Note added

202 7.10.4 Transition Timing Figure 7-39 Bus-Released State

Transition Timing amended

209, 210 8.1.3 Overview of Functions Table 8-1 Overview of DMAC

Functions
SCI transfer source names

amended

290, 291 8.7 Usage Notes DMAC Register Access during

Operation added
Figure 8-40 and figure 8-41 added

296 9.1.2 Block Diagram Figure 9-1 Block Diagram of DTC

amended

310, 311 9.3.3 DTC Vector Table Table 9-4 Interrupt Sources, DTC

Vector Addresses, and
Corresponding DTCEs

8-bit timer channel names amended
327 10.1 Overview Capacitance load value amended
328 to

331
350 to

352

10.3.3 Pin Functions Table 10-5 Port 3 Pin Functions

Table 10-1 Port Functions

amended

amended
363 10.7.1 Overview Figure 10-6 Port A Pin Functions

369 10.8.1 Overview Figure 10-9 Port B Pin Functions

amended

amended

Revisions

Page Item

(See Manual for Details)

396 10.12.3 Pin Functions Table 10-21 Port F Pin Functions

PF3 description amended

522 13.1.2 Block Diagram Figure 13-1 Block Diagram of 8-Bit

Timer amended

523 13.1.3 Pin Configuration Table 13-1 Pin Configuration

amended
563 15.1 Overview Amended
566 15.1.4 Register Configuration Table 15-2 WDT Registers

amended
570, 571 15.2.2 Timer Control/Status Register (TCSR) Bits 2 to 0 (overflow period)

amended
573 15.2.4 Pin Function Control Register (PFCR) Amended
587, 588 16.1.4 Register Configuration Table 16-2 SCI Registers

Note 3 amended
597 16.2.6 Serial Control Register (SCR) Description of bits 1 and 0 amended
646 16.3.5 IrDA Operation Figure 16-22 IrDA Transmit and

Receive Operations amended
653 to

658

16.5 Usage Notes Operation in Case of Mode
Transition added

Switching from SCK Pin Function to
Port Pin Function added

18.1.1 Features Formatless description deleted

692, 693 18.1.2 Block Diagram Description amended

2

Figure 18-1 Block Diagram of I

C

Bus Interface
Dedicated formatless clock deleted

694 18.1.3 Input/Output Pins Table 18-1 I2C Bus Interface Pins

SYNCI pin deleted

699, 700 18.2.2 Slave Address Register (SAR) Bit 0 description amended
701 18.2.3 Second Slave Address Register (SARX) Bit 0 description amended
703 18.2.4 I2C Bus Mode Register (ICMR) Description of bits 5 to 3

705, 708,

18.2.5 I2C Bus Control Register (ICCR) Bit 7 description added

709

ø = 25 MHz added to transfer rates

Bit 1 description amended

Revisions

Page Item

(See Manual for Details)

717 18.2.8 DDC Switch Register (DDCSWR) Description of bits 7 to 4 amended

Bits 3 to 0 amended and Note 2
added

Description of CLR3-0 added

719 18.3.1 I2C Bus Data Format Description amended

2

Figure 18-3 I

2

(I

C Bus Formats)

C Bus Data Formats

Formatless description deleted

720 to

18.3.2 Master Transmit Operation Description amended

722
722 to

724

18.3.3 Master Receive Operation Description amended
Figure 18-8 Example of Master

Receive Mode Operation Timing
(MLS = WAIT = ACKB = 0)
amended

731, 732 18.3.9 Sample Flowcharts Figure 18-14 Flowchart for Master

Transmit Mode (Example) amended
Figure 18-15 Flowchart for Master

Receive Mode (Example) amended

734 to

18.3.10 Initialization of Internal State Added

736
736, 737,

739, 740

18.4 Usage Notes Table 18-6 I2C Bus Timing (SCL
and SDA Output) amended

Table 18-7 Permissible SCL Rise
Time (t

) Values ø = 25 MHz added

Sr

to time indication

2

Table 18-8 I
Maximum Influence of t

C Bus Timing (with

)

Sr/tSf

amended

740 to
743

745 19.1.1 Features Conversion time amended
753 19.2.3 A/D Control Register (ADCR) Bit 3 and 2 (conversion time)

Note on ICDR Read at End of
Master Reception added

Notes on Start Condition Issuance
for Retransmission added

2

Notes on I

C Bus Interface Stop
Condition Instruction Issuance
added

amended

Revisions

Page Item

(See Manual for Details)

760 19.4.3 Input Sampling and A/D Conversion Time Conversion time amended
761 Table 19-4 A/D Conversion Time

(Single Mode) amended

766 19.6 Usage Notes Permissible Signal Source

Impedance amended

771 20.1.4 Register Configuration Table 20-2 D/A Converter

Registers amended

778 21.2.1 System Control Register (SYSCR) Description of bit 0

Note added
779 21.4 Usage Notes Reserved Areas amended
781 22.1 Features Programming/Erasing amended
792, 793 22.5.2 Flash Memory Control Register 2

Amended

(FLMCR2)
797, 798 22.5.7 Serial Control Register X (SCRX) Amended
801 22.6.1 Boot Mode Automatic SCI Bit Rate Adjustment

Bit rate amended
803, 804 22.6.2 User Program Mode Description amended
805 to

22.7 Programming/Erasing Flash Memory Completely revised

812
821 22.11.1 Socket Adapter Pin Correspondence

Diagram

Figure 22-17 Socket Adapter Pin

Correspondence Diagram amended
822 22.11.2 Programmer Mode Operation Table 22-11 Settings for Various

Operating Modes In Programmer

Mode amended
834 to

838
839 22.14 Note on Switching from F-ZTAT Version to

22.13 Flash Memory Programming and Erasing
Precautions

Added

Added

Mask ROM Version
842 23.2.1 System Clock Control Register (SCKCR) Description amended
843, 844 23.2.2 Low-Power Control Register (LPWRCR) Amended
844 23.3 Oscillator Amended

Revisions

Page Item

(See Manual for Details)

844, 845 23.3.1 Connecting a Crystal Resonator Table 23-2 Damping Resistance

Value
25 MHz added
Crystal Resonator amended

845, 846 Table 23-3 Crystal Resonator

Parameters
25 MHz added
Figure 23-5 Points for Attention

when Using PLL Oscillation Circuit
amended

848 23.3.2 External Clock Input External Clock

Description amended
Table 23-4 External Clock Input

Conditions amended
849 23.4 PLL Circuit Amended
854 24.1 Overview Table 24-1 LSI Internal States in

Each Mode

WDT module stop mode description

amended
860, 861 24.2.2 System Clock Control Register (SCKCR) Description amended
871 24.6.3 Setting Oscillation Stabilization Time after

Clearing Software Standby Mode

Table 24-5 Oscillation Stabilization

Time Settings

25 MHz added

880 to

25.2 Power supply voltage and operating
frequency range

25.2 DC Characteristics Amended

Deleted

Following item numbers amended

887
888 25.3 AC Characteristics Figure 25-1 Output Load Circuit

amended
889 25.3.1 Clock Timing Table 25-5 Clock Timing amended
893, 894,

901

25.3.3 Bus Timing Table 25-7 Bus Timing amended
Figure 25-15 External Bus Request

Output Timing added

902 25.3.4 DMAC Timing Table 25-8 DMAC Timing amended

Page Item

Revisions
(See Manual for Details)

906 to
908

25.3.5 Timing of On-Chip Supporting Modules Table 25-9 Timing of On-Chip
Supporting Modules

Note added
Figure 25-21 PPG Output Timing

amended

914 25.4 A/D Conversion Characteristics Table 25-11 A/D Conversion

Characteristics
Conditions amended

915 25.5 D/A Conversion Characteristics Table 25-12 D/A Conversion

Characteristics
Conditions amended

916 25.6 Flash Memory Characteristics Added
925, 927,

942

A.1 Instruction List Table A-1 Instruction Set

Notes on TAS Instruction added
MULXU and MULXS instruction

execution states amended

956, 957 A.2 Instruction Codes Table A-2 Instruction Codes

Notes on TAS Instruction added

974, 975 A.4 Number of States Required for Instruction

Execution

Table A-5 Number of Cycles in
Instruction Execution

Notes on TAS Instruction added

988, 989 A.5 Bus States During Instruction Execution Table A-6 Instruction Execution

Cycles
Notes on TAS Instruction added

996 to

B.1 Addresses Completely revised

1005
1006 to

B.2 Functions Completely revised

1103

Contents

Section 1 Overview............................................................................................................ 1

1.1 Overview............................................................................................................................ 1

1.2 Internal Block Diagram...................................................................................................... 6

1.3 Pin Description................................................................................................................... 7

1.3.1 Pin Arrangement................................................................................................... 7

1.3.2 Pin Functions in Each Operating Mode................................................................ 9

1.3.3 Pin Functions........................................................................................................ 14

Section 2 CPU..................................................................................................................... 21

2.1 Overview............................................................................................................................ 21

2.1.1 Features................................................................................................................. 21

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU................................... 22

2.1.3 Differences from H8/300 CPU ............................................................................. 23

2.1.4 Differences from H8/300H CPU.......................................................................... 23

2.2 CPU Operating Modes....................................................................................................... 24

2.3 Address Space.................................................................................................................... 29

2.4 Register Configuration.......................................................................................................30

2.4.1 Overview............................................................................................................... 30

2.4.2 General Registers.................................................................................................. 31

2.4.3 Control Registers.................................................................................................. 32

2.4.4 Initial Register Values .......................................................................................... 34

2.5 Data Formats...................................................................................................................... 35

2.5.1 General Register Data Formats............................................................................. 35

2.5.2 Memory Data Formats.......................................................................................... 37

2.6 Instruction Set.................................................................................................................... 38

2.6.1 Overview............................................................................................................... 38

2.6.2 Instructions and Addressing Modes...................................................................... 39

2.6.3 Table of Instructions Classified by Function....................................................... 41

2.6.4 Basic Instruction Formats..................................................................................... 48

2.7 Addressing Modes and Effective Address Calculation...................................................... 50

2.7.1 Addressing Mode.................................................................................................. 50

2.7.2 Effective Address Calculation.............................................................................. 53

2.8 Processing States................................................................................................................ 57

2.8.1 Overview............................................................................................................... 57

2.8.2 Reset State ............................................................................................................ 58

2.8.3 Exception-Handling State..................................................................................... 59

2.8.4 Program Execution State ...................................................................................... 62

2.8.5 Bus-Released State................................................................................................ 62

2.8.6 Power-Down State................................................................................................ 62

2.9 Basic Timing...................................................................................................................... 63

i

2.9.1 Overview............................................................................................................... 63

2.9.2 On-Chip Memory (ROM, RAM).......................................................................... 63

2.9.3 On-Chip Supporting Module Access Timing....................................................... 65

2.9.4 External Address Space Access Timing............................................................... 66

2.10 Usage Note......................................................................................................................... 66

2.10.1 TAS Instruction .................................................................................................... 66

Section 3 MCU Operating Modes................................................................................. 67

3.1 Overview............................................................................................................................ 67

3.1.1 Operating Mode Selection.................................................................................... 67

3.1.2 Register Configuration.......................................................................................... 68

3.2 Register Descriptions......................................................................................................... 68

3.2.1 Mode Control Register (MDCR).......................................................................... 68

3.2.2 System Control Register (SYSCR)....................................................................... 69

3.2.3 Pin Function Control Register (PFCR)................................................................. 71

3.3 Operating Mode Descriptions............................................................................................ 74

3.3.1 Mode 4.................................................................................................................. 74

3.3.2 Mode 5 ................................................................................................................. 74

3.3.3 Mode 6.................................................................................................................. 74

3.3.4 Mode 7.................................................................................................................. 74

3.4 Pin Functions in Each Operating Mode............................................................................. 75

3.5 Address Map in Each Operating Mode.............................................................................. 75

Section 4 Exception Handling........................................................................................ 79

4.1 Overview............................................................................................................................ 79

4.1.1 Exception Handling Types and Priority................................................................ 79

4.1.2 Exception Handling Operation ............................................................................. 80

4.1.3 Exception Vector Table........................................................................................ 80

4.2 Reset................................................................................................................................... 82

4.2.1 Overview............................................................................................................... 82

4.2.2 Types of Reset ...................................................................................................... 82

4.2.3 Reset Sequence ..................................................................................................... 83

4.2.4 Interrupts after Reset............................................................................................. 85

4.2.5 State of On-Chip Supporting Modules after Reset Release.................................. 85

4.3 Traces................................................................................................................................. 86

4.4 Interrupts............................................................................................................................ 87

4.5 Trap Instruction.................................................................................................................. 88

4.6 Stack Status after Exception Handling.............................................................................. 89

4.7 Notes on Use of the Stack.................................................................................................. 90

Section 5 Interrupt Controller......................................................................................... 91

5.1 Overview............................................................................................................................ 91

5.1.1 Features................................................................................................................. 91

5.1.2 Block Diagram...................................................................................................... 92

ii

5.1.3 Pin Configuration.................................................................................................. 93

5.1.4 Register Configuration.......................................................................................... 93

5.2 Register Descriptions......................................................................................................... 94

5.2.1 System Control Register (SYSCR)....................................................................... 94

5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO) ............................. 95

5.2.3 IRQ Enable Register (IER)................................................................................... 96

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 97

5.2.5 IRQ Status Register (ISR) .................................................................................... 98

5.3 Interrupt Sources................................................................................................................ 99

5.3.1 External Interrupts................................................................................................ 99

5.3.2 Internal Interrupts.................................................................................................. 100

5.3.3 Interrupt Exception Handling Vector Table ......................................................... 100

5.4 Interrupt Operation............................................................................................................. 105

5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 105

5.4.2 Interrupt Control Mode 0...................................................................................... 108

5.4.3 Interrupt Control Mode 2...................................................................................... 110

5.4.4 Interrupt Exception Handling Sequence............................................................... 112

5.4.5 Interrupt Response Times..................................................................................... 113

5.5 Usage Notes....................................................................................................................... 114

5.5.1 Contention between Interrupt Generation and Disabling ..................................... 114

5.5.2 Instructions that Disable Interrupts....................................................................... 115

5.5.3 Times when Interrupts are Disabled .................................................................... 115

5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 116

5.6 DTC and DMAC Activation by Interrupt.......................................................................... 116

5.6.1 Overview............................................................................................................... 116

5.6.2 Block Diagram...................................................................................................... 116

5.6.3 Operation .............................................................................................................. 117

Section 6 PC Break Controller (PBC).......................................................................... 119

6.1 Overview............................................................................................................................ 119

6.1.1 Features................................................................................................................. 119

6.1.2 Block Diagram...................................................................................................... 120

6.1.3 Register Configuration.......................................................................................... 121

6.2 Register Descriptions......................................................................................................... 121

6.2.1 Break Address Register A (BARA)...................................................................... 121

6.2.2 Break Address Register B (BARB)...................................................................... 122

6.2.3 Break Control Register A (BCRA)....................................................................... 122

6.2.4 Break Control Register B (BCRB) ....................................................................... 124

6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 124

6.3 Operation............................................................................................................................ 125

6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 125

6.3.2 PC Break Interrupt Due to Data Access ............................................................... 125

6.3.3 Notes on PC Break Interrupt Handling................................................................. 126

iii

6.3.4 Operation in Transitions to Power-Down Modes................................................. 126

6.3.5 PC Break Operation in Continuous Data Transfer ............................................... 127

6.3.6 When Instruction Execution is Delayed by One State.......................................... 128

6.3.7 Additional Notes................................................................................................... 129

Section 7 Bus Controller.................................................................................................. 131

7.1 Overview............................................................................................................................ 131

7.1.1 Features................................................................................................................. 131

7.1.2 Block Diagram...................................................................................................... 133

7.1.3 Pin Configuration.................................................................................................. 134

7.1.4 Register Configuration.......................................................................................... 135

7.2 Register Descriptions......................................................................................................... 136

7.2.1 Bus Width Control Register (ABWCR) ............................................................... 136

7.2.2 Access State Control Register (ASTCR).............................................................. 137

7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 138

7.2.4 Bus Control Register H (BCRH).......................................................................... 142

7.2.5 Bus Control Register L (BCRL)........................................................................... 144

7.2.6 Pin Function Control Register (PFCR)................................................................. 146

7.2.7 Memory Control Register (MCR) ........................................................................ 149

7.2.8 DRAM Control Register (DRAMCR).................................................................. 151

7.2.9 Refresh Timer Counter (RTCNT) ........................................................................ 153

7.2.10 Refresh Time Constant Register (RTCOR).......................................................... 153

7.3 Overview of Bus Control................................................................................................... 154

7.3.1 Area Partitioning................................................................................................... 154

7.3.2 Bus Specifications ................................................................................................ 155

7.3.3 Memory Interfaces................................................................................................ 156

7.3.4 Interface Specifications for Each Area................................................................. 157

7.3.5 Chip Select Signals............................................................................................... 158

7.4 Basic Bus Interface............................................................................................................ 159

7.4.1 Overview............................................................................................................... 159

7.4.2 Data Size and Data Alignment.............................................................................. 159

7.4.3 Valid Strobes ........................................................................................................ 161

7.4.4 Basic Timing......................................................................................................... 162

7.4.5 Wait Control.......................................................................................................... 170

7.5 DRAM Interface................................................................................................................ 172

7.5.1 Overview............................................................................................................... 172

7.5.2 Setting up DRAM Space ...................................................................................... 172

7.5.3 Address Multiplexing............................................................................................ 173

7.5.4 Data Bus................................................................................................................ 173

7.5.5 DRAM Interface Pins ........................................................................................... 174

7.5.6 Basic Timing......................................................................................................... 174

7.5.7 Precharge State Control........................................................................................ 176

7.5.8 Wait Control.......................................................................................................... 177

iv

7.5.9 Byte Access Control ............................................................................................. 179

7.5.10 Burst Operation..................................................................................................... 181

7.5.11 Refresh Control..................................................................................................... 185

7.6 DMAC Single Address Mode and DRAM Interface......................................................... 189

7.6.1 DDS=1.................................................................................................................. 189

7.6.2 DDS=0.................................................................................................................. 190

7.7 Burst ROM Interface.......................................................................................................... 191

7.7.1 Overview............................................................................................................... 191

7.7.2 Basic Timing......................................................................................................... 191

7.7.3 Wait Control.......................................................................................................... 193

7.8 Idle Cycle........................................................................................................................... 194

7.8.1 Operation .............................................................................................................. 194

7.8.2 Pin States in Idle Cycle......................................................................................... 198

7.9 Write Data Buffer Function............................................................................................... 199

7.10 Bus Release........................................................................................................................ 200

7.10.1 Overview............................................................................................................... 200

7.10.2 Operation .............................................................................................................. 200

7.10.3 Pin States in External Bus Released State............................................................ 201

7.10.4 Transition Timing ................................................................................................. 202

7.10.5 Notes..................................................................................................................... 203

7.11 Bus Arbitration................................................................................................................... 204

7.11.1 Overview............................................................................................................... 204

7.11.2 Operation .............................................................................................................. 204

7.11.3 Bus Transfer Timing............................................................................................. 205

7.12 Resets and the Bus Controller............................................................................................ 205

Section 8 DMA Controller.............................................................................................. 207

8.1 Overview............................................................................................................................ 207

8.1.1 Features................................................................................................................. 207

8.1.2 Block Diagram...................................................................................................... 208

8.1.3 Overview of Functions.......................................................................................... 209

8.1.4 Pin Configuration.................................................................................................. 211

8.1.5 Register Configuration.......................................................................................... 212

8.2 Register Descriptions (1) (Short Address Mode)............................................................... 213

8.2.1 Memory Address Registers (MAR)...................................................................... 214

8.2.2 I/O Address Register (IOAR) ............................................................................... 215

8.2.3 Execute Transfer Count Register (ETCR)............................................................ 215

8.2.4 DMA Control Register (DMACR) ....................................................................... 216

8.2.5 DMA Band Control Register (DMABCR)........................................................... 220

8.3 Register Descriptions (2) (Full Address Mode)................................................................. 225

8.3.1 Memory Address Register (MAR)........................................................................ 225

8.3.2 I/O Address Register (IOAR) ............................................................................... 225

8.3.3 Execute Transfer Count Register (ETCR)............................................................ 226

v

8.3.4 DMA Control Register (DMACR) ....................................................................... 227

8.3.5 DMA Band Control Register (DMABCR)........................................................... 231

8.4 Register Descriptions (3) ................................................................................................... 236

8.4.1 DMA Write Enable Register (DMAWER)........................................................... 236

8.4.2 DMA Terminal Control Register (DMATCR)..................................................... 238

8.4.3 Module Stop Control Register (MSTPCR)........................................................... 239

8.5 Operation............................................................................................................................ 240

8.5.1 Transfer Modes..................................................................................................... 240

8.5.2 Sequential Mode ................................................................................................... 242

8.5.3 Idle Mode.............................................................................................................. 245

8.5.4 Repeat Mode......................................................................................................... 248

8.5.5 Single Address Mode............................................................................................ 252

8.5.6 Normal Mode........................................................................................................ 255

8.5.7 Block Transfer Mode............................................................................................ 258

8.5.8 DMAC Activation Sources................................................................................... 264

8.5.9 Basic DMAC Bus Cycles...................................................................................... 267

8.5.10 DMAC Bus Cycles (Dual Address Mode)............................................................ 268

8.5.11 DMAC Bus Cycles (Single Address Mode)......................................................... 276

8.5.12 Write Data Buffer Function.................................................................................. 282

8.5.13 DMAC Multi-Channel Operation......................................................................... 283

8.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC,

and the DMAC...................................................................................................... 285

8.5.15 NMI Interrupts and DMAC.................................................................................. 286

8.5.16 Forced Termination of DMAC Operation............................................................ 287

8.5.17 Clearing Full Address Mode................................................................................. 288

8.6 Interrupts............................................................................................................................ 289

8.7 Usage Notes....................................................................................................................... 290

Section 9 Data Transfer Controller (DTC)................................................................. 295

9.1 Overview............................................................................................................................ 295

9.1.1 Features................................................................................................................. 295

9.1.2 Block Diagram...................................................................................................... 296

9.1.3 Register Configuration.......................................................................................... 297

9.2 Register Descriptions......................................................................................................... 298

9.2.1 DTC Mode Register A (MRA)............................................................................. 298

9.2.2 DTC Mode Register B (MRB).............................................................................. 300

9.2.3 DTC Source Address Register (SAR) .................................................................. 301

9.2.4 DTC Destination Address Register (DAR) .......................................................... 301

9.2.5 DTC Transfer Count Register A (CRA)............................................................... 301

9.2.6 DTC Transfer Count Register B (CRB)................................................................ 302

9.2.7 DTC Enable Registers (DTCER).......................................................................... 302

9.2.8 DTC Vector Register (DTVECR) ........................................................................ 303

9.2.9 Module Stop Control Register A (MSTPCRA).................................................... 304

vi

9.3 Operation............................................................................................................................ 305

9.3.1 Overview............................................................................................................... 305

9.3.2 Activation Sources................................................................................................ 307

9.3.3 DTC Vector Table ................................................................................................ 308

9.3.4 Location of Register Information in Address Space............................................. 312

9.3.5 Normal Mode........................................................................................................ 313

9.3.6 Repeat Mode......................................................................................................... 314

9.3.7 Block Transfer Mode............................................................................................ 315

9.3.8 Chain Transfer...................................................................................................... 317

9.3.9 Operation Timing.................................................................................................. 318

9.3.10 Number of DTC Execution States........................................................................ 319

9.3.11 Procedures for Using DTC.................................................................................... 321

9.3.12 Examples of Use of the DTC................................................................................ 322

9.4 Interrupts............................................................................................................................ 325

9.5 Usage Notes........................................................................................................................ 325

Section 10 I/O Ports............................................................................................................. 327

10.1 Overview............................................................................................................................ 327

10.2 Port 1.................................................................................................................................. 332

10.2.1 Overview............................................................................................................... 332

10.2.2 Register Configuration.......................................................................................... 333

10.2.3 Pin Functions........................................................................................................ 335

10.3 Port 3.................................................................................................................................. 347

10.3.1 Overview............................................................................................................... 347

10.3.2 Register Configuration.......................................................................................... 347

10.3.3 Pin Functions........................................................................................................ 350

10.4 Port 4.................................................................................................................................. 353

10.4.1 Overview............................................................................................................... 353

10.4.2 Register Configuration.......................................................................................... 354

10.4.3 Pin Functions........................................................................................................ 354

10.5 Port 7.................................................................................................................................. 355

10.5.1 Overview............................................................................................................... 355

10.5.2 Register Configuration.......................................................................................... 356

10.5.3 Pin Functions........................................................................................................ 358

10.6 Port 9.................................................................................................................................. 361

10.6.1 Overview............................................................................................................... 361

10.6.2 Register Configuration.......................................................................................... 362

10.6.3 Pin Functions........................................................................................................ 362

10.7 Port A................................................................................................................................. 363

10.7.1 Overview............................................................................................................... 363

10.7.2 Register Configuration.......................................................................................... 364

10.7.3 Pin Functions........................................................................................................ 367

10.7.4 MOS Input Pull-Up Function................................................................................ 367

vii

10.8 Port B ................................................................................................................................. 369

10.8.1 Overview............................................................................................................... 369

10.8.2 Register Configuration.......................................................................................... 370

10.8.3 Pin Functions........................................................................................................ 373

10.8.4 MOS Input Pull-Up Function................................................................................ 374

10.9 Port C ................................................................................................................................. 375

10.9.1 Overview............................................................................................................... 375

10.9.2 Register Configuration.......................................................................................... 376

10.9.3 Pin Functions for Each Mode ............................................................................... 379

10.9.4 MOS Input Pull-Up Function................................................................................ 381

10.10 Port D ................................................................................................................................. 382

10.10.1 Overview............................................................................................................... 382

10.10.2 Register Configuration.......................................................................................... 383

10.10.3 Pin Functions........................................................................................................ 385

10.10.4 MOS Input Pull-Up Function................................................................................ 386

10.11 Port E.................................................................................................................................. 387

10.11.1 Overview............................................................................................................... 387

10.11.2 Register Configuration.......................................................................................... 388

10.11.3 Pin Functions........................................................................................................ 390

10.11.4 MOS Input Pull-Up Function................................................................................ 391

10.12 Port F.................................................................................................................................. 392

10.12.1 Overview............................................................................................................... 392

10.12.2 Register Configuration.......................................................................................... 393

10.12.3 Pin Functions........................................................................................................ 395

10.13 Port G ................................................................................................................................. 397

10.13.1 Overview............................................................................................................... 397

10.13.2 Register Configuration.......................................................................................... 398

10.13.3 Pin Functions........................................................................................................ 400

Section 11 16-Bit Timer Pulse Unit (TPU) .................................................................. 403

11.1 Overview............................................................................................................................ 403

11.1.1 Features................................................................................................................. 403

11.1.2 Block Diagram...................................................................................................... 407

11.1.3 Pin Configuration.................................................................................................. 408

11.1.4 Register Configuration.......................................................................................... 410

11.2 Register Descriptions......................................................................................................... 412

11.2.1 Timer Control Register (TCR).............................................................................. 412

11.2.2 Timer Mode Register (TMDR)............................................................................. 417

11.2.3 Timer I/O Control Register (TIOR)...................................................................... 419

11.2.4 Timer Interrupt Enable Register (TIER)............................................................... 432

11.2.5 Timer Status Register (TSR) ................................................................................ 435

11.2.6 Timer Counter (TCNT)......................................................................................... 439

11.2.7 Timer General Register (TGR)............................................................................. 440

viii

11.2.8 Timer Start Register (TSTR)................................................................................ 441

11.2.9 Timer Synchro Register (TSYR).......................................................................... 442

11.2.10 Module Stop Control Register A (MSTPCRA).................................................... 443

11.3 Interface to Bus Master...................................................................................................... 444

11.3.1 16-Bit Registers.................................................................................................... 444

11.3.2 8-Bit Registers...................................................................................................... 444

11.4 Operation............................................................................................................................ 446

11.4.1 Overview............................................................................................................... 446

11.4.2 Basic Functions..................................................................................................... 447

11.4.3 Synchronous Operation ........................................................................................ 453

11.4.4 Buffer Operation................................................................................................... 455

11.4.5 Cascaded Operation.............................................................................................. 459

11.4.6 PWM Modes......................................................................................................... 461

11.4.7 Phase Counting Mode........................................................................................... 466

11.5 Interrupts............................................................................................................................ 473

11.5.1 Interrupt Sources and Priorities............................................................................ 473

11.5.2 DTC/DMAC Activation........................................................................................ 475

11.5.3 A/D Converter Activation..................................................................................... 475

11.6 Operation Timing............................................................................................................... 476

11.6.1 Input/Output Timing............................................................................................. 476

11.6.2 Interrupt Signal Timing ........................................................................................ 480

11.7 Usage Notes ....................................................................................................................... 484

Section 12 Programmable Pulse Generator (PPG)..................................................... 495

12.1 Overview............................................................................................................................ 495

12.1.1 Features................................................................................................................. 495

12.1.2 Block Diagram...................................................................................................... 496

12.1.3 Pin Configuration.................................................................................................. 497

12.1.4 Registers................................................................................................................ 498

12.2 Register Descriptions......................................................................................................... 499

12.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 499

12.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 500

12.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 501

12.2.4 Notes on NDR Access.......................................................................................... 501

12.2.5 PPG Output Control Register (PCR).................................................................... 503

12.2.6 PPG Output Mode Register (PMR)...................................................................... 505

12.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 508

12.2.8 Module Stop Control Register A (MSTPCRA).................................................... 508

12.3 Operation............................................................................................................................ 509

12.3.1 Overview............................................................................................................... 509

12.3.2 Output Timing ...................................................................................................... 510

12.3.3 Normal Pulse Output ............................................................................................ 511

12.3.4 Non-Overlapping Pulse Output ............................................................................ 513

ix

12.3.5 Inverted Pulse Output ........................................................................................... 516

12.3.6 Pulse Output Triggered by Input Capture............................................................. 517

12.4 Usage Notes ...................................................................................................................... 518

Section 13 8-Bit Timers (TMR)....................................................................................... 521

13.1 Overview............................................................................................................................ 521

13.1.1 Features................................................................................................................. 521

13.1.2 Block Diagram...................................................................................................... 522

13.1.3 Pin Configuration.................................................................................................. 523

13.1.4 Register Configuration.......................................................................................... 524

13.2 Register Descriptions......................................................................................................... 525

13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3).......................................................... 525

13.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3)............................... 525

13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3)................................ 526

13.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3)................................................. 526

13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3).................................. 529

13.2.6 Module Stop Control Register A (MSTPCRA).................................................... 532

13.3 Operation............................................................................................................................ 533

13.3.1 TCNT Incrementation Timing.............................................................................. 533

13.3.2 Compare Match Timing........................................................................................ 534

13.3.3 Timing of External RESET on TCNT.................................................................. 536

13.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 536

13.3.5 Operation with Cascaded Connection .................................................................. 537

13.4 Interrupts............................................................................................................................ 538

13.4.1 Interrupt Sources and DTC Activation................................................................. 538

13.4.2 A/D Converter Activation..................................................................................... 538

13.5 Sample Application............................................................................................................ 539

13.6 Usage Notes ....................................................................................................................... 540

13.6.1 Contention between TCNT Write and Clear........................................................ 540

13.6.2 Contention between TCNT Write and Increment................................................. 541

13.6.3 Contention between TCOR Write and Compare Match....................................... 542

13.6.4 Contention between Compare Matches A and B.................................................. 543

13.6.5 Switching of Internal Clocks and TCNT Operation............................................ 543

13.6.6 Interrupts and Module Stop Mode........................................................................ 545

Section 14 14-Bit PWM D/A............................................................................................ 547

14.1 Overview............................................................................................................................ 547

14.1.1 Features................................................................................................................. 547

14.1.2 Block Diagram...................................................................................................... 548

14.1.3 Pin Configuration.................................................................................................. 549

14.1.4 Register Configuration.......................................................................................... 549

14.2 Register Descriptions......................................................................................................... 550

14.2.1 PWM D/A Counter (DACNT).............................................................................. 550

x

14.2.2 PWM D/A Data Registers A and B (DADRA and DADRB) .............................. 551

14.2.3 PWM D/A Control Register (DACR)................................................................... 552

14.2.4 Module Stop Control Register B (MSTPCRB).................................................... 554

14.3 Bus Master Interface.......................................................................................................... 555

14.4 Operation............................................................................................................................ 558

Section 15 Watchdog Timer.............................................................................................. 563

15.1 Overview............................................................................................................................ 563

15.1.1 Features................................................................................................................. 563

15.1.2 Block Diagram...................................................................................................... 564

15.1.3 Pin Configuration.................................................................................................. 566

15.1.4 Register Configuration.......................................................................................... 566

15.2 Register Descriptions......................................................................................................... 567

15.2.1 Timer Counter (TCNT)......................................................................................... 567

15.2.2 Timer Control/Status Register (TCSR) ................................................................ 567

15.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 572

15.2.4 Pin Function Control Register (PFCR)................................................................. 573

15.2.5 Notes on Register Access ..................................................................................... 574

15.3 Operation............................................................................................................................ 576

15.3.1 Watchdog Timer Operation.................................................................................. 576

15.3.2 Interval Timer Operation...................................................................................... 578

15.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 578

15.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 579

15.4 Interrupts............................................................................................................................ 580

15.5 Usage Notes ....................................................................................................................... 580

15.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 580

15.5.2 Changing Value of CKS2 to CKS0...................................................................... 581

15.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 581

15.5.4 System Reset by WDTOVF Signal ...................................................................... 581

15.5.5 Internal Reset in Watchdog Timer Mode.............................................................. 581

Section 16 Serial Communication Interface (SCI, IrDA) ........................................ 583

16.1 Overview............................................................................................................................ 583

16.1.1 Features................................................................................................................. 583

16.1.2 Block Diagram...................................................................................................... 586

16.1.3 Pin Configuration.................................................................................................. 586

16.1.4 Register Configuration.......................................................................................... 587

16.2 Register Descriptions......................................................................................................... 589

16.2.1 Receive Shift Register (RSR) ............................................................................... 589

16.2.2 Receive Data Register (RDR)............................................................................... 589

16.2.3 Transmit Shift Register (TSR).............................................................................. 590

16.2.4 Transmit Data Register (TDR).............................................................................. 590

16.2.5 Serial Mode Register (SMR)................................................................................ 591

xi

16.2.6 Serial Control Register (SCR).............................................................................. 594

16.2.7 Serial Status Register (SSR) ................................................................................. 598

16.2.8 Bit Rate Register (BRR) ....................................................................................... 602

16.2.9 Smart Card Mode Register (SCMR)..................................................................... 611

16.2.10 IrDA Control Register (IrCR)............................................................................... 612

16.2.11 Module Stop Control Registers B and C (MSTPCRB, MSTPCRC).................... 613

16.3 Operation............................................................................................................................ 615

16.3.1 Overview............................................................................................................... 615

16.3.2 Operation in Asynchronous Mode........................................................................ 618

16.3.3 Multiprocessor Communication Function............................................................ 629

16.3.4 Operation in Clocked Synchronous Mode............................................................ 637

16.3.5 IrDA Operation..................................................................................................... 645

16.4 SCI Interrupts..................................................................................................................... 648

16.5 Usage Notes ....................................................................................................................... 650

Section 17 Smart Card Interface...................................................................................... 659

17.1 Overview............................................................................................................................ 659

17.1.1 Features................................................................................................................. 659

17.1.2 Block Diagram...................................................................................................... 660

17.1.3 Pin Configuration.................................................................................................. 661

17.1.4 Register Configuration.......................................................................................... 662

17.2 Register Descriptions......................................................................................................... 664

17.2.1 Smart Card Mode Register (SCMR)..................................................................... 664

17.2.2 Serial Status Register (SSR) ................................................................................. 666

17.2.3 Serial Mode Register (SMR)................................................................................ 668

17.2.4 Serial Control Register (SCR).............................................................................. 670

17.3 Operation............................................................................................................................ 671

17.3.1 Overview............................................................................................................... 671

17.3.2 Pin Connections.................................................................................................... 671

17.3.3 Data Format.......................................................................................................... 673

17.3.4 Register Settings ................................................................................................... 675

17.3.5 Clock..................................................................................................................... 677

17.3.6 Data Transfer Operations...................................................................................... 679

17.3.7 Operation in GSM Mode...................................................................................... 686

17.3.8 Operation in Block Transfer Mode....................................................................... 687

17.4 Usage Notes ....................................................................................................................... 688

Section 18 I2C Bus Interface [Option] ........................................................................... 691

18.1 Overview............................................................................................................................ 691

18.1.1 Features................................................................................................................. 691

18.1.2 Block Diagram...................................................................................................... 692

18.1.3 Input/Output Pins.................................................................................................. 694

18.1.4 Register Configuration.......................................................................................... 695

xii

18.2 Register Descriptions......................................................................................................... 696

18.2.1 I2C Bus Data Register (ICDR).............................................................................. 696

18.2.2 Slave Address Register (SAR).............................................................................. 699

18.2.3 Second Slave Address Register (SARX).............................................................. 700

18.2.4 I2C Bus Mode Register (ICMR)............................................................................ 701

18.2.5 I2C Bus Control Register (ICCR).......................................................................... 704

18.2.6 I2C Bus Status Register (ICSR)............................................................................ 711

18.2.7 Serial Control Register X (SCRX)........................................................................ 716

18.2.8 DDC Switch Register (DDCSWR)....................................................................... 717

18.2.9 Module Stop Control Register B (MSTPCRB).................................................... 718

18.3 Operation............................................................................................................................ 719

18.3.1 I2C Bus Data Format............................................................................................. 719

18.3.2 Master Transmit Operation................................................................................... 720

18.3.3 Master Receive Operation .................................................................................... 722

18.3.4 Slave Receive Operation....................................................................................... 724

18.3.5 Slave Transmit Operation..................................................................................... 726

18.3.6 IRIC Setting Timing and SCL Control................................................................. 728

18.3.7 Operation Using the DTC..................................................................................... 729

18.3.8 Noise Canceler...................................................................................................... 730

18.3.9 Sample Flowcharts................................................................................................ 730

18.3.10 Initialization of Internal State ............................................................................... 734

18.4 Usage Notes ....................................................................................................................... 736

Section 19 A/D Converter.................................................................................................. 745

19.1 Overview............................................................................................................................ 745

19.1.1 Features................................................................................................................. 745

19.1.2 Block Diagram...................................................................................................... 746

19.1.3 Pin Configuration.................................................................................................. 747

19.1.4 Register Configuration.......................................................................................... 748

19.2 Register Descriptions......................................................................................................... 749

19.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 749

19.2.2 A/D Control/Status Register (ADCSR)................................................................ 750

19.2.3 A/D Control Register (ADCR) ............................................................................. 753

19.2.4 Module Stop Control Register A (MSTPCRA).................................................... 754

19.3 Interface to Bus Master...................................................................................................... 755

19.4 Operation............................................................................................................................ 756

19.4.1 Single Mode (SCAN = 0) ..................................................................................... 756

19.4.2 Scan Mode (SCAN = 1)........................................................................................ 758

19.4.3 Input Sampling and A/D Conversion Time.......................................................... 760

19.4.4 External Trigger Input Timing.............................................................................. 761

19.5 Interrupts............................................................................................................................ 762

19.6 Usage Notes ....................................................................................................................... 762

xiii

Section 20 D/A Converter.................................................................................................. 769

20.1 Overview............................................................................................................................ 769

20.1.1 Features................................................................................................................. 769

20.1.2 Block Diagram...................................................................................................... 769

20.1.3 Input and Output Pins ........................................................................................... 771

20.1.4 Register Configuration.......................................................................................... 771

20.2 Register Descriptions......................................................................................................... 772

20.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3).................................................. 772

20.2.2 D/A Control Register 01 and 23 (DACR01 and DACR23).................................. 772

20.2.3 Module Stop Control Register A and C (MSTPCRA and MSTPCRC) ............... 774

20.3 Operation............................................................................................................................ 776

Section 21 RAM.................................................................................................................... 777

21.1 Overview............................................................................................................................ 777

21.1.1 Block Diagram...................................................................................................... 777

21.1.2 Register Configuration.......................................................................................... 778

21.2 Register Descriptions......................................................................................................... 778

21.2.1 System Control Register (SYSCR)....................................................................... 778

21.3 Operation............................................................................................................................ 779

21.4 Usage Notes ....................................................................................................................... 779

Section 22 ROM.................................................................................................................... 781

22.1 Features.............................................................................................................................. 781

22.2 Overview............................................................................................................................ 782

22.2.1 Block Diagram...................................................................................................... 782

22.2.2 Mode Transitions.................................................................................................. 783

22.2.3 On-Board Programming Modes............................................................................ 784

22.2.4 Flash Memory Emulation in RAM....................................................................... 786

22.2.5 Differences between Boot Mode and User Program Mode.................................. 787

22.2.6 Block Configuration.............................................................................................. 788

22.3 Pin Configuration............................................................................................................... 788

22.4 Register Configuration....................................................................................................... 789

22.5 Register Descriptions......................................................................................................... 789

22.5.1 Flash Memory Control Register 1 (FLMCR1) ..................................................... 789

22.5.2 Flash Memory Control Register 2 (FLMCR2) ..................................................... 792

22.5.3 Erase Block Register 1 (EBR1)............................................................................ 793

22.5.4 Erase Block Register 2 (EBR2)............................................................................ 794

22.5.5 RAM Emulation Register (RAMER).................................................................... 795

22.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 797

22.5.7 Serial Control Register X (SCRX)........................................................................ 797

22.6 On-Board Programming Modes......................................................................................... 798

22.6.1 Boot Mode............................................................................................................ 798

xiv

22.6.2 User Program Mode.............................................................................................. 803

22.7 Programming/Erasing Flash Memory................................................................................ 805

22.7.1 Program Mode...................................................................................................... 806

22.7.2 Program-Verify Mode .......................................................................................... 807

22.7.3 Erase Mode ........................................................................................................... 811

22.7.4 Erase-Verify Mode................................................................................................ 811

22.8 Protection ........................................................................................................................... 813

22.8.1 Hardware Protection ............................................................................................. 813

22.8.2 Software Protection .............................................................................................. 814

22.8.3 Error Protection .................................................................................................... 815

22.9 Flash Memory Emulation in RAM .................................................................................... 817

22.10 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 819

22.11 Flash Memory Programmer Mode..................................................................................... 819

22.11.1 Socket Adapter Pin Correspondence Diagram ..................................................... 820

22.11.2 Programmer Mode Operation ............................................................................... 822

22.11.3 Memory Read Mode ............................................................................................. 823

22.11.4 Auto-Program Mode ............................................................................................. 826

22.11.5 Auto-Erase Mode.................................................................................................. 828

22.11.6 Status Read Mode ................................................................................................. 830

22.11.7 Status Polling ........................................................................................................ 831

22.11.8 Programmer Mode Transition Time ..................................................................... 831

22.11.9 Notes on Memory Programming .......................................................................... 832

22.12 Flash Memory and Power-Down States ............................................................................ 833

22.12.1 Note on Power-Down States................................................................................. 833

22.13 Flash Memory Programming and Erasing Precautions...................................................... 834

22.14 Note on Switching from F-ZTAT Version to Mask ROM Version................................... 839

Section 23 Clock Pulse Generator................................................................................... 841

23.1 Overview............................................................................................................................ 841

23.1.1 Block Diagram...................................................................................................... 841

23.1.2 Register Configuration.......................................................................................... 842

23.2 Register Descriptions......................................................................................................... 842

23.2.1 System Clock Control Register (SCKCR)............................................................ 842

23.2.2 Low-Power Control Register (LPWRCR)............................................................ 843

23.3 Oscillator............................................................................................................................ 844

23.3.1 Connecting a Crystal Resonator............................................................................ 844

23.3.2 External Clock Input............................................................................................. 847

23.4 PLL Circuit ........................................................................................................................ 849

23.5 Medium-Speed Clock Divider ........................................................................................... 849

23.6 Bus Master Clock Selection Circuit................................................................................... 849

23.7 Subclock Oscillator............................................................................................................ 850

23.8 Subclock Waveform Shaping Circuit ................................................................................ 851

23.9 Note on Crystal Resonator................................................................................................. 851

xv

Section 24 Power-Down Modes ...................................................................................... 853

24.1 Overview............................................................................................................................ 853

24.1.1 Register Configuration.......................................................................................... 857

24.2 Register Descriptions......................................................................................................... 858

24.2.1 Standby Control Register (SBYCR)..................................................................... 858

24.2.2 System Clock Control Register (SCKCR)............................................................ 860

24.2.3 Low-Power Control Register (LPWRCR)............................................................ 861

24.2.4 Timer Control/Status Register (TCSR) ................................................................ 864

24.2.5 Module Stop Control Register (MSTPCR)........................................................... 865

24.3 Medium-Speed Mode......................................................................................................... 866

24.4 Sleep Mode ........................................................................................................................ 867

24.4.1 Sleep Mode ........................................................................................................... 867

24.4.2 Exiting Sleep Mode .............................................................................................. 867

24.5 Module Stop Mode ............................................................................................................ 868

24.5.1 Module Stop Mode ............................................................................................... 868

24.5.2 Usage Notes.......................................................................................................... 870

24.6 Software Standby Mode..................................................................................................... 870

24.6.1 Software Standby Mode........................................................................................ 870

24.6.2 Clearing Software Standby Mode......................................................................... 870

24.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode... 871

24.6.4 Software Standby Mode Application Example .................................................... 872

24.6.5 Usage Notes.......................................................................................................... 873

24.7 Hardware Standby Mode ................................................................................................... 873

24.7.1 Hardware Standby Mode...................................................................................... 873

24.7.2 Hardware Standby Mode Timing.......................................................................... 874

24.8 Watch Mode....................................................................................................................... 874

24.8.1 Watch Mode.......................................................................................................... 874

24.8.2 Exiting Watch Mode............................................................................................. 875

24.8.3 Notes..................................................................................................................... 875

24.9 Sub-Sleep Mode................................................................................................................. 876

24.9.1 Sub-Sleep Mode.................................................................................................... 876

24.9.2 Exiting Sub-Sleep Mode....................................................................................... 876

24.10 Sub-Active Mode ............................................................................................................... 877

24.10.1 Sub-Active Mode.................................................................................................. 877

24.10.2 Exiting Sub-Active Mode..................................................................................... 877

24.11 Direct Transitions............................................................................................................... 878

24.11.1 Overview of Direct Transitions............................................................................ 878

24.12 ø Clock Output Disabling Function ................................................................................... 878

Section 25 Electrical Characteristics.............................................................................. 879

25.1 Absolute Maximum Ratings.............................................................................................. 879

25.2 DC Characteristics ............................................................................................................. 880

25.3 AC Characteristics ............................................................................................................. 888

xvi

25.3.1 Clock Timing........................................................................................................ 889

25.3.2 Control Signal Timing.......................................................................................... 891

25.3.3 Bus Timing ........................................................................................................... 893

25.3.4 DMAC Timing...................................................................................................... 902

25.3.5 Timing of On-Chip Supporting Modules.............................................................. 906

25.4 A/D Conversion Characteristics ........................................................................................ 914

25.5 D/A Conversion Characteristics ........................................................................................ 915

25.6 Flash Memory Characteristics ........................................................................................... 916

25.7 Usage Note......................................................................................................................... 917

Appendix A Instruction Set............................................................................................... 919

A.1 Instruction List................................................................................................................... 919

A.2 Instruction Codes ............................................................................................................... 943

A.3 Operation Code Map.......................................................................................................... 958

A.4 Number of States Required for Instruction Execution....................................................... 962

A.5 Bus States During Instruction Execution........................................................................... 976

A.6 Condition Code Modification............................................................................................ 990

Appendix B Internal I/O Register.................................................................................... 996

B.1 Addresses ........................................................................................................................... 996

B.2 Functions.......................................................................................................................... 1006

Appendix C I/O Port Block Diagrams ......................................................................... 1104

C.1 Port 1 Block Diagram ...................................................................................................... 1104

C.2 Port 3 Block Diagram ...................................................................................................... 1110

C.3 Port 4 Block Diagram ...................................................................................................... 1118

C.4 Port 7 Block Diagram ...................................................................................................... 1119

C.5 Port 9 Block Diagram ...................................................................................................... 1126

C.6 Port A Block Diagram...................................................................................................... 1127

C.7 Port B Block Diagram...................................................................................................... 1131

C.8 Port C Block Diagram...................................................................................................... 1132

C.9 Port D Block Diagram...................................................................................................... 1134

C.10 Port E Block Diagram...................................................................................................... 1135

C.11 Port E Block Diagram...................................................................................................... 1136

C.12 Port G Block Diagram...................................................................................................... 1144

Appendix D Pin States...................................................................................................... 1148

D.1 Port States in Each Mode................................................................................................. 1148

Appendix E Timing of Transition to and Recovery from

Hardware Standby Mode

Appendix F Product Code Lineup................................................................................. 1153

............................................................................ 1152

xvii

Appendix G Package Dimensions................................................................................. 1154

xviii

Section 1 Overview

1.1 Overview

The H8S/2633 Series is a series of microcomputers (MCUs: microcomputer units), built around
the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral
functions on-chip.

The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include DMA controller (DMAC),
data transfer controller (DTC) bus masters, ROM and RAM memory, a16-bit timer-pulse unit
(TPU), programmable pulse generator (PPG), 8-bit timer, 14-bit PWM timer (PWM) watchdog
timer (WDT), serial communication interface (SCI, IrDA), A/D converter, D/A converter, and I/O
ports. It is also possible to incorporate an on-chip PC bus interface (IIC) as an option.

On-chip ROM is available as 256-kbyte flash memory (F-ZTAT™ version)* or as 256-, 128-, or
64-kbyte mask ROM. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and
word data to be accessed in one state. Instruction fetching has been speeded up, and processing
speed increased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or
external expansion mode.

The features of the H8S/2633 Series are shown in table 1-1.

Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.

1

Table 1-1 Overview

Item Specification

CPU

• General-register machine
 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers

or eight 32-bit registers)

• High-speed operation suitable for realtime control
 Maximum clock rate: 25 MHz
 High-speed arithmetic operations

8/16/32-bit register-register add/subtract : 40 ns
16 × 16-bit register-register multiply : 160 ns
16 × 16 + 42-bit multiply and accumulate : 160 ns
32 ÷ 16-bit register-register divide : 800 ns

• Instruction set suitable for high-speed operation
 Sixty-nine basic instructions
 8/16/32-bit move/arithmetic and logic instructions
 Unsigned/signed multiply and divide instructions
 Multiply-and accumulate instruction
 Powerful bit-manipulation instructions

• Two CPU operating modes
 Normal mode: 64-kbyte address space

(cannot be used in the H8S/2633 Series)

 Advanced mode: 16-Mbyte address space

Bus controller

PC break controller

DMA controller
(DMAC)

• Address space divided into 8 areas, with bus specifications settable
independently for each area

• Choice of 8-bit or 16-bit access space for each area

• 2-state or 3-state access space can be designated for each area

• Number of program wait states can be set for each area

• Burst ROM directly connectable

• Possible to connect a maximum of 8 MB of DRAM (alternatively, it is also

possible to use an interval timer)

• External bus release function

• Supports debugging functions by means of PC break interrupts

• Two break channels

• Short address mode and full address mode selectable

• Short address mode: 4 channels

Full address mode: 2 channels

• Transfer possible in repeat mode/block transfer mode
Transfer possible in single address mode

• Activation by internal interrupt possible

2

Item Specification

Data transfer
controller (DTC)

16-bit timer-pulse
unit (TPU)

Programmable
pulse generator
(PPG)

8-bit timer 4
channels

Watchdog timer
2 channels

• Can be activated by internal interrupt or software

• Multiple transfers or multiple types of transfer possible for one activation

source

• Transfer possible in repeat mode, block transfer mode, etc.

• Request can be sent to CPU for interrupt that activated DTC

• 6-channel 16-bit timer on-chip

• Pulse I/O processing capability for up to 16 pins'

• Automatic 2-phase encoder count capability

• Maximum 16-bit pulse output possible with TPU as time base

• Output trigger selectable in 4-bit groups

• Non-overlap margin can be set

• Direct output or inverse output setting possible

• 8-bit up counter (external event count possible)

• Time constant register × 2

• 2 channel connection possible

• Watchdog timer or interval timer selectable

• Operation using sub-clock supported (WDT1 only)

14-bit PWM timer
(PWM)

Serial
communication
interface (SCI)
5 channels
(SCI0 to SCI4)

IrDA-equipped SCI 1
channel (SCI0)

• Maximum of 4 outputs

• Resolution: 1/16384

• Maximum carrier frequency: 390.6 kHz (operating at 25 MHz)

• Asynchronous mode or synchronous mode selectable

• Multiprocessor communication function

• Smart card interface function

• Supports IrDA standard version 1.0

• TxD and RxD encoding/decoding in IrDA format

• Start/stop synchronization mode or clock synchronization mode selectable

• Multiprocessor communications function

• Smart card interface function

3

Item Specification

A/D converter

D/A converter

I/O ports
Memory

• Resolution: 10 bits

• Input: 16 channels

• High-speed conversion: 10.72 µs minimum conversion time

(at 25 MHz operation)

• Single or scan mode selectable

• Sample and hold circuit

• A/D conversion can be activated by external trigger or timer trigger

• Resolution: 8 bits

• Output: 4 channels

• 73 I/O pins, 16 input-only pins

• PROM or mask ROM

• High-speed static RAM

Product Name ROM RAM

H8S/2633 256 kbytes 16 kbytes
H8S/2632 192 kbytes 12 kbytes
H8S/2631 128 kbytes 8 kbytes

Interrupt controller

Power-down state

• Nine external interrupt pins (NMI, IRQ0 to IRQ7)

• 72 internal interrupt sources (including options)

• Eight priority levels settable

• Medium-speed mode

• Sleep mode

• Module stop mode

• Software standby mode

• Hardware standby mode

• Sub-clock operation (sub-active mode, sub-sleep mode, watch mode)

4

Item Specification

Operating modes Four MCU operating modes

Clock pulse
generator

Packages

I2C bus interface
(IIC) 2 channels
(optional)

CPU
Operating

Mode

Mode Description

4 Advanced On-chip ROM disabled

On-Chip
ROM

Disabled 16 bits 16 bits

External Data Bus

Initial
Value

Maximum
Value

expansion mode

5 On-chip ROM disabled

Disabled 8 bits 16 bits

expansion mode

6 On-chip ROM enabled

Enabled 8 bits 16 bits

expansion mode

7 Single-chip mode Enabled — —

• On-chip PLL circuit (×1, ×2, ×4)

• Input clock frequency: 2 to 25 MHz

• 120-pin plastic TQFP (TFP-120)

• 128-pin plastic QFP (FP-128)

• Conforms to I

2

C bus interface type advocated by Philips

• Single master mode/slave mode

• Possible to determine arbitration lost conditions

• Supports two slave addresses

Product lineup Model Name

Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Packages

HD6432633* HD64F2633 256 k/16 k TFP-120

HD6432632* — 192 k/12 k TFP-120

HD6432631* — 128 k/8 k TFP-120

Note: *In the planning stage.

FP-128

FP-128

FP-128

5

1.2 Internal Block Diagram

Figure 1-1 shows an internal block diagram.

MD2
MD1
MD0
OSC2
OSC1
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS

STBY
RES
WDTOVF

NMI

2

FWE*

PF7/ø
PF6/AS/LCAS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/LCAS /WAIT /BREQO
PF1/BACK/BUZZ
PF0/BREQ/IRQ2

PG4/CS0
PG3/CS1
PG2/CS2
PG1/CS3/OE/IRQ7
PG0/CAS /IRQ6

P77/TxD3
P76/RxD3
P75/TMO3/SCK3
P74/TMO2/MRES
P73/TMO1/TEND1/CS7
P72/TMO0/TEND0/CS6/SYNCI
P71/

TMR23/TMC23/DREQ1/CS5

P70/

TMR01/TMC01/DREQ0/CS4

PVCC1

Port FPort GPort 7

CC2

PV

PLL

VCC

VCC

VSS

VSS

VSS

Clock pulse

Interrupt controller

PC break controller

VSS

VSS

VSS

generator

(2 channels)

ROM

(Mask ROM,

flash memory

RAM

TPU

PPG

PD7/D15

PD6/D14

PD5/D13

Port D Port E

H8S/2600 CPU

*1

)

PE7/D7

PE6/D6

PD4/D12

PD3/D11

PD2/D10

DTC

DMAC

PD1/D9

PD0/D8

Internal data bus

PE5/D5

Internal address bus

WDT × 2 channels

8bit timer × 4 channels

SCI × 5 channels
(IrDA × 1channel)

2

I

C bus interface

(option)

14-bit PWM timer

D/A converter

A/D converter

Port 4Port 1

PE4/D4

PE3/D3

PE2/D2

PE1/D1

Bus controller

Peripheral data bus

PE0/D0

PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2

Port A

PA0/A16

PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/ A11/TIOCD3

Port B

PB2/ A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3

PC7/A7/PWM1

Peripheral address bus

PC6/A6/PWM0
PC5/A5
PC4/A4
PC3/A3

Port C

PC2/A2
PC1/A1
PC0/A0

P37/TxD4
P36/RxD4
P35/SCK1/SCK4/SCL0/

P34/RxD1/SDA0
P33/TxD1/SCL1
P32/SCK0/SDA1/IRQ4
P31/RxD0/IrRxD
P30/TxD0/IrTxD

P97/AN15/DA3
P96/AN14/DA2
P95/AN13
P94/AN12
P93/AN11

Port 9 Port 3

P92/AN10
P91/AN9
P90/AN8

IRQ5

IRQ1

P17/PO15/TIOCB2/PWM3/TCLKD

P16/PO14/TIOCA2/PWM2/

Notes: 1. Applies to the H8S/2633 only.

2. The FWE pin is used only in the flash memory version.

Figure 1-1 Internal Block Diagram

6

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/TCLKB/A23

P12/PO10/TIOCC0/TCLKA/A22

P11/PO9/TIOCB0/DACK1/A21

P10/PO8/TIOCA0/DACK0/A20

Vref

AVCC

AVSS

P47/AN7/DA1

P46/AN6/DA0

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

1.3 Pin Description

1.3.1 Pin Arrangement

Figure 1-2 shows the pin arrangement of the H8S/2633 Series.

PF0/BREQ/IRQ2

PF1/BACK/BUZZ

PF2/LCAS/WAIT/BREQO

PF3/LWR/ADTRG/IRQ3

PF4/HWR

PF5/RD

PF6/AS/LCAS

VSS

PF7/ø

PVCC1

OSC2

OSC1

VSS

EXTAL

VCC

XTAL

FWE

STBY

NMI

RES

PLLVSS

PLLCAP

PLLVCC

WDTOVF

PG4/CS0

PG3/CS1

PG2/CS2

PG1/CS3/OE/IRQ7

PG0/CAS/IRQ6

P37/TxD4

AVCC

Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5

P46/AN6/DA0
P47/AN7/DA1

P90/AN8
P91/AN9

P92/AN10
P93/AN11
P94/AN12

P95/AN13
P96/AN14/DA2
P97/AN15/DA3

AVSS
P70/TMRI01/TMCI01/DREQ0/CS4
P71/TMRI23/TMCI23/DREQ1/CS5

P72/TMO0/TEND0/CS6/SYNCI

P73/TMO1/TEND1/CS7

P74/TMO2/MRES

P75/TMO3/SCK3

P76/RxD3

P77/TxD3

MD0
MD1
MD2

9089888786858483828180797877767574737271706968676665646362

91
92
93
94
95
96
97
98

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

123456789

TOP VIEW

(TFP-120)

101112131415161718192021222324252627282930

61

60

P36/RxD4

59

P35/SCK1/SCK4/SCL0/IRQ5

58

P34/RxD1/SDA0

57

P33/TxD1/SCL1

56

VSS

55

P32/SCK0/SDA1/IRQ4

54

PVCC2

53

P31/RxD0/IrRxD

52

P30/TxD0/IrTxD

51

PD7/D15

50

PD6/D14

49

PD5/D13

48

PD4/D12

47

PD3/D11

46

PD2/D10

45

PD1/D9

44

PVCC1

43

PD0/D8

42

VSS

41

PE7/D7

40

PE6/D6

39

PE5/D5

38

PE4/D4

37

PE3/D3

36

PE2/D2

35

PE1/D1

34

PE0/D0

33

P17/PO15/TIOCB2/PWM3/TCKLD

32

P16/PO14/TIOCA2/PWM2/IRQ1

31

P15/PO13/TIOCB1/TCLKC

PC0/A0

PC1/A1

PC2/A2

Figure 1-2 Pin Arrangement (TFP-120: Top View)

VSS

PC3/A3

VCC

PC4/A4

VSS

PC5/A5

PC6/A6/PWM0

PC7/A7/PWM1

PVCC1

PB0/A8/TIOCA3

PB1/A9/TIOCB3

PB2/A10/TIOCC3

PB3/A11/TIOCD3

PA0/A16

PB4/A12/TIOCA4

PB5/A13/TIOCB4

PB6/A14/TIOCA5

PB7/A15/TIOCB5

VSS

PA1/A17/TxD2

PA2/A18/RxD2

PA3/A19/SCK2

P14/PO12/TIOCA1/IRQ0

P10/PO8/TIOCA0/DACK0/A20

P11/PO9/TIOCB0/DACK1/A21

P12/PO10/TIOCC0/TCLKA/A22

P13/PO11/TIOCD0/TCLKB/A23

7

P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4

P45/AN5
P46/AN6/DA0
P47/AN7/DA1

P90/AN8

P91/AN9

P92/AN10
P93/AN11
P94/AN12

P95/AN13
P96/AN14/DA2
P97/AN15/DA3

P70/TMRI01/TMCI01/DREQ0/CS4
P71/TMRI23/TMCI23/DREQ1/CS5

P72/TMO0/TEND0/CS6/SYNCI

P73/TMO1/TEND1/CS7

P74/TMO2/MRES

P75/TMO3/SCK3

AVSS

P76/RxD3

P77/TxD3

MD0

Vref

AVCCNCNC

PF0/BREQ/IRQ2

9998979695949392919089888786858483828180797877767574737271706968676665

102

101

100

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

123456789

NC

NC

MD1

MD2

PC0/A0

PF1/BACK/BUZZ

PF2/LCAS/WAIT/BREQO

PF3/LWR/ADTRG/IRQ3

PF4/HWR

PF5/RD

PF6/AS/LCAS

VSS

PF7/ø

1011121314151617181920212223242526272829303132333435363738

VSS

PC2/A2

PC3/A3

VCC

PC4/A4

PC5/A5

PC6/A6/PWM0

PC1/A1

PVCC1

OSC2

OSC1

VSS

EXTAL

TOP VIEW

(FP-128)

VSS

PVCC1

PC7/A7/PWM1

PB0/A8/TIOCA3

PB1/A9/TIOCB3

VCC

XTAL

FWE

STBY

NMI

RES

PB4/A12/TIOCA4

PB5/A13/TIOCB4

PB6/A14/TIOCA5

PB2/A10/TIOCC3

PB3/A11/TIOCD3

PB7/A15/TIOCB5

PLLVSS

PLLCAP

PLLVCC

WDTOVF

PA0/A16

PA1/A17/TxD2

PA2/A18/RxD2

PA3/A19/SCK2

PG4/CS0

PG3/CS1

PG2/CS2

VSS

PG1/CS3/OE/IRQ7

PG0/CAS/IRQ6

P37/TxD4NCNC

P36/RxD4

NC

NC

P35/SCK1/SCK4/SCL0/IRQ5

64

P34/RxD1/SDA0

63

P33/TxD1/SCL1

62

VSS

61

P32/SCK0/SDA1/IRQ4

60

PVCC2

59

P31/RxD0/IrRxD

58

P30/TxD0/IrTxD

57

PD7/D15

56

PD6/D14

55

PD5/D13

54

PD4/D12

53

PD3/D11

52

PD2/D10

51

PD1/D9

50

PVCC1

49

PD0/D8

48

VSS

47

PE7/D7

46

PE6/D6

45

PE5/D5

44

PE4/D4

43

PE3/D3

42

PE2/D2

41

PE1/D1

40

PE0/D0

39

P17/PO15/TIOCB2/PWM3/TCLKD

P14/PO12/TIOCA1/IRQ0

P10/PO8/TIOCA0/DACK0/A20

P11/PO9/TIOCB0/DACK1/A21

P12/PO10/TIOCC0/TCLKA/A22

P13/PO11/TIOCD0/TCLKB/A23

Figure 1-3 Pin Arrangement (FP-128: Top View)

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/PWM2/IRQ1

8

1.3.2 Pin Functions in Each Operating Mode

Table 1-2 shows the pin functions of the H8S/2633 Series in each of the operating modes.

Table 1-2 Pin Functions in Each Operating Mode

Pin No. Pin Name

TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7

1 5 A0 A0 PC0/A0 PC0
2 6 A1 A1 PC1/A1 PC1
3 7 A2 A2 PC2/A2 PC2
4 8 A3 A3 PC3/A3 PC3
5 9 VSS VSS VSS VSS
6 10 A4 A4 PC4/A4 PC4
7 11 VCC VCC VCC VCC
8 12 A5 A5 PC5/A5 PC5
9 13 A6 A6 PC6/A6/PWM0 PC6/PWM0
10 14 A7 A7 PC7/A7/PWM1 PC7/PWM1
11 15 VSS VSS VSS VSS
12 16 A8 A8 PB0/A8/TIOCA3 PB0/TIOCA3
13 17 PVCC1 PVCC1 PVCC1 PVCC1
14 18 A9 A9 PB1/A9/TIOCB3 PB1/TIOCB3
15 19 A11 A11 PB3/A11/TIOCD3 PB3/TIOCD3
17 21 A12 A12 PB4/A12/TIOCA4 PB4/TIOCA4
18 22 A13 A13 PB5/A13/TIOCB4 PB5/TIOCB4
19 23 A14 A14 PB6/A14/TIOCA5 PB6/TIOCA5
20 24 A15 A15 PB7/A15/TIOCB5 PB7/TIOCB5
21 25 A16 A16 PA0/A16 PA0
22 26 A17 A17 PA1/A17/TxD2 PA1/TxD2
23 27 A18 A18 PA2/A18/RxD2 PA2/RxD2
24 28 A19 A19 PA3/A19/SCK2 PA3/SCK2
25 29 VSS VSS VSS VSS
26 30 P10/PO8/TIOCA0/

DACK0/A20

27 31 P11/PO9/TIOCB0/

DACK1/A21

P10/PO8/TIOCA0/
DACK0/A20

P11/PO9/TIOCB0/
DACK1/A21

P10/PO8/TIOCA0/
DACK0/A20

P11/PO9/TIOCB0/
DACK1/A21

P10/PO8/TIOCA0/

DACK0

P11/PO9/TIOCB0/

DACK1

9

Pin No. Pin Name

TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7

28 32 P12/PO10/TIOCC0/

TCLKA/A22

29 33 P13/PO11/TIOCD0/

TCLKB/A23

30 34 P14/PO12/TIOCA1/

IRQ0

P12/PO10/TIOCC0/
TCLKA/A22

P13/PO11/TIOCD0/
TCLKB/A23

P14/PO12/TIOCA1/

IRQ0

P12/PO10/TIOCC0/
TCLKA/A22

P13/PO11/TIOCD0/
TCLKB/A23

P14/PO12/TIOCA1/

IRQ0

P12/PO10/TIOCC0/
TCLKA

P13/PO11/TIOCD0/
TCLKB

P14/PO12/TIOCA1/

IRQ0

—35NCNCNCNC
—36NCNCNCNC
31 37 P15/PO13/TIOCB1/

TCLKC

32 38 P16/PO14/TIOCA2/

PWM2/IRQ1

33 39 P17/PO15/TIOCB2/

PWM3/TCLKD

P15/PO13/TIOCB1/
TCLKC

P16/PO14/TIOCA2/
PWM2/IRQ1

P17/PO15/TIOCB2/
PWM3/TCLKD

P15/PO13/TIOCB1/
TCLKC

P16/PO14/TIOCA2/
PWM2/IRQ1

P17/PO15/TIOCB2/
PWM3/TCLKD

P15/PO13/TIOCB1/
TCLKC

P16/PO14/TIOCA2/
PWM2/IRQ1

P17/PO15/TIOCB2/
PWM3/TCLKD

34 40 D0 PE0/D0 PE0/D0 PE0
35 41 D1 PE1/D1 PE1/D1 PE1
36 42 D2 PE2/D2 PE2/D2 PE2
37 43 D3 PE3/D3 PE3/D3 PE3
38 44 D4 PE4/D4 PE4/D4 PE4
39 45 D5 PE5/D5 PE5/D5 PE5
40 46 D6 PE6/D6 PE6/D6 PE6
41 47 D7 PE7/D7 PE7/D7 PE7
42 48 VSS VSS VSS VSS
43 49 D8 D8 D8 PD0
44 50 PVCC1 PVCC1 PVCC1 PVCC1
45 51 D9 D9 D9 PD1
46 52 D10 D10 D10 PD2
47 53 D11 D11 D11 PD3
48 54 D12 D12 D12 PD4
49 55 D13 D13 D13 PD5
50 56 D14 D14 D14 PD6
51 57 D15 D15 D15 PD7
52 58 P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD P30/TxD0/IrTxD

10

Pin No. Pin Name

TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7

53 59 P31/RxD0/IrRxD P31/RxD0/IrRxD P31/RxD0/IrRxD P31/RxD0/IrRxD
54 60 PVCC2 PVCC2 PVCC2 PVCC2
55 61 P32/SCK0/SDA1/

IRQ4

P32/SCK0/SDA1/

IRQ4

P32/SCK0/SDA1/

IRQ4

P32/SCK0/SDA1/

IRQ4

56 62 VSS VSS VSS VSS
57 63 P33/TxD1/SCL1 P33/TxD1/SCL1 P33/TxD1/SCL1 P33/TxD1/SCL1
58 64 P34/RxD1/SDA0 P34/RxD1/SDA0 P34/RxD1/SDA0 P34/RxD1/SDA0
59 65 P35/SCK1/SCK4/

SCL0/IRQ5

P35/SCK1/SCK4/
SCL0/IRQ5

P35/SCK1/SCK4/
SCL0/IRQ5

P35/SCK1/SCK4/
SCL0/IRQ5

60 66 P36/RxD4 P36/RxD4 P36/RxD4 P36/RxD4
—67NCNCNCNC
—68NCNCNCNC
61 69 P37/TxD4 P37/TxD4 P37/TxD4 P37/TxD4
62 70 PG0/CAS/IRQ6 PG0/CAS/IRQ6 PG0/CAS/IRQ6 PG0/IRQ6
63 71 PG1/CS3/OE/IRQ7 PG1/CS3/OE/IRQ7 PG1/CS3/OE/IRQ7 PG1/IRQ7
64 72 PG2/CS2 PG2/CS2 PG2/CS2 PG2
65 73 PG3/CS1 PG3/CS1 PG3/CS1 PG3
66 74 PG4/CS0 PG4/CS0 PG4/CS0 PG4
67 75 WDTOVF WDTOVF WDTOVF WDTOVF
68 76 PLLVCC PLLVCC PLLVCC PLLVCC
69 77 PLLCAP PLLCAP PLLCAP PLLCAP
70 78 PLLVSS PLLVSS PLLVSS PLLVSS
71 79 RES RES RES RES
72 80 NMI NMI NMI NMI
73 81 STBY STBY STBY STBY
74 82 FWE FWE FWE FWE
75 83 XTAL XTAL XTAL XTAL
76 84 VCC VCC VCC VCC
77 85 EXTAL EXTAL EXTAL EXTAL
78 86 VSS VSS VSS VSS
79 87 OSC1 OSC1 OSC1 OSC1

11

Pin No. Pin Name

TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7

80 88 OSC2 OSC2 OSC2 OSC2
81 89 PVCC1 PVCC1 PVCC1 PVCC1
82 90 PF7/ø PF7/ø PF7/ø PF7/ø
83 91 VSS VSS VSS VSS
84 92 AS/LCAS AS/LCAS AS/LCAS PF6
85 93 RD RD RD PF5
86 94 HWR HWR HWR PF4
87 95 LWR PF3/LWR/ADTRG/

IRQ3

88 96 PF2/LCAS/WAIT/

BREQO

PF2/LCAS/WAIT/
BREQO

PF3/LWR/ADTRG/
IRQ3

PF2/LCAS/WAIT/
BREQO

PF3/ADTRG/IRQ3

PF2

89 97 PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BUZZ
90 98 PF0/BREQ/IRQ2 PF0/BREQ/IRQ2 PF0/BREQ/IRQ2 PF0/IRQ2
—99NCNCNCNC
— 100 NC NC NC NC
91 101 AVCC AVCC AVCC AVCC
92 102 Vref Vref Vref Vref
93 103 P40/AN0 P40/AN0 P40/AN0 P40/AN0
94 104 P41/AN1 P41/AN1 P41/AN1 P41/AN1
95 105 P42/AN2 P42/AN2 P42/AN2 P42/AN2
96 106 P43/AN3 P43/AN3 P43/AN3 P43/AN3
97 107 P44/AN4 P44/AN4 P44/AN4 P44/AN4
98 108 P45/AN5 P45/AN5 P45/AN5 P45/AN5
99 109 P46/AN6/DA0 P46/AN6/DA0 P46/AN6/DA0 P46/AN6/DA0
100 110 P47/AN7/DA1 P47/AN7/DA1 P47/AN7/DA1 P47/AN7/DA1
101 111 P90/AN8 P90/AN8 P90/AN8 P90/AN8
102 112 P91/AN9 P91/AN9 P91/AN9 P91/AN9
103 113 P92/AN10 P92/AN10 P92/AN10 P92/AN10
104 114 P93/AN11 P93/AN11 P93/AN11 P93/AN11
105 115 P94/AN12 P94/AN12 P94/AN12 P94/AN12
106 116 P95/AN13 P95/AN13 P95/AN13 P95/AN13

12

Pin No. Pin Name

TFP-120 FP-128 Mode 4 Mode 5 Mode 6 Mode 7

107 117 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2
108 118 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3
109 119 AVSS AVSS AVSS AVSS
110 120 P70/TMRI01/TMCI01/

DREQ0/CS4

111 121 P71/TMRI23/TMCI23/

DREQ1/CS5

112 122 P72/TMO0/TEND0/

CS6/SYNCI

113 123 P73/TMO1/TEND1/

CS7

114 124 P74/TMO2/MRES P74/TMO2/MRES P74/TMO2/MRES P74/TMO2/MRES
115 125 P75/TMO3/SCK3 P75/TMO3/SCK3 P75/TMO3/SCK3 P75/TMO3/SCK3
116 126 P76/RxD3 P76/RxD3 P76/RxD3 P76/RxD3
117 127 P77/TxD3 P77/TxD3 P77/TxD3 P77/TxD3
118 128 MD0 MD0 MD0 MD0
119 1 MD1 MD1 MD1 MD1
120 2 MD2 MD2 MD2 MD2
— 3 NC NC NC NC

P70/TMRI01/TMCI01/
DREQ0/CS4

P71/TMRI23/TMCI23/
DREQ1/CS5

P72/TMO0/TEND0/
CS6/SYNCI

P73/TMO1/TEND1/

CS7

P70/TMRI01/TMCI01/
DREQ0/CS4

P71/TMRI23/TMCI23/
DREQ1/CS5

P72/TMO0/TEND0/
CS6/SYNCI

P73/TMO1/TEND1/

CS7

P70/TMRI01/TMCI01/

DREQ0

P71/TMRI23/TMCI23/

DREQ1

P72/TMO0/TEND0/
SYNCI

P73/TMO1/TEND1

— 4 NC NC NC NC

Note: NC pins should be connected to VSS or left open.

13

1.3.3 Pin Functions

Table 1-3 outlines the pin functions of the H8S/2633 Series.

Table 1-3 Pin Functions

Type Symbol I/O Name and Function

Power VCC Input Power supply: For connection to the power supply.

All VCC pins should be connected to the system power
supply.

PVCC1,
PVCC2

VSS Input Ground: For connection to ground

Clock PLLVCC Input PLL power supply: Power supply for on-chip PLL

PLLVSS Input PLL ground: Ground for on-chip PLL oscillator.
PLLCAP Input PLL capacitance: External capacitance pin for on-chip

XTAL Input Connects to a crystal oscillator.

EXTAL Input Connects to a crystal oscillator.

Input Port power supply pin. Connect all pins to the same

power supply.

(0 V). All VSS pins should be connected to the system
power supply (0 V).

oscillator.

PLL oscillator.

See section 23, Clock Pulse Generator, for typical
connection diagrams for a crystal oscillator and
external clock input.

The EXTAL pin can also input an external clock.
See section 23, Clock Pulse Generator, for typical
connection diagrams for a crystal oscillator and
external clock input.

OSC1 Input Subclock: Connects to a 32.768 kHz crystal oscillator.

OSC2 Input Subclock: Connects to a 32.768 kHz crystal oscillator.

ø Output System clock: Supplies the system clock to an external

14

See Chapter 23 Clock Oscillator for examples of
connections to a crystal oscillator.

See Chapter 23 Clock Oscillator for examples of
connections to a crystal oscillator.

device.

Type Symbol I/O Name and Function

Operating mode
control

MD2 to MD0 Input Mode pins: These pins set the operating mode.

The relation between the settings of pins MD2 to MD0
and the operating mode is shown below. These pins
should not be changed while the H8S/2633 Series is
operating.

MD2 MD1 MD0 Operating Mode

000—

1—

10—

1—

1 0 0 Mode 4

1 Mode 5

1 0 Mode 6

1 Mode 7

System control RES Input Reset input: When this pin is driven low, the chip is

reset.

MRES Input Manual reset: When this pin is driven low, a

transmission is made to manual reset mode.

STBY Input Standby: When this pin is driven low, a transition is

made to hardware standby mode.

BREQ Input Bus request: Used by an external bus master to issue

a bus request to the H8S/2633 Series.

BREQO Output Bus request output: The external bus request signal

used when an internal bus master accesses external
space in the external bus-released state.

BACK Output Bus request acknowledge: Indicates that the bus has

been released to an external bus master.

FWE Input Flash write enable: Pin for flash memory use (in

planning stage).

15

Type Symbol I/O Name and Function

Interrupts NMI Input Nonmaskable interrupt: Requests a nonmaskable

interrupt. When this pin is not used, it should be fixed
high.

IRQ7 to IRQ0 Input Interrupt request 7 to 0: These pins request a

maskable interrupt.
Address bus A23 to A0 Output Address bus: These pins output an address.
Data bus D15 to D0 I/O Data bus: These pins constitute a bidirectional data

bus.
Bus control CS7 to CS0 Output Chip select: Selection signal for areas 0 to 7.

AS Output Address strobe: When this pin is low, it indicates that

address output on the address bus is enabled.

RD Output Read: When this pin is low, it indicates that the

external address space can be read.

HWR Output High write/write enable/upper write enable:

A strobe signal that writes to external space and

indicates that the upper half (D15 to D8) of the data

bus is enabled.

The 2CAS type DRAM write enable signal.

The 2WE type DRAM upper write enable signal.

LWR Output Low write/lower column address strobe/lower write

enable:

A strobe signal that writes to external space and

indicates that the lower half (D7 to D0) of the data bus

is enabled.

The 2CAS type (LCASS = 1) DRAM lower column

address strobe signal.

The 2WE type DRAM lower write enable signal.

CAS Output Upper column address strobe/column address strobe:

The 2CAS type DRAM upper column address strobe

signal.

LCAS Output Lower column address strobe:

The 2CAS type DRAM lower column address strobe

signal.

OE Output Output enable:

Output enable signal for DRAM space read access.

WAIT Input Wait: Requests insertion of a wait state in the bus

cycle when accessing external 3-state address space.

16

Type Symbol I/O Name and Function

DMA controller
(DMAC)

16-bit timer­pulse unit (TPU)

DREQ1,

DREQ0

TEND1,

TEND0

DACK1,

DACK0

TCLKD to
TCLKA

TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0

TIOCA1,
TIOCB1

TIOCA2,
TIOCB2

Input DMA request 1,0:

Requests DMAC activation.

Output DMA transfer completed 1,0:

Indicates DMAC data transfer end.

Output DMA transfer acknowledge 1,0:

DMAC single address transfer acknowledge pin.

Input Clock input D to A: These pins input an external clock.

I/O Input capture/ output compare match A0 to D0:

The TGR0A to TGR0D input capture input or output
compare output, or PWM output pins.

I/O Input capture/ output compare match A1 and B1:

The TGR1A and TGR1B input capture input or output
compare output, or PWM output pins.

I/O Input capture/ output compare match A2 and B2:

The TGR2A and TGR2B input capture input or output
compare output, or PWM output pins.

TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3

TIOCA4,
TIOCB4

TIOCA5,
TIOCB5

Programmable

PO15 to PO8 Output Pulse output 15 to 8: Pulse output pins.
pulse generator
(PPG)

8-bit timer TMO0 to

TMO3

TMCI01,

TMCI23

TMRI01,

TMRI23

I/O Input capture/ output compare match A3 to D3:

The TGR3A to TGR3D input capture input or output
compare output, or PWM output pins.

I/O Input capture/output compare match A4 and B4:

The TGR4A and TGR4B input capture input or output
compare output, or PWM output pins.

I/O Input capture/output compare match A5 and B5:

The TGR5A and TGR5B input capture input or output
compare output, or PWM output pins.

Output Compare match output: The compare match output

pins.

Input Counter external clock input: Input pins for the external

clock input to the counter.

Input Counter external reset input: The counter reset input

pins.

17

Type Symbol I/O Name and Function

14-bit PWM timer
(PWMX)

Watchdog
timer (WDT)

Serial
communication
interface (SCI)/
Smart Card
interface

PWM0 to

Output PWMX timer output: PWM D/A pulse output pins.

PWM3
WDTOVF Output Watchdog timer overflows: The counter overflows

signal output pin in watchdog timer mode.

BUZZ Output BUZZ output: Output pins for the pulse divided by the

watchdog timer.

TxD4,

Output Transmit data (channel 0, 1, 2): Data output pins.
TxD3,
TxD2,
TxD1,
TxD0

RxD4,

Input Receive data (channel 0, 1, 2): Data input pins.
RxD3,
RxD2,
RxD1,
RxD0

SCK4,
SCK3,

I/O Serial clock (channel 0, 1, 2): Clock I/O pins.

SCK0 output type is NMOS push-pull.
SCK2,
SCK1
SCK0

IrDA-equipped
SCI 1 channel

IrTxD
IrRxD

Output/
Input

IrDA transmission data/receive data: Input/output pins

for the data encoded for the IrDA.

(SCI0)
I2C bus interface

(IIC) (optional)

SCL0
SCL1

I/O I2C clock input (channel 1, 0):

2

I

C clock input/output pins.
These functions have a bus driving function.
SCL0's output format is an NMOS open drain.

SDA0
SDA1

I/O I2C data input/output (channel 1, 0):

2

I

C clock input/output pins.
These functions have a bus driving function.
SCL0's output format is an NMOS open drain.

A/D converter AN15 to AN0 Input Analog 15 to 0: Analog input pins.

ADTRG Input A/D conversion external trigger input: Pin for input of

an external trigger to start A/D conversion.

D/A converter DA3 to DA0 Output Analog output: Analog output pins for D/A converter.
A/D converter,

D/A converter

AVCC Input A/D converter and D/A converter power supply pin

When the A/D converter and D/A converter are not
used, this pin should be connected to the system
power supply (+5 V).

18

Type Symbol I/O Name and Function

A/D converter,
D/A converter

AVSS Input Analog circuit ground and reference voltage

A/D converter and D/A converter ground and reference
voltage.

Connect to system power supply (0 V).

Vref Input A/D converter and D/A converter reference voltage

input pin
When the A/D converter and D/A converter are not

used, this pin should be connected to the system
power supply (+5 V).

I/O ports P17 to P10 I/O Port 1: An 8-bit I/O port. Input or output can be

designated for each bit by means of the port 1 data
direction register (P1DDR).

P37 to P30 I/O Port 3: An 8-bit I/O port. Input or output can be

designated for each bit by means of the port 3 data

direction register (P3DDR).
P47 to P40 Input Port 4: An 8-bit input port.
P77 to P70 I/O Port 7: An 8-bit I/O port. Input or output can be

designated for each bit by means of the port 7 data

direction register (P7DDR).
P97 to P90 Input Port 9: An 8-bit input port.
PA3 to PA0 I/O Port A: A 4-bit I/O port. Input or output can be

designated for each bit by means of the port A data

direction register (PADDR).
PB7 to PB0 I/O Port B: An 8-bit I/O port. Input or output can be

designated for each bit by means of the port B data

direction register (PBDDR).
PC7 to PC0 I/O Port C: An 8-bit I/O port. Input or output can be

designated for each bit by means of the port C data

direction register (PCDDR).
PD7 to PD0 I/O Port D: An 8-bit I/O port. Input or output can be

designated for each bit by means of the port D data

direction register (PDDDR).
PE7 to PE0 I/O Port E: An 8-bit I/O port. Input or output can be

designated for each bit by means of the port E data

direction register (PEDDR).
PF7 to PF0 I/O Port F: An 8-bit I/O port. Input or output can be

designated for each bit by means of the port F data

direction register (PFDDR).
PG4 to PG0 I/O Port G: An 5-bit I/O port. Input or output can be

designated for each bit by means of the port G data

direction register (PGDDR).

19

Section 2 CPU

2.1 Overview

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is
ideal for realtime control.

2.1.1 Features

The H8S/2600 CPU has the following features.

• Upward-compatible with H8/300 and H8/300H CPUs
 Can execute H8/300 and H8/300H object programs

• General-register architecture
 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit

registers)

• Sixty-nine basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
 Multiply-and-accumulate instruction

• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]

• 16-Mbyte address space
 Program: 16 Mbytes
 Data: 16 Mbytes (4 Gbytes architecturally)

21

• High-speed operation
 All frequently-used instructions execute in one or two states
 Maximum clock rate : 25 MHz
 8/16/32-bit register-register add/subtract : 40 ns
 8 × 8-bit register-register multiply : 120 ns
 16 ÷ 8-bit register-register divide : 480 ns
 16 × 16-bit register-register multiply : 160 ns
 32 ÷ 16-bit register-register divide : 800 ns

• Two CPU operating modes
 Normal mode*
 Advanced mode

Note: * Not available in the H8S/2633 Series.

• Power-down state
 Transition to power-down state by SLEEP instruction
 CPU clock speed selection

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration
The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• Number of execution states
The number of execution states of the MULXU and MULXS instructions is different in each

CPU.

Execution States

Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

22

In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.

2.1.3 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.

• More general registers and control registers
 Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been

added.

• Expanded address space
 Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.
 Advanced mode supports a maximum 16-Mbyte address space.

Note: * Not available in the H8S/2633 Series.

• Enhanced addressing
 The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Signed multiply and divide instructions have been added.
 A multiply-and-accumulate instruction has been added.
 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.

• Higher speed
 Basic instructions execute twice as fast.

2.1.4 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.

• Additional control register
 One 8-bit and two 32-bit control registers have been added.

• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 A multiply-and-accumulate instruction has been added.

23

 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.

• Higher speed
 Basic instructions execute twice as fast.

2.2 CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for
program and data areas combined). The mode is selected by the mode pins of the microcontroller.

Note: * Not available in the H8S/2633 Series.

Normal mode*

CPU operating modes

Advanced mode

Note: * Not available in the H8S/2633 Series.

Maximum 64 kbytes, program
and data areas combined

Maximum 16-Mbytes for
program and data areas
combined

Figure 2-1 CPU Operating Modes

(1) Normal Mode (Not Available in the H8S/2633 Series)

The exception vector table and stack have the same structure as in the H8/300 CPU.

Address Space: A maximum address space of 64 kbytes can be accessed.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain
any value, even when the corresponding general register (Rn) is used as an address register. If the
general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn)
or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (En) will be affected.

24

Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of
effective addresses (EA) are valid.

Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16
bits (figure 2-2). The exception vector table differs depending on the microcontroller. For details
of the exception vector table, see section 4, Exception Handling.

H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B

Power-on reset exception vector

Manual reset exception vector

(Reserved for system use)

Exception vector 1

Exception vector 2

Figure 2-2 Exception Vector Table (Normal Mode)

Exception
vector table

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16­bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.

25

Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call,
and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto
the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is
not pushed onto the stack. For details, see section 4, Exception Handling.

SP

(a) Subroutine Branch (b) Exception Handling

Notes: 1.

When EXR is not used it is not stored on the stack.

2.

SP when EXR is not used.

3.

Ignored when returning.

(2) Advanced Mode

PC

(16 bits)

SP

*2

(SP )

Figure 2-3 Stack Structure in Normal Mode

EXR

Reserved

CCR

CCR

PC

(16 bits)

*1

*1,*3

*3

Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally
a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4
Gbytes for program and data areas combined).

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers or address registers.

Instruction Set: All instructions and addressing modes can be used.

26

Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top
area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32
bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4).
For details of the exception vector table, see section 4, Exception Handling.

H'00000000

H'00000003
H'00000004

H'00000007
H'00000008

H'0000000B
H'0000000C

Reserved

Power-on reset exception vector

Reserved

Manual reset exception vector

Exception vector table

(Reserved for system use)

H'00000010

Reserved

Exception vector 1

Figure 2-4 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing
a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as
H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the
first part of this range is also the exception vector table.

27

Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a
subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR)
are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When
EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.

SP

Notes: 1.

EXR

CCR

*1

*1,*3

Reserved

SP

*2

(SP )

Reserved

PC

(24 bits)

PC

(24 bits)

(a) Subroutine Branch (b) Exception Handling

When EXR is not used it is not stored on the stack.

2.

SP when EXR is not used.

3.

Ignored when returning.

Figure 2-5 Stack Structure in Advanced Mode

28

2.3 Address Space

Figure 2-6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode.

H'0000

H'FFFF

H'00000000

H'00FFFFFF

H'FFFFFFFF

Program area

Data area

Cannot be
used by the
H8S/2633
Series

(a) Normal Mode*

Note: * Not available in the H8S/2633 Series.

Figure 2-6 Memory Map

(b) Advanced Mode

29

2.4 Register Configuration

2.4.1 Overview

The CPU has the internal registers shown in figure 2-7. There are two types of registers: general
registers and control registers.

General Registers (Rn) and Extended Registers (En)

15 07 07 0
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)

Control Registers (CR)

63 32

MAC

E0
E1
E2
E3
E4
E5
E6
E7

23 0

Sign extension

R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H

PC

41

MACL

R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L

76543210
T

————

76543210

IUIHUNZVCCCR

MACH

I2 I1I0EXR

031

Legend

SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:

Note: * Cannot be used as an interrupt mask bit in the H8S/2633 Series.

Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit*

30

H:
U:
N:
Z:
V:
C:
MAC:

Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Multiply-accumulate register

Figure 2-7 CPU Registers

2.4.2 General Registers

The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a data
register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used
as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.

Figure 2-8 illustrates the usage of the general registers. The usage of each register can be selected
independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

E registers (extended registers)

(E0 to E7)

ER registers

(ER0 to ER7)

R registers
(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 2-8 Usage of General Registers

31

General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the
stack.

Free area

SP (ER7)

Stack area

Figure 2-9 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),
8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC).

(1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the
CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant
PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.)

(2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three
interrupt mask bits (I2 to I0).

Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed
in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is
executed.

Bits 6 to 3—Reserved: They are always read as 1.

32

Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to

7). For details, refer to section 5, Interrupt Controller.

Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. All interrupts, including NMI, are disabled for three states after one of these
instructions is executed, except for STC.

(3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status
information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z),
overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception­handling sequence. For details, refer to section 5, Interrupt Controller.

Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details, refer to section 5, Interrupt Controller.

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.

Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to store the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

33

Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, refer to Appendix A.1, List of Instructions.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.

(4) Multiply-Accumulate Register (MAC): This 64-bit register stores the results of multiply­and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The
lower 10 bits of MACH are valid; the upper bits are a sign extension.

2.4.4 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.

34

2.5 Data Formats

The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit
BCD data.

2.5.1 General Register Data Formats

Figure 2-10 shows the data formats in general registers.

Data Type Register Number Data Format

1-bit data

1-bit data

4-bit BCD data

4-bit BCD data

Byte data

RnH

RnL

RnH

RnL

RnH

70

76543210 Don’t care

70

Don’t care 76543210

70

70

MSB LSB

43

Don’t care

Don’t careUpper Lower

70

Upper

43

Lower

Don’t care

Byte data

RnL

Figure 2-10 General Register Data Formats

Don’t care

70

MSB

LSB

35

Data Type Register Number Data Format

Word data

Word data

15

Rn

En

0

MSB LSB

Longword data

31

MSB

ERn

16

En Rn

Legend

ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:

General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit

15

0

MSB LSB

15

0

LSB

Figure 2-10 General Register Data Formats (cont)

36

2.5.2 Memory Data Formats

Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data
in memory, but word or longword data must begin at an even address. If an attempt is made to
access word or longword data at an odd address, no address error occurs but the least significant
bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to
instruction fetches.

Data Type Data Format

Address

70

1-bit data

Byte data

Word data

Longword data

Address L

Address L

Address 2M

Address 2M + 1

Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3

76543210

MSB LSB

MSB

LSB

MSB

LSB

When ER7 is used as an address register to access the stack, the operand size should be word size
or longword size.

Figure 2-11 Memory Data Formats

37

2.6 Instruction Set

2.6.1 Overview

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2-1.

Table 2-1 Instruction Classification

Function Instructions Size Types

Data transfer MOV BWL 5

POP*1, PUSH*
LDM, STM L
MOVFPE*3, MOVTPE*

Arithmetic ADD, SUB, CMP, NEG BWL 23
operations

ADDX, SUBX, DAA, DAS B

1

3

WL

B

INC, DEC BWL
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS BW
EXTU, EXTS WL
TAS B

MAC, LDMAC, STMAC, CLRMAC —
Logic operations AND, OR, XOR, NOT BWL 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

B14

BIAND, BOR, BIOR, BXOR, BIXOR
Branch Bcc*2, JMP, BSR, JSR, RTS — 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9
Block data transfer EEPMOV — 1

Notes: B-byte size; W-word size; L-longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.

2. Bcc is the general name for conditional branch instructions.

3. Not available in the H8S/2633 Series.

38

2.6.2 Instructions and Addressing Modes

Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.

Table 2-2 Combinations of Instructions and Addressing Modes

—

@@aa:8

@(d:16,PC)

@(d:8,PC)

@aa:32

@aa:24

Addressing Modes

@aa:16

@aa:8

@–ERn/@ERn+

@(d:32,ERn)

@(d:16,ERn)

@ERn

Rn

#xx

, —— —————B — —————

*

*

Instruction

Function

MOV BWL BWL BWL BWL BWL BWL B BWL — BWL ————

Data

transfer

POP, PUSH —— ——————— ————WL

LDM, STM —— ——————— ————L

MOVEPE

MOVTPE

ADD, CMP BWL BWL ——————— — ————

SUB WL BWL ——————— —————

Arithmetic

operations

INC, DEC — BWL ——————— —————

ADDX, SUBX B B ——————— —————

ADDS, SUBS — L ——————— —————

DIVXU

MULXS, — BW ——————— —————

MULXU, — BW ——————— —————

DAA, DAS — B ——————— —————

DIVXS

TAS —— B —————— —————

EXTU, EXTS — WL ————————————

NEG — BWL ————————————

STMAC

LDMAC, — L ——————— —————

MAC —— ——— ——— —————

CLRMAC —— ——————— ————

39

—

@@aa:8

@(d:16,PC)

@(d:8,PC)

@aa:32

@aa:24

@aa:16

@aa:8

Addressing Modes

Instruction

@–ERn/@ERn+

@(d:32,ERn)

@(d:16,ERn)

@ERn

Rn

#xx

NOT — BWL ——————— —————

AND, OR, BWL BWL ——————— —————

XOR

— BWL ——————— —————

— BB———BB— B ————

Bcc, BSR —— ——————— — ——

JMP, JSR —— ——————l ——— —

RTS —— ———— ——— — ———

TRAPA —— ——————— ————

RTE —— ———— ——— — ———

SLEEP —— ——————— ————

ANDC, B — ——————— —————

LDC B B WWWW— W — W ————

STC — B WWWW— W — W ————

—— ——————— ————BW

NOP —— ——————— ————

ORC, XORC

Logic

operations

Shift

Function

Bit manipulation

40

Branch

System

control

Block data transfer

Legend

B: Byte

W: Word

L: Longword

Note: * Not available in the H8S/2633 Series.

2.6.3 Table of Instructions Classified by Function

Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3
is defined below.

Operation Notation

Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
MAC Multiply-accumulate register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
EXR Extended control register
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division

∧ Logical AND
∨ Logical OR
⊕ Logical exclusive OR
→ Move

¬ NOT (logical complement)
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

41

Table 2-3 Instructions Classified by Function

Type Instruction Size*

1

Function

Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead)

Moves data between two general registers or between a
general register and memory, or moves immediate data

to a general register.
MOVFPE B Cannot be used in the H8S/2633 Series.
MOVTPE B Cannot be used in the H8S/2633 Series.
POP W/L @SP+ → Rn

Pops a register from the stack. POP.W Rn is identical to

MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L

@SP+, ERn.
PUSH W/L Rn → @–SP

Pushes a register onto the stack. PUSH.W Rn is

identical to MOV.W Rn, @–SP. PUSH.L ERn is identical

to MOV.L ERn, @–SP.
LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

Arithmetic
operations

STM L Rn (register list) → @–SP

Pushes two or more general registers onto the stack.
ADD

SUB

B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general

registers, or on immediate data and data in a general

register. (Immediate byte data cannot be subtracted from

byte data in a general register. Use the SUBX or ADD

instruction.)
ADDX

SUBX

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on

byte data in two general registers, or on immediate data

and data in a general register.
INC

DEC

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2.

(Byte operands can be incremented or decremented by

1 only.)
ADDS

SUBS

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a

32-bit register.
DAA

DAS

42

B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a

general register by referring to the CCR to produce 4-bit

BCD data.

Type Instruction Size*

1

Function

Arithmetic
operations

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16­bit remainder.

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16­bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of
data in a general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.

2

TAS*

B @ERd – 0, 1 → (<bit 7> of @Erd)

Tests memory contents, and sets the most significant bit
(bit 7) to 1.

MAC — (EAs) × (EAd) + MAC → MAC

Performs signed multiplication on memory contents and
adds the result to the multiply-accumulate register. The
following operations can be performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating

43

Type Instruction Size*

1

Function

Arithmetic
operations

Logic
operations

Shift
operations

CLRMAC — 0 → MAC

Clears the multiply-accumulate register to zero.
LDMAC

STMAC

L Rs → MAC, MAC → Rd

Transfers data between a general register and a

multiply-accumulate register.
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register

and another general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register

and another general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general

register and another general register or immediate data.
NOT B/W/L ¬ (Rd) → (Rd)

Takes the one's complement of general register

contents.
SHAL

SHAR

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

1-bit or 2-bit shift is possible.

Bit­manipulation
instructions

SHLL
SHLR

B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

1-bit or 2-bit shift is possible.
ROTL

ROTR

B/W/L Rd (rotate) → Rd

Rotates general register contents.

1-bit or 2-bit rotation is possible.
ROTXL

ROTXR

B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.

1-bit or 2-bit rotation is possible.
BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory

operand to 1. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

register.
BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory

operand to 0. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

44

Inverts a specified bit in a general register or memory

operand. The bit number is specified by 3-bit immediate

data or the lower three bits of a general register.

Type Instruction Size*

1

Function

Bit­manipulation
instructions

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory
operand and sets or clears the Z flag accordingly. The
bit number is specified by 3-bit immediate data or the
lower three bits of a general register.

BAND

B

C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.

BIAND

B

C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in
a general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.

BOR

B

C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.

BIOR

B

C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.

BXOR

BIXOR

BLD

BILD

B

C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a
general register or memory operand and stores the
result in the carry flag.

B

C ⊕ ¬ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with the inverse of a
specified bit in a general register or memory operand
and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.

B

(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory
operand to the carry flag.

B

¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general
register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.

45

Type Instruction Size*

1

Function

Bit­manipulation
instructions

Branch
instructions

BST

B

C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a

general register or memory operand.
BIST

B

¬ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a

specified bit in a general register or memory operand.

The bit number is specified by 3-bit immediate data.
Bcc — Branches to a specified address if a specified condition

is true. The branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always

BRN(BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC(BHS) Carry clear

C = 0

(high or same)
BCS(BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1

JMP — Branches unconditionally to a specified address.
BSR — Branches to a subroutine at a specified address.
JSR — Branches to a subroutine at a specified address.
RTS — Returns from a subroutine

System control TRAPA — Starts trap-instruction exception handling.
instructions

RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to a power-down state.

46

Type Instruction Size*

1

Function

System control
instructions

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the source operand contents or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit
registers, word-size transfers are performed between
them and memory. The upper 8 bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or
memory. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and
memory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with
immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate
data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with
immediate data.

Block data
transfer
instruction

NOP — PC + 2 → PC

Only increments the program counter.

EEPMOV.B

if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;

EEPMOV.W——

if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;

Transfers a data block according to parameters set in
general registers R4L or R4, ER5, and ER6.

R4L or R4: size of block (bytes)
ER5: starting source address
ER6: starting destination address

Execution of the next instruction begins as soon as the
transfer is completed.

Notes: 1. Size refers to the operand size.

B: Byte
W: Word
L: Longword

2. This instruction should be used with the ER0, ER1, ER4, or ER5 general register only.

47

2.6.4 Basic Instruction Formats

The H8S/2633 Series instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op field), a register field (r field), an effective address extension (EA field), and a
condition field (cc).

(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the
operation to be carried out on the operand. The operation field always includes the first four bits of
the instruction. Some instructions have two operation fields.

(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data
registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register
field.

(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.

(4) Condition Field: Specifies the branching condition of Bcc instructions.

48

Figure 2-12 shows examples of instruction formats.

(1) Operation field only

op

(2) Operation field and register fields

op

rn

rm

(3) Operation field, register fields, and effective address extension

op

rn rm

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16, etc

Figure 2-12 Instruction Formats (Examples)

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

49

2.7 Addressing Modes and Effective Address Calculation

2.7.1 Addressing Mode

The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of
these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-counter
relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2-4 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)
4 Register indirect with post-increment

Register indirect with pre-decrement
5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8

@ERn+
@–ERn

(1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit
general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit
registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified
as 32-bit registers.

(2) Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn) which contains the address of the operand on memory. If the address is a program
instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit
displacement contained in the instruction is added to an address register (ERn) specified by the
register field of the instruction, and the sum gives the address of a memory operand. A 16-bit
displacement is sign-extended when added.

50

(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or
longword transfer instruction, the register value should be even.

• Register indirect with pre-decrement—@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer
instruction, or 4 for longword transfer instruction. For word or longword transfer instruction,
the register value should be even.

(5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the
absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits
long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32).

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).

Table 2-5 indicates the accessible absolute address ranges.

Table 2-5 Absolute Address Access Ranges

Absolute Address Normal Mode* Advanced Mode

Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF

16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

32 bits (@aa:32) H'000000 to H'FFFFFF

Program instruction
address

24 bits (@aa:24)

Note: *Not available in the H8S/2633 Series.

51

(6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.

(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and
added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch
address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the
displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.

(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The upper bits of the absolute address are all assumed to be 0,
so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in
advanced mode). In normal mode* the memory operand is a word operand and the branch address
is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of
which is assumed to be all 0 (H'00).

Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.

Note: * Not available in the H8S/2633 Series.

52

Specified
by @aa:8

Branch address

Specified
by @aa:8

Reserved

Branch address

(a) Normal Mode

Note: * Not available in the H8S/2633 Series.

*

(b) Advanced Mode

Figure 2-13 Branch Address Specification in Memory Indirect Mode

If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)

2.7.2 Effective Address Calculation

Table 2-6 indicates how effective addresses are calculated in each addressing mode. In normal
mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Note: * Not available in the H8S/2633 Series.

53

Table 2-6 Effective Address Calculation

24 23

Effective Address (EA)

Don’t care

Operand is general register contents.

Effective Address Calculation

31 0

General register contents

31 0

24 23

Don’t care

31 0

disp

General register contents

Sign extension

31 0

31 0

24 23

Don’t care

31 0

1, 2, or 4

General register contents

31 0

24 23

Don’t care

31 0

1, 2, or 4

1

General register contents

Byte

31 0

Operand Size Value added

2

4

Word

Longword

rop

op rm rn

Register indirect (@ERn)2

1 Register direct (Rn)

No. Addressing Mode and Instruction Format

54

disp

op r

Register indirect with displacement

@(d:16, ERn) or @(d:32, ERn)

3

Register indirect with post-increment or

4

r

op

pre-decrement

• Register indirect with post-increment @ERn+

• Register indirect with pre-decrement @–ERn

r

op

H'FFFF

16 15

Sign extension

Effective Address (EA)

24 23

31 08 7

Don’t care

24 23

31 0

Effective Address Calculation

Don’t care

24 23

31 0

Don’t care

24 23

31 0

Don’t care

Operand is immediate data.

abs

op

op abs

@aa:8

Absolute address

5

No. Addressing Mode and Instruction Format

@aa:16

abs

op

@aa:24

op

@aa:32

IMM

abs

op

Immediate #xx:8/#xx:16/#xx:32

6

55

16 15

H'00

Effective Address (EA)

0

PC contents

23

Effective Address Calculation

0

Sign

23

24 23

Don’t care

31 0

disp

extension

0

31 8 7

24 23

Don’t care

31 0

abs

H'000000

0

0

Memory contents

15

0

31 8 7

24 23

31 0

0

abs

H'000000

31

Don’t care

Memory contents

disp

op

Program-counter relative

@(d:8, PC)/@(d:16, PC)8Memory indirect @@aa:8

7

No. Addressing Mode and Instruction Format

56

*

op abs

• Normal mode

op abs

• Advanced mode

Note: * Not available in the H8S/2633 Series.

2.8 Processing States

2.8.1 Overview

The CPU has five main processing states: the reset state, exception handling state, program
execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the
processing states. Figure 2-15 indicates the state transitions.

Reset state

The CPU and all on-chip supporting modules have been
initialized and are stopped.

Exception-handling

state

A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.

Processing

states

Note: *The power-down state also includes a medium-speed mode, module stop mode,

subactive mode, subsleep mode, and watch mode.

Program execution

state

The CPU executes program instructions in sequence.

Bus-released state

The external bus has been released in response to a bus
request signal from a bus master other than the CPU.

Sleep mode

Power-down state

CPU operation is stopped
to conserve power.*

Software standby

mode

Hardware standby

mode

Figure 2-14 Processing States

57

End of bus

request

Bus request

End of bus request

Bus request

Program execution state

SLEEP
instruction
with

SSBY = 0

MRES= High

Notes: 1.

Bus-released state

End of exception

Exception handling state

Manual reset state *

Reset state *1

handling

1

Interrupt request

Request for exception handling

External interrupt request

RES= High

Power-on reset state *

1

SLEEP
instruction
with
SSBY = 1

STBY= High, RES= Low

Sleep mode

Software standby mode

Hardware standby mode*

Power-down state*

2

3

From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES
goes low. From any state except hardware standby mode and power-on reset mode, a transition to the manual
reset state occurs whenever MRES goes low. A transition can also be made to the reset state when the
watchdog timer overflows.

2.

From any state, a transition to hardware standby mode occurs when STBY goes low.

3.

Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.
See Chapter 24 Power-Down States

Figure 2-15 State Transitions

2.8.2 Reset State

The CPU enters the reset state when the RES pin goes low, or when the MRES pin goes low while
manual resets are enabled by the MRESE bit. In the reset state, currently executing processing is
halted and all interrupts are disabled.

For details of MRESE bit setting, see section 3.2.2, System Control Register (SYSCR).

Reset exception handling starts when the RES or MRES pin* changes from low to high.

The reset state can also be entered in the event of watchdog timer overflow. For details see section
15, Watchdog Timer.

Note: * MRES pin in the case of a manual reset.

58

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.

(1) Types of Exception Handling and Their Priority

Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7
indicates the types of exception handling and their priority. Trap instruction exception handling is
always accepted, in the program execution state.

Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.

Table 2-7 Exception Handling Types and Priority

Priority Type of Exception Detection Timing Start of Exception Handling

High Reset Synchronized with clock Exception handling starts

immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.

Trace End of instruction

execution or end of
exception-handling
sequence*

1

Interrupt End of instruction

execution or end of
exception-handling
sequence*

2

When the trace (T) bit is set to
1, the trace starts at the end of
the current instruction or current
exception-handling sequence

When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence

Trap instruction When TRAPA instruction

is executed

Low

Exception handling starts when
a trap (TRAPA) instruction is
executed*

3

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not

executed at the end of the RTE instruction.

2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.

3. Trap instruction exception handling is always accepted, in the program execution state.

59

(2) Reset Exception Handling

After the RES pin has gone low and the reset state has been entered, when RES pin goes high
again, reset exception handling starts. After the reset state has been entered by driving the MRES
pin low while manual resets are enabled by the MRESE bit, reset exception handling starts when
MRES pin is driven high again. The CPU enters the power-on reset state when the RES pin is low,
and enters the manual reset state when the MRES pin is low. When reset exception handling starts
the CPU fetches a start address (vector) from the exception vector table and starts program
execution from that address. All interrupts, including NMI, are disabled during reset exception
handling and after it ends.

(3) Traces

Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR
is set to 1. When trace mode is established, trace exception handling starts at the end of each
instruction.

At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode
is cleared. Interrupt masks are not affected.

The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to
return from the trace exception-handling routine, trace mode is entered again. Trace exception­handling is not executed at the end of the RTE instruction.

Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.

(4) Interrupt Exception Handling and Trap Instruction Exception Handling

When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.

Figure 2-16 shows the stack after exception handling ends.

60

Normal mode

*2

SP

(a) Interrupt control mode 0 (b) Interrupt control mode 2

Advanced mode

CCR

*1

CCR

PC

(16 bits)

SP

SP

EXR

Reserved

CCR

*1

CCR

PC

(16 bits)

EXR

Reserved

*1

*1

SP

CCR

PC

(24 bits)

(c) Interrupt control mode 0 (d) Interrupt control mode 2

Notes: 1. Ignored when returning.

2. Not available in the H8S/2633 Series.

Figure 2-16 Stack Structure after Exception Handling (Examples)

CCR

PC

(24 bits)

61

2.8.4 Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5 Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts operations.

Bus masters other than the CPU are DMA controller (DMAC) and data transfer controller (DTC).

For further details, refer to section 7, Bus Controller.

2.8.6 Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also
three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In
medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module
stop mode permits halting of the operation of individual modules, other than the CPU. Subactive
mode, subsleep mode, and watch mode are power-down states using subclock input. For details,
refer to section 24, Power-Down State.

(1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while
the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep
mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of
CPU registers are retained.

(2) Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the
CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the
contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their
existing states.

(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY
pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop.
The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip
RAM contents are retained.

62

2.9 Basic Timing

2.9.1 Overview

The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one
rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of
one, two, or three states. Different methods are used to access on-chip memory, on-chip
supporting modules, and the external address space.

2.9.2 On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2-17 shows the on-chip memory access cycle. Figure 2-18 shows
the pin states.

Bus cycle

ø

Internal address bus

Internal read signal

Read
access

Internal data bus

Internal write signal

Write
access

Internal data bus

Figure 2-17 On-Chip Memory Access Cycle

T1

Address

Read data

Write data

63

Bus cycle

T1

ø

UnchangedAddress bus

AS

RD

HWR, LWR

Data bus

High-impedance state

High

High

High

Figure 2-18 Pin States during On-Chip Memory Access

64

2.9.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the
access timing for the on-chip supporting modules. Figure 2-20 shows the pin states.

Bus cycle

T1 T2

ø

Internal address bus

Internal read signal

Read
access

Internal data bus

Internal write signal

Write
access

Internal data bus

Figure 2-19 On-Chip Supporting Module Access Cycle

Address

Read data

Write data

65

Bus cycle

T1 T2

ø

Address bus

AS

RD

HWR, LWR

Data bus

Unchanged

High

High

High

High-impedance state

Figure 2-20 Pin States during On-Chip Supporting Module Access

2.9.4 External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 7, Bus Controller.

2.10 Usage Note

2.10.1 TAS Instruction

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS
instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or
ER5 is used.

66

Section 3 MCU Operating Modes

3.1 Overview

3.1.1 Operating Mode Selection

The H8S/2633 Series has four operating modes (modes 4 to 7). These modes enable selection of
the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by
setting the mode pins (MD2 to MD0).

Table 3-1 lists the MCU operating modes.

Table 3-1 MCU Operating Mode Selection

MCU CPU
Operating

Mode MD2 MD1 MD0

0* 000— — — —
1* 1—
2* 10
3* 1
4 1 0 0 Advanced On-chip ROM disabled,

5 1 8 bits 16 bits
6 1 0 On-chip ROM enabled,

7 1 Single-chip mode —
Note: * Not available in the H8S/2633 Series.

Operating
Mode Description

expanded mode

expanded mode

On-Chip
ROM

Disabled 16 bits 16 bits

Enabled 8 bits 16 bits

External Data Bus

Initial
Width

Max.
Width

The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2633 Series actually
accesses a maximum of 16 Mbytes.

Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral
devices.

The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program
execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus
controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit
access is selected for all areas, 8-bit bus mode is set.

Note that the functions of each pin depend on the operating mode.

67

The H8S/2633 Series can be used only in modes 4 to 7. This means that the mode pins must be set
to select one of these modes. Do not change the inputs at the mode pins during operation.

3.1.2 Register Configuration

The H8S/2633 Series has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the
H8S/2633 Series. Table 3-2 summarizes these registers.

Table 3-2 MCU Registers

Name Abbreviation R/W Initial Value Address*

Mode control register MDCR R/W Undetermined H'FDE7
System control register SYSCR R/W H'01 H'FDE5
Pin function control register PFCR R/W H'0D/H'00 H'FDEB

Note: * Lower 16 bits of the address.

3.2 Register Descriptions

3.2.1 Mode Control Register (MDCR)

Bit

Initial value
R/W

Note: * Determined by pins MD2 to MD0.

:

:
:

7

—

1

R/W

MDCR is an 8-bit register that indicates the current operating mode of the H8S/2633 Series.

Bit 7—Reserved: Only 1 should be written to this bit.

Bits 6 to 3—Reserved: These bits always read as 0 and cannot be modified.

6

—

0

—

5

—

0

—

4

—

0

—

3

—

0

—

2

MDS2

—*

R

1

MDS1

—*

R

MDS0

—*

0

R

Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0.
MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input
levels are latched into these bits when MDCR is read. These latches are cancelled by a power-on
reset, but maintained by a manual reset.

68

3.2.2 System Control Register (SYSCR)

Bit

Initial value
R/W

:

:
:

7

MACS

0

R/W

6

—

0

—

5

INTM1

0

R/W

4

INTM0

0

R/W

3

NMIEG

0

R/W

2

MRESE

0

R/W

1

—

0

—

0

RAME

1

R/W

SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI,
enables or disenables MRES pin input, and enables or disenables on-chip RAM.

SYSCR is initialized to H'01 by a power-on reset and in hardware standby mode. MACS, INTM1,
INTM0, NMIEG, and RAME bits are initialized in manual reset mode, but the MRESE bit is not
initialized. SYSCR is not initialized in software standby mode.

Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the
MAC instruction.

Bit 7
MACS Description

0 Non-saturating calculation for MAC instruction (Initial value)
1 Saturating calculation for MAC instruction

Bit 6—Reserved: This bit always read as 0 and cannot be modified.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control

mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.

Bit 5 Bit 4
INTM1 INTM0 Control Mode Description

0 0 0 Control of interrupts by I bit (Initial value)

1 — Setting prohibited

1 0 2 Control of interrupts by I2 to I0 bits and IPR

1 — Setting prohibited

Interrupt

69

Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.

Bit 3
NMIEG Description

0 An interrupt is requested at the falling edge of NMI input (Initial value)
1 An interrupt is requested at the rising edge of NMI input

Bit 2—Manual Reset Selection Bit (MRESE): Enables or disenables manual reset input. It is
possible to set the P74/TM02/MRES pin to the manual reset input (MRES).

Table 3-3 shows the relationship between the MRES pin power-on reset and manual reset.

Bit 2
MRESE Description

0 Disenables manual reset.

Possible to use P74/TM02/MRES pin as P74/TM02 input pin. (Initial value)

1 Enables manual reset.

Possible to use P74/TM02/MRES pin as MRES input pin.

Table 3-3 Relationship Between Power-On Reset and Manual Reset

Pin

RES MRES Reset Type

0 * Power-on reset (Initial state)
1 0 Manual reset
1 1 Operation state

*: Don’t care

Bit 1—Reserved: This bit always read as 0 and cannot be modified.

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized when the reset status is released. It is not initialized in software standby mode.

Bit 0
RAME Description

0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)

Note: When the DTC is used, the RAME bit must be set to 1.

70

3.2.3 Pin Function Control Register (PFCR)

Bit

Initial value
R/W

:

:
:

7

CSS07

0

R/W

6

CSS36

0

R/W

5

BUZZE

0

R/W

4

LCASS

0

R/W

3

AE3

1/0

R/W

2

AE2

1/0

R/W

1

AE1

0

R/W

0

AE0

1/0

R/W

PFCR is an 8-bit readable-writable register that carries out CS selection control for PG4 and PG1
pins, LCAS selection control for PF2 and PF6 pins, and address output control during extension
modes with ROM.

PFCR is initialized by H'0D/H'00 by a power-on reset or a hardware standby mode. The
immediately previous state is maintained in manual reset or software standby mode.

Bit 7—CS0/CS7 Select (CSS07): Selects the CS output content for PG4 pin. In modes 4 to 6, the
selected CS is output by setting the corresponding DDR to 1.

Bit 7
CSS07 Description

0 Select CS0. (Initial value)
1 Select CS7.

Bit 6—CS3/CS6 Select (CSS36): Selects the CS output content for PG1 pin. In modes 4 to 6, the
selected CS is output by setting the corresponding DDR to 1.

Bit 6
CSS36 Description

0 Select CS3. (Initial value)
1 Select CS6

71

Bit 5—BUZZ Output Enable (BUZZE): Disenables/enables BUZZ output of PF1 pin. Input
clock of WDT1 selected by PSS, CKS2 to CKS0 bits is output as a BUZZ signal.

Bit 5
BUZZE Description

0 Functions as PF1 input pin (Initial value)
1 Functions as BUZZ output pin

Bit 4—LCAS Output Pin Selection Bit (LCASS): Selects the LCAS signal output pin.

Bit 4
LCASS Description

0 Outputs LCAS signal from PF2 (Initial Value)
1 Outputs LCAS signal from PF6

Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling
of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is
enabled for address output, the address is output regardless of the corresponding DDR setting.
When a pin is disabled for address output, it becomes an output port when the corresponding DDR
bit is set to 1.

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Bit 3 Bit 2 Bit 1 Bit 0
AE3 AE2 AE1 AE0 Description

0000A8–A23 address output disabled (Initial value*)

1 A8 address output enabled; A9–A23 address output disabled

1 0 A8, A9 address output enabled; A10–A23 address output

disabled

1A8–A10 address output enabled; A11–A23 address output

disabled

100A8–A11 address output enabled; A12–A23 address output

disabled

1A8–A12 address output enabled; A13–A23 address output

disabled

10A8–A13 address output enabled; A14–A23 address output

disabled

1A8–A14 address output enabled; A15–A23 address output

disabled

1000A8–A15 address output enabled; A16–A23 address output

disabled

1A8–A16 address output enabled; A17–A23 address output

disabled

10A8–A17 address output enabled; A18–A23 address output

disabled

1A8–A18 address output enabled; A19–A23 address output

disabled

100A8–A19 address output enabled; A20–A23 address output

disabled

1A8–A20 address output enabled; A21–A23 address output

disabled (Initial value*)

10A8–A21 address output enabled; A22, A23 address output

disabled

1A8–A23 address output enabled

Note: *In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.

In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to

1.

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