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H8/3635
Hardware Manual
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Hitachi H8/3637, H8/3635, H8/3636 Hardware Manual

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Page 1
H8/3637 Series
H8/3637, H8/3636, H8/3635
Hardware Manual
ADE-602-152 Rev. 1.0 8/1/98 Hitachi, Ltd. MC-Setsu
Page 2
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Page 3

Preface

The H8/300L Series of single-chip microcomputers has a high-speed H8/300L CPU core, with many necessary peripheral system functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU.
On-chip peripheral functions of the H8/3637 Series include a high-precision DTMF generator for tone dialing, a 14-bit PWM, five types of timers, two serial communication interface channels, and an A/D converter.
This manual describes the hardware of the H8/3637 Series. For details on the H8/3637 Series instruction set, refer to the H8/300L Series Programming Manual.
Page 4

Contents

Section 1 Overview........................................................................................................... 1
1.1 Overview............................................................................................................................ 1
1.2 Internal Block Diagram..................................................................................................... 5
1.3 Pin Arrangement and Functions........................................................................................ 6
1.3.1 Pin Arrangement .................................................................................................. 6
1.3.2 Pin Functions........................................................................................................ 8
Section 2 CPU..................................................................................................................... 13
2.1 Overview ........................................................................................................................... 13
2.1.1 Features ................................................................................................................ 13
2.1.2 Address Space ...................................................................................................... 14
2.1.3 Register Configuration ......................................................................................... 14
2.2 Register Descriptions......................................................................................................... 15
2.2.1 General Registers.................................................................................................. 15
2.2.2 Control Registers.................................................................................................. 15
2.2.3 Initial Register Values.......................................................................................... 17
2.3 Data Formats...................................................................................................................... 17
2.3.1 Data Formats in General Registers....................................................................... 18
2.3.2 Memory Data Formats.......................................................................................... 19
2.4 Addressing Modes............................................................................................................. 20
2.4.1 Addressing Modes................................................................................................ 20
2.4.2 Effective Address Calculation.............................................................................. 22
2.5 Instruction Set.................................................................................................................... 26
2.5.1 Data Transfer Instructions.................................................................................... 28
2.5.2 Arithmetic Operations.......................................................................................... 30
2.5.3 Logic Operations.................................................................................................. 31
2.5.4 Shift Operations.................................................................................................... 31
2.5.5 Bit Manipulations................................................................................................. 33
2.5.6 Branching Instructions.......................................................................................... 37
2.5.7 System Control Instructions ................................................................................. 39
2.5.8 Block Data Transfer Instruction ........................................................................... 40
2.6 Basic Operational Timing.................................................................................................. 42
2.6.1 Access to On-Chip Memory (RAM, ROM)......................................................... 42
2.6.2 Access to On-Chip Peripheral Modules ............................................................... 43
2.7 CPU States......................................................................................................................... 44
2.7.1 Overview.............................................................................................................. 44
2.7.2 Program Execution State...................................................................................... 46
2.7.3 Program Halt State ............................................................................................... 46
2.7.4 Exception-Handling State .................................................................................... 46
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2.8 Memory Map..................................................................................................................... 47
2.9 Application Notes.............................................................................................................. 48
2.9.1 Notes on Data Access........................................................................................... 48
2.9.2 Notes on Bit Manipulation ................................................................................... 50
2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 56
Section 3 Exception Handling........................................................................................ 57
3.1 Overview............................................................................................................................ 57
3.2 Reset.................................................................................................................................. 57
3.2.1 Overview.............................................................................................................. 57
3.2.2 Reset Sequence..................................................................................................... 57
3.2.3 Interrupt Immediately after Reset ........................................................................ 58
3.3 Interrupts............................................................................................................................ 59
3.3.1 Overview.............................................................................................................. 59
3.3.2 Interrupt Control Registers................................................................................... 61
3.3.3 External Interrupts................................................................................................ 69
3.3.4 Internal Interrupts................................................................................................. 70
3.3.5 Interrupt Operations.............................................................................................. 70
3.3.6 Interrupt Response Time ...................................................................................... 75
3.4 Application Notes.............................................................................................................. 76
3.4.1 Notes on Stack Area Use...................................................................................... 76
3.4.2 Notes on Rewriting Port Mode Registers............................................................. 76
Section 4 Clock Pulse Generators................................................................................. 79
4.1 Overview............................................................................................................................ 79
4.1.1 Block Diagram...................................................................................................... 79
4.1.2 System Clock and Subclock ................................................................................. 79
4.2 System Clock Generator.................................................................................................... 80
4.3 Subclock Generator ........................................................................................................... 83
4.4 Prescalers........................................................................................................................... 84
4.5 Note on Oscillators............................................................................................................ 84
Section 5 Power-Down Modes...................................................................................... 87
5.1 Overview............................................................................................................................ 87
5.1.1 System Control Registers ..................................................................................... 90
5.2 Sleep Mode........................................................................................................................ 93
5.2.1 Transition to Sleep Mode ..................................................................................... 93
5.2.2 Clearing Sleep Mode............................................................................................ 93
5.3 Standby Mode.................................................................................................................... 94
5.3.1 Transition to Standby Mode ................................................................................. 94
5.3.2 Clearing Standby Mode........................................................................................ 94
5.3.3 Oscillator Settling Time after Standby Mode is Cleared...................................... 95
5.3.4 Transition to Standby Mode and Pin States ......................................................... 96
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5.4 Watch Mode ...................................................................................................................... 97
5.4.1 Transition to Watch Mode.................................................................................... 97
5.4.2 Clearing Watch Mode .......................................................................................... 97
5.4.3 Oscillator Settling Time after Watch Mode is Cleared........................................ 97
5.5 Subsleep Mode .................................................................................................................. 98
5.5.1 Transition to Subsleep Mode................................................................................ 98
5.5.2 Clearing Subsleep Mode ...................................................................................... 98
5.6 Subactive Mode................................................................................................................. 99
5.6.1 Transition to Subactive Mode .............................................................................. 99
5.6.2 Clearing Subactive Mode ..................................................................................... 99
5.6.3 Operating Frequency in Subactive Mode............................................................. 99
5.7 Active (medium-speed) Mode........................................................................................... 100
5.7.1 Transition to Active (medium-speed) Mode ........................................................ 100
5.7.2 Clearing Active (medium-speed) Mode ............................................................... 100
5.7.3 Operating Frequency in Active (medium-speed) Mode....................................... 100
5.8 Direct Transfer................................................................................................................... 101
5.8.1 Overview.............................................................................................................. 101
5.8.2 Direct Transfer Time............................................................................................ 102
Section 6 ROM................................................................................................................... 105
6.1 Overview............................................................................................................................ 105
6.1.1 Block Diagram...................................................................................................... 105
6.2 PROM Mode...................................................................................................................... 106
6.2.1 Selection of PROM Mode.................................................................................... 106
6.2.2 Socket Adapter Pin Arrangement and Memory Map........................................... 106
6.3 Programming ..................................................................................................................... 109
6.3.1 Programming and Verification............................................................................. 110
6.3.2 Programming Precautions .................................................................................... 114
6.4 Reliability of Programmed Data........................................................................................ 115
Section 7 RAM................................................................................................................... 117
7.1 Overview............................................................................................................................ 117
7.1.1 Block Diagram...................................................................................................... 117
Section 8 I/O Ports ............................................................................................................ 119
8.1 Overview............................................................................................................................ 119
8.2 Port 1.................................................................................................................................. 121
8.2.1 Overview.............................................................................................................. 121
8.2.2 Register Configuration and Description............................................................... 121
8.2.3 Pin Functions........................................................................................................ 125
8.2.4 Pin States.............................................................................................................. 127
8.2.5 MOS Input Pull-Up .............................................................................................. 127
8.3 Port 2.................................................................................................................................. 128
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8.3.1 Overview.............................................................................................................. 128
8.3.2 Register Configuration and Description............................................................... 128
8.3.3 Pin Functions........................................................................................................ 133
8.3.4 Pin States.............................................................................................................. 135
8.3.5 MOS Input Pull-Up.............................................................................................. 135
8.4 Port 5.................................................................................................................................. 136
8.4.1 Overview.............................................................................................................. 136
8.4.2 Register Configuration and Description............................................................... 136
8.4.3 Pin Functions........................................................................................................ 138
8.4.4 Pin States.............................................................................................................. 139
8.4.5 MOS Input Pull-Up .............................................................................................. 139
8.5 Port 6.................................................................................................................................. 140
8.5.1 Overview.............................................................................................................. 140
8.5.2 Register Configuration and Description............................................................... 140
8.5.3 Pin Functions........................................................................................................ 142
8.5.4 Pin States.............................................................................................................. 142
8.5.5 MOS Input Pull-Up .............................................................................................. 142
8.6 Port 7.................................................................................................................................. 143
8.6.1 Overview.............................................................................................................. 143
8.6.2 Register Configuration and Description............................................................... 143
8.6.3 Pin Functions........................................................................................................ 145
8.6.4 Pin States.............................................................................................................. 145
8.7 Port 8.................................................................................................................................. 146
8.7.1 Overview.............................................................................................................. 146
8.7.2 Register Configuration and Description............................................................... 146
8.7.3 Pin Functions........................................................................................................ 148
8.7.4 Pin States.............................................................................................................. 148
8.8 Port 9.................................................................................................................................. 149
8.8.1 Overview.............................................................................................................. 149
8.8.2 Register Configuration and Description............................................................... 149
8.8.3 Pin Functions........................................................................................................ 151
8.8.4 Pin States.............................................................................................................. 151
8.9 Port A................................................................................................................................. 152
8.9.1 Overview.............................................................................................................. 152
8.9.2 Register Configuration and Description............................................................... 152
8.9.3 Pin Functions........................................................................................................ 154
8.9.4 Pin States.............................................................................................................. 154
8.10 Port B................................................................................................................................. 155
8.10.1 Overview.............................................................................................................. 155
8.10.2 Register Configuration and Description............................................................... 155
8.11 Port E................................................................................................................................. 156
8.11.1 Overview.............................................................................................................. 156
8.11.2 Register Configuration and Description............................................................... 156
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8.11.3 Pin Functions........................................................................................................ 157
8.11.4 Pin States.............................................................................................................. 157
Section 9 Timers................................................................................................................ 159
9.1 Overview............................................................................................................................ 159
9.2 Timer A.............................................................................................................................. 160
9.2.1 Overview.............................................................................................................. 160
9.2.2 Register Descriptions............................................................................................ 161
9.2.3 Timer Operation ................................................................................................... 163
9.2.4 Timer A Operation States..................................................................................... 164
9.3 Timer F.............................................................................................................................. 165
9.3.1 Overview.............................................................................................................. 165
9.3.2 Register Descriptions............................................................................................ 167
9.3.3 Interface with the CPU ......................................................................................... 174
9.3.4 Timer Operation ................................................................................................... 177
9.3.5 Application Notes................................................................................................. 179
9.4 Timer G.............................................................................................................................. 181
9.4.1 Overview.............................................................................................................. 181
9.4.2 Register Descriptions............................................................................................ 183
9.4.3 Noise Canceller Circuit ........................................................................................ 187
9.4.4 Timer Operation ................................................................................................... 188
9.4.5 Application Notes................................................................................................. 192
9.4.6 Sample Timer G Application................................................................................ 196
9.5 Timer Y.............................................................................................................................. 196
9.5.1 Overview.............................................................................................................. 196
9.5.2 Register Descriptions............................................................................................ 198
9.5.3 Interface with the CPU ......................................................................................... 200
9.5.4 Operation.............................................................................................................. 203
9.5.5 Timer Y Operating Modes.................................................................................... 204
9.6 Watchdog Timer................................................................................................................ 204
9.6.1 Overview.............................................................................................................. 204
9.6.2 Register Descriptions............................................................................................ 206
9.6.3 Operation.............................................................................................................. 208
9.6.4 Watchdog Timer Operating Modes...................................................................... 209
Section 10 Serial Communication Interface................................................................ 211
10.1 Overview............................................................................................................................ 211
10.2 SCI1................................................................................................................................... 211
10.2.1 Overview.............................................................................................................. 211
10.2.2 Register Descriptions............................................................................................ 213
10.2.3 Operation.............................................................................................................. 217
10.2.4 Interrupt Sources .................................................................................................. 219
10.3 SCI3................................................................................................................................... 220
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10.3.1 Overview.............................................................................................................. 220
10.3.2 Register Descriptions............................................................................................ 222
10.3.3 Operation.............................................................................................................. 239
10.3.4 Operation in Asynchronous Mode........................................................................ 244
10.3.5 Operation in Synchronous Mode.......................................................................... 252
10.3.6 Multiprocessor Communication Function............................................................ 260
10.3.7 Interrupts .............................................................................................................. 266
10.3.8 Application Notes................................................................................................. 267
Section 11 DTMF Generator............................................................................................ 271
11.1 Overview............................................................................................................................ 271
11.1.1 Features ................................................................................................................ 272
11.1.2 Block Diagram...................................................................................................... 273
11.1.3 Pin Configuration ................................................................................................. 274
11.1.4 Register Configuration ......................................................................................... 274
11.2 Register Descriptions......................................................................................................... 275
11.2.1 DTMF Control Register (DTCR)......................................................................... 275
11.2.2 DTMF Load Register (DTLR) ............................................................................. 277
11.3 Operation ........................................................................................................................... 278
11.3.1 Output Waveform................................................................................................. 278
11.3.2 Operation Flow..................................................................................................... 279
11.4 Typical Use........................................................................................................................ 280
11.5 Application Notes.............................................................................................................. 280
Section 12 A/D Converter ................................................................................................. 281
12.1 Overview............................................................................................................................ 281
12.1.1 Features ................................................................................................................ 281
12.1.2 Block Diagram...................................................................................................... 282
12.1.3 Pin Configuration ................................................................................................. 283
12.1.4 Register Configuration ......................................................................................... 283
12.2 Register Descriptions......................................................................................................... 284
12.2.1 A/D Result Register (ADRR)............................................................................... 284
12.2.2 A/D Mode Register (AMR).................................................................................. 284
12.2.3 A/D Start Register (ADSR).................................................................................. 286
12.3 Operation ........................................................................................................................... 287
12.3.1 A/D Conversion Operation................................................................................... 287
12.3.2 Start of A/D Conversion by External Trigger Input............................................. 287
12.4 Interrupts............................................................................................................................ 288
12.5 Typical Use........................................................................................................................ 288
12.6 Application Notes.............................................................................................................. 291
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Section 13 14-bit Pulse Width Modulator (PWM).................................................... 293
13.1 Overview............................................................................................................................ 293
13.1.1 Features ................................................................................................................ 293
13.1.2 Block Diagram...................................................................................................... 293
13.1.3 Pin Configuration ................................................................................................. 294
13.1.4 Register Configuration ......................................................................................... 294
13.2 Register Descriptions......................................................................................................... 294
13.2.1 PWM Control Register (PWCR).......................................................................... 294
13.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 295
13.3 Operation ........................................................................................................................... 296
Section 14 Electrical Characteristics.............................................................................. 297
14.1 Absolute Maximum Ratings.............................................................................................. 297
14.2 Electrical Characteristics................................................................................................... 298
14.2.1 Power Supply Voltage and Operating Range....................................................... 298
14.2.2 DC Characteristics................................................................................................ 300
14.2.3 AC Characteristics................................................................................................ 305
14.2.4 A/D Converter Characteristics ............................................................................. 308
14.2.5 DTMF Characteristics.......................................................................................... 309
14.3 Operation Timing .............................................................................................................. 310
14.4 Output Load Circuits ......................................................................................................... 313
Appendix A CPU Instruction Set ................................................................................... 315
A.1 Instructions........................................................................................................................ 315
A.2 Operation Code Map.......................................................................................................... 323
A.3 Number of Execution States.............................................................................................. 325
Appendix B On-Chip Registers...................................................................................... 332
B.1 I/O Registers (1) ................................................................................................................ 332
B.2 I/O Registers (2) ................................................................................................................ 336
Appendix C I/O Port Block Diagrams.......................................................................... 375
C.1 Port 1 Block Diagrams ...................................................................................................... 375
C.2 Port 2 Block Diagrams ...................................................................................................... 382
C.3 Port 5 Block Diagram........................................................................................................ 390
C.4 Port 6 Block Diagram........................................................................................................ 391
C.5 Port 7 Block Diagram........................................................................................................ 392
C.6 Port 8 Block Diagram........................................................................................................ 393
C.7 Port 9 Block Diagram........................................................................................................ 394
C.8 Port A Block Diagram ....................................................................................................... 395
C.9 Port B Block Diagram ....................................................................................................... 395
C.10 Port E Block Diagram........................................................................................................ 396
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Appendix D Port States in the Different Processing States.................................... 397
Appendix E Product Line-Up.......................................................................................... 398
Appendix F Package Dimensions.................................................................................. 399
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Section 1 Overview

1.1 Overview

The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3637 Series of single-chip microcomputers features a high­precision DTMF generator for tone dialing. Other on-chip peripheral functions include five types of timers, two serial communication interface channels, an A/D converter, and a 14-bit pulse width modulator (PWM). The H8/3637 Series includes three models, the H8/3637, H8/3636, and H8/3635, with different amounts of on-chip memory: the H8/3637 has 60 kbytes of ROM and 2 kbytes of RAM; the H8/3636 has 48 kbytes of ROM and 2 kbytes of RAM; and the H8/3635 has 40 kbytes of ROM and 2 kbytes of RAM.
The H8/3637 has a ZTAT version with user-programmable on-chip PROM.
Table 1.1 summarizes the features of the H8/3637 Series.
Note: * ZTATTM is a trademark of Hitachi, Ltd.
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Page 13
Table 1.1 Features
Item Description
CPU High-speed H8/300L CPU
• General-register architectureGeneral registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
• Operating speedMax. operating speed: 5 MHzAdd/subtract: 0.4 µs (operating at ø= 5 MHz)Multiply/divide: 2.8 µs (operating at ø= 5 MHz)Can run on 32.768 kHz subclock
• Instruction set compatible with H8/300 CPUInstruction length of 2 bytes or 4 bytesBasic arithmetic operations between registersMOV instruction for data transfer between memory and registers
• Instruction featuresMultiply (8 bits × 8 bits)Divide (16 bits ÷ 8 bits)Bit accumulatorRegister-indirect designation of bit position
Interrupts 30 interrupt sources
• 13 external interrupt sources: IRQ
• 17 internal interrupt sources
Clock pulse generators
Power-down modes
Two on-chip clock pulse generators
• System clock pulse generator: 1 MHz to 10 MHz
• Subclock pulse generator: 32.768 kHz
Six power-down modes
• Sleep mode
• Standby mode
• Watch mode
• Subsleep mode
• Subactive mode
• Active (medium-speed) mode
to IRQ0, WKP7 to WKP
4
0
2
Page 14
Table 1.1 Features (cont)
Item Description
Memory Large on-chip memory
• H8/3637: 60-kbyte ROM, 2-kbyte RAM
• H8/3636: 48-kbyte ROM, 2-kbyte RAM
• H8/3635: 40-kbyte ROM, 2-kbyte RAM
I/O ports 66 I/O ports
• I/O pins: 61
• Input pins: 5
Timers Five on-chip timers
• Timer A: 8-bit timer with built-in interval/watch clock time base functionCount-up timer with selection of eight internal clock signals divided from
the system clock (ø)* and four clock signals divided from the watch clock (ø
• Timer F: 16-bit timer with built-in output compare functionCan be used as two independent 8-bit timers.Count-up timer with selection of four internal clock signals or event
input from external pin
Compare-match function with toggle output
• Timer G: 8-bit timer with built-in input capture/interval functionsCount-up timer with selection of four internal clock signalsInput capture function with built-in noise canceller circuit
• Timer Y: 16-bit timer with built-in interval/auto-reload functionsCount-up timer with selection of seven internal clocks or event input
from external pin
Auto-reload function
• Watchdog timerReset signal generated on 8-bit timer overflow
Serial communication interface
Two serial communication interface channels on chip
• SCI1: synchronous serial interfaceChoice of 8-bit or 16-bit data transfer
• SCI3: 8-bit synchronous or asynchronous serial interfaceBuilt-in function for multiprocessor communication
Note: *ø and øw are defined in section 4, Clock Pulse Generators.
)*
w
3
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Table 1.1 Features (cont)
Item Description
A/D converter 8-bit successive-approximations A/D converter using a resistance ladder
• 4-channel analog input port
• Conversion time: 31/ø, 62/ø or 124/ø per channel
DTMF generator Built-in tone dialer supporting OSC clock frequencies from 1.2 MHz to 10 MHz
in 400-kHz steps
14-bit PWM Pulse-division PWM to reduce ripple
• Can be used as a 14-bit D/A converter by connecting a low-pass filter externally
Product lineup Product Code
Mask ROM Version
HD6433637F HD6473637F 80-pin QFP
HD6433637X HD6473637X 80-pin TQFP
HD6433637W HD6473637W 80-pin TQFP
HD6433636F — 80-pin QFP
HD6433636X — 80-pin TQFP
HD6433636W — 80-pin TQFP
HD6433635F — 80-pin QFP
HD6433635X — 80-pin TQFP
HD6433635W — 80-pin TQFP
ZTAT™ Version Package ROM/RAM Size
ROM: 60 kbytes
(FP-80B)
(TFP-80F)
(TFP-80C)
(FP-80B)
(TFP-80F)
(TFP-80C)
(FP-80B)
(TFP-80F)
(TFP-80C)
RAM: 2 kbytes
ROM: 48 kbytes RAM: 2 kbytes
ROM: 40 kbytes RAM: 2 kbytes
4
Page 16

1.2 Internal Block Diagram

Figure 1.1 shows a block diagram of the H8/3637 Series.
P10/TMOW P1
/TMOFL
1
P1
/TMOFH
2
P1
/TMIG
3
P1
/PWM
4
P1
/IRQ1
5
P16/IRQ2/TMCIY P1
/IRQ3/TMIF
7
/IRQ4/ADTRG
P2
0
P2
/SCK1
1
P2
/SI1
2
P2
/SO1
3
P2
/SCK3
4
P2
/RXD
5
P2
/TXD
6
P2
/IRQ0
7
/WKP0
P5
0
P5
/WKP1
1
P5
/WKP2
2
P5
/WKP3
3
P5
/WKP4
4
P5
/WKP5
5
P5
/WKP6
6
P5
/WKP7
7
VSSVSSVCCV
CC
RES
TEST
OSC2OSC1X1X
2
CPU (8-bit)
generator
System clock
Subclock pulse
pulse generator
Address bus
Data bus (upper)
Data bus (lower)
ROM (40 k/48 k/ 60 kbytes)
Timer A
RAM
(2 kbytes)
SCI1
Timer F
Timer G
P6
0
P6
1
P6
2
P6
3
P6
4
Port 6 Port 5 Port 2 Port 1
P6
5
P6
6
P6
7
Timer Y
WDT DTMF
SCI3
PWM
A/D converter
Port EPort APort 9Port 8Port 7
PE
3
PE
2
PA
3
PA
2
PA
1
PA
0
P9
7
P9
6
P9
5
P9
4
P9
3
P9
2
P9
1
P9
0
P8
7
P8
6
P8
5
P8
4
P8
3
P8
2
P8
1
P8
0
P7
7
P7
6
P7
5
P7
4
P7
3
P7
2
P7
1
P7
0
Port B
4
5
6
AVCCAV
SS
/AN
4
PB
/AN
5
PB
/AN
6
PB
7
/AN
7
PB
Figure 1.1 Block Diagram
ref
VT
TONED
5
Page 17

1.3 Pin Arrangement and Functions

1.3.1 Pin Arrangement
The H8/3637 Series pin arrangement is shown in figure 1.2 and 1.3.
P8 P8 P9 P9 P9 P9 P9 P9 P9 P9 PE PE
TONED
VT
AV PB7/AN PB6/AN PB5/AN PB4/AN
AV
P85P84P83P82P81P80P77P76P75P74P73P72P71P70P67P66P65P64P63P6
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
6
62
7
63
0
64
1
65
2
66
3
67
4
68
5
69
6
70
7
71
2
72
3
73 74
ref
75
CC
76
7
77
6
78
5
79
4
80
SS
1234567891011121314151617181920
2
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P6
1
P6
0
P57/WKP P56/WKP P55/WKP P54/WKP P53/WKP P52/WKP P51/WKP P50/WKP PA
0
PA
1
PA
2
PA
3
V
CC
V
SS
P10/TMOW P1
/TMOFL
1
P1
/TMOFH
2
P1
/TMIG
3
7
6
5
4
3
2
1
0
/TMIF
3
/IRQ
7
P1
1
/IRQ
5
/TMCIY
2
P1
/IRQ
6
P1
/PWM
4
P1
X1X
1
1
1
SS
V
1
OSC2OSC
TEST
CC
V
RES
/SCK
1
2
P2
/IRQ4/ADTRG
0
/SI
2
P2
/SO
3
P2
3
/SCK
4
P2
/RXD
5
P2
/TXD
6
P2
/IRQ0
7
P2
P2
Figure 1.2 Pin Arrangement (TFP-80F, TFP-80C: Top View)
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P87P86P85P84P83P82P81P80P77P76P75P74P73P72P71P70P67P66P65P64P63P62P61P6
0
PE PE
TONED
VT
AV PB7/AN PB6/AN PB5/AN
P9
65
0
P9
66
1
P9
67
2
P9
68
3
P9
69
4
P9
70
5
P9
71
6
P9
72
7
73
2
74
3
75 76
ref
77
CC
78
7
79
6
80
5
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
P57/WKP P56/WKP P55/WKP P54/WKP P53/WKP P52/WKP P51/WKP P50/WKP PA
0
PA
1
PA
2
PA
3
V
CC
V
SS
P10/TMOW P1
/TMOFL
1
7
6
5
4
3
2
1
0
123456789101112131415161718192021222324
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
4
/AN
4
PB
AV
/RXD
5
P2
/TXD
6
P2
0
/IRQ
7
P2
1
1
1
SS
V
1
OSC2OSC
TEST
CC
V
RES
/SCK
1
/ADTRG
4
P2
/IRQ
0
P2
2
SS
X1X
3
/SI
2
/SO
3
/SCK
4
P2
P2
P2
/TMIF
3
/IRQ
7
P1
/IRQ
/TMCIY
2
P1
/IRQ
6
P1
1
/PWM
5
/TMIG
4
3
/TMOFH
2
P1
P1
P1
Figure 1.3 Pin Arrangement (FP-80B: Top View)
7
Page 19
1.3.2 Pin Functions
Table 1.2 outlines the pin functions.
Table 1.2 Pin Functions
Pin No.
TFP-80F
Type Symbol
Power
V
CC
source pins
V
SS
AV
CC
AV
SS
VT
ref
Clock pins OSC
OSC
TFP-80C FP-80B I/O Name and Functions
7, 26 9, 28 Input Power supply: All VCC pins should be
3, 25 5, 27 Input Ground: All VSS pins should be
75 77 Input Analog power supply: This is the power
80 2 Input Analog ground: This is the A/D
74 76 Input DTMF generator reference level: This
5 7 Input System clock: These pins connect to a
1
4 6 Output
2
connected to the system power supply (+5 V)
connected to the system power supply (0 V)
supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V).
converter ground pin. It should be connected to the system power supply (0 V).
is a power supply pin for the reference level for DTMF.
crystal or ceramic oscillator, or can be used to input an external clock. See
section 4, Clock Pulse Generators, for a typical connection diagram.
System control
8
X
1
1 3 Input Subclock: These pins connect to a
32.768-kHz crystal oscillator. See section
X
2
2 4 Output
4, Clock Pulse Generators, for a typical connection diagram.
RES 8 10 Input Reset: When this pin is driven low, the
chip is reset
TEST 6 8 Input Test: This is a test pin, not for use in
applica-tion systems. It should be connected to V
.
SS
Page 20
Table 1.2 Pin Functions (cont)
Pin No.
TFP-80F
Type Symbol
Interrupt pins
IRQ IRQ IRQ IRQ IRQ
0 1 2 3 4
WKP WKP
Timer pins TMOW 24 26 Output Clock output: This is an output pin for
TMIF 17 19 Input Timer F event counter input: This is an
TMOFL 23 25 Output Timer FL output: This is an output pin
TMOFH 22 24 Output Timer FH output: This is an output pin
TMIG 21 23 Input Timer G capture input: This is an input
TMCIY 18 20 Input Timer Y clock input: This pin inputs an
14-bit PWM PWM 20 22 Output 14-bit PWM output: This pin outputs the
TFP-80C FP-80B I/O Name and Functions
16 19 18 17 9
to
38 to 31 40 to 33 Input Wakeup interrupt request 0 to 7:
7 0
18 21 20 19 11
Input External interrupt request 0 to 4:
These are input pins for external interrupts for which there is a choice between rising and falling edge sensing
These are input pins for external interrupts that are detected at the falling edge
wave-forms generated by the timer A output circuit
event input pin for input to the timer F counter
for waveforms generated by the timer FL output compare function
for waveforms generated by the timer FH output compare function
pin for the timer G input capture function
external clock to the timer Y counter.
waveform generated by the 14-bit PWM.
9
Page 21
Table 1.2 Pin Functions (cont)
Pin No.
TFP-80F
Type Symbol
I/O ports PB7 to
PB
4
PA3 to PA
0
PE3, PE272, 71 74, 73 I/O Port E: This is a 2-bit I/O port. Input or
P17 to P1
0
P2
7
P26 to P2
0
P57 to P5
0
P67 to P6
0
P77 to P7
0
P87 to P8
0
P97 to P9
0
TFP-80C FP-80B I/O Name and Functions
76 to 79 78 to 80,1Input Port B: This is a 4-bit input port
27 to 30 29 to 32 I/O Port A: This is a 4-bit I/O port. Input or
17 to 24 19 to 26 I/O Port 1: This is an 8-bit I/O port. Input or
16 18 Input Port 2 (bit 7): This is a 1-bit input port. 15 to 9 17 to 11 I/O Port 2 (bits 6 to 0): This is a 7-bit I/O
38 to 31 40 to 33 I/O Port 5: This is an 8-bit I/O port. Input or
46 to 39 48 to 41 I/O Port 6: This is an 8-bit I/O port. Input or
54 to 47 56 to 49 I/O Port 7: This is an 8-bit I/O port. Input or
62 to 55 64 to 57 I/O Port 8: This is an 8-bit I/O port. Input or
70 to 63 72 to 65 I/O Port 9: This is an 8-bit I/O port. Input or
output can be designated for each bit by means of port control register A (PCRA).
output can be designated for each bit by means of port control register E (PCRE).
output can be designated for each bit be means of port control register 1 (PCR1).
port. Input or output can be designated for each bit by means of port control register 2 (PCR2).
output can be designated for each bit by means of port control register 5 (PCR5).
output can be designated for each bit by means of port control register 6 (PCR6).
output can be designated for each bit by means of port control register 7 (PCR7).
output can be designated for each bit by means of port control register 8 (PCR8).
output can be designated for each bit by means of port control register 9 (PCR9).
10
Page 22
Table 1.2 Pin Functions (cont)
Pin No.
TFP-80F
Type Symbol
Serial com-
SI
1
munication interface
(SCI)
SO
1
SCK
RXD 14 16 Input SCI3 receive data input: This is the
TXD 15 17 Output SCI3 send data output: This is the SCI3
SCK
A/D c onv er ter
AN7 to AN
4
ADTRG 9 11 Input A/D converter trigger input: This is the
DTMF
TONED 73 75 Output DTMF signal: This is the output pin for
generator
TFP-80C FP-80B I/O Name and Functions
11 13 Input SCI1 receive data input: This is the
12 14 Output SCI1 send data output: This is the SCI1
10 12 I/O SCI1 clock I/O :This is the SCI1 clock
1
13 15 I/O SCI3 clock I/O: This is the SCI3 clock
3
76 to 79 78 to 80,1Input Analog input channels 4 to 7: These
SCI1 data input pin
data output pin
I/O pin
SCI3 data input pin
data output pin
I/O pin
are analog data input channels to the A/D converter
external trigger input pin to the A/D converter
the DTMF signal
11
Page 23
Section 2 CPU

2.1 Overview

The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation.
2.1.1 Features
Features of the H8/300L CPU are listed below.
• General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
• Instruction set with 55 basic instructions, including:Multiply and divide instructionsPowerful bit-manipulation instructions
• Eight addressing modesRegister directRegister indirectRegister indirect with displacementRegister indirect with post-increment or pre-decrementAbsolute addressImmediateProgram-counter relativeMemory indirect
• 64-kbyte address space
• High-speed operationAll frequently used instructions are executed in two to four statesHigh-speed arithmetic and logic operations
8- or 16-bit register-register add or subtract: 0.4 µs* 8 × 8-bit multiply: 2.8 µs* 16 ÷ 8-bit divide: 2.8 µs*
• Low-power operation modes SLEEP instruction for transition to low-power operation
Note: * These values are at ø = 5 MHz.
13
Page 24
2.1.2 Address Space
The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data.
See 2.8, Memory Map, for details of the memory map.
2.1.3 Register Configuration
Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
General registers (Rn)
7070
R0H R1H R2H R3H R4H R5H R6H R7H
(SP)
R0L R1L R2L R3L R4L R5L R6L R7L
SP: Stack Pointer
14
Control registers (CR)
15 0
PC
75321064
CCR I U H U N Z V C
Figure 2.1 CPU Registers
PC: Program Counter
CCR: Condition Code Register Carry flag
Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit
Page 25

2.2 Register Descriptions

2.2.1 General Registers
All the general registers have the same functions, and can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception handling and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7) points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2.2 Stack Pointer
2.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0).
15
Page 26
(2) Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions.
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see 3.3, Interrupts.
Bit 6—User Bit (U): Can be used freely by the user.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be used freely by the user.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift/rotate carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits.
16
Page 27
2.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. R7 initialization should therefore be carried out immediately after a reset.

2.3 Data Formats

The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data.
Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7).
All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU
(16 bits ÷ 8 bits) instructions operate on word data.
The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in two-digit 4-bit BCD form.
17
Page 28
2.3.1 Data Formats in General Registers
General register data formats are shown in figure 2.3.
Data Type Register No. Data Format
70
1-bit data RnH
1-bit data RnL
Byte data RnH
Byte data RnL
Word data Rn
4-bit BCD data RnH
76543210 Don’t care
70
MSB LSB Don’t care
15 0
MSB LSB
7034
Upper digit Lower digit
70
76543210Don’t care
70
MSB LSBDon’t care
Don’t care
4-bit BCD data RnL
Legend:
Upper byte of general register
RnH:
Lower byte of general register
RnL:
Most significant bit
MSB:
Least significant bit
LSB:
18
70
Don’t care
Figure 2.3 Register Data Formats
34
Upper digit Lower digit
Page 29
2.3.2 Memory Data Formats
Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching.
1-bit data
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
CCR: Condition code register Note: Ignored on return*
AddressData Type
Address n
Address n
Even address
Odd address
Even address
Odd address
Even address
Odd address
Data Format
70
76543210
MSB LSB
MSB
MSB LSBCCR MSB LSB
MSB
Upper 8 bits Lower 8 bits
CCR*
LSB
LSB
Figure 2.4 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored.
19
Page 30

2.4 Addressing Modes

2.4.1 Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes.
Table 2.1 Addressing Modes
No. Address Modes Symbol
1 Register direct Rn 2 Register indirect @Rn 3 Register indirect with displacement @(d:16, Rn) 4 Register indirect with post-increment
Register indirect with pre-decrement 5 Absolute address @aa:8 or @aa:16 6 Immediate #xx:8 or #xx:16 7 Program-counter relative @(d:8, PC) 8 Memory indirect @@aa:8
1. Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand.
@Rn+ @–Rn
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory.
3. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even.
20
Page 31
4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
• Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of
the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
• Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by
1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even.
5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535).
6. Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number.
7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address. The result of the addition should be an even number.
21
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8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information.
2.4.2 Effective Address Calculation
Table 2.2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position.
22
Page 33
Table 2.2 Effective Address Calculation
No.
1
2
3
4
Addressing Mode and Instruction Format
Register direct, Rn
87 34015
op rm rn
Register indirect, @Rn
76 34015
op rm
Register indirect with displacement, @(d:16, Rn)
76 34015
op rm
disp
Register indirect with post-increment, @Rn+
76 34015
op rm
Register indirect with pre-decrement, @–Rn
76 34015
op rm
Effective Address Calculation Method Effective Address (EA)
30rn30
rm
Operand is contents of registers indicated by rm/rn
015
Contents (16 bits) of
register indicated by rm
015
Contents (16 bits) of
register indicated by rm
disp
015
Contents (16 bits) of
register indicated by rm
1 or 2
015
Contents (16 bits) of
register indicated by rm
Incremented or decremented by 1 if operand is byte size,
1 or 2
and by 2 if word size
015
015
015
015
23
Page 34
Table 2.2 Effective Address Calculation (cont)
Addressing Mode and
No.
Instruction Format
5
Absolute address @aa:8
op
@aa:16
6
Immediate #xx:8
op
#xx:16
87 015
op
abs
87 015
op
IMM
abs
IMM
Effective Address Calculation Method Effective Address (EA)
87 015
H'FF
015
015
Operand is 1- or 2-byte immediate data
015
7
24
Program-counter relative @(d:8, PC)
7015
8
op disp
PC contents
Sign
extension
015
015
disp
Page 35
Table 2.2 Effective Address Calculation (cont)
Addressing Mode and
No.
8
Instruction Format
Memory indirect, @@aa:8
87 015
op
Legend: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address
abs
Effective Address Calculation Method Effective Address (EA)
87 015
H'00
abs
Memory contents
(16 bits)
015
25
Page 36

2.5 Instruction Set

The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3.
Table 2.3 Instruction Set
Function Instructions Number
*1
*1
Data transfer MOV, PUSH Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,
SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,
ROTXL, ROTXR Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Branch Bcc*2, JMP, BSR, JSR, RTS 5 System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8 Block data transfer EEPMOV 1
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn. The machine language is also the same.
2. Bcc is a conditional branch instruction in which cc represents a condition code.
, POP
1 14
8
14
Total: 55
The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next.
The functions of the instructions are shown in tables 2.4 to 2.11. The meaning of the operation symbols used in the tables is as follows.
26
Page 37
Notation
Rd General register (destination) Rs General register (source) Rn General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction
× Multiplication ÷ Division ∧ AND logical ∨ OR logical ⊕ Exclusive OR logical → Move
~ Logical negation (logical complement) :3 3-bit length :8 8-bit length :16 16-bit length ( ), < > Contents of operand indicated by effective address
27
Page 38
2.5.1 Data Transfer Instructions
Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats.
Table 2.4 Data Transfer Instructions
Instruction Size* Function
MOV B/W (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for byte or word data. The @aa:8
addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes. POP W @SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn. PUSH W Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to
MOV.W Rn, @–SP. Note: *Size: Operand size
B: Byte W: Word
Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details.
28
Page 39
15 087
op rm rn
15 087
op rm rn
15 087
op rm rn
disp
MOV Rm→Rn
@Rm←→Rn
@(d:16, Rm)←→Rn
15 087
op rm rn
15 087
op rn abs
15 087
op rn
abs
15 087
op rn IMM
15 087
op rn
IMM
15 087
op rn
Legend: op: rm, rn: disp: abs: IMM:
Operation field Register field Displacement Absolute address Immediate data
111
@Rm+→Rn, or Rn →@–Rm
@aa:8←→Rn
@aa:16←→Rn
#xx:8→Rn
#xx:16→Rn
PUSH, POP @SP+ Rn, or
→
Rn @–SP
→
Figure 2.5 Data Transfer Instruction Codes
29
Page 40
2.5.2 Arithmetic Operations
Table 2.5 describes the arithmetic instructions.
Table 2.5 Arithmetic Instructions
Instruction Size* Function
ADD SUB
ADDX SUBX
INC DEC
ADDS SUBS
DAA DAS
MULXU B Rd × Rs → Rd
DIVXU B Rd ÷ Rs → Rd
CMP B/W Rd – Rs, Rd – #IMM
NEG B 0 – Rd → Rd
Note: *Size: Operand size
B: Byte W: Word
B/W Rd ± Rs → Rd, Rd + #IMM → Rd
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data
can be added or subtracted only when both words are in general
registers.
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data
and data in a general register.
B Rd ± 1 → Rd
Increments or decrements a general register
W Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts immediate data to or from data in a general
register. The immediate data must be 1 or 2.
B Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed 4-bit BCD) an addition or
subtraction result in a general register by referring to the CCR
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder
Compares data in a general register with data in another general
register or with immediate data, and the result is stored in the CCR.
Word data can be compared only between two general registers.
Obtains the two’s complement (arithmetic complement) of data in a
general register
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2.5.3 Logic Operations
Table 2.6 describes the four instructions that perform logic operations.
Table 2.6 Logic Operation Instructions
Instruction Size* Function
AND B Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another general register or immediate data
OR B Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another general register or immediate data
XOR B Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and another general register or immediate data
NOT B ~ Rd → Rd
Obtains the one’s complement (logical complement) of general register contents
Note: *Size: Operand size
B: Byte
2.5.4 Shift Operations
Table 2.7 describes the eight shift instructions.
Table 2.7 Shift Instructions
Instruction Size* Function
SHAL SHAR SHLL SHLR
ROTL ROTR
ROTXL ROTXR Note: *Size: Operand size
B: Byte
B Rd shift → Rd
Performs an arithmetic shift operation on general register contents
B Rd shift → Rd
Performs a logical shift operation on general register contents
B Rd rotate → Rd
Rotates general register contents
B Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit
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Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15 087
op rm rn
15 087
op rn
15 087
op rn
15 087
op
15 087
rn IMM
op rn
15 087
op
15 087
rn IMM
op
Legend: op: rm, rn: IMM:
Operation field Register field Immediate data
rm
rm
ADD, SUB, CMP, ADDX, SUBX (Rm)
ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT
MULXU, DIVXU
ADD, ADDX, SUBX, CMP (#XX:8)
AND, OR, XOR (Rm)
AND, OR, XOR (#xx:8)
rn
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
32
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
Page 43
2.5.5 Bit Manipulations
Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats.
Table 2.8 Bit-Manipulation Instructions
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BTST B ~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory, and stores the result in the C flag.
BIAND B C ∧ [~ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag.
BIOR B C ∨ [~ (<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
Note: *Size: Operand size
B: Byte
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Table 2.8 Bit-Manipulation Instructions (cont)
Instruction Size* Function
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag. BIXOR B C ⊕ [~(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general
register or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data. BLD B (<bit-No.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C flag. BILD B ~ (<bit-No.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or memory
to the C flag.
The bit number is specified by 3-bit immediate data. BST B C → (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory. BIST B ~ C → (<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data. Note: *Size: Operand size
B: Byte
Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for details.
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15 087
op IMM rn
BSET, BCLR, BNOT, BTST
Operand: Bit No.:
register direct (Rn) immediate (#xx:3)
15 087
op rn
15 087
op 0
op
15 087
op 0
15 087
op
op
15 087
op
15 087
op IMM rn
rm
rn
rn
abs
abs
Operand: Bit No.:
Operand:
0000000IMM
Bit No.:
Operand:
0000000rmop
Bit No.:
Operand:
0000IMM
Bit No.:
Operand:
0000rmop
Bit No.:
register direct (Rn) register direct (Rm)
register indirect (@Rn) immediate (#xx:3)
register indirect (@Rn) register direct (Rm)
absolute (@aa:8) immediate (#xx:3)
absolute (@aa:8) register direct (Rm)
BAND, BOR, BXOR, BLD, BST
Operand: Bit No.:
register direct (Rn) immediate (#xx:3)
15 087
op 0
15 087
op
Legend: op: rm, rn: abs: IMM:
Operation field Register field Absolute address Immediate data
Figure 2.7 Bit Manipulation Instruction Codes
rn
0000000IMMop
abs
0000IMMop
Operand: Bit No.:
Operand: Bit No.:
register indirect (@Rn) immediate (#xx:3)
absolute (@aa:8) immediate (#xx:3)
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15 087
op IMM rn
15 087
op 0
15 087
op
Legend: op: rm, rn: abs: IMM:
Operation field Register field Absolute address Immediate data
Figure 2.7 Bit Manipulation Instruction Codes (cont)
BIAND, BIOR, BIXOR, BILD, BIST
Operand: Bit No.:
rn
0000000IMMop
abs
0000IMMop
Operand: Bit No.:
Operand: Bit No.:
register direct (Rn) immediate (#xx:3)
register indirect (@Rn) immediate (#xx:3)
absolute (@aa:8) immediate (#xx:3)
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2.5.6 Branching Instructions
Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats.
Table 2.9 Branching Instructions
Instruction Size Function
Bcc — Branches to the designated address if the specified condition is true.
The branching conditions are given below.
Mnemonic Description Condition
BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 BCC (BHS) Carry clear (high or same) C = 0 BCS (BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1
JMP — Branches unconditionally to a specified address BSR — Branches to a subroutine at a specified address JSR — Branches to a subroutine at a specified address RTS — Returns from a subroutine
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15 087
op cc disp
15 087
op rm 0
15 087
op
abs
15 087
op abs
15 087
op disp
15 087
op rm 0
15 087
op
abs
000
000
Bcc
JMP (@Rm)
JMP (@aa:16)
JMP (@@aa:8)
BSR
JSR (@Rm)
JSR (@aa:16)
38
15 087
op abs
15 087
op
Legend: op:
Operation field
cc:
Condition field
rm:
Register field
disp:
Displacement
abs:
Absolute address
Figure 2.8 Branching Instruction Codes
JSR (@@aa:8)
RTS
Page 49
2.5.7 System Control Instructions
Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats.
Table 2.10 System Control Instructions
Instruction Size* Function
RTE — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See
section 5, Power-Down Modes, for details
LDC B Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to the condition code register
STC B CCR → Rd
Copies the condition code register to a specified general register
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data
ORC B CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data
XORC B CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data
NOP — PC + 2 → PC
Only increments the program counter
Note: *Size: Operand size
B: Byte
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15 087
op
15 087
op rn
RTE, SLEEP, NOP
LDC, STC (Rn)
15 087
op IMM
Legend: op:
Operation field
rn:
Register field
IMM:
Immediate data
ANDC, ORC, XORC, LDC (#xx:8)
Figure 2.9 System Control Instruction Codes
2.5.8 Block Data Transfer Instruction
Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.
Table 2.11 Block Data Transfer Instruction
Instruction Size Function
EEPMOV — If R4L ≠ 0 then
repeat @R5+ → @R6+, R4L – 1 → R4L
until R4L = 0 else next; Block transfer instruction. Transfers the number of bytes specified by
R4L, from locations starting at the address specified by R5, to locations starting at the address specified by R6. On completion of the transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the EEPMOV Instruction, for details.
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15 087
op op
Legend: op: Operation field
Figure 2.10 Block Data Transfer Instruction Code
41
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2.6 Basic Operational Timing

CPU operation is synchronized by a system clock (ø) or a subclock (ø clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø
). For details on these
SUB
SUB
to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Acess to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Bus cycle
ø or ø
SUB
Internal address bus
Internal read signal
Internal data bus (read access)
T1 state
Address
T2 state
Read data
42
Internal write signal
Internal data bus (write access)
Figure 2.11 On-Chip Memory Access Cycle
Write data
Page 53
2.6.2 Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Two-state access to on-chip peripheral modules
Figure 2.12 shows operation timings for accessing on-chip peripheral modules in 2 states.
Bus cycle
ø or ø
SUB
Internal address bus
Internal read signal
Internal data bus (read access)
Internal write signal
Internal data bus (write access)
T1 state
Address
state
T
2
Read data
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
Three-state access to on-chip peripheral modules
Figure 2.13 shows operation timings for accessing on-chip peripheral modules in 3 states.
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Bus cycle
ø or ø
SUB
Internal address bus
Internal read signal
Internal data bus (read access)
Internal write signal
Internal data bus (write access)
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)

2.7 CPU States

T1 state
T2 state T3 state
Address
Read data
Write data
2.7.1 Overview
There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium­speed) mode and subactive mode. In the program halt state there are a sleep mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.14.
Figure 2.15 shows the state transitions.
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CPU state Reset state
The CPU is initialized.
Program
execution state
Active
(high speed) mode
The CPU executes successive program instructions at high speed, synchronized by the system clock
(medium speed) mode
The CPU executes successive program instructions at reduced speed, synchronized by the system clock
The CPU executes successive program instructions at reduced speed, synchronized by the subclock
Active
Subactive mode
Low-power
modes
Program halt state
A state in which some or all of the chip functions are stopped to conserve power
Exception-
handling state
A transient state in which the CPU changes the processing flow due to a reset or an interrupt exception handling source.
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Sleep mode
Standby mode
Watch mode
Subsleep mode
Figure 2.14 CPU Operation States
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Reset state
Reset cleared
Exception-handling state
Reset occurs
Reset occurs
Program halt state
Reset occurs
SLEEP instruction executed
Interrupt source
Exception­handling request
Program execution state
Exception­handling complete
Figure 2.15 State Transitions
2.7.2 Program Execution State
In the program execution state the CPU executes program instructions in sequence.
There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes.
2.7.3 Program Halt State
In the program halt state there are four modes: sleep mode, standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes.
2.7.4 Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see 3.3, Interrupts.
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2.8 Memory Map

Figure 2.16 shows a memory map for the H8/3637 Series.
H'0000
H'0029
H'002A
H'9FFF
H'BFFF
H'EDFF
H'F77F
H'F780
Interrupt vectors
(42 bytes)
On-chip ROM
Reserved
H8/3635
40 kbytes
H8/3637H8/3636
48 kbytes
60 kbytes
H'FF7F H'FF80
H'FF8F H'FF90
H'FFFF
On-chip RAM
Reserved
Internal I/O registers
(112 bytes)
2 kbytes
Figure 2.16 H8/3637 Series Memory Map
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2.9 Application Notes

2.9.1 Notes on Data Access
Access to Empty Area: The address space of the H8/300L CPU includes empty areas in addition
to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
• Data transfer from CPU to empty area:
The transferred data will be lost. This action may also cause the CPU to misoperate.
• Data transfer from empty area to CPU:
Unpredictable data is transferred.
Access to the Internal I/O Register: Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur.
• Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost.
• Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register.
Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas.
Figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed.
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H'0000
H'0029
H'002A
Interrupt vectors
(42 bytes)
H8/3635 H8/3637H8/3636
Access
Word Byte
States
H'9FFF
H'BFFF
H'EDFF
H'F77F H'F780
H'FF7F
H'FF80
H'FF8F
H'FF90
H'FFFF
On-chip ROM
Reserved
On-chip RAM
Reserved
Internal I/O registers
(112 bytes)
40 kbytes
2 kbytes
48 kbytes
60 kbytes
———
—
×
: Access possible
×
: Not possible
2
2
——
2 or 3
Figure 2.17 Data Size and Number of States for Access to and from
On-Chip Peripheral Modules
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2.9.2 Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write­only bits, and when the instruction accesses an I/O.
Order of Operation Operation
1 Read Read byte data at the designated address 2 Modify Modify a designated bit in the read data 3 Write Write the altered byte data to the designated address
Bit Manipulation in Two Registers Assigned to the Same Address
Example 1: Bit manipulation to the timer load register and the timer counter
Figure 2.18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place.
Order of Operation Operation
1 Read Timer counter data is read (one byte) 2 Modify The CPU modifies (sets or resets) the bit designated in the instruction 3 Write The altered byte data is written to the timer load register
The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value.
Count clock Timer counter
Reload
Timer load register
R
R:W:Read
Write
W
Internal bus
Figure 2.18 Timer Configuration Example
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Example 2: Here a BSET instruction is executed designating port 6.
P67 and P66 are designated as input pins, with a low-level signal input at P67 and a high-level signal at P66. The remaining pins, P65 to P60, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P60 to high-level output.
[A: Prior to executing BSET]
P6
7
P6
6
P6
P6
5
4
P6
P6
3
P6
2
P6
1
0
Input/output Input Input Output Output Output Output Output Output Pin state Low
level
High level
Low level
Low level
Low level
Low level
Low level
Low
level PCR6 00111111 PDR6 10000000
[B: BSET instruction executed]
BSET #0, @PDR6
The BSET instruction is executed designating port 6.
[C: After executing BSET]
P6
7
Input/output Input Input Output Output Output Output Output Output Pin state Low
level PCR6 00111111 PDR6 0 1000001
P6
High level
6
P6
Low level
P6
5
4
Low level
P6
Low level
P6
3
Low level
P6
2
Low level
P6
1
0
High level
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 6.
Since P67 and P66 are input pins, the CPU reads the pin states (low-level and high-level input). P65 to P60 are output pins, so the CPU reads the value in PDR6. In this example PDR6 has a value of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR6 data to H'41. Finally, the CPU writes this value (H'41) to PDR6, completing execution of BSET.
As a result of this operation, bit 0 in PDR6 becomes 1, and P60 outputs a high-level signal. However, bits 7 and 6 of PDR6 end up with different values.
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To avoid this problem, store a copy of the PDR6 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR6.
[A: Prior to executing BSET]
MOV. B #80, R0L MOV. B R0L, @RAM0 MOV. B R0L, @PDR6
P6
P6
7
6
The PDR6 value (H'80) is written to a work area in memory (RAM0) as well as to PDR6.
P6
P6
5
P6
4
P6
3
P6
2
1
P6
0
Input/output Input Input Output Output Output Output Output Output Pin state Low
level
High level
Low level
Low level
Low level
Low level
Low level
Low
level PCR6 00111111 PDR6 10000000 RAM0 10000000
[B: BSET instruction executed]
BSET #0, @RAM0
The BSET instruction is executed designating the PDR6 work area (RAM0).
[C: After executing BSET]
MOV. B @RAM0, R0L
The work area (RAM0) value is written to PDR6.
MOV. B R0L, @PDR6
P6
P6
7
6
P6
P6
5
P6
4
P6
3
P6
2
1
P6
0
Input/output Input Input Output Output Output Output Output Output Pin state Low
level
High level
Low level
Low level
Low level
Low level
Low level
High
level PCR6 00111111 PDR6 10000001 RAM0 10000001
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Bit Manipulation in a Register Containing a Write-only Bit
Example 3: In this example, the port 6 control register PCR6 is accessed by a BCLR instruction.
As in the examples above, P67 and P66 are input pins, with a low-level signal input at P67 and a high-level signal at P66. The remaining pins, P65 to P60, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P60 to an input port. It is assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
P6
7
P6
6
P6
P6
5
4
P6
P6
3
P6
2
P6
1
0
Input/output Input Input Output Output Output Output Output Output Pin state Low
level
High level
Low level
Low level
Low level
Low level
Low level
Low
level PCR6 00111111 PDR6 10000000
[B: BCLR instruction executed]
BCLR #0, @PCR6
The BCLR instruction is executed designating PCR6.
[C: After executing BCLR]
P6
7
Input/output Output Output Output Output Output Output Output Input Pin state Low
level PCR6 1 1 111110 PDR6 10000000
P6
High level
6
P6
Low level
P6
5
4
Low level
P6
Low level
P6
3
Low level
P6
2
Low level
P6
1
0
High level
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR6. Since PCR6 is a write-only register, the CPU reads a value of H'FF, even though the PCR6 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR6 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR6 becomes 0, making P60 an input port. However, bits 7 and 6 in PCR6 change to 1, so that P67 and P66 change from input pins to output pins.
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To avoid this problem, store a copy of the PCR6 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR6.
[A: Prior to executing BCLR]
MOV. B #3F, R0L MOV. B R0L, @RAM0 MOV. B R0L, @PCR6
P6
P6
7
6
The PCR6 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR6.
P6
P6
5
P6
4
P6
3
P6
2
1
P6
0
Input/output Input Input Output Output Output Output Output Output Pin state Low
level
High level
Low level
Low level
Low level
Low level
Low level
Low
level PCR6 00111111 PDR6 10000000 RAM0 00111111
[B: BCLR instruction executed]
BCLR #0, @RAM0
The BCLR instruction is executed designating the PCR6 work area (RAM0).
[C: After executing BCLR]
MOV. B @RAM0, R0L
The work area (RAM0) value is written to PCR6.
MOV. B R0L, @PCR6
P6
P6
7
6
P6
P6
5
P6
4
P6
3
P6
2
1
P6
0
Input/output Input Input Output Output Output Output Output Output Pin state Low
level
High level
Low level
Low level
Low level
Low level
Low level
High
level PCR6 00111110 PDR6 10000000 RAM0 00111110
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Table 2.12 lists the registers with shared addresses. Table 2.13 lists the registers that contain write­only bits.
Table 2.12 Registers with Shared Addresses
Register Name Abbreviation Address
Timer counter YH / timer load register YH TCYH/TLYH H'FFCE Timer counter YL / timer load register YL TCYL/TLYL H'FFCF Port data register 1* PDR1 H'FFD4 Port data register 2* PDR2 H'FFD5 Port data register 5* PDR5 H'FFD8 Port data register 6* PDR6 H'FFD9 Port data register 7* PDR7 H'FFDA Port data register 8* PDR8 H'FFDB Port data register 9* PDR9 H'FFDC Port data register A* PDRA H'FFDD Port data register E* PDRE H'FFD3
Note: *The port data register addresses are also assigned directly to input pins.
Table 2.13 Registers with Write-Only Bits
Register Name Abbreviation Address
Port control register 1 PCR1 H'FFE4 Port control register 2 PCR2 H'FFE5 Port control register 5 PCR5 H'FFE8 Port control register 6 PCR6 H'FFE9 Port control register 7 PCR7 H'FFEA Port control register 8 PCR8 H'FFEB Port control register 9 PCR9 H'FFEC Port control register A PCRA H'FFED Port control register E PCRE H'FFE3 Timer control register F TCRF H'FFB6 PWM control register PWCR H'FFA4 PWM data register U PWDRU H'FFA5 PWM data register L PWDRL H'FFA6
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2.9.3 Notes on Use of the EEPMOV Instruction
• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
→
R5
←
R6
R5 + R4L
→
←
R6 + R4L
• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction.
→
R5
←
R6
R5 + R4L
→
Not allowed
H'FFFF
←
R6 + R4L
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Section 3 Exception Handling

3.1 Overview

Exception handling is performed in the H8/3637 Series when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling.
Table 3.1 Exception Handling Types and Priorities
Priority Exception Source Time of Start of Exception Handling
High Reset Exception handling starts as soon as the reset state is cleared
Interrupt When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling
Low

3.2 Reset

3.2.1 Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the on­chip peripheral modules are initialized.
in progress is completed
3.2.2 Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the H8/3637 Series enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• When an external clock or ceramic oscillator is used, also, at power on the RES pin must be
held low for the crystal oscillator oscillation stabilization time shown in table 14.3 in section 14, Electrical Characteristics.
• Resetting during operation: Hold the RES pin low for at least 18 system clock cycles.
Reset exception handling begins when the RES pin is held low for a given period, then returned to the high level. Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
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• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence.
Reset cleared
Program initial instruction prefetch
RES
ø
Vector fetch
Internal processing
Internal address bus
Internal read signal
Internal write signal
Internal data bus (16-bit)
(1)
(2) (3)
(1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program
(2)
Figure 3.1 Reset Sequence
3.2.3 Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
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3.3 Interrupts

3.3.1 Overview
The interrupt sources include 13 external interrupts (WKP0 to WKP7, IRQ0 to IRQ4), and 17 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed.
The interrupts have the following features:
• Internal and external interrupts can be masked by the I bit of CCR. When this bit is set to 1,
interrupt request flags are set but interrupts are not accepted.
• IRQ0 to IRQ4 can each be set independently to either rising edge sensing or falling edge
sensing.
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Table 3.2 Interrupt Sources and Priorities
Interrupt Source Interrupt Vector Number Vector Address Priority
RES Reset 0 H'0000 to H'0001 High IRQ
0
IRQ
1
IRQ
2
IRQ
3
IRQ
4
WKP
0
WKP
1
WKP
2
WKP
3
WKP
4
WKP
5
WKP
6
WKP
7
SCI1 SCI1 transfer complete 10 H'0014 to H'0015 Timer A Timer A overflow 11 H'0016 to H'0017 Timer Y Timer Y overflow 12 H'0018 to H'0019 Timer FL Timer FL compare match
Timer FH Timer FH compare match
Timer G Timer G input capture
SCI3 SCI3 receive data full
A/D converter A/D conversion end 19 H'0026 to H'0027 (SLEEP instruction
executed) Note: Vector addresses H'0002 to H'0007, H'001A to H'001B, and H'0022 to H'0023 are reserved
and cannot be used.
IRQ IRQ IRQ IRQ IRQ
WKP WKP WKP WKP WKP WKP WKP WKP
0
1
2
3
4
0
1
2
3
4
5
6
7
4 H'0008 to H'0009 5 H'000A to H'000B 6 H'000C to H'000D 7 H'000E to H'000F 8 H'0010 to H'0011
9 H'0012 to H'0013
14 H'001C to H'001D
Timer FL overflow
15 H'001E to H'001F
Timer FH overflow
16 H'0020 to H'0021
Timer G overflow
18 H'0024 to H'0025 SCI3 transmit data empty SCI3 transmit end SCI3 overrun error SCI3 framing error SCI3 parity error
Direct transfer 20 H'0028 to H'0029
Low
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3.3.2 Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name Abbreviation R/W Initial Value Address
Interrupt edge select register IEGR R/W H'60 H'FFF2 Interrupt enable register 1 IENR1 R/W H'00 H'FFF3 Interrupt enable register 2 IENR2 R/W H'01 H'FFF4 Interrupt request register 1 IRR1 R/W* H'20 H'FFF6 Interrupt request register 2 IRR2 R/W* H'03 H'FFF7 Wakeup interrupt request register IWPR R/W* H'00 H'FFF9
Note: *Write is enabled only for writing of 0 to clear a flag.
Interrupt Edge Select Register (IEGR)
Bit 76543210
— — — IEG4 IEG3 IEG2 IEG1 IEG0
Initial value 01100000 Read/Write — — — R/W R/W R/W R/W R/W
IEGR is an 8-bit read/write register, used to designate whether pins IRQ0 to IRQ4 are set to rising edge sensing or falling edge sensing.
Bit 7—Reserved Bit: Bit 7 is reserved: it is always read as 0, and should be used cleared to 0.
Bits 6 and 5—Reserved Bits: Bits 6 and 5 are reserved; they are always read as 1, and cannot be
modified.
Bit 4—IRQ4 Edge Select (IEG4): Bit 4 selects the input sensing of pin IRQ4/ADTRG.
Bit 4: IEG4 Description
0 Falling edge of IRQ 1 Rising edge of IRQ4/ADTRG pin input is detected
/ADTRG pin input is detected (initial value)
4
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Bit 3—IRQ3 Edge Select(IEG3): Bit 3 selects the input sensing of pin IRQ3/TMIF.
Bit 3: IEG3 Description
0 Falling edge of IRQ
/TMIF pin input is detected (initial value)
3
1 Rising edge of IRQ3/TMIF pin input is detected
Bit 2—IRQ2 Edge Select(IEG2): Bit 2 selects the input sensing of pin IRQ2/TMCIY.
Bit 2: IEG2 Description
0 Falling edge of IRQ
/TMCIY pin input is detected (initial value)
2
1 Rising edge of IRQ2/TMCIY pin input is detected
Bit 1—IRQ1 Edge Select(IEG1): Bit 1 selects the input sensing of pin IRQ1.
Bit 1: IEG1 Description
0 Falling edge of IRQ
pin input is detected (initial value)
1
1 Rising edge of IRQ1 pin input is detected
Bit 0—IRQ0 Edge Select(IEG0): Bit 0 selects the input sensing of pin IRQ0.
Bit 0: IEG0 Description
0 Falling edge of IRQ 1 Rising edge of IRQ0 pin input is detected
pin input is detected (initial value)
0
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Interrupt Enable Register 1 (IENR1)
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 76543210
IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0
Initial value 00000000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7—Timer A Interrupt Enable (IENTA): Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7: IENTA Description
0 Disables timer A interrupts (initial value) 1 Enables timer A interrupts
Bit 6—SCI1 Interrupt Enable (IENS1): Bit 6 enables or disables SCI1 transfer complete interrupt requests.
Bit 6: IENS1 Description
0 Disables SCI1 interrupts (initial value) 1 Enables SCI1 interrupts
Bit 5—Wakeup Interrupt Enable (IENWP): Bit 5 enables or disables WKP7 to WKP0 interrupt requests.
Bit 5: IENWP Description
0 Disables interrupt requests from WKP
to WKP
7
1 Enables interrupt requests from WKP7 to WKP
0
0
(initial value)
Bits 4 to 0: IRQ4 to IRQ0 Interrupt Enable (IEN4 to IEN0): Bits 4 to 0 enable or disable IRQ to IRQ0 interrupt requests.
Bits 4 to 0: IEN4 to IEN0 Description
0 Disables interrupt requests from IRQ4 to IRQ 1 Enables interrupt requests from IRQ4 to IRQ
0
0
(initial value)
4
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Interrupt Enable Register 2 (IENR2)
Bit 76543210
IENDT IENAD — IENTG IENTFH IENTFL IENTY —
Initial value 00000001 Read/Write R/W R/W — R/W R/W R/W R/W —
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer interrupt requests.
Bit 7: IENDT Description
0 Disables direct transfer interrupt requests (initial value) 1 Enables direct transfer interrupt requests
Bit 6—A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter end interrupt requests.
Bit 6: IENAD Description
0 Disables A/D converter interrupt requests (initial value) 1 Enables A/D converter interrupt requests
Bit 5—Reserved Bit: Bit 5 is reserved: it is always read as 0, and should be used cleared to 0.
Bit 4—Timer G Interrupt Enable (IENTG): Bit 4 enables or disables timer G input capture and
overflow interrupt requests.
Bit 4: IENTG Description
0 Disables timer G interrupts (initial value) 1 Enables timer G interrupts
Bit 3—Timer FH Interrupt Enable (IENTFH): Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3: IENTFH Description
0 Disables timer FH interrupts (initial value) 1 Enables timer FH interrupts
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Bit 2—Timer FL Interrupt Enable (IENTFL): Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2: IENTFL Description
0 Disables timer FL interrupts (initial value) 1 Enables timer FL interrupts
Bit 1—Timer Y Interrupt Enable (IENTY): Bit 1 enables or disables timer Y overflow interrupt requests.
Bit 1: IENTY Description
0 Disables timer Y interrupts (initial value) 1 Enables timer Y interrupts
Bit 0—Reserved Bit: Bit 0 is reserved: it is always read as 1, and cannot be modified.
For details of SCI3 interrupt control, see Serial Control Register 3 (SCR3), in section 10.3.2.
Interrupt Request Register 1 (IRR1)
Bit 76543210
IRRTA IRRS1 — IRRI4 IRRI3 IRRI2 IRRI1 IRRI0
Initial value 00100000 Read/Write R/W* R/W* — R/W* R/W* R/W* R/W* R/W*
Note: *Only a write of 0 for flag clearing is possible.
IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A, SCI1, or IRQ4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7: IRRTA Description
0 [Clearing conditions] (initial value)
When IRRTA = 1, it is cleared by writing 0
1 [Setting conditions]
When the timer A counter value overflows (goes from H'FF to H'00)
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Bit 6—SCI1 Interrupt Request Flag (IRRS1)
Bit 6: IRRS1 Description
0 [Clearing conditions] (initial value)
When IRRS1 = 1, it is cleared by writing 0
1 [Setting conditions]
When an SCI1 transfer is completed
Bit 5—Reserved Bit: Bit 5 is reserved; it is always read as 1, and cannot be modified.
Bits 4 to 0—IRQ4 to IRQ0 Interrupt Request Flags (IRRI4 to IRRI0)
Bits 4 to 0: IRRI4 to IRRI0 Description
0 [Clearing conditions] (initial value)
When IRRIn = 1, it is cleared by writing 0 to IRRIn.
1 [Setting conditions]
IRRIn is set when pin IRQ edge is detected.
is set to interrupt input, and the designated signal
n
(n = 4 to 0)
Interrupt Request Register 2 (IRR2)
Bit 76543210
IRRDT IRRAD — IRRTG IRRTFH IRRTFL IRRTY IRRTYC
Initial value 00000001 Read/Write R/W* R/W* — R/W* R/W* R/W* RW*
Note: *Only a write of 0 for flag clearing is possible.
IRR2 is an 8-bit register containing direct transfer, A/D converter, timer G, timer FH, timer FL, and timer Y interrupt flags. When a direct transfer, A/D converter, timer G, timer FH, timer FL, or timer Y interrupt is requested, the corresponding flag is set to 1. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. However, the timer Y interrupt request flag (IRRTY) is cleared by writing 0 to bit 0 (IRRTYC).
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Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT Description
0 [Clearing conditions] (initial value)
When IRRDT = 1, it is cleared by writing 0
1 [Setting conditions]
When DTON = 1 and a direct transfer is made immediately after a SLEEP instruction is executed
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6: IRRAD Description
0 [Clearing conditions] (initial value)
When IRRAD = 1, it is cleared by writing 0
1 [Setting conditions]
When A/D conversion is completed and ADSF is reset
Bit 5—Reserved Bit: Bit 5 is reserved: it is always read as 0, and should be used cleared to 0.
Bit 4—Timer G Interrupt Request Flag (IRRTG)
Bit 4: IRRTG Description
0 [Clearing conditions] (initial value)
When IRRTG = 1, it is cleared by writing 0
1 [Setting conditions]
When pin TMIG is set to TMIG input and the designated signal edge is detected, or when TCG overflows (from H’FF to H’00) while TMG OVIE is set to 1
Bit 3—Timer FH Interrupt Request Flag (IRRTFH)
Bit 3: IRRTFH Description
0 [Clearing conditions] (initial value)
When IRRTFH = 1, it is cleared by writing 0
1 [Setting conditions]
When counter FH matches output compare register FH in 8-bit timer mode, or when 16-bit counter F (TCFL, TCFH) matches output compare register F (OCRFL, OCRFH) in 16-bit timer mode
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Bit 2—Timer FL Interrupt Request Flag (IRRTFL)
Bit 2: IRRTFL Description
0 [Clearing conditions] (initial value)
When IRRTFL = 1, it is cleared by writing 0
1 [Setting conditions]
When counter FL matches output compare register FL in 8-bit timer mode
Bit 1—Timer Y Interrupt Request Flag (IRRTY)
Bit 1: IRRTY Description
0 [Clearing conditions] (initial value)
When IRRTY is 1, it is cleared by writing 0 to IRRTYC
1 [Setting conditions]
When the timer Y counter value overflows (from H’FFFF to H’0000)
Note: This bit is read-only. It is cleared by writing 0 to bit 0 (IRRTYC).
Bit 0—Timer Y Interrupt Request Clear Flag (IRRTYC): Bit 0 is a special bit for clearing the IRRTY interrupt request flag. Writing 0 to this bit clears bit 1 (IRRTY) to 0. Note that writing 0 to this bit does not give the bit itself a value of 0.
Bit 0 is always read as 1, and only a write of 0 to this bit is valid.
Wakeup Interrupt Request Register (IWPR)
Bit 76543210
IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
Initial value 00000000 Read/Write R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: *Only a write of 0 for flag clearing is possible.
IWPR is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins WKP7 to WKP0 are set to wakeup input and a pin receives a falling edge input. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
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Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0)
Bits 7 to 0: IWPF7 to IWPF0 Description
0 [Clearing conditions] (initial value)
When IWPFn = 1, it is cleared by writing 0 to IWPFn.
1 [Setting conditions]
IWPFn is set when pin WKP edge input is detected at the pin.
is set to wakeup interrupt input, and a falling
n
(n = 7 to 0)
3.3.3 External Interrupts
There are 13 external interrupts, WKP0 to WKP7 and IRQ0 to IRQ4.
Interrupts WKP0 to WKP7: Interrupts WKP0 to WKP7 are requested by falling edge inputs at pins WKP0 to WKP7. When these pins are designated as WKP0 to WKP7 pins in port mode register 5 (PMR5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request register (IWPR) is set to 1, requesting an interrupt. Wakeup interrupt requests can be disabled by clearing the IENWP bit in IENR1 to 0. It is also possible to mask all interrupts by setting the CCR I bit to 1.
When an interrupt exception handling request is received for interrupts WKP0 to WKP7, the CCR I bit is set to 1. The vector number for interrupts WKP0 to WKP7 is 9. Since all eight interrupts are assigned the same vector number, the interrupt source must be determined by the exception handling routine.
Interrupts IRQ0 to IRQ4: Interrupts IRQ0 to IRQ4 are requested by inputs into pins IRQ0 to IRQ4.
These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR).
When these pins are designated as pins IRQ0 to IRQ4 in port mode registers 1 and 2 (PMR1 and PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Interrupts IRQ0 to IRQ4 can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0. All interrupts can be masked by setting the I bit in CCR to 1.
When IRQ0 to IRQ4 interrupt exception handling is initiated, the I bit in CCR is set to 1. Vector numbers 4 to 8 are assigned to interrupts IRQ0 to IRQ4. The order of priority is from IRQ0 (high) to IRQ4 (low). Table 3.2 gives details.
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3.3.4 Internal Interrupts
There are 17 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt request is accepted, the I bit in CCR is set to 1. Vector numbers 10 to 20 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules.
3.3.5 Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Interrupt controller
External or internal interrupts
Interrupt request
Priority decision logic
External interrupts or internal interrupt enable signals
CCR (CPU)I
Figure 3.2 Block Diagram of Interrupt Controller
Interrupt operation is described as follows.
1. When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller.
2. When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
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3. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2 for a list of interrupt priorities.)
4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending.
5. If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling.
6. The I bit of CCR is set to 1, masking all further interrupts.
7. The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked (I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed.
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Program execution state
IRRI0 = 1
Yes
IEN0 = 1
Yes
I = 0
No
No
No
IRRI1 = 1
Yes
IEN1 = 1
Yes
No
No
IRRI2 = 1
Yes
IEN2 = 1
Yes
No
No
IRRDT = 1
IENDT = 1
No
Yes
No
Yes
72
PC contents saved
CCR contents saved
Branch to interrupt
handling routine
Legend: PC:
Program counter
CCR:
Condition code register
I:
I bit of CCR
Yes
I ← 1
Figure 3.3 Flow up to Interrupt Acceptance
Page 83
SP – 4 SP – 3 SP – 2 SP – 1 SP (R7)
Stack area
SP (R7) SP + 1 SP + 2 SP + 3 SP + 4
CCR
CCR*
PC
H
PC
L
Even address
Prior to start of interrupt
exception handling
Legend: PC
Upper 8 bits of program counter (PC)
:
H
Lower 8 bits of program counter (PC)
PC
:
L
Condition code register
CCR:
Stack pointer
SP:
1.2.PC shows the address of the first instruction to be executed upon
Notes:
PC and CCR
saved to stack
After completion of interrupt
exception handling
return from the interrupt handling routine. Register contents must always be saved and restored by word access, starting from an even-numbered address.
* Ignored on return from interrupt.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
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Prefetch instruction of
interrupt-handling routine
Internal
processing
Vector fetch
Stack access
Internal
processing
Instruction
prefetch
(9)
(3) (9)(8)(6)(5)
(4) (1) (7) (10)
74
Interrupt is
accepted
Interrupt level
decision and wait for
end of instruction
Interrupt
request signal
(1)
ø
Internal
address bus
Internal read
signal
Internal write
signal
Figure 3.5 Interrupt Sequence
(2)
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
Internal data bus
(16 bits)
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3.3.6 Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed.
Table 3.4 Interrupt Wait States
Item States Total
Waiting time for completion of executing instruction* 1 to 13 15 to 27 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4
Note: *Not including EEPMOV instruction.
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3.4 Application Notes

3.4.1 Notes on Stack Area Use
When word data is accessed in the H8/3637 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
PC
→
SP
→
SP
BSR instruction
SP set to H'FEFF Stack accessed beyond SP
Legend: PC
:
Upper byte of program counter
H
PC
:
Lower byte of program counter
L
R1L:
General register R1L
SP:
Stack pointer
PC
H
L
MOV. B R1L, @–R7
→
SP
Contents of PC are lost
R1L
PC
L
H'FEFC H'FEFD
H'FEFF
H
Figure 3.6 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored.
3.4.2 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed.
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When an external interrupt pin function is switched by rewriting the port mode register that controls these pins (IRQ4 to IRQ0, and WKP7 to WKP0), the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching pin functions. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way.
Table 3.5 Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request Flags Set to 1 Conditions
IRR1 IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
IWPR IWPF7 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low
IWPF6 When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low IWPF5 When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low IWPF4 When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low IWPF3 When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low IWPF2 When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low IWPF1 When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low IWPF0 When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low
• When PMR2 bit IRQ4 is changed from 0 to 1 while pin IRQ IEGR bit IEG4 = 0.
• When PMR2 bit IRQ4 is changed from 1 to 0 while pin IRQ IEGR bit IEG4 = 1.
• When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ IEGR bit IEG3 = 0.
• When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ IEGR bit IEG3 = 1.
• When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ IEGR bit IEG2 = 0.
• When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ IEGR bit IEG2 = 1.
• When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ IEGR bit IEG1 = 0.
• When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ IEGR bit IEG1 = 1.
• When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ IEGR bit IEG0 = 0.
• When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ IEGR bit IEG0 = 1.
is low and
4
is low and
4
is low and
3
is low and
3
is low and
2
is low and
2
is low and
1
is low and
1
is low and
0
is low and
0
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Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
Interrupts masked. (Another possibility
CCR I bit 1
Set port mode register bit
Execute NOP instruction
Clear interrupt request flag to 0
←
is to disable the relevant interrupt in interrupt enable register 1.)
After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0
78
CCR I bit 0
←
Interrupt mask cleared
Figure 3.7 Port Mode Register Setting and Interrupt Request Flag
Clearing Procedure
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Section 4 Clock Pulse Generators

4.1 Overview

Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
4.1.1 Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators.
ø
OSC
ø/2 to ø/8192
ø
W
ø /2
W
ø /4
W
ø /8
W
to ø /128
W
OSC OSC
1
System clock
2
X
1
X
2
oscillator
System clock pulse generator
Subclock oscillator
Subclock pulse generator
ø
OSC
(f )
ø
(f )
OSC
W
W
System clock
divider (1/2)
Subclock
divider
(1/2, 1/4, 1/8)
ø /2
OSC
System clock
divider (1/8)
ø /2
W
ø /4
W
ø /8
W
ø /16
OSC
ø
Prescaler S
(13 bits)
ø
SUB
Prescaler W
(5 bits)
Figure 4.1 Block Diagram of Clock Pulse Generators
4.1.2 System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are ø and ø the clock signals have names: ø is the system clock, ø
is the subclock, ø
SUB
is the oscillator
OSC
. Four of
SUB
clock, and øW is the watch clock.
The clock signals available for use by peripheral modules are ø
, ø/2, ø/4, ø/8, ø/16, ø/32, ø/64,
OSC
ø/128, ø/256, ø/512, ø/1024, ø/2048, ø/4096, ø/8192, øW, øW/2, øW/4, øW/8, øW/16, øW/32, øW/64, and øW/128. The clock requirements differ from one module to another.

4.2 System Clock Generator

Clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input.
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Connecting a Crystal Oscillator: Figure 4.2 shows a typical method of connecting a crystal oscillator.
C
OSC
OSC
1
R
f
2
1
R = 1 M ±20% C = C = 12 pF ±20%
C
2
12
Ω
f
Figure 4.2 Typical Connection to Crystal Oscillator
Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 4.1 should be used.
C
S
OSC
L
S
1
C
0
R
S
OSC
2
Figure 4.3 Equivalent Circuit of Crystal Oscillator
Table 4.1 Crystal Oscillator Parameters
Frequency 2 MHz 4 MHz 8 MHz 10 MHz RS (max) 500 Ω 100 Ω 50 Ω 30 Ω C0 (max) 7 pF 7 pF 7 pF 7 pF
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Connecting a Ceramic Oscillator: Figure 4.4 shows a typical method of connecting a ceramic oscillator.
C
OSC
OSC
1
R
f
2
1
Rf = 1 MΩ ± 20% C
= 30 pF ± 10%
C
2
1
C
= 30 pF ± 10%
2
Ceramic oscillator: Murata
Figure 4.4 Typical Connection to Ceramic Oscillator
Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic
oscillator, pay careful attention to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4.5.)
The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2.
To be avoided
C
1
C
2
Figure 4.5 Board Design of Oscillator Circuit
Signal A Signal B
OSC
OSC
1
2
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External Clock Input Method: Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.6 shows a typical connection.
OSC
1
OSC
2
Open
Figure 4.6 External Clock Input (Example)
Frequency Oscillator Clock (ø
Duty cycle 45% to 55%
OSC
External clock input
)
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4.3 Subclock Generator

Connecting a 32.768-kHz Crystal Oscillator: Clock pulses can be supplied to the subclock
divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4.7. Follow the same precautions as noted in 4.2, Notes on Board Design.
C
X
1
R
f
X
2
Figure 4.7 Typical Connection to 32.768-kHz Crystal Oscillator
Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal oscillator.
C
S
1
C = C = 15 pF (typ.)
C
2
12
R
= 10 MΩ (typ.)
f
LR
X
1
S
C
0
S
C = 1.5 pF typ
0
R = 14 k typ
S
f = 32.768 kHz
W
Ω
X
2
Crystal oscillator: MX38T
(Nihon Denpa Kogyo)
Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Oscillator
Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X1 to
VCC and leave pin X2 open, as shown in figure 4.9.
V
CC
X
1
X
2
Open
Figure 4.9 Pin Connection when not Using Subclock
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4.4 Prescalers

The H8/3637 Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 (øW/4) as its input clock. Its prescaled outputs are used by timer A as a time base for timekeeping.
Prescaler S (PSS): Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is ø
OSC
/16.
Prescaler W (PSW): Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (øW/4) as its input clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base for timekeeping.

4.5 Note on Oscillators

Oscillator characteristics of both the masked ROM and ZTATTM versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section and figure 4.10, Example of Crystal and Ceramic Oscillator Layout. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating.
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AV
X
X
V
OSC
OSC
SS
1
2
SS
2
1
TEST
(VSS)
Figure 4.10 Example of Crystal and Ceramic Oscillator Layout.
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Section 5 Power-Down Modes

5.1 Overview

The H8/3637 Series has seven modes of operation after a reset. These include six power-down modes, in which power dissipation is significantly reduced.
Table 5.1 gives a summary of the seven operation modes.
Table 5.1 Operation Modes
Operating Mode Description
Active (high-speed) mode The CPU runs on the system clock, executing program
instructions at high speed
Active (medium-speed) mode The CPU runs on the system clock, executing program
instructions at reduced speed
Subactive mode The CPU runs on the subclock, executing program instructions
at reduced speed
Sleep mode The CPU halts. On-chip peripheral modules continue to operate
on the system clock.
Subsleep mode The CPU halts. Timer A, and timer G, continue to operate on
the subclock.
Watch mode The CPU halts. The time-base function of Timer A continues to
operate on the subclock.
Standby mode The CPU and all on-chip peripheral modules stop operating
All but the active (high-speed) mode are power-down modes.
In this section the two active modes (high-speed and medium-speed) are referred to collectively as active mode.
Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal states in each mode.
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Reset state
Program executing Program execution stopped
LSON = 0, MSON = 0
Program execution stopped
SSBY = 1, TMA3 = 0, LSON = 0
Standby mode
SLEEP instruction
SLEEP instruction
SSBY = 1, TMA3 = 1
Watch mode
DTON = 1
SLEEP instruction
SLEEP instruction
Active (high-speed)
*
4
SLEEP instruction
LSON = 0, MSON = 1
*
4
*
1
(medium-speed)
DTON = 1
*
1
LSON = 1, TMA3 = 1
mode
*
1
DTON = 1
Active
mode
SLEEP
instruction
*
3
SLEEP instruction
*
3
SLEEP instruction
*
2
SSBY = 0, LSON = 0
Sleep mode
SSBY = 0, LSON = 1, TMA3 = 1
Subsleep modeSubactive mode
: Transition caused by exception handling→
Power-down mode
A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that the interrupt is accepted and interrupt handling is performed. Details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 through 5.8.
Notes: Timer A interrupt, IRQ interrupt, WKP to WKP interrupts
1. Timer A interrupt, timer G interrupt, IRQ0 to IRQ4 interrupts, WKP0 to WKP7
2.
007
interrupts All interrupts
3.
4.
IRQ interrupt, IRQ interrupt, WKP to WKP interrupts
01 07
Figure 5.1 Operation Mode Transition Diagram
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Table 5.2 Internal State in Each Operation Mode
Active Mode
Function High
Speed
System clock oscillator Functional Functional Functional Stopped Stopped Stopped Stopped Subclock oscillator Functional Functional Functional Functional Functional Functional Functional CPU Instructions Functional Functional Stopped Stopped Functional Stopped Stopped
operation
RAM Retained Retained Retained Retained Registers I/O Retained
External IRQ interrupts
IRQ IRQ IRQ IRQ WKP WKP WKP WKP WKP WKP WKP WKP
0
1
2
3
4
Functional Functional Functional Functional Functional Functional Functional
Functional Functional Functional Functional Functional Functional Functional
0
1
2
3
4
5
6
7
Peripheral Timer A Functional Functional Functional Functional module functions
Timer F Retained Retained Retained Timer G Functional/
Timer Y Functional Functional Functional Retained Retained Retained Retained Watchdog
timer SCI1 Functional Functional Functional Retained Retained Retained Retained SCI3 Reset Reset Reset Reset PWM Functional Functional Retained Retained Retained Retained Retained DTMF Functional Functional Functional Reset Reset Reset Reset A/D Functional Functional Functional Retained Retained Retained Retained
Notes: 1. Register contents held; high-impedance output.
2. Functional only if ø
3. Functional when timekeeping time-base function is selected.
4. External interrupt requests are ignored. The interrupt request register contents are not affected.
Medium Speed
/2 internal clock is selected; otherwise stopped and retained.
W
Sleep Mode
Watch Mode
Retained
Subactive Mode
4
*
3
*
Functional
Retained
Subsleep Mode
3
*
Functional
Functional/
2
*
Retained
*
2
*
Standby Mode
Retained
3
Retained
1
*
4
*
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5.1.1 System Control Registers
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3 System Control Register
Name Abbreviation R/W Initial Value Address
System control register 1 SYSCR1 R/W H'07 H'FFF0 System control register 2 SYSCR2 R/W H'E0 H'FFF1
System Control Register 1 (SYSCR1)
Bit 76543210
SSBY STS2 STS1 STS0 LSON — — —
Initial value 00000111 Read/Write R/W R/W R/W R/W R/W — — —
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'07.
Bit 7—Software Standby (SSBY): This bit designates transition to standby mode or watch mode.
Bit 7: SSBY Description
0
1
• When a SLEEP instruction is executed in active mode, a transition is made to sleep mode.
• When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode. (initial value)
• When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode.
• When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode.
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 10 ms.
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Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description
0 0 0 Wait time = 8,192 states (initial value)
1 Wait time = 16,384 states
1 0 Wait time = 32,768 states
1 Wait time = 65,536 states
1 **Wait time = 131,072 states Note: *Don’t care
Bit 3—Low Speed on Flag (LSON): This bit chooses the system clock (ø) or subclock (ø
SUB
) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input.
Bit 3: LSON Description
0 The CPU operates on the system clock (ø) (initial value) 1 The CPU operates on the subclock (ø
SUB
)
Bits 2 to 0—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified.
System Control Register 2 (SYSCR2)
Bit 76543210
— — — NESEL DTON MSON SA1 SA0
Initial value 11100000 Read/Write — — — R/W R/W R/W R/W R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Upon reset, SYSCR2 is initialized to H'E0.
Bits 7 to 5—Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified.
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