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H8/3060
Hardware Manual
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Hitachi H8/3062, HD6433062, HD6433060, H8/3062F-ZTAT, HD64F3062 Hardware Manual

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Page 1
Hitachi Single-Chip Microcomputer
H8/3062 Series
H8/3062
HD6433062
H8/3061
HD6433061
H8/3060
HD6433060
H8/3062F-ZTAT™
HD64F3062, HD64F3062R, HD64F3062A
H8/3064F-ZTAT™
HD64F3064
Hardware Manual
Page 2
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.
Page 3
Preface
The H8/3062 Series is a series of high-performance single-chip microcontrollers that integrate system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space.
The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities. The two­channel SCI supports a smart card interface handling ISO/IEC7816-3 character transmission as an expansion function. Functions have also been added to reduce power consumption in battery­powered applications: individual modules can be placed in standby mode, and the frequency of the system clock supplied to the chip can be divided under program control.
The address space is divided into eight areas. The data bus width and access cycle length can be selected independently for each area, simplifying the connection of different types of memory. Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of initial data bus width and address space size.
With these features, the H8/3062 Series enables easy implementation of compact, high­performance systems.
In addition to its mask ROM versions, the H8/3062 Series has F-ZTAT™* versions with on-chip flash memory that allows programs to be rewritten after the chip is mounted on a board. This version offers flexibility in the development of new products to meet fast-changing market needs.
This manual describes the H8/3062 Series hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual.
Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.
Page 4
List of Items Revised or Added for This Version
Page Item Description
All — H8/3064F-ZTAT and
H8/3062F-ZTAT A-Mask Version descriptions added
Product code descriptions
amended 2 Table 1.1 Features CPU Description amended 6 Figure 1.1 Block Diagram Notes amended 7 Table 1.2 Comparison of H8/3062 Series Pin
Arrangements
10 Figure 1.4 Pin Arrangement of H8/3064F-ZTAT and
H8/3062F-ZTAT A-Mask Version(FP-100B or TFP­100B Package, Top View)
11 Figure 1.5 Pin Arrangement of H8/3064F-ZTAT and
H8/3062F-ZTAT A-Mask Version(FP-100A Package, Top View)
12 to 15
19 Table 1.4 Pin Assignments in Each Mode Notes amended 20 1.4.1 Pin Arrangement Description added 22 Table 1.6 Differences between H8/3062F-ZTAT,
22 1.5 Notes on H8/3064F-ZTAT and H8/3062F-ZTAT
1.3.2 Pin Functions Table 1.3 Pin Functions
H8/3062F-ZTAT R-Mask Version, and On-Chip Mask ROM Versions
A-Mask Version
Added
Added
Added
Description added and
revised
Description added
Added
22 1.5.1 Pin Arrangement Description revised 24, 25 1.5.3 VCL Pin Description added 24 Figure 1.6 H8/3062F-ZTAT A-Mask Version and
H8/3064F-ZTAT
25 Figure 1.7 Difference between 5 V and 3 V Operation
Models 26 1.6 Setting Oscillation Settling Wait Time Added 26 1.7 Caution on Crystal Resonator Connection Description added 27, 28 2.1.1 Features Description added 37 2.6.1 Instruction Set Overview Total number of instructions
Description amended
Description added
amended
Page 5
Page Item Description
44, 45 Table 2.7 Bit Manipulation Instructions Function descriptions added 49, 50 2.6.5 Notes on Use of Bit Manipulation Instructions Description added 54 Table 2.13 Effective Address Calculation No. 1 Addressing Mode and
Instruction Format amended 65 Table 3.1 Operating Mode Selection Table amended 66 3.1.1 Operating Mode Selection Description added 70 3.4.5 Mode 5 Description added 72 3.6.1 Comparison of H8/3062 Series Memory Maps Added 80 Figure 3.4 H8/3064F-ZTAT Memory Map in Each
Added
Operating Mode
80, 81 Figure 3.4 H8/3064F-ZTAT Memory Map in Each
Addresses revised
Operating Mode
132 6.2.5 Bus Control Register(BCR) Bit 1
Note added 136,
Figure 6.3 Memory Map in 16-Mbyte Mode Description added
137 153 Figure 6.17 Example of Wait State Insertion Timing Amended 205 to
Table 7.21 Port A Pin Functions (Modes 1 to 7) Description added
207 212,
Table 7.23 Port B Pin Functions (Modes 1 to 5) Description added
213 214,
Table 7.24 Port B Pin Functions (Modes 6 and 7) Description amended
215 217 to
Section 8 16-Bit Timer Register names amended
279 242 8.2.11 Timer Output Level Setting Register C (TOLR) Description added 281 to
Section 9 8-Bit Timers Register names amended
318 285 Table 9.2 8-Bit Timer Registers Initial value amended
288 9.2.3 Time Constant Registers B (TCORB) Note added 290,
9.2.4 Timer Control Register (8TCR) Descriptions of bits 4 to 0
291 292 to
9.2.5 Timer control/status register Description added and
296 298 Figures 9.5 and 9.7 8TCNT Access Operations Amended
(8TCSR2)
amended
amended
Page 6
Page Item Description
302 to 306
9.4.4 Timing of Status Flag Setting
9.4.5 Operation with Cascaded Connection
Description amended
9.4.6 Input Capture Setting 307 9.5.1 Interrupt Sources Description amended 308 9.6 8-Bit Timer Application Example Amended 315 9.7.7 Contention between 8TCNT Byte Write and
Description amended Increment in 16-Bit Count Mode (Cascaded Connection)
Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
379 Table 12.3 Examples of Bit Rates and BRR Settings in
25 MHz added Asynchronous Mode
380 Table 12.4 Examples of Bit Rates and BRR Settings in
25 MHz added Synchronous Mode
382 Table 12.5 Maximum Bit Rates for Various
25 MHz added Frequencies (Asynchronous Mode)
383 Table 12.6 Maximum Bit Rates with External Clock
25 MHz added Input (Asynchronous Mode)
384 Table 12.7 Maximum Bit Rates with External Clock
25 MHz added Input (Synchronous Mode)
391 Figure 12.5 Sample Flowchart for Transmitting Serial
Description added Data
417 13.1 Overview Description amended 430 Table 13.5 Bit Rates (bits/s) for Various BRR Settings
(When n=0)
431 Table 13.6 BRR Settings for Typical Bit Rates
25 MHz added
Note amended
25 MHz added (bits/s)(When n=0)
Table 13.7 Maximum Bit Rates for Various
20 MHz and 25 MHz added Frequencies (Smart Card Interface Mode)
438 Figure 13.10 Procedure for Stopping and Restarting
Amended the Clock
441 13.4 Usage Notes Description added 443 14.1 Overview Description added
14.1.1 Features High-speed conversion
471 Table 16.1 H8/3062 Series On-Chip RAM
Specifications
25 MHz added
Added
Page 7
Page Item Description
486 Table 17.6 On-Board Programming Mode Setting Note amended 509 Table 17.10 H8/3062F-ZTAT and H8/3062F-ZTAT R-
Added
Mask Version Socket Adapter Product Codes
513 to 515
513 17.9 Flash Memory Programming and Erasing
17.9 Flash Memory Programming and Erasing Precautions
9 added
Note added
Precautions
516 Figure 17.19 ROM Block Diagram (H8/3062 Mask
Amended
ROM Version) 517 17.11 Notes on Ordering Mask ROM Version Chips 4 added 518 17.12 Notes when Converting the F-ZTAT Application
Description added
Software to the Mask-ROM Versions 519 to
Section 18 Flash Memory [H8/3064F-ZTAT] Added 567
569 to
Section 19 Flash Memory [H8/3062F-ZTAT] Added 618
620 20.2.1 Connecting a Crystal Resonator
Table 20.1(1) Damping Resistance Value
Description added and revised
Table 20.1(2) External Capacitance Values 621 Table 20.2 Crystal Resonator Parameters 25 MHz added 623 Table 20.3 (1) Clock Timing for On-Chip Flash
Table amended
Memory Versions
Table 20.3 (2) Clock Timing for On-Chip Mask ROM
Table added
Versions 626 Table 20.5 Comparison of H8/3062 Series Operating
Revised
Frequency Ranges 635 21.4.3 Selection of Waiting Time for Exit from
Software Standby Mode
When Using External Clock Amendment and addition of 1 and 2
636 Table 21.3 Clock Frequency and Waiting Time for
25 MHz added
Clock to Settle 638 21.4.6 Cautions on Clearing the software Standby
Mode of F-ZTAT Version 643 Table 22.1 Electrical Characteristics of H8/3062
Addition of (3) Comparison of products in H8/3062 Series
Added
Series Products 650 Table 22.3 DC Characteristics (2) Current dissipation typ value
amended
Page 8
Page Item Description
653 Table 22.3 DC Characteristics (3) Current dissipation typ value
amended 658 Table 22.6 Control Signal Timing Description added 669 Table 22.12 DC Characteristics (1) Note 4 added 672 Table 22.12 DC Characteristics (2) Note 4 added 676 Table 22.15 Control Signal Timing Description added 688 to
22.3 Electrical Characteristics of H8/3064F-ZTAT Added
709 710 to
731 738 Figure 22.19 Basic Bus Cycle: Three-State Access
22.4 Electrical Characteristics of H8/3062F-ZTAT A­Mask Version
Added
Amended
with One Wait State
768 Table B.1 Comparison of H8/3062 Series Internal I/O
Table added
Register Specifications
779 to
B.2 Address List (H8/3064F-ZTAT) Table added
788 789 to
B.3 Address List (H8/3062F-ZTAT A-Mask Version) Table added
798 799 to
873
B.4 Functions Amendments and additions
Note added 912 Table F.1 H8/3062 Series H8/3064F-ZTAT and
H8/3062F-ZTAT A-mask
version added 919 H.1 Differences between H8/3067 and H8/3062
Series, H8/3048 Series, H8/3007 and H8/3006, and
A/D converter conversion
states added
H8/3002
923 Table H.1 Pin Arrangement of Each Product Note amended
Page 9
Comparison of H8/3062 Series Product Specifications
There are seven members of the H8/3062 Series: the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT A-mask version, and H8/3064F-ZTAT (all with on-chip flash memory), and the H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version.
The specifications of these products are compared below.
H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,
H8/3062F-ZTAT
H8/3062F-ZTAT R-Mask Version
H8/3060 Mask ROM Version H8/3064F-ZTAT
H8/3062F-ZTAT A-Mask Version
Product specifica­tions
Product code
Pin arrange­ment
RAM size 4 kbytes 4 kbytes H8/3062:
On-chip single­power-supply flash memory
HD64F3062 HD64F3062R HD6433062
See figures 1.2 and 1.3, Pin Arrangement, in section 1
H8/3062F-ZTAT version with address output functions added
See figures 1.2 and 1.3, Pin Arrangement, in section 1
Mask ROM version
HD6433061 HD6433060
See figures 1.2 and 1.3, Pin Arrangement, in section 1
4 kbytes
On-chip large­capacity single­power-supply flash memory
Internal step-down circuit
HD64F3064 HD64F3062A
5 V operation model has VCL pin, and requires connection of external capacitor
See figures 1.4 and 1.5, Pin Arrangement, in section 1
8 kbytes 4 kbytes
H8/3062 F-ZTAT high-speed operation version
5 V operation model has VCL pin, and requires connection of external capacitor
See figures 1.4 and 1.5, Pin Arrangement, in section 1
ROM size 128 kbytes 128 kbytes H8/3062:
H8/3061: 4 kbytes
H8/3060: 2 kbytes
256 kbytes 128 kbytes
128 kbytes H8/3061:
96 kbytes H8/3060:
64 kbytes
Page 10
H8/3062F-ZTAT
H8/3062F-ZTAT R-Mask Version
H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version H8/3064F-ZTAT
H8/3062F-ZTAT A-Mask Version
Address output functions
Flash memory
Electrical charac­teristics (operating frequency)
Compatible with previous H8/300H Series
See section 17, ROM
See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22
Address update mode 1 or 2 selectable
See 6.3.5, Address Output Method, in section 6
See section 17, ROM
See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22
Address update mode 1 or 2 selectable
See 6.3.5, Address Output Method, in section 6
Address update mode 1 or 2 selectable
See 6.3.5, Address Output Method, in section 6
— See 18.1.1,
Differences between H8/3062F-ZTAT and H8/3062F­ZTAT R-Mask Version, in section 18
See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22
See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22
Address update mode 1 or 2 selectable
See 6.3.5, Address Output Method, in section 6
See 19.1.1, Differences between H8/3062F-ZTAT and H8/3062F­ZTAT R-Mask Version, in section 19
See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22
1 to 20 MHz 1 to 20 MHz 1 to 20 MHz 2 to 25 MHz 2 to 25 MHz
Registers See table B.1,
Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B
See appendix B.1, Address List
Usage notes
See 1.4, H8/3062F-ZTAT R-Mask Version Usage Note, in section 1
See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B
See appendix B.1, Address List
See 1.4, H8/3062F-ZTAT R-Mask Version Usage Note, in section 1
See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B
See appendix B.1, Address List
See 1.4, H8/3062F-ZTAT R-Mask Version Usage Note, in section 1
See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B
See appendix B.2, Address List
See 1.5, H8/3064F-ZTAT and H8/3062F­ZTAT A-Mask Version Usage Note, in section 1
See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications, in appendix B
See appendix B.3, Address List
See 1.5, H8/3064F-ZTAT and H8/3062F­ZTAT A-Mask Version Usage Note, in section 1
Page 11
Contents
Section 1 Overview............................................................................................................ 1
1.1 Overview............................................................................................................................ 1
1.2 Block Diagram.................................................................................................................... 6
1.3 Pin Description................................................................................................................... 7
1.3.1 Pin Arrangement ................................................................................................... 7
1.3.2 Pin Functions......................................................................................................... 12
1.3.3 Pin Assignments in Each Mode............................................................................ 16
1.4 Notes on H8/3062F-ZTAT R-Mask Version ..................................................................... 20
1.4.1 Pin Arrangement ................................................................................................... 20
1.4.2 Product Type Names and Markings...................................................................... 21
1.4.3 Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version.. 21
1.5 Notes on H8/3064F-ZTAT and H8/3062F-ZTAT A-Mask Version.................................. 22
1.5.1 Pin Arrangement ................................................................................................... 22
1.5.2 Product Type Names and Markings...................................................................... 23
1.5.3 VCL Pin .................................................................................................................. 24
1.5.4 Note on Changeover to Mask ROM Version........................................................ 25
1.6 Setting Oscillation Settling Wait Time .............................................................................. 26
1.7 Caution on Crystal Resonator Connection......................................................................... 26
Section 2 CPU...................................................................................................................... 27
2.1 Overview............................................................................................................................ 27
2.1.1 Features ................................................................................................................. 27
2.1.2 Differences from H8/300 CPU.............................................................................. 28
2.2 CPU Operating Modes ....................................................................................................... 28
2.3 Address Space .................................................................................................................... 29
2.4 Register Configuration ....................................................................................................... 30
2.4.1 Overview............................................................................................................... 30
2.4.2 General Registers.................................................................................................. 31
2.4.3 Control Registers................................................................................................... 32
2.4.4 Initial CPU Register Values.................................................................................. 33
2.5 Data Formats ...................................................................................................................... 34
2.5.1 General Register Data Formats............................................................................. 34
2.5.2 Memory Data Formats.......................................................................................... 35
2.6 Instruction Set .................................................................................................................... 37
2.6.1 Instruction Set Overview ...................................................................................... 37
2.6.2 Instructions and Addressing Modes...................................................................... 38
2.6.3 Tables of Instructions Classified by Function....................................................... 39
2.6.4 Basic Instruction Formats...................................................................................... 48
2.6.5 Notes on Use of Bit Manipulation Instructions .................................................... 49
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2.7 Addressing Modes and Effective Address Calculation...................................................... 51
2.7.1 Addressing Modes................................................................................................. 51
2.7.2 Effective Address Calculation............................................................................... 53
2.8 Processing States................................................................................................................ 57
2.8.1 Overview............................................................................................................... 57
2.8.2 Program Execution State....................................................................................... 57
2.8.3 Exception-Handling State ..................................................................................... 58
2.8.4 Exception Handling Operation.............................................................................. 59
2.8.5 Bus-Released State................................................................................................ 60
2.8.6 Reset State............................................................................................................. 60
2.8.7 Power-Down State ................................................................................................ 61
2.9 Basic Operational Timing .................................................................................................. 61
2.9.1 Overview............................................................................................................... 61
2.9.2 On-Chip Memory Access Timing......................................................................... 61
2.9.3 On-Chip Supporting Module Access Timing........................................................ 62
2.9.4 Access to External Address Space........................................................................ 63
Section 3 MCU Operating Modes................................................................................. 65
3.1 Overview............................................................................................................................ 65
3.1.1 Operating Mode Selection .................................................................................... 65
3.1.2 Register Configuration.......................................................................................... 66
3.2 Mode Control Register (MDCR)........................................................................................ 66
3.3 System Control Register (SYSCR) .................................................................................... 67
3.4 Operating Mode Descriptions ............................................................................................ 69
3.4.1 Mode 1 .................................................................................................................. 69
3.4.2 Mode 2 .................................................................................................................. 69
3.4.3 Mode 3 .................................................................................................................. 70
3.4.4 Mode 4 .................................................................................................................. 70
3.4.5 Mode 5 .................................................................................................................. 70
3.4.6 Mode 6 .................................................................................................................. 70
3.4.7 Mode 7 .................................................................................................................. 70
3.5 Pin Functions in Each Operating Mode.............................................................................. 71
3.6 Memory Map in Each Operating Mode.............................................................................. 72
3.6.1 Comparison of H8/3062 Series Memory Maps.................................................... 72
3.6.2 Reserved Areas...................................................................................................... 73
Section 4 Exception Handling........................................................................................ 83
4.1 Overview............................................................................................................................ 83
4.1.1 Exception Handling Types and Priority................................................................ 83
4.1.2 Exception Handling Operation.............................................................................. 83
4.1.3 Exception Vector Table ........................................................................................ 84
4.2 Reset................................................................................................................................... 86
4.2.1 Overview............................................................................................................... 86
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4.2.2 Reset Sequence...................................................................................................... 86
4.2.3 Interrupts after Reset............................................................................................. 89
4.3 Interrupts ............................................................................................................................ 90
4.4 Trap Instruction.................................................................................................................. 90
4.5 Stack Status after Exception Handling............................................................................... 91
4.6 Notes on Stack Usage......................................................................................................... 92
Section 5 Interrupt Controller......................................................................................... 95
5.1 Overview............................................................................................................................ 95
5.1.1 Features ................................................................................................................. 95
5.1.2 Block Diagram...................................................................................................... 96
5.1.3 Pin Configuration.................................................................................................. 97
5.1.4 Register Configuration.......................................................................................... 97
5.2 Register Descriptions.......................................................................................................... 97
5.2.1 System Control Register (SYSCR)....................................................................... 97
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB).............................................. 98
5.2.3 IRQ Status Register (ISR)..................................................................................... 103
5.2.4 IRQ Enable Register (IER) ................................................................................... 104
5.2.5 IRQ Sense Control Register (ISCR)...................................................................... 105
5.3 Interrupt Sources ................................................................................................................ 106
5.3.1 External Interrupts................................................................................................. 106
5.3.2 Internal Interrupts.................................................................................................. 107
5.3.3 Interrupt Exception Handling Vector Table.......................................................... 107
5.4 Interrupt Operation............................................................................................................. 111
5.4.1 Interrupt Handling Process.................................................................................... 111
5.4.2 Interrupt Exception Handling Sequence ............................................................... 116
5.4.3 Interrupt Response Time....................................................................................... 117
5.5 Usage Notes........................................................................................................................ 118
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction....................... 118
5.5.2 Instructions that Inhibit Interrupts......................................................................... 119
5.5.3 Interrupts during EEPMOV Instruction Execution............................................... 119
Section 6 Bus Controller.................................................................................................. 121
6.1 Overview............................................................................................................................ 121
6.1.1 Features ................................................................................................................. 121
6.1.2 Block Diagram...................................................................................................... 122
6.1.3 Pin Configuration.................................................................................................. 123
6.1.4 Register Configuration.......................................................................................... 124
6.2 Register Descriptions.......................................................................................................... 124
6.2.1 Bus Width Control Register (ABWCR)................................................................ 124
6.2.2 Access State Control Register (ASTCR).............................................................. 125
6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 126
6.2.4 Bus Release Control Register (BRCR)................................................................. 130
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6.2.5 Bus Control Register (BCR) ................................................................................. 131
6.2.6 Chip Select Control Register (CSCR)................................................................... 133
6.2.7 Address Control Register (ADRCR)..................................................................... 134
6.3 Operation............................................................................................................................ 135
6.3.1 Area Division........................................................................................................ 135
6.3.2 Bus Specifications................................................................................................. 138
6.3.3 Memory Interfaces................................................................................................ 139
6.3.4 Chip Select Signals................................................................................................ 139
6.3.5 Address Output Method........................................................................................ 140
6.4 Basic Bus Interface............................................................................................................. 142
6.4.1 Overview............................................................................................................... 142
6.4.2 Data Size and Data Alignment.............................................................................. 142
6.4.3 Valid Strobes......................................................................................................... 143
6.4.4 Memory Areas....................................................................................................... 144
6.4.5 Basic Bus Control Signal Timing.......................................................................... 145
6.4.6 Wait Control.......................................................................................................... 152
6.5 Idle Cycle............................................................................................................................ 154
6.5.1 Operation............................................................................................................... 154
6.5.2 Pin States in Idle Cycle......................................................................................... 156
6.6 Bus Arbiter ......................................................................................................................... 156
6.6.1 Operation............................................................................................................... 157
6.7 Register and Pin Input Timing ........................................................................................... 159
6.7.1 Register Write Timing .......................................................................................... 159
6.7.2 BREQ Pin Input Timing........................................................................................ 160
Section 7 I/O Ports ............................................................................................................. 161
7.1 Overview............................................................................................................................ 161
7.2 Port 1 .................................................................................................................................. 165
7.2.1 Overview............................................................................................................... 165
7.2.2 Register Descriptions............................................................................................ 165
7.3 Port 2 .................................................................................................................................. 168
7.3.1 Overview............................................................................................................... 168
7.3.2 Register Descriptions............................................................................................ 169
7.4 Port 3 .................................................................................................................................. 172
7.4.1 Overview............................................................................................................... 172
7.4.2 Register Descriptions............................................................................................ 172
7.5 Port 4 .................................................................................................................................. 174
7.5.1 Overview............................................................................................................... 174
7.5.2 Register Descriptions............................................................................................ 175
7.6 Port 5 .................................................................................................................................. 177
7.6.1 Overview............................................................................................................... 177
7.6.2 Register Descriptions............................................................................................ 178
7.7 Port 6 .................................................................................................................................. 180
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7.7.1 Overview............................................................................................................... 180
7.7.2 Register Descriptions............................................................................................ 181
7.8 Port 7 .................................................................................................................................. 184
7.8.1 Overview............................................................................................................... 184
7.8.2 Register Description.............................................................................................. 185
7.9 Port 8 .................................................................................................................................. 186
7.9.1 Overview............................................................................................................... 186
7.9.2 Register Descriptions............................................................................................ 187
7.10 Port 9 .................................................................................................................................. 191
7.10.1 Overview............................................................................................................... 191
7.10.2 Register Descriptions............................................................................................ 192
7.11 Port A.................................................................................................................................. 196
7.11.1 Overview............................................................................................................... 196
7.11.2 Register Descriptions............................................................................................ 198
7.12 Port B.................................................................................................................................. 208
7.12.1 Overview............................................................................................................... 208
7.12.2 Register Descriptions............................................................................................ 210
Section 8 16-Bit Timer...................................................................................................... 217
8.1 Overview............................................................................................................................ 217
8.1.1 Features ................................................................................................................. 217
8.1.2 Block Diagrams..................................................................................................... 219
8.1.3 Pin Configuration.................................................................................................. 222
8.1.4 Register Configuration.......................................................................................... 223
8.2 Register Descriptions.......................................................................................................... 224
8.2.1 Timer Start Register (TSTR)................................................................................. 224
8.2.2 Timer Synchro Register (TSNC).......................................................................... 225
8.2.3 Timer Mode Register (TMDR)............................................................................. 226
8.2.4 Timer Interrupt Status Register A (TISRA).......................................................... 229
8.2.5 Timer Interrupt Status Register B (TISRB).......................................................... 231
8.2.6 Timer Interrupt Status Register C (TISRC).......................................................... 234
8.2.7 Timer Counters (16TCNT).................................................................................... 236
8.2.8 General Registers (GRA, GRB)............................................................................ 237
8.2.9 Timer Control Registers (16TCR)........................................................................ 238
8.2.10 Timer I/O Control Register (TIOR)...................................................................... 240
8.2.11 Timer Output Level Setting Register C (TOLR) .................................................. 242
8.3 CPU Interface..................................................................................................................... 244
8.3.1 16-Bit Accessible Registers.................................................................................. 244
8.3.2 8-Bit Accessible Registers.................................................................................... 246
8.4 Operation............................................................................................................................ 247
8.4.1 Overview............................................................................................................... 247
8.4.2 Basic Functions ..................................................................................................... 247
8.4.3 Synchronization .................................................................................................... 255
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8.4.4 PWM Mode........................................................................................................... 257
8.4.5 Phase Counting Mode........................................................................................... 261
8.4.6 16-Bit Timer Output Timing................................................................................. 263
8.5 Interrupts ............................................................................................................................ 264
8.5.1 Setting of Status Flags........................................................................................... 264
8.5.2 Timing of Clearing of Status Flags....................................................................... 266
8.5.3 Interrupt Sources ................................................................................................... 267
8.6 Usage Notes........................................................................................................................ 268
Section 9 8-Bit Timers...................................................................................................... 281
9.1 Overview............................................................................................................................ 281
9.1.1 Features ................................................................................................................. 281
9.1.2 Block Diagram...................................................................................................... 283
9.1.3 Pin Configuration.................................................................................................. 284
9.1.4 Register Configuration.......................................................................................... 285
9.2 Register Descriptions.......................................................................................................... 286
9.2.1 Timer Counters (8TCNT)...................................................................................... 286
9.2.2 Time Constant Registers A (TCORA).................................................................. 287
9.2.3 Time Constant Registers B (TCORB) .................................................................. 288
9.2.4 Timer Control Register (8TCR)............................................................................ 289
9.2.5 Timer Control/Status Registers (8TCSR) ............................................................. 292
9.3 CPU Interface..................................................................................................................... 297
9.3.1 8-Bit Registers....................................................................................................... 297
9.4 Operation............................................................................................................................ 299
9.4.1 8TCNT Count Timing........................................................................................... 299
9.4.2 Compare Match Timing........................................................................................ 300
9.4.3 Input Capture Signal Timing................................................................................. 301
9.4.4 Timing of Status Flag Setting................................................................................ 302
9.4.5 Operation with Cascaded Connection................................................................... 303
9.4.6 Input Capture Setting............................................................................................ 306
9.5 Interrupt.............................................................................................................................. 307
9.5.1 Interrupt Sources ................................................................................................... 307
9.5.2 A/D Converter Activation..................................................................................... 308
9.6 8-Bit Timer Application Example...................................................................................... 308
9.7 Usage Notes........................................................................................................................ 309
9.7.1 Contention between 8TCNT Write and Clear....................................................... 309
9.7.2 Contention between 8TCNT Write and Increment............................................... 310
9.7.3 Contention between TCOR Write and Compare Match....................................... 311
9.7.4 Contention between TCOR Read and Input Capture............................................ 312
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment 313
9.7.6 Contention between TCOR Write and Input Capture........................................... 314
9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection) ......................................................................................... 315
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9.7.8 Contention between Compare Matches A and B.................................................. 316
9.7.9 8TCNT Operation and Internal Clock Source Switchover................................... 316
Section 10 Programmable Timing Pattern Controller (TPC).................................. 319
10.1 Overview............................................................................................................................ 319
10.1.1 Features ................................................................................................................. 319
10.1.2 Block Diagram...................................................................................................... 320
10.1.3 Pin Configuration.................................................................................................. 321
10.1.4 Register Configuration.......................................................................................... 322
10.2 Register Descriptions.......................................................................................................... 323
10.2.1 Port A Data Direction Register (PADDR)............................................................ 323
10.2.2 Port A Data Register (PADR)............................................................................... 323
10.2.3 Port B Data Direction Register (PBDDR) ............................................................ 324
10.2.4 Port B Data Register (PBDR)................................................................................ 324
10.2.5 Next Data Register A (NDRA) ............................................................................. 325
10.2.6 Next Data Register B (NDRB).............................................................................. 327
10.2.7 Next Data Enable Register A (NDERA)............................................................... 329
10.2.8 Next Data Enable Register B (NDERB) ............................................................... 330
10.2.9 TPC Output Control Register (TPCR).................................................................. 331
10.2.10 TPC Output Mode Register (TPMR) .................................................................... 333
10.3 Operation............................................................................................................................ 335
10.3.1 Overview............................................................................................................... 335
10.3.2 Output Timing....................................................................................................... 336
10.3.3 Normal TPC Output.............................................................................................. 337
10.3.4 Non-Overlapping TPC Output.............................................................................. 339
10.3.5 TPC Output Triggering by Input Capture ............................................................. 341
10.4 Usage Notes........................................................................................................................ 342
10.4.1 Operation of TPC Output Pins.............................................................................. 342
10.4.2 Note on Non-Overlapping Output......................................................................... 342
Section 11 Watchdog Timer.............................................................................................. 345
11.1 Overview............................................................................................................................ 345
11.1.1 Features ................................................................................................................. 345
11.1.2 Block Diagram...................................................................................................... 346
11.1.3 Pin Configuration.................................................................................................. 346
11.1.4 Register Configuration.......................................................................................... 347
11.2 Register Descriptions.......................................................................................................... 347
11.2.1 Timer Counter (TCNT)......................................................................................... 347
11.2.2 Timer Control/Status Register (TCSR)................................................................. 348
11.2.3 Reset Control/Status Register (RSTCSR)............................................................. 350
11.2.4 Notes on Register Access...................................................................................... 351
11.3 Operation............................................................................................................................ 353
11.3.1 Watchdog Timer Operation .................................................................................. 353
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11.3.2 Interval Timer Operation ...................................................................................... 354
11.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 354
11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ................................... 355
11.4 Interrupts ............................................................................................................................ 356
11.5 Usage Notes........................................................................................................................ 356
Section 12 Serial Communication Interface ................................................................. 357
12.1 Overview............................................................................................................................ 357
12.1.1 Features ................................................................................................................. 357
12.1.2 Block Diagram...................................................................................................... 359
12.1.3 Pin Configuration.................................................................................................. 360
12.1.4 Register Configuration.......................................................................................... 361
12.2 Register Descriptions.......................................................................................................... 362
12.2.1 Receive Shift Register (RSR)................................................................................ 362
12.2.2 Receive Data Register (RDR) ............................................................................... 362
12.2.3 Transmit Shift Register (TSR).............................................................................. 363
12.2.4 Transmit Data Register (TDR).............................................................................. 363
12.2.5 Serial Mode Register (SMR)................................................................................. 364
12.2.6 Serial Control Register (SCR)............................................................................... 367
12.2.7 Serial Status Register (SSR).................................................................................. 371
12.2.8 Bit Rate Register (BRR)........................................................................................ 376
12.3 Operation............................................................................................................................ 384
12.3.1 Overview............................................................................................................... 384
12.3.2 Operation in Asynchronous Mode........................................................................ 387
12.3.3 Multiprocessor Communication............................................................................ 396
12.3.4 Synchronous Operation......................................................................................... 403
12.4 SCI Interrupts ..................................................................................................................... 411
12.5 Usage Notes........................................................................................................................ 412
12.5.1 Notes on Use of SCI.............................................................................................. 412
Section 13 Smart Card Interface ...................................................................................... 417
13.1 Overview............................................................................................................................ 417
13.1.1 Features ................................................................................................................. 417
13.1.2 Block Diagram...................................................................................................... 418
13.1.3 Pin Configuration.................................................................................................. 418
13.1.4 Register Configuration.......................................................................................... 419
13.2 Register Descriptions.......................................................................................................... 420
13.2.1 Smart Card Mode Register (SCMR)..................................................................... 420
13.2.2 Serial Status Register (SSR).................................................................................. 422
13.2.3 Serial Mode Register (SMR)................................................................................. 423
13.2.4 Serial Control Register (SCR)............................................................................... 424
13.3 Operation............................................................................................................................ 425
13.3.1 Overview............................................................................................................... 425
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13.3.2 Pin Connections.................................................................................................... 425
13.3.3 Data Format........................................................................................................... 426
13.3.4 Register Settings.................................................................................................... 428
13.3.5 Clock ..................................................................................................................... 430
13.3.6 Transmitting and Receiving Data.......................................................................... 432
13.4 Usage Notes........................................................................................................................ 439
Section 14 A/D Converter.................................................................................................. 443
14.1 Overview............................................................................................................................ 443
14.1.1 Features ................................................................................................................. 443
14.1.2 Block Diagram...................................................................................................... 444
14.1.3 Pin Configuration.................................................................................................. 445
14.1.4 Register Configuration.......................................................................................... 446
14.2 Register Descriptions.......................................................................................................... 446
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 446
14.2.2 A/D Control/Status Register (ADCSR) ................................................................ 447
14.2.3 A/D Control Register (ADCR).............................................................................. 449
14.3 CPU Interface ..................................................................................................................... 450
14.4 Operation............................................................................................................................ 452
14.4.1 Single Mode (SCAN = 0)...................................................................................... 452
14.4.2 Scan Mode (SCAN = 1)........................................................................................ 454
14.4.3 Input Sampling and A/D Conversion Time .......................................................... 456
14.4.4 External Trigger Input Timing.............................................................................. 457
14.5 Interrupts ............................................................................................................................ 458
14.6 Usage Notes........................................................................................................................ 458
Section 15 D/A Converter.................................................................................................. 463
15.1 Overview............................................................................................................................ 463
15.1.1 Features ................................................................................................................. 463
15.1.2 Block Diagram...................................................................................................... 464
15.1.3 Pin Configuration.................................................................................................. 465
15.1.4 Register Configuration.......................................................................................... 465
15.2 Register Descriptions.......................................................................................................... 466
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 466
15.2.2 D/A Control Register (DACR).............................................................................. 466
15.2.3 D/A Standby Control Register (DASTCR)........................................................... 468
15.3 Operation............................................................................................................................ 468
15.4 D/A Output Control............................................................................................................ 470
Section 16 RAM.................................................................................................................... 471
16.1 Overview............................................................................................................................ 471
16.1.1 Block Diagram...................................................................................................... 472
16.1.2 Register Configuration.......................................................................................... 472
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16.2 System Control Register (SYSCR) .................................................................................... 473
16.3 Operation............................................................................................................................ 474
Section 17 ROM [H8/3062F-ZTAT, H8/3062F-ZTAT ROM Version,
On-Chip Mask ROM Models]
17.1 Overview............................................................................................................................ 475
17.2 Overview of Flash Memory (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version)....... 476
17.2.1 Features ................................................................................................................. 476
17.2.2 Block Diagram...................................................................................................... 477
17.2.3 Pin Configuration.................................................................................................. 478
17.2.4 Register Configuration.......................................................................................... 478
17.3 Flash Memory Register Descriptions ................................................................................. 479
17.3.1 Flash Memory Control Register (FLMCR) .......................................................... 479
17.3.2 Erase Block Register (EBR).................................................................................. 482
17.3.3 RAM Control Register (RAMCR)........................................................................ 483
17.3.4 Flash Memory Status Register (FLMSR).............................................................. 485
17.4 On-Board Programming Mode........................................................................................... 486
17.4.1 Boot Mode............................................................................................................. 489
17.4.2 User Program Mode.............................................................................................. 494
17.5 Flash Memory Programming/Erasing ................................................................................ 496
17.5.1 Program Mode....................................................................................................... 497
17.5.2 Program-Verify Mode........................................................................................... 498
..................................................................... 475
17.5.3 Erase Mode............................................................................................................ 500
17.5.4 Erase-Verify Mode................................................................................................ 500
17.6 Flash Memory Protection ................................................................................................... 502
17.6.1 Hardware Protection.............................................................................................. 502
17.6.2 Software Protection............................................................................................... 504
17.6.3 Error Protection..................................................................................................... 504
17.6.4 NMI Input Disabling Conditions .......................................................................... 506
17.7 Flash Memory Emulation in RAM..................................................................................... 507
17.8 Flash Memory PROM Mode.............................................................................................. 509
17.8.1 Socket Adapters and Memory Map ...................................................................... 509
17.8.2 Notes on Use of PROM Mode.............................................................................. 510
17.9 Flash Memory Programming and Erasing Precautions...................................................... 511
17.10 Mask ROM (H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,
H8/3060 Mask ROM Version) Overview.......................................................................... 516
17.10.1 Block Diagram...................................................................................................... 516
17.11 Notes on Ordering Mask ROM Version Chips .................................................................. 517
17.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions. 518
Section 18 Flash Memory [H8/3064F-ZTAT]............................................................. 519
18.1 Overview............................................................................................................................ 519
18.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version........ 520
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18.2 Features .............................................................................................................................. 521
18.2.1 Block Diagram...................................................................................................... 522
18.2.2 Pin Configuration.................................................................................................. 523
18.2.3 Register Configuration.......................................................................................... 523
18.3 Register Descriptions.......................................................................................................... 524
18.3.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 524
18.3.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 527
18.3.3 Erase Block Register 1 (EBR1) ............................................................................ 528
18.3.4 Erase Block Register 2 (EBR2) ............................................................................ 528
18.3.5 RAM Control Register (RAMCR)........................................................................ 529
18.4 Overview of Operation....................................................................................................... 531
18.4.1 Mode Transitions.................................................................................................. 531
18.4.2 On-Board Programming Modes............................................................................ 533
18.4.3 Flash Memory Emulation in RAM........................................................................ 535
18.4.4 Block Configuration.............................................................................................. 536
18.5 On-Board Programming Mode........................................................................................... 537
18.5.1 Boot Mode............................................................................................................. 538
18.5.2 User Program Mode.............................................................................................. 543
18.6 Flash Memory Programming/Erasing ................................................................................ 545
18.6.1 Program Mode....................................................................................................... 547
18.6.2 Program-Verify Mode........................................................................................... 548
18.6.3 Erase Mode............................................................................................................ 552
18.6.4 Erase-Verify Mode................................................................................................ 552
18.7 Flash Memory Protection ................................................................................................... 554
18.7.1 Hardware Protection.............................................................................................. 554
18.7.2 Software Protection............................................................................................... 555
18.7.3 Error Protection..................................................................................................... 555
18.8 Flash Memory Emulation in RAM..................................................................................... 558
18.9 NMI Input Disabling Conditions........................................................................................ 560
18.10 Flash Memory PROM Mode.............................................................................................. 561
18.10.1 Socket Adapters and Memory Map ...................................................................... 561
18.10.2 Notes on Use of PROM Mode .............................................................................. 562
18.11 Flash Memory Programming and Erasing Precautions...................................................... 562
Section 19 Flash Memory [H8/3062F-ZTAT A-Mask Version]............................ 569
19.1 Overview............................................................................................................................ 569
19.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version........ 570
19.2 Features............................................................................................................................... 571
19.2.1 Block Diagram...................................................................................................... 572
19.2.2 Pin Configuration.................................................................................................. 573
19.2.3 Register Configuration.......................................................................................... 573
19.3 Register Descriptions.......................................................................................................... 574
19.3.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 574
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19.3.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 577
19.3.3 Erase Block Register (EBR).................................................................................. 578
19.3.4 RAM Control Register (RAMCR)........................................................................ 579
19.4 Overview of Operation....................................................................................................... 581
19.4.1 Mode Transitions.................................................................................................. 581
19.4.2 On-Board Programming Modes............................................................................ 583
19.4.3 Flash Memory Emulation in RAM........................................................................ 585
19.4.4 Block Configuration.............................................................................................. 586
19.5 On-Board Programming Mode........................................................................................... 587
19.5.1 Boot Mode............................................................................................................. 588
19.5.2 User Program Mode.............................................................................................. 593
19.6 Flash Memory Programming/Erasing ................................................................................ 595
19.6.1 Program Mode....................................................................................................... 597
19.6.2 Program-Verify Mode........................................................................................... 598
19.6.3 Erase Mode............................................................................................................ 602
19.6.4 Erase-Verify Mode................................................................................................ 602
19.7 Flash Memory Protection ................................................................................................... 604
19.7.1 Hardware Protection.............................................................................................. 604
19.7.2 Software Protection............................................................................................... 605
19.7.3 Error Protection..................................................................................................... 605
19.8 Flash Memory Emulation in RAM..................................................................................... 608
19.9 NMI Input Disabling Conditions........................................................................................ 609
19.10 Flash Memory PROM Mode.............................................................................................. 610
19.10.1 Socket Adapters and Memory Map....................................................................... 610
19.10.2 Notes on Use of PROM Mode .............................................................................. 611
19.11 Flash Memory Programming and Erasing Precautions...................................................... 612
19.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions 618
Section 20 Clock Pulse Generator ................................................................................... 619
20.1 Overview............................................................................................................................ 619
20.1.1 Block Diagram...................................................................................................... 619
20.2 Oscillator Circuit................................................................................................................ 620
20.2.1 Connecting a Crystal Resonator............................................................................ 620
20.2.2 External Clock Input ............................................................................................. 622
20.3 Duty Adjustment Circuit .................................................................................................... 624
20.4 Prescalers............................................................................................................................ 624
20.5 Frequency Divider.............................................................................................................. 624
20.5.1 Register Configuration.......................................................................................... 625
20.5.2 Division Control Register (DIVCR) ..................................................................... 625
20.5.3 Usage Notes.......................................................................................................... 626
Section 21 Power-Down State .......................................................................................... 627
21.1 Overview............................................................................................................................ 627
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21.2 Register Configuration ....................................................................................................... 629
21.2.1 System Control Register (SYSCR) ....................................................................... 629
21.2.2 Module Standby Control Register H (MSTCRH)................................................. 631
21.2.3 Module Standby Control Register L (MSTCRL).................................................. 632
21.3 Sleep Mode......................................................................................................................... 634
21.3.1 Transition to Sleep Mode...................................................................................... 634
21.3.2 Exit from Sleep Mode ........................................................................................... 634
21.4 Software Standby Mode ..................................................................................................... 634
21.4.1 Transition to Software Standby Mode .................................................................. 634
21.4.2 Exit from Software Standby Mode........................................................................ 635
21.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 635
21.4.4 Sample Application of Software Standby Mode................................................... 637
21.4.5 Note....................................................................................................................... 637
21.4.6 Cautions on Clearing the software Standby Mode of F-ZTAT Version............... 638
21.5 Hardware Standby Mode.................................................................................................... 639
21.5.1 Transition to Hardware Standby Mode................................................................. 639
21.5.2 Exit from Hardware Standby Mode...................................................................... 639
21.5.3 Timing for Hardware Standby Mode.................................................................... 639
21.6 Module Standby Function .................................................................................................. 640
21.6.1 Module Standby Timing........................................................................................ 640
21.6.2 Read/Write in Module Standby............................................................................. 640
21.6.3 Usage Notes.......................................................................................................... 640
21.7 System Clock Output Disabling Function.......................................................................... 641
Section 22 Electrical Characteristics............................................................................... 643
22.1 Electrical Characteristics of H8/3062 Mask ROM Version,
H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version.................................... 645
22.1.1 Absolute Maximum Ratings.................................................................................. 645
22.1.2 DC Characteristics................................................................................................ 646
22.1.3 AC Characteristics................................................................................................ 657
22.1.4 A/D Conversion Characteristics............................................................................ 663
22.1.5 D/A Conversion Characteristics............................................................................ 665
22.2 Electrical Characteristics of H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version.... 666
22.2.1 Absolute Maximum Ratings.................................................................................. 666
22.2.2 DC Characteristics................................................................................................ 667
22.2.3 AC Characteristics................................................................................................ 675
22.2.4 A/D Conversion Characteristics............................................................................ 681
22.2.5 D/A Conversion Characteristics............................................................................ 683
22.2.6 Flash Memory Characteristics .............................................................................. 684
22.3 Electrical Characteristics of H8/3064F-ZTAT................................................................... 688
22.3.1 Absolute Maximum Ratings.................................................................................. 688
22.3.2 DC Characteristics................................................................................................ 689
22.3.3 AC Characteristics................................................................................................ 697
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22.3.4 A/D Conversion Characteristics............................................................................ 703
22.3.5 D/A Conversion Characteristics............................................................................ 705
22.3.6 Flash Memory Characteristics .............................................................................. 706
22.4 Electrical Characteristics of H8/3062F-ZTAT A-Mask Version ....................................... 710
22.4.1 Absolute Maximum Ratings.................................................................................. 710
22.4.2 DC Characteristics................................................................................................ 711
22.4.3 AC Characteristics................................................................................................ 719
22.4.4 A/D Conversion Characteristics............................................................................ 725
22.4.5 D/A Conversion Characteristics............................................................................ 727
22.4.6 Flash Memory Characteristics .............................................................................. 728
22.5 Operational Timing ............................................................................................................ 732
22.5.1 Clock Timing........................................................................................................ 732
22.5.2 Control Signal Timing .......................................................................................... 733
22.5.3 Bus Timing............................................................................................................ 735
22.5.4 TPC and I/O Port Timing...................................................................................... 739
22.5.5 Timer Input/Output Timing .................................................................................. 739
22.5.6 SCI Input/Output Timing...................................................................................... 740
Appendix A Instruction Set............................................................................................... 741
A.1 Instruction List.................................................................................................................... 741
A.2 Operation Code Maps......................................................................................................... 756
A.3 Number of States Required for Execution.......................................................................... 759
Appendix B Internal I/O Registers................................................................................. 768
B.1 Address List (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,
H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,
H8/3060 Mask ROM Version)........................................................................................... 769
B.2 Address List (H8/3064F-ZTAT) ........................................................................................ 779
B.3 Address List (H8/3062F-ZTAT A-Mask Version) ............................................................ 789
B.4 Functions............................................................................................................................ 799
Appendix C I/O Port Block Diagrams........................................................................... 874
C.1 Port 1 Block Diagram......................................................................................................... 874
C.2 Port 2 Block Diagram......................................................................................................... 875
C.3 Port 3 Block Diagram......................................................................................................... 876
C.4 Port 4 Block Diagram......................................................................................................... 877
C.5 Port 5 Block Diagram......................................................................................................... 878
C.6 Port 6 Block Diagrams ....................................................................................................... 879
C.7 Port 7 Block Diagrams ....................................................................................................... 884
C.8 Port 8 Block Diagrams ....................................................................................................... 885
C.9 Port 9 Block Diagrams ....................................................................................................... 889
C.10 Port A Block Diagrams...................................................................................................... 895
C.11 Port B Block Diagrams ...................................................................................................... 898
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Appendix D Pin States........................................................................................................ 904
D.1 Port States in Each Mode ................................................................................................... 904
D.2 Pin States at Reset.............................................................................................................. 908
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode
............................................................................................... 911
Appendix F Product Code Lineup.................................................................................. 912
Appendix G Package Dimensions................................................................................... 914
Appendix H Comparison of H8/300H Series Product Specifications.................. 917
H.1 Differences between H8/3067 and H8/3062 Series, H8/3048 Series,
H8/3007 and H8/3006, and H8/3002.................................................................................. 917
H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)......... 920
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Section 1 Overview
1.1 Overview
The H8/3062 Series is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities.
The seven members of the H8/3062 Series are the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 (mask ROM version), H8/3061 (mask ROM version), H8/3060 (mask ROM version), H8/3064F-ZTAT, and H8/3062F-ZTAT A-mask version.
Seven MCU operating modes offer a choice of bus width and address space size. The modes (modes 1 to 7) include two single-chip modes and five expanded modes.
In addition to its mask ROM versions, the H8/3062 Series has F-ZTAT™* versions with on-chip flash memory that allows programs to be freely rewritten by the user. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions.
Table 1.1 summarizes the features of the H8/3062 Series.
Note: * F-ZTATTM (Flexible ZTAT) is a trademark of Hitachi, Ltd.
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Table 1.1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight 32-bit registers)
High-speed operation
H8/3062F-ZTZT
Maximum clock rate
20 MHz 100 ns 700 ns
Add /subtract
Multiply /divide
H8/3062F-ZTAT R-Mask version H8/3062 (mask ROM version) H8/3061 (mask ROM version) H8/3060 (mask ROM version)
H8/3064F-ZTAT
25 MHz 80 ns 560 ns
H8/3062F-ZTAT A-Mask version 16-Mbyte address space
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
Memory ROM RAM
H8/3062F-ZTAT
128 kbytes 4 kbytes H8/3062F-ZTAT R-mask version H8/3062F-ZTAT A-mask version H8/3062 (mask ROM version)
H8/3061 (mask ROM version) 96 kbytes 4 kbytes H8/3060 (mask ROM version) 64 kbytes 2 kbytes H8/3064F-ZTAT 256 kbytes 8 kbytes
Interrupt controller
• Seven external interrupt pins: NMI, IRQ
• 27 internal interrupts
to IRQ
0
5
• Three selectable interrupt priority levels
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Feature Description
Bus controller
16-bit timer, 3 channels
• Address space can be partitioned into eight areas, with independent bus specifications in each area
• Chip select output available for areas 0 to 7
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of two wait modes
• Number of program wait states selectable for each area
• Bus arbitration function
• Two address update modes (not available in the H8/3062F-ZTAT)
• Three 16-bit timer channels, capable of processing up to six pulse outputs or
six pulse inputs
• 16-bit timer counter (channels 0 to 2)
• Two multiplexed output compare/input capture pins (channels 0 to 2)
• Operation can be synchronized (channels 0 to 2)
• PWM mode available (channels 0 to 2)
8-bit timer, 4 channels
Programmable timing pattern controller (TPC)
Watchdog timer (WDT), 1 channel
Serial communication interface (SCI), 2 channels
• Phase counting mode available (channel 2)
• 8-bit up-counter (external event count capability)
• Two time constant registers
• Two channels can be connected
• Maximum 16-bit pulse output, using 16-bit timer as time base
• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
• Non-overlap mode available
• Internal reset signal can be generated by overflow
• Reset signal can be output externally (not available in on-chip flash memory
versions)
• Usable as an interval timer
• Selection of asynchronous or synchronous mode
• Full duplex: can transmit and receive simultaneously
• On-chip baud-rate generator
• Smart card interface functions added
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Feature Description
A/D converter
• Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• A/D conversion can be started by an external trigger or 8-bit timer compare-
match
D/A converter
• Resolution: 8 bits
• Two channels
• D/A outputs can be sustained in software standby mode
I/O ports
• 70 input/output pins
• 9 input-only pins
Operating modes Seven MCU operating modes
Address
Mode
Space
Mode 1 1 Mbyte A
Address Pins
to A
19
Initial Bus Width
0
8 bits 16 bits
Max. Bus Width
Power-down state
Other features
Mode 2 1 Mbyte A19 to A Mode 3 16 Mbytes A23 to A Mode 4 16 Mbytes A23 to A Mode 5 16 Mbytes A23 to A
0
0
0
0
16 bits 16 bits 8 bits 16 bits 16 bits 16 bits
8 bits 16 bits Mode 6 64 kbytes — — — Mode 7 1 Mbyte — — —
• On-chip ROM is disabled in modes 1 to 4
• In the versions with on-chip flash memory, an on-board programming mode is
supported that allows flash memory to be programmed in modes 5 and 7.
• Sleep mode
• Software standby mode
• Hardware standby mode
• Module standby function
• Programmable system clock frequency division
• On-chip clock pulse generator
4
Page 30
Feature Description
Product lineup
Package
Product Type Model
H8/3062F-ZTAT 5 V operation HD64F3062F 100-pin QFP (FP-100B)
HD64F3062TE 100-pin TQFP (TFP-100B) HD64F3062FP 100-pin QFP (FP-100A)
H8/3062F-ZTAT 5 V operation HD64F3062RF 100-pin QFP (FP-100B) R-mask version
3 V operation HD64F3062RVF 100-pin QFP (FP-100B)
H8/3062 mask 5 V operation HD6433062F 100-pin QFP (FP-100B) ROM version
Low-voltage HD6433062VF 100-pin QFP (FP-100B) operation
H8/3061 mask 5 V operation HD6433061F 100-pin QFP (FP-100B) ROM version
HD64F3062RTE 100-pin TQFP (TFP-100B) HD64F3062RFP 100-pin QFP (FP-100A)
HD64F3062RVTE 100-pin TQFP (TFP-100B) HD64F3062RVFP 100-pin QFP (FP-100A)
HD6433062TE 100-pin TQFP (TFP-100B) HD6433062FP 100-pin QFP (FP-100A)
HD6433062VTE 100-pin TQFP (TFP-100B) HD6433062VFP 100-pin QFP (FP-100A)
HD6433061TE 100-pin TQFP (TFP-100B)
(Hitachi Package Code)
HD6433061FP 100-pin QFP (FP-100A)
Low-voltage HD6433061VF 100-pin QFP (FP-100B) operation
H8/3060 mask 5 V operation HD6433060F 100-pin QFP (FP-100B) ROM version
Low-voltage HD6433060VF 100-pin QFP (FP-100B) operation
H8/3064F-ZTAT 5 V operation HD64F3064F 100-pin QFP (FP-100B)
3 V operation HD64F3064VF 100-pin QFP (FP-100B)
H8/3062F-ZTAT 5 V operation HD64F3062AF 100-pin QFP (FP-100B) A-mask version
HD6433061VTE 100-pin TQFP (TFP-100B) HD6433061VFP 100-pin QFP (FP-100A)
HD6433060TE 100-pin TQFP (TFP-100B) HD6433060FP 100-pin QFP (FP-100A)
HD6433060VTE 100-pin TQFP (TFP-100B) HD6433060VFP 100-pin QFP (FP-100A)
HD64F3064TE 100-pin TQFP (TFP-100B) HD64F3064FP 100-pin QFP (FP-100A)
HD64F3064VTE 100-pin TQFP (TFP-100B) HD64F3064VFP 100-pin QFP (FP-100A)
HD64F3062ATE 100-pin TQFP (TFP-100B)
HD64F3062AFP 100-pin QFP (FP-100A)
3 V operation HD64F3062AVF 100-pin QFP (FP-100B)
HD64F3062AVTE 100-pin TQFP (TFP-100B) HD64F3062AVFP 100-pin QFP (FP-100A)
5
Page 31
1.2 Block Diagram
Figure 1.1 shows an internal block diagram.
ADTRG/CS
CS CS
MD MD MD
EXTAL
XTAL STBY
RES
RESO/FWE
φ/P6
LWR/P66
HWR/P6
RD/P6
AS/P6
BACK/P6
BREQ/P6
WAIT/P6
CS0/P84
/IRQ3/P83
1
/IRQ2/P82
2
/IRQ1/P81
3
IRQ
/P80
0
NMI
*2
CCCCSSSSSSSSSS
CL
VVVVVVVVV
1514131211109 7654321
SS
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
8
7654321
0
7654321
P3 /D
P3 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
0 0
P4 /D
Port 3 Port 4
Address bus
P5 /A
3
2 1 0
Data bus (upper)
Data bus (lower)
Port 5Port 9
H8/300H CPU
*1
generator
Clock pulse
Port 2
7
5 4 3
Port 6
2 1 0
Interrupt controller
ROM (mask ROM or flash memory)
Bus controller
Port 1
RAM
Watchdog timer
(WDT)
Port 8
16-bit timer unit
8-bit timer unit
Programmable
timing pattern
controller (TPC)
Serial communication
interface
×
(SCI) 2 channels
A/D converter
D/A converter
19
P5 /A
2
18
P5 /A
1
17
P5 /A
0
16
P2 /A
7
15
P2 /A
6
14
P2 /A
5
13
P2 /A
4
12
P2 /A
3
11
P2 /A
2
10
P2 /A
1
9
P2 /A
0
8
P1 /A
7
7
P1 /A
6
6
P1 /A
5
5
P1 /A
4
4
P1 /A
3
3
P1 /A
2
2
P1 /A
1
1
P1 /A
0
0
P9 /SCK /IRQ
5
1
P9 /SCK /IRQ
4
0
P9 /RxD
3
1
P9 /RxD
2
0
P9 /TxD
1
1
P9 /TxD
0
0
5 4
Port B
7
6
5
/PB
14
TP
/PB
13
TP
4
/PB
12
TP
/PB
15
TP
Notes: 1. Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash memory versions.
2. The 5 V operation models of the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version have a V require the connection of an external capacitor.
6
Port A
7
6
5
4
3
3
/PB
11
/TP
3
/TMIO
4
CS
2
/PB
10
/TP
2
/TMO
5
CS
1
/PB
9
/TP
1
/TMIO
6
CS
0
/PB
8
/TP
0
/TMO
7
CS
/PA
/PA
7
6
/TP
/TP
2
2
/TIOCB
/TIOCA
20
21
A
A
/PA
5
/TP
1
/TIOCB
22
A
2
/PA
/PA
/PA
4
3
2
/TP
/TP
/TP
1
0
0
/TIOCA
23
A
TCLKD/TIOCB
TCLKC/TIOCA
1
/PA
1
TCLKB/TP
Figure 1.1 Block Diagram
0
REF
/PA
V
0
TCLKA/TP
CC
AV
AV
Port 7
7
6
5
4
3
2
1
SS
/P7
/P7
/P7
/P7
5
AN
4
AN
/P7
3
AN
7
/AN
1
DA
6
/AN
0
DA
/P7
2
AN
/P7
1
AN
0
/P7
0
AN
pin, and
CL
Page 32
1.3 Pin Description
1.3.1 Pin Arrangement
The pin arrangement of the H8/3062 Series is shown in figures 1.2 to 1.5. Differences in the H8/3062 Series pin arrangements are shown in table 1.2. The 5 V operation models of the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version have a VCL pin. See section 1.5, Notes on H8/3064F-ZTAT and H8/3062F-ZTAT A-Mask Version. Except for the differences shown in table 1.2, the pin arrangements are the same.
Table 1.2 Comparison of H8/3062 Series Pin Arrangements
H8/3062 F-ZTAT
H8/3064
H8/3062F-ZTAT, H8/3062 H8/3061 H8/3060
F-ZTAT
Pin H8/3062F-ZTAT Mask ROM Mask ROM Mask ROM Operation Model
Package Number R-Mask Version Version Version Version 5 V 3 V 5 V 3 V
A-Mask Version
FP-100B 1 V (TFP-100B)
10 FWE RESO RESO RESO FWE FWE FWE FWE
FP-100A 3 V
12 FWE RESO RESO RESO FWE FWE FWE FWE
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
V
CL
CL
V
V
CC
CC
V
V
CL
CL
V
CC
V
CC
7
Page 33
2
1
0
MDMDMD
6
P6 /LWR
P6 /HWR
543
P6 /RD
CC
P6 /ASVXTAL
SS
EXTALVNMI
RES
/φ
STBY
P6
7
2
1
P6 /BACK
P6 /BREQ
1918171615
0
3
SS
P6 /WAITVP5 /A
P5 /A
2
1
0
P5 /A
P5 /A
7
P2 /A
P2 /A
14 6
AV
CC
V
REF
P7 /AN
0
P7 /AN
1
P7 /AN
2
P7 /AN
3
P7 /AN
4
P7 /AN
5
P7 /AN /DA
6
6
P7 /AN /DA
7
7
AV
SS
/P8 IRQ
0
/P8 /IRQCS
3
1
CS2/IRQ2/P8
ADTRG/CS1/IRQ3/P8
CS0/P8
V TCLKA/TP0/PA TCLKB/TP1/PA
TCLKC/TIOCA0/TP2/PA TCLKD/TIOCB0/TP3/PA
A23/TIOCA1/TP4/PA A22/TIOCB1/TP5/PA A21/TIOCA2/TP6/PA A20/TIOCB2/TP7/PA
75747372717069686766656463626160595857565554535251
76 77 78
0
79
1
80
2
81
3
82
4
83
5
84
0
85
1
86
0
87 88
1
89
2
90
3
91
4
92
SS
93
0
94
1
95
2
96
3
97
4
98
5
99
6
100
7
123
0
CC
V
/PB
8
/TP
0
/TMO
7
CS
4
1
/PB
/PB
9
/TP
1
/TP
/ TMIO
/TMO
6
CS
CS
2
10 2
5
567
3
4
/PB
/PB
11
12
TP
/TP
3
/ TMIO
4
CS
89101112131415161718192021222324
5
6
7
/PB
/PB
/PB
13
14
15
TP
TP
TP
Top view
(FP-100B, TFP-100B)
*
0
1
2
SS
V
FWE
/RESO
0
TxD /P9
3
1
0
1
TxD /P9
RxD /P9
RxD /P9
4
5
0
1
0
1
0
1
D /P4
D /P4
D /P4
4
5
IRQ /SCK /P9
IRQ /SCK /P9
2 2
3
SS
V
3
D /P4
4
5
4
5
D /P4
D /P4
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
25
6 6
D /P4
A /P2
13
A /P2
12
A /P2
11
A /P2
10
A /P2
9
A /P2
8
V
SS
A /P1
7
A /P1
6
A /P1
5
A /P1
4
A /P1
3
A /P1
2
A /P1
1
A /P1
0
V
CC
D /P3
15
D /P3
14
D /P3
13
D /P3
12
D /P3
11
D /P3
10
D /P3
9
D /P3
8
D /P4
7
5 4 3 2 1 0
7 6
5 4 3 2 1 0
7 6
5 4 3 2 1 0 7
Note: * Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash memory versions.
Figure 1.2 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,
H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,
(FP-100B or TFP-100B Package, Top View)
8
and H8/3060 Mask ROM Version
Page 34
0
/AN
0
REF
P7
V
AVCCMD2MD1MD0P6
/LWR
/HWR
6
5
P6
/RD
4
P6
/AS
3
P6
CC
V
XTAL
EXTAL
VSSNMI
RES
19
18
17
16
15
14
13
/φ
/BACK
/BREQ
/WAIT
/A
/A
/A
/A
7
2
1
0
3
STBY
P6
P6
P6
P6
SS
P5
P5
V
/A
2
1
0
7
P5
P5
P2
/A P2
12
/A
/A
6
5
4
P2
P2
P71/AN P72/AN P73/AN P74/AN
P75/AN P76/AN6/DA P77/AN7/DA
P80/IRQ P81/IRQ1/CS P82/IRQ2/CS
P83/IRQ3/CS1/ADTRG
P8
PA0/TP0/TCLKA PA
/TP1/TCLKB
PA
/TP2/TIOCA0/TCLKC
2
PA
/TP3/TIOCB0/TCLKD
3
PA PA5/TP5/TIOCB1/A
1
/TP4/TIOCA1/A
4
AV
4
/CS
V
SS
SS
8079787776
81
1
82
2
83
3
84
4
85
5
86
0
87
1
88 89
0
90
3
91
2
92 93
0
94 95 96 97 98 99
23
100
22
1234567891011121314151617181920212223242526272829
6
7
26
27
21
20
A /TIOCA /TP /PA
A /TIOCB /TP /PA
75747372717069686766656463626160595857565554535251
Top view (FP-100A)
2
0
2
1
CC
V
08
19
7
6
CS /TMO /TP /PB
CS /TMIO /TP /PB
4125136
3
11
TP /PB
3
210
5
4
CS /TMO /TP /PB
CS /TMIO /TP /PB
7
14
15
TP /PB
TP /PB
TP /PB
*
0
SS
V
0
TxD /P9
RESO/FWE
3
1
0
1
1
TxD /P9
RxD /P9
RxD /P9
0
2
3
1
0
1
2
D /P4
D /P4
3
D /P4
D /P4
404
515
IRQ /SCK /P9
IRQ /SCK /P9
SS
V
6
5
4
5
6770819
4
D /P4
D /P4
D /P4
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
30
D /P4
D /P3
D /P3
A
/P2
A
/P2
A
/P2
A
/P2
8
V
SS
A /P1
7
A /P1
6
A /P1
5
A /P1
4
A /P1
3
A /P1
2
A /P1
1
A /P1
0
V
CC
D /P3
15
D /P3
14
D /P3
13
D /P3
12
D /P3
11
D /P3
10
3 11
210 19 0
7 6 5 4 3 2
1 0
7 6 5 4 3
2
Note: * Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash memory versions.
Figure 1.3 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,
H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,
and H8/3060 Mask ROM Version
(FP-100A Package, Top View)
9
Page 35
2
1
0
MDMDMD
6
P6 /LWR
P6 /HWR
5
4
3
P6 /RD
P6 /ASVXTAL
CC
SS
EXTALVNMI
RES
/φ
STBY
P6
7
2
1
P6 /BACK
P6 /BREQ
1918171615
0
3
SS
P6 /WAITVP5 /A
P5 /A
2
1
P5 /A
P5 /A
0
7
P2 /A
P2 /A
14 6
AV
CC
V
REF
P7 /AN
0
P7 /AN
1
P7 /AN
2
P7 /AN
3
P7 /AN
4
P7 /AN
5
P7 /AN /DA
6
6
P7 /AN /DA
7
7
AV
SS
/P8 IRQ
0
/P8 /IRQCS
3
1
CS2/IRQ2/P8
ADTRG/CS1/IRQ3/P8
CS0/P8
V TCLKA/TP0/PA TCLKB/TP1/PA
TCLKC/TIOCA0/TP2/PA TCLKD/TIOCB0/TP3/PA
A23/TIOCA1/TP4/PA A22/TIOCB1/TP5/PA A21/TIOCA2/TP6/PA A20/TIOCB2/TP7/PA
75747372717069686766656463626160595857565554535251
76 77 78
0
79
1
80
2
81
3
82
4
83
5
84
0
85
1
86
0
87 88
1
89
2
90
3
91
4
92
SS
93
0
94
1
95
2
96
3
97
4
98
5
99
6
100
7
1
*
CL
/V
CC
V
234
0
1
/PB
/PB
8
9
/TP
/TP
0
1
/TMO
/ TMIO
7
6
CS
CS
2
/PB
10
/TP
2
/TMO
5
CS
567
3
4
/PB
/PB
11
12
TP
/TP
3
/ TMIO
4
CS
5
/PB
13
TP
8
6
/PB
14
TP
9
7
/PB
15
TP
Top view
(FP-100B, TFP-100B)
101112131415161718192021222324
FWE
SS
V
TxD /P9
0
1
0
1
TxD /P9
2
3
4
0
1
0
RxD /P9
RxD /P9
4
IRQ /SCK /P9
5
0
1
1
0
1
D /P4
D /P4
5
IRQ /SCK /P9
2
3
2
3
D /P4
D /P4
V
SS
4
5
4
5
D /P4
D /P4
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
25
6 6
D /P4
1
P25/A
13
P24/A
12
P23/A
11
P22/A
10
P21/A
9
P2
0/A8
V
SS
P17/A
7
P16/A
6
P15/A
5
P14/A
4
P13/A
3
P12/A
2
P11/A
1
P1
0/A0
V
CC
D15/P37 D
/P36
14
D13/P35 D12/P3 D11/P33 D10/P32 D9/P31 D8/P3
0
D7/P47
4
0.1 µF
Note: * VCL pin in 5 V operation models, VCC pin in 3 V operation models.
An external capacitor must be connected to the VCL pin.
Figure 1.4 Pin Arrangement of H8/3064F-ZTAT and H8/3062F-ZTAT A-Mask Version
(FP-100B or TFP-100B Package, Top View)
10
Page 36
0
/AN
0
REF
P7
V
AVCCMD2MD1MD0P6
/LWR
/HWR
6
5
P6
/RD
4
P6
/AS
3
P6
CC
V
XTAL
EXTAL
VSSNMI
RES
STBY
/φ
7
P6
/BACK
/BREQ
2
1
P6
P6
/WAIT
0
SS
P6
V
19
/A
3
P5
/A P5
18
17
16
15
14
13
/A
/A
/A
2
1
0
7
P5
P5
P2
/A P2
12
/A
/A
6
5
4
P2
P2
P71/AN P72/AN P73/AN P74/AN
P75/AN P76/AN6/DA P77/AN7/DA
P80/IRQ P81/IRQ1/CS P82/IRQ2/CS
P83/IRQ3/CS1/ADTRG
P8
PA0/TP0/TCLKA PA
/TP1/TCLKB
PA
/TP2/TIOCA0/TCLKC
2
PA
/TP3/TIOCB0/TCLKD
3
PA PA5/TP5/TIOCB1/A
1
/TP4/TIOCA1/A
4
AV
4
/CS
V
SS
SS
8079787776
81
1
82
2
83
3
84
4
85
5
86
0
87
1
88 89
0
90
3
91
2
92 93
0
94 95 96 97 98 99
23
100
22
1234567891011121314151617181920212223242526272829
6
7
26
27
21
20
A /TIOCA /TP /PA
A /TIOCB /TP /PA
75747372717069686766656463626160595857565554535251
Top view (FP-100A)
2
0
2
1
*
CL
/V
CC
V
08
19
7
6
CS /TMO /TP /PB
CS /TMIO /TP /PB
4125136
3
11
TP /PB
3
210
5
4
CS /TMO /TP /PB
CS /TMIO /TP /PB
7
14
15
TP /PB
TP /PB
TP /PB
V
FWE
SS
0
TxD /P9
0
1
0
1
TxD /P9
RxD /P9
3
1
RxD /P9
0
1
0
1
D /P4
D /P4
404
515
IRQ /SCK /P9
IRQ /SCK /P9
2
3
V
2
3
D /P4
D /P4
SS
6
5
4
5
6770819
4
D /P4
D /P4
D /P4
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
30
D /P4
D /P3
D /P3
3
P23/A
11
P22/A
10
P21/A
9
P20/A
8
V
SS
P17/A
7
P16/A6 P1
5/A5
P14/A
4
P13/A
3
P12/A
2
P11/A
1
P10/A
0
V
CC
D /P3
15
D /P3
14
D /P3
13
D /P3
12
D /P3
11
D /P3
10
7 6 5 4 3
2
0.1 µF
Note: * VCL pin in 5 V operation models, VCC pin in 3 V operation models.
An external capacitor must be connected to the VCL pin.
Figure 1.5 Pin Arrangement of H8/3064F-ZTAT and H8/3062F-ZTAT A-Mask Version
(FP-100A Package, Top View)
11
Page 37
1.3.2 Pin Functions
Table 1.3 summarizes the pin functions. The H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version 5 V operation models have a VCL pin, and require the connection of an external capacitor.
Table 1.3 Pin Functions
Pin No.
FP-100B
Type Symbol
TFP-100B FP-100A I/O Name and Function
Power V
CC
1*1, 35, 68
3*1, 37,70Input Power: For connection to the power supply.
Connect all V
pins to the system power
CC
supply.
Internal step-down pin
V
SS
V
CL
11, 22, 44, 57, 65, 92
2
1*
13, 24, 46, 59, 67, 94
2
3*
Input Ground: For connection to ground (0 V).
Connect all V
pins to the 0-V system power
SS
supply.
Output Connect an external capacitor between this
pin and GND (0 V). Do not connect to V
V
CL
0.1 µF
Clock XTAL 67 69 Input For connection to a crystal resonator.
For examples of crystal resonator and external clock input, see section 20, Clock Pulse Generator.
EXTAL 66 68 Input For connection to a crystal resonator or input
of an external clock signal. For examples of crystal resonator and external clock input, see section 20, Clock Pulse Generator.
CC
.
Operating mode control
12
φ 61 63 Output System clock: Supplies the system clock to
external devices.
MD2 to MD
0
75 to 73 77 to 75 Input Mode 2 to mode 0: For setting the operating
mode, as follows. Inputs at these pins must not be changed during operation.
MD
MD
2
MD
1
Operating Mode
0
0 0 0 Setting prohibited 0 0 1 Mode 1 0 1 0 Mode 2 0 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 1 1 0 Mode 6 1 1 1 Mode 7
Page 38
Type Symbol
Pin No.
FP-100B TFP-100B FP-100A I/O Name and Function
System control
RES 63 65 Input Reset input: When driven low, this pin resets
the chip. This pin must be driven low at power­up.
RESO 10 12 Output Reset output (On-chip mask ROM
versions): Outputs the reset signal generated
by the watchdog timer to external devices
FWE 10 12 Input Write enable signal (On-chip flash memory
versions): Flash memory programming control signal
STBY 62 64 Input Standby: When driven low, this pin forces
a transition to hardware standby mode
BREQ 59 61 Input Bus request: Used by an external bus master
to request the bus right
BACK 60 62 Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus master
Interrupts NMI 64 66 Input Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ
Address bus
to
5
IRQ
0
A23 to A097 to 100,
17, 16, 90 to 87
56 to 45, 43 to 36
Data bus D15 to D034 to 23,
21 to 18
Bus control
CS CS
7 0
to
2 to 5, 88 to 91
AS 69 71 Output Address strobe: Goes low to indicate valid
RD 70 72 Output Read: Goes low to indicate reading from the
HWR 71 73 Output High write: Goes low to indicate writing to the
LWR 72 74 Output Low write: Goes low to indicate writing to the
19, 18, 92 to 89
99, 100, 1, 2, 58 to 47, 45 to 38
36 to 25, 23 to 20
4 to 7, 90 to 93
Input Interrupt request 5 to 0: Maskable interrupt
request pins
Output Address bus: Outputs address signals
Input/
Data bus: Bidirectional data bus
output Output Chip select: Select signals for areas 7 to 0
address output on the address bus
external address space
external address space; indicates valid data on the upper data bus (D
to D8).
15
external address space; indicates valid data on the lower data bus (D
to D0).
7
WAIT 58 60 Input Wait: Requests insertion of wait states in bus
cycles during access to the external address space
13
Page 39
Type Symbol
Pin No.
FP-100B TFP-100B FP-100A I/O Name and Function
16-bit timer
TCLKD to TCLKA
TIOCA2 to TIOCA
TIOCB2 to TIOCB
8-bit timer TMO0,
TMO TMIO1,
TMIO
TCLKD to TCLKA
Program­mable
TP TP
to
15 0
timing pattern controller (TPC)
96 to 93 98 to95 Input Clock input D to A: External clock inputs
99, 97, 95 1, 99, 97 Input/
0
output
Input capture/output compare A2 to A0:
GRA2 to GRA0 output compare or input capture, or PWM output
100, 98,962, 100,98Input/
0
output
Input capture/output compare B2 to B0:
GRB2 to GRB0 output compare or input capture
2, 4 4, 6 Output Compare match output: Compare match
2
3, 5 5, 7 Input/
3
output
output pins
Input capture input/compare match output:
Input capture input or compare match output pins
96 to 93 98 to 95 Input Counter external clock input: These pins
input an external clock to the counters.
9 to 2, 100 to 93
11 to 4, 2, 1,
Output TPC output 15 to 0: Pulse output
100 to 95
Serial communi-
cation interface
(SCI)
A/D converter
D/A converter
Analog power supply
TxD1, TxD
0
RxD
,
1
RxD
0
SCK1, SCK
0
AN7 to AN
0
13, 12 15, 14 Output Transmit data (channels 0, 1): SCI data
output
15, 14 17, 16 Input Receive data (channels 0, 1): SCI data input
17, 16 19, 18 Input/
output
Serial clock (channels 0, 1): SCI clock input/output
85 to 78 87 to 80 Input Analog 7 to 0: Analog input pins
ADTRG 90 92 Input A/D conversion external trigger input:
External trigger input for starting A/D conversion
DA1, DA085, 84 87, 86 Output Analog output: Analog output from the
D/A converter
AV
CC
76 78 Input Power supply pin for the A/D and D/A
converters. Connect to the system power supply when not using the A/D and D/A converters.
14
Page 40
Type Symbol
Pin No.
FP-100B TFP-100B FP-100A I/O Name and Function
Analog
AV
SS
86 88 Input Ground pin for the A/D and D/A converters.
power supply
V
REF
77 79 Input Reference voltage input pin for the A/D and
I/O ports P17 to P1043 to 36 45 to 38 Input/
output
P27 to P2052 to 45 54 to 47 Input/
output
P37 to P3034 to 27 36 to 29 Input/
output
P47 to P4026 to 23,
21 to 18
28 to 25, 23 to 20
Input/ output
Connect to system ground (0 V).
D/A converters. Connect to the system power supply when not using the A/D and D/A converters.
Port 1: Eight input/output pins. The direction of each pin can be selected in the port 1 data direction register (P1DDR).
Port 2: Eight input/output pins. The direction of each pin can be selected in the port 2 data direction register (P2DDR).
Port 3: Eight input/output pins. The direction of each pin can be selected in the port 3 data direction register (P3DDR).
Port 4: Eight input/output pins. The direction of each pin can be selected in the port 4 data direction register (P4DDR).
P53 to P5056 to 53 58 to 55 Input/
output
Port 5: Four input/output pins. The direction of each pin can be selected in the port 5 data direction register (P5DDR).
P67 to P6061,
72 to 69, 60 to 58
63, 74 to 71, 62 to 60
Input/ output
Port 6: Eight input/output pins. The direction of each pin can be selected in the port 6 data
direction register (P6DDR). P77 to P7085 to 78 87 to 80 Input Port 7: Eight input pins P84 to P8091 to 87 93 to 89 Input/
output
Port 8: Five input/output pins. The direction of
each pin can be selected in the port 8 data
direction register (P8DDR). P95 to P9017 to 12 19 to 14 Input/
output
Port 9: Six input/output pins. The direction of
each pin can be selected in the port 9 data
direction register (P9DDR). PA7 to
PA
0
PB7 to PB
0
100 to 93 2, 1,
100 to
Input/ output
95
9 to 2 11 to 4 Input/
output
Port A: Eight input/output pins. The direction
of each pin can be selected in the port A data
direction register (PADDR).
Port B: Eight input/output pins. The direction
of each pin can be selected in the port B data
direction register (PBDDR).
Notes: 1. In the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version,
H8/3061 mask ROM version, and H8/3060 mask ROM version
2. In the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version (5 V operation models). This is a V
pin in 3 V operation models.
CC
15
Page 41
1.3.3 Pin Assignments in Each Mode
Table 1.4 lists the pin assignments in each mode.
Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A)
Pin No. Pin Name
FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
13v 24PB
TMO0/CS
35PB
TMIO1/CS
46PB
TMO2/CS
57PB
TMIO3/CS 68PB 79PB 810PB 911PB 10 12 RESO/
FWE* 11 13 V
CC (vCL
/TP8/
0
/TP9/
1
/TP10/
2
/TP11/
3
/TP
4
/TP
5
/TP
6
/TP
7
SS
)*4v
12
13
14
15
3
CC
PB0/TP8/ TMO0/CS
7
PB1/TP9/ TMIO1/CS
6
PB2/TP10/ TMO2/CS
5
PB3/TP11/ TMIO3/CS
4
PB4/TP PB5/TP PB6/TP PB7/TP RESO/
FWE* V
SS
3
12 14 P90/TxD0P90/TxD
v
CC
PB0/TP8/ TMO0/CS
7
PB1/TP9/ TMIO1/CS
6
PB2/TP10/ TMO2/CS
5
PB3/TP11/ TMIO3/CS
4
PB4/TP
12
13
14
15
PB5/TP PB6/TP PB7/TP
12
13
14
15
RESO/
3
FWE* V
SS
P90/TxD0P90/TxD
0
v
CC
PB0/TP8/ TMO0/CS
7
PB1/TP9/ TMIO1/CS
6
PB2/TP10/ TMO2/CS
5
PB3/TP11/ TMIO3/CS
4
PB4/TP PB5/TP PB6/TP PB7/TP RESO/
FWE* V
SS
v
CC
PB0/TP8/ TMO0/CS
7
PB1/TP9/ TMIO1/CS
6
PB2/TP10/ TMO2/CS
5
PB3/TP11/ TMIO3/CS
4
PB4/TP
12
PB5/TP
13
PB6/TP
14
PB7/TP
15
RESO/
3
0
3
FWE* V
SS
P90/TxD0P90/TxD0P90/TxD
7
5
12
13
14
15
v
CC
PB0/TP8/ TMO
PB1/TP9/ TMIO
6
PB2/TP10/ TMO
PB3/TP11/ TMIO
4
PB4/TP PB5/TP PB6/TP PB7/TP RESO/
FWE* V
SS
v
CC
PB0/TP8/
0
TMO
0
PB1/TP9/
1
TMIO
1
PB2/TP10/
2
TMO
2
PB3/TP11/
12
13
14
15
TMIO
3
PB4/TP PB5/TP PB6/TP PB7/TP
12
13
14
15
3
RESO/
3
FWE* V
SS
3
0
13 15 P91/TxD1P91/TxD
P91/TxD1P91/TxD
1
P91/TxD1P91/TxD1P91/TxD
1
14 16 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD 15 17 P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD 16 18 P94 /SCK0/
IRQ
4
17 19 P95 /SCK1/
IRQ
5
18 20 P40/D0* 19 21 P41/D1* 20 22 P42/D2* 21 23 P43/D3* 22 24 V
SS
23 25 P44/D4* 24 26 P45/D5*
1
1
1
1
1
1
P94 /SCK0/
IRQ
4
P95 /SCK1/
IRQ
5
P40/D0* P41/D1* P42/D2* P43/D3* V P44/D4* P45/D5*
2
2
2
2
SS
2
2
P94 /SCK0/
IRQ
4
P95 /SCK1/
IRQ
5
P40/D0* P41/D1* P42/D2* P43/D3* V P44/D4* P45/D5*
1
1
1
1
SS
1
1
P94 /SCK0/
IRQ
4
P95 /SCK1/
IRQ
5
P40/D0* P41/D1* P42/D2* P43/D3* V P44/D4* P45/D5*
2
2
2
2
SS
2
2
P94 /SCK0/
IRQ
4
P95 /SCK1/
IRQ
5
P40/D0* P41/D1* P42/D2* P43/D3* V P44/D4* P45/D5*
1
1
1
1
SS
1
1
P94 /SCK0/
IRQ
4
P95 /SCK1/
IRQ
5
P4
0
P4
1
P4
2
P4
3
V
SS
P4
4
P4
5
P94 /SCK0/
IRQ
4
P95 /SCK1/
IRQ
5
P4
0
P4
1
P4
2
P4
3
V
SS
P4
4
P4
5
1
0
1
16
Page 42
Pin No. Pin Name
FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
25 27 P46/D6* 26 28 P47/D7*
1
1
P46/D6* P47/D7*
2
2
P46/D6* P47/D7*
1
1
P46/D6* P47/D7*
2
2
P46/D6* P47/D7*
1
P4
6
1
P4
7
P4 P4
6
7
27 29 D 28 30 D 29 31 D 30 32 D 31 33 D 32 34 D 33 35 D 34 36 D 35 37 V 36 38 A 37 39 A 38 40 A 39 41 A 40 42 A 41 43 A
8
9
10
11
12
13
14
15
CC
0
1
2
3
4
5
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
V
CC
P10/A P11/A P12/A P13/A P14/A P15/A
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P3
6
P3
7
V
CC
0
1
2
3
4
5
P1 P1 P1 P1 P1 P1
0
1
2
3
4
5
P3 P3 P3 P3 P3 P3 P3 P3 V P1 P1 P1 P1 P1 P1
0
1
2
3
4
5
6
7
CC
0
1
2
3
4
5
42 44 A 43 45 A 44 46 V 45 47 A 46 48 A 47 49 A 48 50 A 49 51 A 50 52 A 51 53 A 52 54 A 53 55 A 54 56 A 55 57 A 56 58 A
6
7
SS
8
9
10
11
12
13
14
15
16
17
18
19
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
P16/A P17/A V
SS
P20/A P21/A P22/A P23/A P24/A P25/A P26/A P27/A P50/A P51/A P52/A P53/A
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P1 P1 V P2 P2 P2 P2 P2 P2 P2 P2 P5 P5 P5 P5
6
7
SS
0
1
2
3
4
5
6
7
0
1
2
3
P1 P1 V P2 P2 P2 P2 P2 P2 P2 P2 P5 P5 P5 P5
6
7
SS
0
1
2
3
4
5
6
7
0
1
2
3
57 59 V
SS
58 60 P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT P6
V
SS
V
SS
V
SS
V
SS
V
SS
0
V P6
SS
0
17
Page 43
Pin No. Pin Name
FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
59 61 P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ P6 60 62 P62/BACK P62/BACK P62/BACK P62/BACK P62/BACK P6
1
2
P6 P6
1
2
61 63 φφφφP67/φ P67/φ P67/φ 62 64 STBY STBY STBY STBY STBY STBY STBY 63 65 RES RES RES RES RES RES RES 64 66 NMI NMI NMI NMI NMI NMI NMI 65 67 V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
66 68 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 67 69 XTAL XTAL XTAL XTAL XTAL XTAL XTAL 68 70 V
CC
69 71 AS AS AS AS AS P6 70 72 RD RD RD RD RD P6 71 73 HWR HWR HWR HWR HWR P6 72 74 LWR LWR LWR LWR LWR P6 73 75 MD
0
V
CC
MD
V
CC
0
MD
0
V
CC
MD
V
CC
0
MD
0
V
CC
MD
V
CC
3
4
5
6
0
P6 P6 P6 P6 MD
3
4
5
6
0
74 76 MD 75 77 MD 76 78 AV 77 79 V
1
2
CC
REF
78 80 P70/AN 79 81 P71/AN 80 82 P72/AN 81 83 P73/AN 82 84 P74/AN 83 85 P75/AN
0
1
2
3
4
5
MD
1
MD
2
AV
CC
V
REF
P70/AN P71/AN P72/AN P73/AN P74/AN P75/AN
0
1
2
3
4
5
MD
1
MD
2
AV
CC
V
REF
P70/AN P71/AN P72/AN P73/AN P74/AN P75/AN
0
1
2
3
4
5
MD
1
MD
2
AV
CC
V
REF
P70/AN P71/AN P72/AN P73/AN P74/AN P75/AN
0
1
2
3
4
5
MD
1
MD
2
AV
CC
V
REF
P70/AN P71/AN P72/AN P73/AN P74/AN P75/AN
0
1
2
3
4
5
MD
1
MD
2
AV
CC
V
REF
P70/AN P71/AN P72/AN P73/AN P74/AN P75/AN
0
1
2
3
4
5
MD
1
MD
2
AV
CC
V
REF
P70/AN P71/AN P72/AN P73/AN P74/AN P75/AN
0
1
2
3
4
5
84 86 P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA 85 87 P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA 86 88 AV
SS
87 89 P80/IRQ0P80/IRQ 88 90 P81/IRQ1/
CS
3
AV
SS
P81/IRQ1/
CS
3
AV
SS
P80/IRQ0P80/IRQ
0
P81/IRQ1/
CS
3
AV
SS
P81/IRQ1/
CS
3
AV
SS
P80/IRQ0P80/IRQ0P80/IRQ
0
P81/IRQ1/
CS
3
AV
SS
P81/IRQ1P81/IRQ
AV
SS
0
1
0
1
89 91 P82/IRQ2/
CS
2
18
P82/IRQ2/ CS
2
P82/IRQ2/
CS
2
P82/IRQ2/
CS
2
P82/IRQ2/
CS
2
P82/IRQ2P82/IRQ
2
Page 44
Pin No. Pin Name
FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
90 92 P83/IRQ3/
CS
/
1
ADTRG
91 93 P84/CS 92 94 V
0
SS
93 95 PA0/TP0/
TCLKA
94 96 PA1/TP1/
TCLKB
95 97 PA2/TP2/
TIOCA0/ TCLKC
96 98 PA3/TP3/
TIOCB0/ TCLKD
97 99 PA4/TP4/
TIOCA
1
98 100 PA5/TP5/
TIOCB
1
P83/IRQ3/
CS
/
1
ADTRG
P84/CS V
0
SS
PA0/TP0/ TCLKA
PA1/TP1/ TCLKB
PA2/TP2/ TIOCA0/ TCLKC
PA3/TP3/ TIOCB0/ TCLKD
PA4/TP4/ TIOCA
1
PA5/TP5/ TIOCB
1
P83/IRQ3/
CS
/
1
ADTRG
P84/CS V
0
SS
PA0/TP0/ TCLKA
PA1/TP
1
/TCLKB PA2/TP2/
TIOCA0/ TCLKC
PA3/TP3/ TIOCB0/ TCLKD
PA4/TP4/ TIOCA1/A
PA5/TP5/ TIOCB1/A
P83/IRQ3/
CS ADTRG
P84/CS V
SS
PA0/TP0/ TCLKA
PA1/TP1/ TCLKB
PA2/TP2/ TIOCA0/ TCLKC
PA3/TP3/ TIOCB0/ TCLKD
PA4/TP4/ TIOCA1/A
23
PA5/TP5/ TIOCB1/A
22
P83/IRQ3/
/
1
CS
/
1
P83/IRQ3/
ADTRG
P83/IRQ3/ ADTRG
ADTRG
0
23
22
P84/CS V
SS
PA0/TP0/ TCLKA
PA1/TP1/ TCLKB
PA2/TP2/ TIOCA0/ TCLKC
PA3/TP3/ TIOCB0/ TCLKD
PA4/TP4/ TIOCA1/A
PA5/TP5/ TIOCB1/A
0
P8 V
SS
PA0/TP0/ TCLKA
PA1/TP1/ TCLKB
PA2/TP2/ TIOCA0/ TCLKC
PA3/TP3/ TIOCB0/ TCLKD
PA4/TP4/ TIOCA
23
PA5/TP5/ TIOCB
22
4
P8 V
4
SS
PA0/TP0/ TCLKA
PA1/TP1/ TCLKB
PA2/TP2/ TIOCA0/ TCLKC
PA3/TP3/ TIOCB0/ TCLKD
PA4/TP4/ TIOCA
1
1
PA5/TP5/ TIOCB
1
1
99 1 PA6/TP6/
TIOCA
100 2 PA7/TP7/
TIOCB
2
2
PA6/TP6/ TIOCA
2
PA7/TP7/ TIOCB
2
PA6/TP6/ TIOCA2/A
A
20
PA6/TP6/ TIOCA2/A
21
A
20
PA6/TP6/ TIOCA2/A
21
PA7/TP7/ TIOCB2/A
PA6/TP6/ TIOCA
21
PA7/TP7/ TIOCB
20
2
2
PA6/TP6/ TIOCA
2
PA7/TP7/ TIOCB
2
Notes: 1. In modes 1, 3, and 5 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after
a reset, but they can be changed by software.
2. In modes 2 and 4 the D
to D7 functions of pins P40/D0 to P47/D7 are selected after a
0
reset, but they can be changed by software.
3. Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash memory versions. Functions as the programming control signal in modes 5 and 7.
4. Functions as V
in the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062
CC
mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version. In the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version, this pin functions as V
CL
in 5 V operation models, and as VCC in 3 V operation models.
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1.4 Notes on H8/3062F-ZTAT R-Mask Version
There are two models with on-chip flash memory in the H8/3062 Series: the H8/3062F-ZTAT (HD64F3062) and the H8/3062F-ZTAT R-mask version (HD64F3062R). Points to be noted when using the H8/3062F-ZTAT R-mask version are given below.
1.4.1 Pin Arrangement
The H8/3062F-ZTAT R-mask version has the same pin arrangement as the H8/3062F-ZTAT and the H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version. Except for the VCL pin, it also has the same pin arrangement as the H8/3062F-ZTAT A-mask version and H8/3064F-ZTAT 5 V operation models.
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1.4.2 Product Type Names and Markings
Table 1.5 shows the product type names and differences in sample markings for the H8/3062F­ZTAT and the H8/3062F-ZTAT R-mask version.
Table 1.5 Differences in H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version
Markings
H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version
TFP-100 Product type name HD64F3062TE HD64F3062RTE
Sample markings
FP-100B Product type name HD64F3062F HD64F3062RF
Sample markings
FP-100A Product type name HD64F3062FP HD64F3062RFP
Sample markings
H8/3062
HD 64F3062TE20
JAPAN
H8/3062
HD 64F3062F20
JAPAN
H8/3062
HD 64F3062FP20
H8/3062 R
HD 64F3062TE20
JAPAN
“R” is printed above the type name
H8/3062 R
HD 64F3062F20
JAPAN
“R” is printed above the type name
H8/3062 R
HD 64F3062FP20
1.4.3 Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version
Table 1.6 shows the differences between the H8/3062F-ZTAT, the H8/3062F-ZTAT R-mask version, and the on-chip mask ROM versions.
JAPAN
JAPAN
“R” is printed above the type name
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Table 1.6 Differences between H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, and
On-Chip Mask ROM Versions
On-Chip Flash On-Chip Flash Memory Version
Item
HD64F3062
ROM 128 kbytes flash
memory
Address output functions
ADRCR register (H'FEE01E)
Compatible with previous H8/300H Series
— Corresponding
address consists of reserved bits
Memory Version HD64F3062R HD6433062 HD6433061 HD6433060
128 kbytes flash memory
Choice of address update mode 1 (compatible with previous H8/300H Series) or address update mode 2
See the section on the bus controller for details.
7
—
—
6
5
—
See the section on the bus controller for the bit function.
On-Chip Mask ROM Versions
128 kbytes mask ROM
4
—
96 kbytes mask ROM
3
—
2
—
64 kbytes mask ROM
1
—
The address output functions and ADRCR register specification of the H8/3064F-ZTAT and H8/3062F-ZTAT A-mask version are the same as for the H8/3062F-ZTAT R-mask version.
0
ADRCTL
1.5 Notes on H8/3064F-ZTAT and H8/3062F-ZTAT A-Mask Version
The H8/3062 Series includes one model with 128-kbyte on-chip flash memory, the H8/3062F­ZTAT A-mask version (HD64F3062A) developed on the basis of the H8/3062F-ZTAT R-mask version, and one model with 256-kbyte large-capacity on-chip flash memory, the H8/3064F-ZTAT (HD64F3064).
The H8/3062F-ZTAT A-mask version and H8/3064F-ZTAT have the following features:
1. Low power consumption
2. Low-voltage, high-speed operation
3. Functional compatibility with the H8/3062F-ZTAT R-mask version
4. Pin arrangement compatibility (except for the VCL pin in 5 V operation models)
Points to be noted when using the H8/3062F-ZTAT A-mask version or the H8/3064F-ZTAT are given below.
1.5.1 Pin Arrangement
Except for the VCL pin, the H8/3062F-ZTAT and the H8/3062F-ZTAT R-mask version have the same pin arrangement as the H8/3064F-ZTAT and H8/3062F-ZTAT A-mask version 5 V operation models. 3 V operation models have no VCL pin, and so have an identical pin arrangement.
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1.5.2 Product Type Names and Markings
Table 1.7 shows the product type names and differences in sample markings for the H8/3062F­ZTAT R-mask version and the H8/3062F-ZTAT A-mask version and H8/3064F-ZTAT.
Table 1.7 Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT A-Mask
Version, and H8/3064F-ZTAT Markings
TFP-100 Product type
name Sample
markings
FP-100B Product type
name Sample
markings
H8/3062F-ZTAT R-Mask Version
HD64F3062RTE HD64F3062ATE HD64F3064TE
H8/3062 R
HD 64F3062TE20
JAPAN
HD64F3062RF HD64F3062AF HD64F3064F
H8/3062 R
HD 64F3062F20
JAPAN
H8/3062F-ZTAT A-Mask Version H8/3064F-ZTAT
H8/3062 A
HD 64F3062TE20
JAPAN
“A” is printed above the type name
H8/3062 A
HD 64F3062F20
JAPAN
H8/3064
HD 64F3064TE20
JAPAN
H8/3064
HD 64F3064F20
JAPAN
FP-100A Product type
name Sample
markings
“A” is printed above the type name
HD64F3062RFP HD64F3062AFP HD64F3064FP
H8/3062 R
HD 64F3062FP20
JAPAN
“A” is printed above the type name
H8/3062 A
HD 64F3062FP20
JAPAN
H8/3064
HD 64F3064FP20
JAPAN
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1.5.3 VCL Pin
The H8/3064F-ZTAT and H8/3062F-ZTAT A-mask version 5 V operation models have a V (internal step-down) pin, to which a 0.1 µF internal voltage stabilization capacitor must be connected.
The method of connecting the external capacitor is shown in figure 1.6.
Do not connect the V
power supply to the V
CC
pin. (Connect the VCC power supply to other V
CL
pins as usual.) Note that the VCL output pin occupies the same location as a VCC pin in the H8/3062F-ZTAT R-mask version and on-chip mask ROM models (H8/3062, H8/3061, and H8/3060).
VCC power
supply External capacitor
0.1 µF
V
CL
H8/3062F-ZTAT A-mask version or H8/3064F-ZTAT (5 V operation model)
V
CC
H8/3062F-ZTAT R-mask version H8/3062 mask ROM version H8/3061 mask ROM version H8/3060 mask ROM version
CL
CC
Do not connect the V the V supply to other V
pin. (Connect the VCC power
CL
CC
power supply to
CC
pins as usual.)
Place the capacitor close to the pin.
These versions have a V pin in the same pin position as a V
power supply
CC
CC
pin in the H8/3062F-ZTAT A-mask version and the H8/3064F-ZTAT.
Figure 1.6 H8/3062F-ZTAT A-Mask Version and H8/3064F-ZTAT
The 3 V operation models of the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version do not have a VCL pin. The 3 V operation models have a VCC power supply pin at the location of the VCL pin in the 5 V operation models. Therefore, 3 V operation models do not require connection of an external capacitor, and this pin should be connected to the power supply in the same way as other VCC pins.
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External capacitor
VCC power supply
V
CL
V
CC
0.1 µF 5 V operation model
3 V operation model
Figure 1.7 Difference between 5 V and 3 V Operation Models
1.5.4 Note on Changeover to Mask ROM Version
Care is required when changing from the H8/3062F-ZTAT A-mask version with on-chip flash memory to a model with on-chip mask ROM (H8/3062, H8/3061, or H8/3060).
An external capacitor must be connected to the VCL pin of the H8/3062F-ZTAT A-mask version (5 V model). This VCL pin occupies the same location as a VCC pin in the on-chip mask ROM versions. Changeover to a mask ROM version must therefore be taken into account when undertaking pattern design, etc., in the board design stage.
H8/3062 Series chip
V
pin
CC
V
pin
CL
V
CC
supply
power
← Land pattern for mask ROM version
(0 Ω resistance mounted)
← Land pattern for H8/3062F-ZTAT A-mask version
(0.1 µF capacitor mounted)
Figure 1.8 Example of Board Pattern Providing for External Capacitor
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1.6 Setting Oscillation Settling Wait Time
When software standby mode is used, after exiting software standby mode a wait period must be provided to allow the clock to stabilize. Select the length of time for which the CPU and peripheral functions are to wait by setting bits STS2 to STS0 in the system control register (SYSCR) and bits DIV1 and DIV0 in the division ratio control register (DIVCR) according to the operating frequency of the chip.
For the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version, ensure that the oscillation settling wait time is at least 0.1 ms when operating on an external clock.
For setting details, see section 21.4.3, Setting Oscillation Settling Wait Time after Exiting Software Standby Mode.
1.7 Caution on Crystal Resonator Connection
The H8/3064F-ZTAT and H8/3062F-ZTAT A-mask version support an operating frequency of up to 25 MHz. If a crystal resonator with a frequency higher than 20 MHz is connected, attention must be paid to circuit constants such as external load capacitance values. For details see section
20.2.1, Connecting a Crystal Resonator.
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Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1 Features
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• 64 basic instructions8/16/32-bit arithmetic and logic instructionsMultiply and divide instructionsPowerful bit-manipulation instructions
• Eight addressing modesRegister direct [Rn]Register indirect [@ERn]Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]Absolute address [@aa:8, @aa:16, or @aa:24]Immediate [#xx:8, #xx:16, or #xx:32]Program-counter relative [@(d:8, PC) or @(d:16, PC)]Memory indirect [@@aa:8]
• 16-Mbyte linear address space
• High-speed operationAll frequently-used instructions execute in two to four statesMaximum clock frequency: 20 MHz (H8/3062F-ZTAT, H8/3062F-ZTAT R-
8/16/32-bit register-register add/subtract: 100 ns@20 MHz (80 ns@25 MHz)8 × 8-bit register-register multiply: 700 ns@20 MHz (560 ns@25 MHz)
Mask version, H8/3062, H8/3061, H8/3060)
25 MHz (H8/3064F-ZTAT, H8/3062F-ZTAT A­Mask version)
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16 ÷ 8-bit register-register divide: 700 ns@20 MHz (560 ns@25 MHz)16 × 16-bit register-register multiply: 1.1 µs@20 MHz (0.88 µs@25 MHz)32 ÷ 16-bit register-register divide: 1.1 µs@20 MHz (0.88 µs@25 MHz)
• Two CPU operating modesNormal modeAdvanced mode
• Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
• More general registers Eight 16-bit registers have been added.
• Expanded address spaceAdvanced mode supports a maximum 16-Mbyte address space.Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
• Enhanced instructionsData transfer, arithmetic, and logic instructions can operate on 32-bit data.Signed multiply/divide instructions and other instructions have been added.
2.2 CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes.
Normal mode
Maximum 64 kbytes, program and data areas combined
CPU operating modes
Figure 2.1 CPU Operating Modes
28
Advanced mode
Maximum 16 Mbytes, program and data areas combined
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2.3 Address Space
Figure 2.2 shows a simple memory map for the H8/3062 Series. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are ignored.
H'0000
H'FFFF
H'00000
H'FFFFF
a. 1-Mbyte mode b. 16-Mbyte mode
Figure 2.2 Memory Map
H'000000
H'FFFFFF
Advanced modeNormal mode
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2.4 Register Configuration
2.4.1 Overview
The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers.
General Registers (ERn)
0707015
ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7
Control Registers (CR)
PC
Legend: SP:
PC: CCR: I: UI: H: U: N: Z: V: C:
Stack pointer Program counter Condition code register Interrupt mask bit User bit or interrupt mask bit Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag
E0 E1 E2 E3 E4 E5 E6 E7
23 0
(SP)
R0H R1H R2H R3H R4H R5H R6H R7H
CCR
7
IUIHUNZVC
R0L R1L R2L R3L R4L R5L R6L R7L
6543210
30
Figure 2.3 CPU Registers
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2.4.2 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers.
Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected independently.
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers E registers
(extended registers)
E0 to E7
ER registers
ER0 to ER7
R registers
R0 to R7
RH registers
R0H to R7H
RL registers
R0L to R7L
Figure 2.4 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack.
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Free area
SP (ER7)
Stack area
Figure 2.5 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see section 5, Interrupt Controller.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign bit.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
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Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and UI bits, see section 5, Interrupt Controller.
2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must therefore be initialized by an MOV.L instruction executed immediately after a reset.
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2.5 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figures 2.6 and 2.7 show the data formats in general registers.
General
Data Type Data Format
1-bit data
1-bit data
Register
RnH
RnL
70 7
6543210
Don’t care
Don’t care
70 76543210
4-bit BCD data
4-bit BCD data
Byte data
Byte data
Legend: RnH: General register RH
RnL: General register RL
Figure 2.6 General Register Data Formats
RnH
RnL
RnH
RnL
70
70
MSB LSB
43
Lower digitUpper digit
Don’t care
Don’t care
Don’t care
7
70
MSB LSB
43
Don’t care
0
Lower digitUpper digit
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Word data
General RegisterData Type Data Format
15 0
Rn
MSB LSB
15 0
Word data
Longword data
Legend: ERn:
En: Rn: MSB: LSB:
General register General register E General register R Most significant bit Least significant bit
En
ERn
MSB LSB
31 16
MSB
15 0
LSB
Figure 2.7 General Register Data Formats
2.5.2 Memory Data Formats
Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
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AddressData T ype Data Format
70
1-bit data
Byte data
Word data
Longword data
76543210Address L
Address L
Address 2M
MSB LSB
MSB
Address 2M + 1
Address 2N
MSB
Address 2N + 1 Address 2N + 2 Address 2N + 3
Figure 2.8 Memory Data Formats
LSB
LSB
When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
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2.6 Instruction Set
2.6.1 Instruction Set Overview
The H8/300H CPU has 64 types of instructions, which are classified in table 2.1.
Table 2.1 Instruction Classification
Function Instruction Types
Data transfer MOV, PUSH*
1
, POP*1, MOVTPE*2, MOVFPE*
2
5
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,
MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU Logic operations AND, OR, XOR, NOT 4 Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR,
BIXOR, BLD, BILD, BST, BIST Branch Bcc*3, JMP, BSR, JSR, RTS 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9 Block data transfer EEPMOV 1
Total 64 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP.
2.
Not available in the H8/3062 Series.
3. Bcc is a generic branching instruction.
18
14
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2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU.
Table 2.2 Instructions and Addressing Modes
Addressing Modes
@ (d:16,
Function Instruction #xx Rn @ERn
Data MOV BWL BWL BWL BWL BWL BWL B BWL BWL — — — — transfer
Arithmetic ADD, CMP BWL BWL — — — — ——————— operations
POP, PUSH — — — — — — ——————WL MOVFPE, — — — — — — ———————
MOVTPE
SUB WLBWL— ——— ——————— ADDX, SUBX B B — — — — ——————— ADDS, SUBS — L — — — — ——————— INC, DEC — BWL — — — — ——————— DAA, DAS — B — — — — ——————— MULXU, — BW — — — — ———————
MULXS, DIVXU, DIVXS
NEG —BWL———— ——————— EXTU, EXTS — WL — — — — ———————
ERn)
@ (d:24, ERn)
@ERn+/ @–ERn@aa:8@aa:16@aa:24
@ (d:8, PC)
@ (d:16, PC)@@aa:8 —
Logic operations
Shift instructions — BWL — — — — ——————— Bit manipulation — B B — — — B —————— Branch Bcc, BSR — — — — — — ———————
System TRAPA — — — — — — —————— control
Block data transfer — — — — — — ——————BW
AND, OR, XOR — BWL — — — — ———————
NOT —BWL———— ———————
JMP, JSR — — ——— ——— —— RTS —————— —— —— —
RTE —————— —————— SLEEP — — — — — — —————— LDC BB WWWW —WW——— STC —B WWWW —WW———— ANDC, ORC,
XORC NOP —————— ——————
B————— ———————
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2.6.3 Tables of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next.
Operation Notation
Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register or address register)* (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction
× Multiplication ÷ Division ∧ AND logical ∨ OR logical ⊕ Exclusive OR logical → Move
¬ NOT (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
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Table 2.3 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in this LSI.
MOVTPE B Rs → (EAs)
Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Size refers to the operand size.
B: Byte W: Word L: Longword
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Table 2.4 Arithmetic Operation Instructions
Instruction Size* Function
ADD,SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.)
ADDX, SUBX
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register.
INC, DEC
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.)
ADDS, SUBS
DAA, DAS
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
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Instruction Size* Function
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register or with immediate data, and sets CCR according to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a general register.
EXTS W/L Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit.
EXTU W/L Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros.
Note: * Size refers to the operand size.
B: Byte W: Word L: Longword
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Table 2.5 Logic Operation Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and another general register or immediate data.
NOT B/W/L ¬ Rd → Rd
Takes the one’s complement (logical complement) of general register contents.
Note: * Size refers to the operand size.
B: Byte W: Word L: Longword
Table 2.6 Shift Instructions
Instruction Size* Function
SHAL, SHAR
SHLL, SHLR
ROTL, ROTR
ROTXL, ROTXR
Note: * Size refers to the operand size.
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents, including the carry bit.
B: Byte W: Word L: Longword
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Table 2.7 Bit Manipulation Instructions
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Instruction Size* Function
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BILD B ¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data.
BIST B C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
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Table 2.8 Branching Instructions
Instruction Size Function
Bcc — Branches to a specified address if address specified condition is met. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always BRN (BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 Bcc (BHS) Carry clear (high or same) C = 0 BCS (BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1
JMP — Branches unconditionally to a specified address BSR — Branches to a subroutine at a specified address JSR — Branches to a subroutine at a specified address RTS — Returns from a subroutine
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Table 2.9 System Control Instructions
Instruction Size* Function
TRAPA — Starts trap-instruction exception handling RTE — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state LDC B/W (EAs) → CCR
Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data.
NOP — PC + 2 → PC
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte W: Word
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Table 2.10 Block Transfer Instruction
Instruction Size Function
EEPMOV.B — if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L until R4L = 0 else next;
EEPMOV.W — if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4 until R4 = 0 else next;
Block transfer instruction. This instruction transfers the number of data bytes specified by R4L or R4, starting from the address indicated by ER5, to the location starting at the address indicated by ER6. At the end of the transfer, the next instruction is executed.
2.6.4 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.9 shows examples of instruction formats.
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Operation field only
op
Operation field and register fields
op rn rm
Operation field, register fields, and effective address extension
op rn rm
EA (disp)
Operation field, effective address extension, and condition field
op cc EA (disp)
Figure 2.9 Instruction Formats
2.6.5 Notes on Use of Bit Manipulation Instructions
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
BRA d:8
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports.
Step Description
1 Read Read one data byte at the specified address 2 Modify Modify one bit in the data byte 3 Write Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under the following conditions.
P47, P46: Input pins P45 – P40: Output pins
The intended purpose of this BCLR instruction is to switch P40 from output to input.
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Before Execution of BCLR Instruction
P4
7
P4
6
P4
5
P4
4
P4
3
P4
2
P4
1
P4
0
Input/output Input Input Output Output Output Output Output Output DDR 00111111
Execution of BCLR Instruction
BCLR #0, P4DDR ; Execute BCLR instruction on DDR
After Execution of BCLR Instruction
P4
7
Input/output Output Output Output Output Output Output Output Input DDR 11111110
P4
6
P4
5
P4
4
P4
3
P4
2
P4
1
P4
0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR are set to 1, making P47 and P46 output pins.
The BCLR instruction can be used to clear flags in the on-chip registers to 0. In the case of the IRQ status register (ISR), for example, a flag must be read as a condition for clearing it, but when using the BCLR instruction, if it is known that a flag has been set to 1 in an interrupt-handling routine, for instance, it is not necessary to read the flag ahead of time.
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2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program­counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) 4 Register indirect with post-increment
Register indirect with pre-decrement 5 Absolute address @aa:8/@aa:16/@aa:24 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8, PC)/@(d:16, PC) 8 Memory indirect @@aa:8
@ERn+ @–ERn
1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand.
3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended when added.
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4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even.
• Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the resulting register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible address ranges.
Table 2.12 Absolute Address Access Ranges
Absolute Address 1-Mbyte Modes 16-Mbyte Modes
8 bits (@aa:8) H'FFF00 to H'FFFFF
(1048320 to 1048575)
16 bits (@aa:16) H'00000 to H'07FFF,
H'F8000 to H'FFFFF (0 to 32767, 1015808 to 1048575)
24 bits (@aa:24) H'00000 to H'FFFFF
(0 to 1048575)
H'FFFF00 to H'FFFFFF (16776960 to 16777215)
H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32767, 16744448 to 16777215)
H'000000 to H'FFFFFF (0 to 16777215)
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data specifying a vector address.
7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-
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extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area. For further details see section 5, Interrupt Controller.
Specified by @aa:8
Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address. See section 2.5.2, Memory Data Formats.
2.7.2 Effective Address Calculation
Table 2.13 explains how an effective address is calculated in each addressing mode. In the 1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address.
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Table 2.13 Effective Address Calculation
23 0
Operand is general
register contents
General register contents
31 0
23 0
General register contents
Sign extension disp
31 0
23 0
1, 2, or 4
General register contents
31 0
23 0
1, 2, or 4
General register contents
31 0
1 for a byte operand,
2 for a word operand,
4 for a longword operand
op rm rn
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Register direct (Rn)
1
Register indirect (@ERn)
2
op r
54
op r
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
3
Register indirect with post-increment
or pre-decrement
Register indirect with post-increment
@ERn+
4
op r
Register indirect with pre-decrement
@–ERn
op r
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23 087
H'FFFF
Sign
23 016 15
extension
23 0
23 0
Operand is immediate data
0
disp
PC contents
Sign
23 0
extension
abs
op
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Absolute address
@aa:8
5
op abs
@aa:16
op
@aa:24
abs
op IMM
Program-counter relative
Immediate
#xx:8, #xx:16, or #xx:32
6
@(d:8, PC) or @(d:16, PC)
7
op disp
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16 15
H'00Memory contents
23 0
23 0
0
abs
23 087
H'0000
abs
15 0
H'0000
23 087
Memory contents
31
abs
op
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Memory indirect @@aa:8
Normal mode
8
8
56
abs
op
Advanced mode
Register field
Operation field
Displacement
Legend:
r, rm, rn:
op:
disp:
Immediate data
Absolute address
IMM:
abs:
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2.8 Processing States
2.8.1 Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states. Figure 2.13 indicates the state transitions.
Processing states Program execution state
The CPU executes program instructions in sequence
Exception-handling state
A transient state in which the CPU executes a hardware sequence (saving PC and CCR, fetching a vector, etc.) in response to a reset, interrupt, or other exception
Bus-released state
The external bus has been released in response to a bus request signal from a bus master other than the CPU
Reset state
The CPU and all on-chip supporting modules are initialized and halted
Power-down state
The CPU is halted to conserve power
Figure 2.11 Processing States
2.8.2 Program Execution State
Sleep mode
Software standby mode
Hardware standby mode
In this state the CPU executes program instructions in normal sequence.
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2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Types and Priority
Priority Type of Exception Detection Timing Start of Exception Handling
High Reset Synchronized with clock Exception handling starts immediately
when RES changes from low to high
Interrupt End of instruction
execution or end of exception handling*
Trap instruction When TRAPA instruction
Low
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling.
is executed
When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence
Exception handling starts when a trap (TRAPA) instruction is executed
Figure 2.12 classifies the exception sources. For further details about exception sources, vector numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt Controller.
Reset
External interrupts
Exception sources
Interrupt
Internal interrupts (from on-chip supporting modules)
Trap instruction
Figure 2.12 Classification of Exception Sources
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Bus request
End of bus release
End of bus release
Bus-released state
End of exception handling
Exception-handling state
RES = "High"
Reset state
*1
Program execution state
Bus request
Exception handling source
Interrupt source
NMI, IRQ , IRQ , or IRQ interrupt
STBY="High", RES ="Low"
01
2
SLEEP instruction with SSBY = 0
Sleep mode
SLEEP instruction with SSBY = 1
Software standby mode
Hardware standby mode
Power-down state
*2
Notes: 1.2.From any state except hardware standby mode, a transition to the reset state occurs
whenever goes low. From any state, a transition to hardware standby mode occurs when goes low.
RES
STBY
Figure 2.13 State Transitions
2.8.4 Exception Handling Operation
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during the reset exception-handling sequence and immediately after it ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the program counter and condition code register on the stack. Next, if the UE bit in the system control register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address.
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Figure 2.14 shows the stack after the exception-handling sequence.
SP–4 SP–3 SP–2 SP–1
SP (ER7)
Legend: CCR:
SP: Notes: 1.2.PC is the address of the first instruction executed after the return from the
Condition code register Stack pointer
exception-handling routine.
Registers must be saved and restored by word access or longword access,
starting at an even address.
Stack area
Before exception handling starts
SP (ER7)
SP+1 SP+2 SP+3 SP+4
Pushed on stack
CCR
PC
After exception handling ends
Even address
Figure 2.14 Stack Structure after Exception Handling
2.8.5 Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU is an external bus master. While the bus is released, the CPU halts except for internal operations. Interrupt requests are not accepted. For details see section 6.6, Bus Arbiter.
2.8.6 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 11, Watchdog Timer.
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2.8.7 Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop immediately after execution of the SLEEP instruction, but the contents of CPU registers are retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained.
For further information see section 21, Power-Down State.
2.9 Basic Operational Timing
2.9.1 Overview
The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of two or three states. The CPU uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. Access to the external address space can be controlled by the bus controller.
2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin states. All H8/3062 Series models except the H8/3062F-ZTAT have a function for changing the method of outputting addresses from the address pins. For details see section 6.3.5, Address Output Method.
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Bus cycle
φ
Internal address bus
Internal read signal Internal data bus
(read access)
Internal write signal Internal data bus
(write access)
Figure 2.15 On-Chip Memory Access Cycle
T state
1
Address
Read data
Write data
T state
2
T
1
T
2
φ
Address bus
RD HWR LWR
, , ,AS
Address
High
High impedance
D to D
15 0
Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1)
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting module access timing. Figure 2.18 indicates the pin states.
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Bus cycle
Read access
Write access
T state
1
T state
2
φ
Address bus
Address
Internal read signal
Internal data bus
Read data
Internal write signal
Internal data bus
Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
T state
3
T
1
T
2
T
3
φ
Address bus
RD HWR LWR
, , ,AS
Address
High
High impedance
D to D
15 0
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area is accessed via an 8-bit or 16-bit data bus, and whether it is accessed in two or three states. For details see section 6, Bus Controller.
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Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Operating Mode Selection
The H8/3062 Series has seven operating modes (modes 1 to 7) that are selected by the mode pins (MD2 to MD0) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode.
Table 3.1 Operating Mode Selection
Description
Operating Mode MD2MD1MD
— 0 0 0 Setting prohibited Setting
Mode Pins
Address Space Mode*
0
Initial Bus On-Chip On-Chip
1
ROM RAM
prohibited
Setting prohibited
Setting
prohibited Mode 1 0 0 1 Expanded mode 8 bits Disabled Enabled* Mode 2 0 1 0 Expanded mode 16 bits Disabled Enabled* Mode 3 0 1 1 Expanded mode 8 bits Disabled Enabled* Mode 4 1 0 0 Expanded mode 16 bits Disabled Enabled* Mode 5 1 0 1 Expanded mode 8 bits Enabled Enabled* Mode 6 1 1 0 Single-chip normal mode — Enabled Enabled Mode 7 1 1 1 Single-chip advanced
— Enabled Enabled
mode
Notes: 1. In modes 1 to 5, an 8-bit or 16-bit data bus can be selected on a per-area basis by
settings made in the area bus width control register (ABWCR). For details see section 6, Bus Controller.
2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.
2
2
2
2
2
For the address space size there are three choices: 64 kbytes, 1 Mbyte, or 16 Mbyte. The external data bus is either 8 or 16 bits wide depending on ABWCR settings. 8-bit bus mode is used only if 8-bit access is selected for all areas. For details see section 6, Bus Controller.
Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes.
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Mode 5 is an externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 16 Mbytes.
Modes 6 and 7 are single-chip modes in which the chip operates using only the on-chip ROM, RAM, and I/O registers. All ports are available in these modes. Mode 6 supports a maximum address space of 64 kbytes. Mode 7 supports a maximum address space of 1 Mbyte.
The H8/3062 Series can be used only in modes 1 to 7. The inputs at the mode pins must select one of these seven modes. The inputs at the mode pins must not be changed during operation. Set the reset state before changing the inputs at these pins.
3.1.2 Register Configuration
The H8/3062 Series has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers.
Table 3.2 Registers
Address* Name Abbreviation R/W Initial Value
H'EE011 Mode control register MDCR R Undetermined H'EE012 System control register SYSCR R/W H'09
Note: * Lower 20 bits of the address in advanced mode.
3.2 Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3062 Series.
Bit
Initial value Read/Write
7
—
1
—
6
—
1
—
Reserved bits
5
—
0
—
4
—
0
—
3
—
0
—
2
MDS2
*
—
R
Mode select 2 to 0
Bits indicating the current operating mode
1
MDS1
— R**
0
MDS0
—
R
Note: Determined by pins MD to MD .*
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Bits 7 and 6—Reserved: These bits can not be modified and are always read as 1.
Bits 5 to 3—Reserved: These bits can not be modified and are always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched into these bits when MDCR is read.
Note: The versions with on-chip flash memory have a boot mode in which flash memory can be
programmed. In boot mode, the MDS2 bit value is the inverse of the level at the MD2 pin.
3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3062 Series.
Bit
Initial value Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
User bit enable
Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit
3
UE
1
R/W
2
NMIEG
0
R/W
NMI edge select
Selects the valid edge of the NMI input
1
SSOE
0
R/W
Software standby output port enable
Selects the output state of the address bus and bus control signals in software standby mode
0
RAME
1
R/W
RAM enable
Enables or disables on-chip RAM
Standby timer select 2 to 0
These bits select the waiting time at recovery from software standby mode
Software standby
Enables transition to software standby mode
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Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 21, Power-Down State.)
When software standby mode is exited by an external interrupt, and a transition is made to normal operation, this bit remains set to 1. To clear this bit, write 0.
Bit 7 SSBY Description
0 SLEEP instruction causes transition to sleep mode (Initial value) 1 SLEEP instruction causes transition to software standby mode
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt.
When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate. When operating on an external clock, care is required in the case of the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version.
For further information about waiting time selection, see section 21.4.3, Selection of Waiting Time for Exit from Software Standby Mode.
Bit 6 STS2
0 0 0 Waiting time = 8,192 states (Initial value) 0 0 1 Waiting time = 16,384 states 0 1 0 Waiting time = 32,768 states 0 1 1 Waiting time = 65,536 states 1 0 0 Waiting time = 131,072 states 1 0 1 Waiting time = 262,144 states 1 1 0 Waiting time = 1,024 states 1 1 1 Illegal setting
Bit 5 STS1
Bit 4 STS0 Description
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit.
Bit 3 UE Description
0 UI bit in CCR is used as an interrupt mask bit 1 UI bit in CCR is used as a user bit (Initial value)
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Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2 NMIEG Description
0 An interrupt is requested at the falling edge of NMI (Initial value) 1 An interrupt is requested at the rising edge of NMI
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR) are kept as outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1 SSOE Description
0 In software standby mode, the address bus and bus control signals are all high-
impedance (Initial value)
1 In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0 RAME Description
0 On-chip RAM is disabled 1 On-chip RAM is enabled (Initial value)
3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2 Mode 2
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
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3.4.3 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register (BRCR). (In this mode A20 is always used for address output.)
3.4.4 Mode 4
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits. A23 to A21 are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20 is always used for address output.)
3.4.5 Mode 5
Ports 1, 2, and 5 and part of port A can function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set to 1, setting ports 1, 2, and 5 to output mode. For A23 to A20 output, write 0 in bits 7 to 4 of BRCR. The versions with on-chip flash memory support an on-board programming mode in which the flash memory can be programmed. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.6 Mode 6
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 6 supports a maximum address space of 64 kbytes.
3.4.7 Mode 7
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 7 supports a 1-Mbyte address space.
The versions with on-chip flash memory support an on-board programming mode in which the flash memory can be programmed.
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3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode.
Table 3.3 Pin Functions in Each Mode
Port Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
Port 1 A7 to A
0
Port 2 A15 to A Port 3 D15 to D Port 4 P47 to P40*1D7 to D0* Port 5 A19 to A
8
8
16
A7 to A A15 to A D15 to D
A19 to A
8
8
1
16
A7 to A A15 to A D15 to D
0
8
8
P47 to P40* A19 to A
16
1
0
A7 to A
0
A15 to A D15 to D D7 to D0* A19 to A
P17 to P10*2P17 to P10P17 to P1
8
8
1
16
P27 to P20*2P27 to P20P27 to P2 D15 to D
P37 to P30P37 to P3
8
P47 to P40*1P47 to P40P47 to P4 P53 to P50*2P53 to P50P53 to P5
Port A PA7 to PA4PA7 to PA4PA6 to PA4, A20*3PA6 to PA4, A20*3PA7 to PA4*4PA7 to PA4PA7 to PA
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P4
to P40 in 8-bit bus mode, and as D7 to D0 in 16-bit bus mode.
7
2. Initial state. These pins become address output pins when the corresponding bits in the data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
3. Initial state. A A
output by writing 0 in bits 7 to 5 of BRCR.
21
4. Initial state. PA
is always an address output pin. PA6 to PA4 are switched over to A23 to
20
to PA4 are switched over to A23 to A20 output by writing 0 in bits 7 to 4 of
7
BRCR.
0
0
0
0
0
4
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3.6 Memory Map in Each Operating Mode
Figures 3.1 to 3.4 show memory maps of the H8/3062 Series. In the expanded modes, the address space is divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and on-chip registers differ between the 64-kbyte mode (mode 6), the 1-Mbyte modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5). The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs.
3.6.1 Comparison of H8/3062 Series Memory Maps
In the H8/3062 Series, the address maps vary according to the size of the on-chip ROM and RAM. The internal I/O register space is the same in all models, and the H8/3062F-ZTAT A-mask version and H8/3062 have the same address map. Table 3.4 shows the various address maps in mode 5.
Table 3.4 Address Maps in Mode 5
H8/3062 Mask ROM Version, H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT A-Mask Version
On-chip ROM
On-chip RAM
Size 128 kbytes 96 kbytes 64 kbytes 256 kbytes
Address area
Size 4 kbytes 4 kbytes 2 kbytes 8 kbytes
Address area
H'000000 to H'01FFFF
H'FFEF20 to H'FFFF1F
H8/3061 Mask ROM Version
H'000000 to H'017FFF
H'FFEF20 to H'FFFF1F
H8/3060 Mask ROM Version H8/3064F-ZTAT
H'000000 to H'00FFFF
H'FFF720 to H'FFFF1F
H'000000 to H'03FFFF
H'FFDF20 to H'FFFF1F
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3.6.2 Reserved Areas
The H8/3062 Series memory map includes reserved areas to which access (reading or writing) is prohibited. Normal operation cannot be guaranteed if the following reserved areas are accessed.
Reserved Area in Internal I/O Register Space: The H8/3062 Series internal I/O register space includes a reserved area to which access is prohibited. For details see Appendix B, Internal I/O Registers.
Other Reserved Areas: In mode 5 in the H8/3061 mask ROM version and H8/3060 mask ROM version there is a reserved area in area 0, as shown in figures 3.2 and 3.3.
In modes 1 to 5 in the H8/3060 mask ROM version there is a reserved area in area 7, as shown in figure 3.3.
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Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'00000
H'000FF
H'07FFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000
H'EE000
H'EE0FF
H'F8000 H'FEF1F
H'FEF20 H'FFF00 H'FFF1F
H'FFF20
H'FFFE9 H'FFFEA
H'FFFFF
Vector area
External address
space
Internal I/O
registers (1)
External address
space
On-chip RAM*
Internal I/O
registers (2)
External
address
space
H'000000
H'0000FF
16-bit absolute
Memory-indirect
Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7
8-bit absolute addresses
addresses
branch addresses
H'007FFF
H'1FFFFF H'200000
H'3FFFFF H'400000
H'5FFFFF H'600000
H'7FFFFF H'800000
H'9FFFFF H'A00000
H'BFFFFF H'C00000
H'DFFFFF H'E00000
H'FEE000
H'FEE0FF
16-bit absolute addresses
H'FF8000
Vector area
External address
space
Internal I/O
registers (1)
External address
space
16-bit absolute
Memory-indirect
branch addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
addresses
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.1 Memory Map of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,
H8/3062F-ZTAT A-Mask Version, and
H8/3062 Mask ROM Version in Each Operating Mode
74
H'FFEF1F H'FFEF20
H'FFFF00 H'FFFF1F
H'FFFF20
H'FFFFE9 H'FFFFEA
H'FFFFFF
On-chip RAM*
Internal I/O
registers (2)
External address
space
8-bit absolute addresses
16-bit absolute addresses
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Mode 5
(16-Mbyte expanded mode with
on-chip ROM enabled)
Mode 6
(single-chip normal mode)
Mode 7
(single-chip advanced mode)
H'000000
H'0000FF
H'007FFF H'01FFFF
H'020000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000
H'FEE000
H'FEE0FF H'FF8000
H'FFEF1F H'FFEF20
H'FFFF00 H'FFFF1F
H'FFFF20 H'FFFFE9
H'FFFFEA
H'FFFFFF
Vector area
On-chip ROM
External address
space
Internal I/O
registers (1)
External address
space
On-chip RAM*
Internal I/O
registers (2)
External
address
space
H'0000
H'00FF
16-bit absolute
Memory-indirect
Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7
8-bit absolute addresses
addresses
branch addresses
H'DFFF H'E000
H'E0FF
H'EF20
H'FF00 H'FF1F
H'FF20 H'FFE9
H'FFFF
16-bit absolute addresses
Vector area
On-chip ROM
Internal I/O
registers (1)
On-chip RAM
Internal I/O
registers (2)
H'00000
H'000FF
On-chip ROM
Memory-indirect
branch addresses
8-bit absolute addresses
H'07FFF
H'1FFFF
H'EE000
H'EE0FF H'F8000
H'FEF20 H'FFF00
H'FFF1F H'FFF20
H'FFFE9
H'FFFFF
On-chip RAM
Vector area
Internal I/O
registers (1)
Internal I/O
registers (2)
16-bit absolute
Memory-indirect
8-bit absolute addresses
addresses
branch addresses
16-bit absolute addresses
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.1 Memory Map of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,
H8/3062F-ZTAT A-Mask Version, and
H8/3062 Mask ROM Version in Each Operating Mode (cont)
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Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'00000
H'000FF
H'07FFF
H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000
H'EE000
H'EE0FF
H'F8000 H'FEF1F
H'FEF20 H'FFF00 H'FFF1F
H'FFF20
H'FFFE9 H'FFFEA
H'FFFFF
Vector area
External address
space
Internal I/O
registers (1)
External address
space
On-chip RAM*
Internal I/O
registers (2)
External
address
space
H'000000
H'0000FF
16-bit absolute
Memory-indirect
addresses
branch addresses
H'007FFF
Area 0 Area 1
H'1FFFFF H'200000
Area 2 Area 3
H'3FFFFF H'400000
Area 4 Area 5
H'5FFFFF H'600000
Area 6 Area 7
H'7FFFFF H'800000
H'9FFFFF H'A00000
H'BFFFFF H'C00000
H'DFFFFF H'E00000
H'FEE000
H'FEE0FF
16-bit absolute addresses
8-bit absolute addresses
H'FF8000
Vector area
External address
space
Internal I/O
registers (1)
External address
space
16-bit absolute
Memory-indirect
branch addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
addresses
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3.2 Memory Map of H8/3061 Mask ROM Version in Each Operating Mode
76
H'FFEF1F H'FFEF20
H'FFFF00 H'FFFF1F
H'FFFF20
H'FFFFE9 H'FFFFEA
H'FFFFFF
On-chip RAM*
Internal I/O
registers (2)
External address
space
8-bit absolute addresses
16-bit absolute addresses
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