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H8/3045
Hardware Manual
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Hitachi H8/3048, HD6473048, HD64F3048, HD6433047, H8/3047 Hardware Manual

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Hitachi Single-Chip Microcomputer
H8/3048 Series
H8/3048
HD64F3048, HD6473048, HD6433048
H8/3047
HD6433047
H8/3045
HD6433045
H8/3044
HD6433044
Hardware Manual
ADE-602-073B
查询64F3048F16供应商
Preface
The H8/3048 Series is a series of high-performance microcontrollers that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space.
The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to reduce power consumption in battery-powered applications: individual modules can be placed in standby, and the frequency of the system clock supplied to the chip can be divided down under software control.
The address space is divided into eight areas. The data bus width and access cycle length can be selected independently in each area, simplifying the connection of different types of memory. Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and address space size.
With these features, the H8/3048 Series can be used to implement compact, high-performance systems easily.
In addition to its masked-ROM versions, the H8/3048 Series has a ZTAT™*1version with user­programmable on-chip PROM and an F-ZTAT™*2version with on-chip flash memory that can be programmed on-board. These versions enable users to respond quickly and flexibly to changing application specifications.
This manual describes the H8/3048 Series hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual.
Notes: 1. ZTAT™ (Zero Turn-Around-time) is a trademark of Hitachi, Ltd.
2. F-ZTAT™ (Flexible ZTAT) is a trademark of Hitachi, Ltd.
Contents
Section 1 Overview...................................................................................................... 1
1.1 Overview......................................................................................................................... 1
1.2 Block Diagram................................................................................................................5
1.3 Pin Description ............................................................................................................... 6
1.3.1 Pin Arrangement............................................................................................. 6
1.3.2 Pin Assignments in Each Mode...................................................................... 7
1.3.3 Pin Functions.................................................................................................. 10
Section 2 CPU............................................................................................................... 15
2.1 Overview......................................................................................................................... 15
2.1.1 Features........................................................................................................... 15
2.1.2 Differences from H8/300 CPU....................................................................... 16
2.2 CPU Operating Modes.................................................................................................... 17
2.3 Address Space................................................................................................................. 18
2.4 Register Configuration.................................................................................................... 19
2.4.1 Overview......................................................................................................... 19
2.4.2 General Registers............................................................................................ 20
2.4.3 Control Registers............................................................................................ 21
2.4.4 Initial CPU Register Values............................................................................ 22
2.5 Data Formats................................................................................................................... 23
2.5.1 General Register Data Formats....................................................................... 23
2.5.2 Memory Data Formats.................................................................................... 25
2.6 Instruction Set................................................................................................................. 26
2.6.1 Instruction Set Overview................................................................................ 26
2.6.2 Instructions and Addressing Modes................................................................ 27
2.6.3 Tables of Instructions Classified by Function................................................. 28
2.6.4 Basic Instruction Formats............................................................................... 38
2.6.5 Notes on Use of Bit Manipulation Instructions.............................................. 39
2.7 Addressing Modes and Effective Address Calculation.................................................. 39
2.7.1 Addressing Modes.......................................................................................... 39
2.7.2 Effective Address Calculation........................................................................ 42
2.8 Processing States ............................................................................................................46
2.8.1 Overview......................................................................................................... 46
2.8.2 Program Execution State ................................................................................ 47
2.8.3 Exception-Handling State............................................................................... 47
2.8.4 Exception-Handling Sequences...................................................................... 49
2.8.5 Bus-Released State ......................................................................................... 50
2.8.6 Reset State ...................................................................................................... 50
2.8.7 Power-Down State .......................................................................................... 50
2.9 Basic Operational Timing............................................................................................... 51
2.9.1 Overview......................................................................................................... 51
2.9.2 On-Chip Memory Access Timing................................................................... 51
2.9.3 On-Chip Supporting Module Access Timing................................................. 53
2.9.4 Access to External Address Space.................................................................. 54
Section 3 MCU Operating Modes........................................................................... 55
3.1 Overview......................................................................................................................... 55
3.1.1 Operating Mode Selection.............................................................................. 55
3.1.2 Register Configuration.................................................................................... 56
3.2 Mode Control Register (MDCR).................................................................................... 57
3.3 System Control Register (SYSCR)................................................................................. 58
3.4 Operating Mode Descriptions......................................................................................... 60
3.4.1 Mode 1............................................................................................................ 60
3.4.2 Mode 2............................................................................................................ 60
3.4.3 Mode 3............................................................................................................ 60
3.4.4 Mode 4............................................................................................................ 60
3.4.5 Mode 5............................................................................................................ 60
3.4.6 Mode 6 ........................................................................................................... 60
3.4.7 Mode 7 ........................................................................................................... 61
3.5 Pin Functions in Each Operating Mode.......................................................................... 61
3.6 Memory Map in Each Operating Mode.......................................................................... 61
Section 4 Exception Handling.................................................................................. 71
4.1 Overview......................................................................................................................... 71
4.1.1 Exception Handling Types and Priority.......................................................... 71
4.1.2 Exception Handling Operation....................................................................... 71
4.1.3 Exception Vector Table................................................................................... 72
4.2 Reset ............................................................................................................................... 73
4.2.1 Overview......................................................................................................... 73
4.2.2 Reset Sequence............................................................................................... 73
4.2.3 Interrupts after Reset....................................................................................... 76
4.3 Interrupts......................................................................................................................... 77
4.4 Trap Instruction............................................................................................................... 78
4.5 Stack Status after Exception Handling........................................................................... 79
4.6 Notes on Stack Usage..................................................................................................... 80
Section 5 Interrupt Controller................................................................................... 81
5.1 Overview......................................................................................................................... 81
5.1.1 Features........................................................................................................... 81
5.1.2 Block Diagram................................................................................................ 82
5.1.3 Pin Configuration............................................................................................ 83
5.1.4 Register Configuration.................................................................................... 83
5.2 Register Descriptions...................................................................................................... 84
5.2.1 System Control Register (SYSCR)................................................................. 84
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)....................................... 85
5.2.3 IRQ Status Register (ISR) .............................................................................. 92
5.2.4 IRQ Enable Register (IER)............................................................................. 93
5.2.5 IRQ Sense Control Register (ISCR)............................................................... 94
5.3 Interrupt Sources............................................................................................................. 95
5.3.1 External Interrupts.......................................................................................... 95
5.3.2 Internal Interrupts ........................................................................................... 96
5.3.3 Interrupt Vector Table..................................................................................... 96
5.4 Interrupt Operation ......................................................................................................... 100
5.4.1 Interrupt Handling Process............................................................................. 100
5.4.2 Interrupt Sequence.......................................................................................... 105
5.4.3 Interrupt Response Time................................................................................. 106
5.5 Usage Notes.................................................................................................................... 107
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction................ 107
5.5.2 Instructions that Inhibit Interrupts.................................................................. 108
5.5.3 Interrupts during EEPMOV Instruction Execution......................................... 108
5.5.4 Notes on External Interrup to during Use....................................................... 108
Section 6 Bus Controller............................................................................................ 111
6.1 Overview......................................................................................................................... 111
6.1.1 Features........................................................................................................... 111
6.1.2 Block Diagram................................................................................................ 112
6.1.3 Input/Output Pins............................................................................................ 113
6.1.4 Register Configuration.................................................................................... 113
6.2 Register Descriptions...................................................................................................... 114
6.2.1 Bus Width Control Register (ABWCR)......................................................... 114
6.2.2 Access State Control Register (ASTCR)........................................................ 115
6.2.3 Wait Control Register (WCR)......................................................................... 116
6.2.4 Wait State Controller Enable Register (WCER)............................................. 117
6.2.5 Bus Release Control Register (BRCR)........................................................... 118
6.2.6 Chip Select Control Register (CSCR) ............................................................ 119
6.3 Operation ........................................................................................................................ 121
6.3.1 Area Division.................................................................................................. 121
6.3.2 Chip Select Signals......................................................................................... 123
6.3.3 Data Bus.......................................................................................................... 124
6.3.4 Bus Control Signal Timing............................................................................. 125
6.3.5 Wait Modes..................................................................................................... 133
6.3.6 Interconnections with Memory (Example)..................................................... 139
6.3.7 Bus Arbiter Operation..................................................................................... 141
6.4 Usage Notes.................................................................................................................... 144
6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM................................ 144
6.4.2 Register Write Timing.................................................................................... 144
6.4.3 BREQ Input Timing........................................................................................ 144
6.4.4 Transition to Software Standby Mode............................................................ 146
Section 7 Refresh Controller .................................................................................... 147
7.1 Overview......................................................................................................................... 147
7.1.1 Features........................................................................................................... 147
7.1.2 Block Diagram................................................................................................ 148
7.1.3 Input/Output Pins............................................................................................ 149
7.1.4 Register Configuration.................................................................................... 149
7.2 Register Descriptions...................................................................................................... 150
7.2.1 Refresh Control Register (RFSHCR) ............................................................. 150
7.2.2 Refresh Timer Control/Status Register (RTMCSR)....................................... 153
7.2.3 Refresh Timer Counter (RTCNT)................................................................... 155
7.2.4 Refresh Time Constant Register (RTCOR) .................................................... 155
7.3 Operation ........................................................................................................................ 156
7.3.1 Overview......................................................................................................... 156
7.3.2 DRAM Refresh Control.................................................................................. 157
7.3.3 Pseudo-Static RAM Refresh Control.............................................................. 172
7.3.4 Interval Timing............................................................................................... 177
7.4 Interrupt Source.............................................................................................................. 183
7.5 Usage Notes.................................................................................................................... 183
Section 8 DMA Controller........................................................................................ 185
8.1 Overview......................................................................................................................... 185
8.1.1 Features........................................................................................................... 185
8.1.2 Block Diagram................................................................................................ 186
8.1.3 Functional Overview....................................................................................... 187
8.1.4 Input/Output Pins............................................................................................ 188
8.1.5 Register Configuration.................................................................................... 188
8.2 Register Descriptions (Short Address Mode)................................................................. 190
8.2.1 Memory Address Registers (MAR)................................................................ 190
8.2.2 I/O Address Registers (IOAR)........................................................................ 191
8.2.3 Execute Transfer Count Registers (ETCR)..................................................... 191
8.2.4 Data Transfer Control Registers (DTCR)....................................................... 193
8.3 Register Descriptions (Full Address Mode)................................................................... 196
8.3.1 Memory Address Registers (MAR)................................................................ 196
8.3.2 I/O Address Registers (IOAR)........................................................................ 196
8.3.3 Execute Transfer Count Registers (ETCR)..................................................... 197
8.3.4 Data Transfer Control Registers (DTCR)....................................................... 199
8.4 Operation ........................................................................................................................ 205
8.4.1 Overview......................................................................................................... 205
8.4.2 I/O Mode......................................................................................................... 207
8.4.3 Idle Mode........................................................................................................ 209
8.4.4 Repeat Mode................................................................................................... 212
8.4.5 Normal Mode.................................................................................................. 215
8.4.6 Block Transfer Mode...................................................................................... 218
8.4.7 DMAC Activation........................................................................................... 223
8.4.8 DMAC Bus Cycle........................................................................................... 225
8.4.9 Multiple-Channel Operation........................................................................... 231
8.4.10 External Bus Requests, Refresh Controller, and DMAC................................ 232
8.4.11 NMI Interrupts and DMAC............................................................................ 233
8.4.12 Aborting a DMA Transfer.............................................................................. 234
8.4.13 Exiting Full Address Mode............................................................................. 235
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.................... 236
8.5 Interrupts......................................................................................................................... 237
8.6 Usage Notes.................................................................................................................... 238
8.6.1 Note on Word Data Transfer........................................................................... 238
8.6.2 DMAC Self-Access........................................................................................ 238
8.6.3 Longword Access to Memory Address Registers........................................... 238
8.6.4 Note on Full Address Mode Setup.................................................................. 238
8.6.5 Note on Activating DMAC by Internal Interrupts.......................................... 239
8.6.6 NMI Interrupts and Block Transfer Mode...................................................... 240
8.6.7 Memory and I/O Address Register Values ..................................................... 240
8.6.8 Bus Cycle when Transfer is Aborted.............................................................. 241
Section 9 I/O Ports....................................................................................................... 243
9.1 Overview......................................................................................................................... 243
9.2 Port 1............................................................................................................................... 246
9.2.1 Overview......................................................................................................... 246
9.2.2 Register Descriptions...................................................................................... 247
9.3 Port 2............................................................................................................................... 249
9.3.1 Overview......................................................................................................... 249
9.3.2 Register Descriptions...................................................................................... 250
9.4 Port 3............................................................................................................................... 253
9.4.1 Overview......................................................................................................... 253
9.4.2 Register Descriptions...................................................................................... 253
9.5 Port 4............................................................................................................................... 255
9.5.1 Overview......................................................................................................... 255
9.5.2 Register Descriptions...................................................................................... 256
9.6 Port 5............................................................................................................................... 259
9.6.1 Overview......................................................................................................... 259
9.6.2 Register Descriptions...................................................................................... 259
9.7 Port 6............................................................................................................................... 262
9.7.1 Overview......................................................................................................... 262
9.7.2 Register Descriptions...................................................................................... 262
9.8 Port 7............................................................................................................................... 265
9.8.1 Overview......................................................................................................... 265
9.8.2 Register Description ....................................................................................... 266
9.9 Port 8............................................................................................................................... 267
9.9.1 Overview......................................................................................................... 267
9.9.2 Register Descriptions...................................................................................... 268
9.10 Port 9............................................................................................................................... 272
9.10.1 Overview......................................................................................................... 272
9.10.2 Register Descriptions...................................................................................... 272
9.11 Port A.............................................................................................................................. 276
9.11.1 Overview......................................................................................................... 276
9.11.2 Register Descriptions...................................................................................... 278
9.11.3 Pin Functions.................................................................................................. 279
9.12 Port B.............................................................................................................................. 284
9.12.1 Overview......................................................................................................... 284
9.12.2 Register Descriptions...................................................................................... 286
9.12.3 Pin Functions.................................................................................................. 288
Section 10 16-Bit Integrated Timer Unit (ITU)..................................................... 295
10.1 Overview......................................................................................................................... 295
10.1.1 Features........................................................................................................... 295
10.1.2 Block Diagrams.............................................................................................. 298
10.1.3 Input/Output Pins............................................................................................ 303
10.1.4 Register Configuration.................................................................................... 304
10.2 Register Descriptions...................................................................................................... 307
10.2.1 Timer Start Register (TSTR).......................................................................... 307
10.2.2 Timer Synchro Register (TSNC).................................................................... 308
10.2.3 Timer Mode Register (TMDR)....................................................................... 310
10.2.4 Timer Function Control Register (TFCR)...................................................... 313
10.2.5 Timer Output Master Enable Register (TOER).............................................. 315
10.2.6 Timer Output Control Register (TOCR)......................................................... 318
10.2.7 Timer Counters (TCNT)................................................................................. 319
10.2.8 General Registers (GRA, GRB) ..................................................................... 320
10.2.9 Buffer Registers (BRA, BRB)........................................................................ 321
10.2.10 Timer Control Registers (TCR)...................................................................... 322
10.2.11 Timer I/O Control Register (TIOR)................................................................ 324
10.2.12 Timer Status Register (TSR)........................................................................... 326
10.2.13 Timer Interrupt Enable Register (TIER)......................................................... 329
10.3 CPU Interface ................................................................................................................. 331
10.3.1 16-Bit Accessible Registers............................................................................ 331
10.3.2 8-Bit Accessible Registers.............................................................................. 333
10.4 Operation ........................................................................................................................ 335
10.4.1 Overview......................................................................................................... 335
10.4.2 Basic Functions............................................................................................... 336
10.4.3 Synchronization.............................................................................................. 346
10.4.4 PWM Mode .................................................................................................... 348
10.4.5 Reset-Synchronized PWM Mode................................................................... 352
10.4.6 Complementary PWM Mode.......................................................................... 355
10.4.7 Phase Counting Mode..................................................................................... 365
10.4.8 Buffering......................................................................................................... 367
10.4.9 ITU Output Timing......................................................................................... 374
10.5 Interrupts......................................................................................................................... 376
10.5.1 Setting of Status Flags.................................................................................... 376
10.5.2 Clearing of Status Flags.................................................................................. 378
10.5.3 Interrupt Sources and DMA Controller Activation........................................ 379
10.6 Usage Notes.................................................................................................................... 380
Section 11 Programmable Timing Pattern Controller......................................... 395
11.1 Overview......................................................................................................................... 395
11.1.1 Features........................................................................................................... 395
11.1.2 Block Diagram................................................................................................ 396
11.1.3 TPC Pins......................................................................................................... 397
11.1.4 Registers ......................................................................................................... 398
11.2 Register Descriptions...................................................................................................... 399
11.2.1 Port A Data Direction Register (PADDR)...................................................... 399
11.2.2 Port A Data Register (PADR)......................................................................... 399
11.2.3 Port B Data Direction Register (PBDDR)...................................................... 400
11.2.4 Port B Data Register (PBDR)......................................................................... 400
11.2.5 Next Data Register A (NDRA)....................................................................... 401
11.2.6 Next Data Register B (NDRB)....................................................................... 403
11.2.7 Next Data Enable Register A (NDERA)........................................................ 405
11.2.8 Next Data Enable Register B (NDERB)......................................................... 406
11.2.9 TPC Output Control Register (TPCR)............................................................ 407
11.2.10 TPC Output Mode Register (TPMR).............................................................. 410
11.3 Operation ........................................................................................................................... 412
11.3.1 Overview......................................................................................................... 412
11.3.2 Output Timing................................................................................................. 413
11.3.3 Normal TPC Output........................................................................................ 414
11.3.4 Non-Overlapping TPC Output........................................................................ 416
11.3.5 TPC Output Triggering by Input Capture....................................................... 418
11.4 Usage Notes.................................................................................................................... 419
11.4.1 Operation of TPC Output Pins........................................................................ 419
11.4.2 Note on Non-Overlapping Output.................................................................. 419
Section 12 Watchdog Timer........................................................................................ 421
12.1 Overview......................................................................................................................... 421
12.1.1 Features........................................................................................................... 421
12.1.2 Block Diagram................................................................................................ 422
12.1.3 Pin Configuration............................................................................................ 422
12.1.4 Register Configuration.................................................................................... 423
12.2 Register Descriptions...................................................................................................... 424
12.2.1 Timer Counter (TCNT)................................................................................... 424
12.2.2 Timer Control/Status Register (TCSR)........................................................... 425
12.2.3 Reset Control/Status Register (RSTCSR) ...................................................... 427
12.2.4 Notes on Register Access ............................................................................... 429
12.3 Operation ........................................................................................................................ 431
12.3.1 Watchdog Timer Operation............................................................................. 431
12.3.2 Interval Timer Operation................................................................................ 432
12.3.3 Timing of Setting of Overflow Flag (OVF).................................................... 433
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)............................. 434
12.4 Interrupts......................................................................................................................... 435
12.5 Usage Notes.................................................................................................................... 435
Section 13 Serial Communication Interface........................................................... 437
13.1 Overview......................................................................................................................... 437
13.1.1 Features........................................................................................................... 437
13.1.2 Block Diagram................................................................................................ 439
13.1.3 Input/Output Pins............................................................................................ 440
13.1.4 Register Configuration.................................................................................... 440
13.2 Register Descriptions...................................................................................................... 441
13.2.1 Receive Shift Register (RSR)......................................................................... 441
13.2.2 Receive Data Register (RDR)......................................................................... 441
13.2.3 Transmit Shift Register (TSR)........................................................................ 442
13.2.4 Transmit Data Register (TDR)........................................................................ 442
13.2.5 Serial Mode Register (SMR).......................................................................... 443
13.2.6 Serial Control Register (SCR)........................................................................ 447
13.2.7 Serial Status Register (SSR)........................................................................... 451
13.2.8 Bit Rate Register (BRR)................................................................................. 455
13.3 Operation ........................................................................................................................ 464
13.3.1 Overview......................................................................................................... 464
13.3.2 Operation in Asynchronous Mode.................................................................. 466
13.3.3 Multiprocessor Communication ..................................................................... 475
13.3.4 Synchronous Operation .................................................................................. 482
13.4 SCI Interrupts.................................................................................................................. 491
13.5 Usage Notes.................................................................................................................... 492
Section 14 Smart Card Interface................................................................................ 497
14.1 Overview......................................................................................................................... 497
14.1.1 Features........................................................................................................... 497
14.1.2 Block Diagram................................................................................................ 498
14.1.3 Input/Output Pins............................................................................................ 499
14.1.4 Register Configuration.................................................................................... 499
14.2 Register Descriptions...................................................................................................... 500
14.2.1 Smart Card Mode Register (SCMR)............................................................... 500
14.2.2 Serial Status Register (SSR)........................................................................... 501
14.2.3 Serial Mode Register (SMR).......................................................................... 503
14.2.4 Serial Control Register (SCR)........................................................................ 504
14.3 Operation ........................................................................................................................ 505
14.3.1 Overview......................................................................................................... 505
14.3.2 Pin Connections.............................................................................................. 505
14.3.3 Data Format.................................................................................................... 506
14.3.4 Register Settings............................................................................................. 508
14.3.5 Clock............................................................................................................... 510
14.3.6 Transmitting and Receiving Data................................................................... 512
14.4 Usage Notes.................................................................................................................... 519
Section 15 A/D Converter............................................................................................ 523
15.1 Overview......................................................................................................................... 523
15.1.1 Features........................................................................................................... 523
15.1.2 Block Diagram................................................................................................ 524
15.1.3 Input Pins........................................................................................................ 525
15.1.4 Register Configuration.................................................................................... 526
15.2 Register Descriptions...................................................................................................... 527
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................ 527
15.2.2 A/D Control/Status Register (ADCSR).......................................................... 528
15.2.3 A/D Control Register (ADCR)....................................................................... 531
15.3 CPU Interface ................................................................................................................. 532
15.4 Operation ........................................................................................................................ 533
15.4.1 Single Mode (SCAN = 0)............................................................................... 533
15.4.2 Scan Mode (SCAN = 1).................................................................................. 535
15.4.3 Input Sampling and A/D Conversion Time .................................................... 537
15.4.4 External Trigger Input Timing........................................................................ 538
15.5 Interrupts......................................................................................................................... 539
15.6 Usage Notes.................................................................................................................... 539
Section 16 D/A Converter............................................................................................ 545
16.1 Overview......................................................................................................................... 545
16.1.1 Features........................................................................................................... 545
16.1.2 Block Diagram................................................................................................ 545
16.1.3 Input/Output Pins............................................................................................ 546
16.1.4 Register Configuration.................................................................................... 546
16.2 Register Descriptions...................................................................................................... 547
16.2.1 D/A Data Registers 0 and 1 (DADR0/1)........................................................ 547
16.2.2 D/A Control Register (DACR) ....................................................................... 547
16.2.3 D/A Standby Control Register (DASTCR)..................................................... 549
16.3 Operation ........................................................................................................................ 550
16.4 D/A Output Control........................................................................................................ 551
16.5 Usage Notes.................................................................................................................... 551
Section 17 RAM............................................................................................................. 553
17.1 Overview......................................................................................................................... 553
17.1.1 Block Diagram................................................................................................ 553
17.1.2 Register Configuration.................................................................................... 554
17.2 System Control Register (SYSCR)................................................................................. 555
17.3 Operation ........................................................................................................................ 556
Section 18 ROM.............................................................................................................. 557
18.1 Overview......................................................................................................................... 557
18.1.1 Block Diagram................................................................................................ 558
18.2 PROM Mode................................................................................................................... 559
18.2.1 PROM Mode Setting ...................................................................................... 559
18.2.2 Socket Adapter and Memory Map.................................................................. 559
18.3 PROM Programming...................................................................................................... 562
18.3.1 Programming and Verification........................................................................ 562
18.3.2 Programming Precautions............................................................................... 567
18.3.3 Reliability of Programmed Data..................................................................... 568
18.4 Flash Memory Overview................................................................................................ 569
18.4.1 Flash Memory Operation................................................................................ 569
18.4.2 Mode Programming and Flash Memory Address Space................................ 570
18.4.3 Features........................................................................................................... 570
18.4.4 Block Diagram................................................................................................ 572
18.4.5 Input/Output Pins............................................................................................ 573
18.4.6 Register Configuration.................................................................................... 573
18.5 Flash Memory Register Descriptions ............................................................................. 574
18.5.1 Flash Memory Control Register ..................................................................... 574
18.5.2 Erase Block Register 1.................................................................................... 577
18.5.3 Erase Block Register 2.................................................................................... 578
18.5.4 RAM Control Register (RAMCR).................................................................. 580
18.6 On-Board Programming Modes ..................................................................................... 582
18.6.1 Boot Mode...................................................................................................... 582
18.6.2 User Program Mode........................................................................................ 587
18.7 Programming and Erasing Flash Memory...................................................................... 589
18.7.1 Program Mode................................................................................................ 590
18.7.2 Program-Verify Mode..................................................................................... 590
18.7.3 Programming Flowchart and Sample Program............................................... 591
18.7.4 Erase Mode..................................................................................................... 593
18.7.5 Erase-Verify Mode.......................................................................................... 594
18.7.6 Erasing Flowchart and Sample Program ........................................................ 595
18.7.7 Prewrite-Verify Mode..................................................................................... 607
18.7.8 Protect Modes................................................................................................. 607
18.7.9 NMI Input Masking........................................................................................ 610
18.8 Flash Memory Emulation by RAM................................................................................ 611
18.9 PROM Mode................................................................................................................... 613
18.9.1 PROM Mode Setting ...................................................................................... 613
18.9.2 Socket Adapter and Memory Map.................................................................. 614
18.9.3 Operation in PROM Mode.............................................................................. 616
18.10 Flash Memory Programming and Erasing Precautions.................................................. 624
Section 19 Clock Pulse Generator............................................................................. 633
19.1 Overview......................................................................................................................... 633
19.1.1 Block Diagram................................................................................................ 633
19.2 Oscillator Circuit ............................................................................................................ 634
19.2.1 Connecting a Crystal Resonator ..................................................................... 634
19.2.2 External Clock Input....................................................................................... 636
19.3 Duty Adjustment Circuit................................................................................................. 639
19.4 Prescalers........................................................................................................................ 639
19.5 Frequency Divider.......................................................................................................... 639
19.5.1 Register Configuration.................................................................................... 639
19.5.2 Division Control Register (DIVCR)............................................................... 639
19.5.3 Usage Notes.................................................................................................... 640
Section 20 Power-Down State.................................................................................... 641
20.1 Overview......................................................................................................................... 641
20.2 Register Configuration.................................................................................................... 643
20.2.1 System Control Register (SYSCR)................................................................. 643
20.2.2 Module Standby Control Register (MSTCR)................................................. 645
20.3 Sleep Mode..................................................................................................................... 647
20.3.1 Transition to Sleep Mode................................................................................ 647
20.3.2 Exit from Sleep Mode..................................................................................... 647
20.4 Software Standby Mode ................................................................................................. 648
20.4.1 Transition to Software Standby Mode............................................................ 648
20.4.2 Exit from Software Standby Mode................................................................. 648
20.4.3 Selection of Waiting Time for Exit from Software Standby Mode................ 649
20.4.4 Sample Application of Software Standby Mode............................................ 650
20.4.5 Note................................................................................................................. 650
20.5 Hardware Standby Mode................................................................................................ 651
20.5.1 Transition to Hardware Standby Mode........................................................... 651
20.5.2 Exit from Hardware Standby Mode................................................................ 651
20.5.3 Timing for Hardware Standby Mode.............................................................. 651
20.6 Module Standby Function............................................................................................... 652
20.6.1 Module Standby Timing................................................................................. 652
20.6.2 Read/Write in Module Standby...................................................................... 652
20.6.3 Usage Notes.................................................................................................... 652
20.7 System Clock Output Disabling Function...................................................................... 653
Section 21 Electrical Characteristics........................................................................ 649
21.1 Absolute Maximum Ratings........................................................................................... 649
21.2 Electrical Characteristics of Masked ROM and PROM Versions................................... 650
21.2.1 DC Characteristics.......................................................................................... 650
21.2.2 AC Characteristics.......................................................................................... 658
21.2.3 A/D Conversion Characteristics..................................................................... 666
21.2.4 D/A Conversion Characteristics..................................................................... 667
21.3 Electrical Characteristics of Flash Memory Version...................................................... 668
21.3.1 DC Characteristics.......................................................................................... 668
21.3.2 AC Characteristics.......................................................................................... 677
21.3.3 A/D Conversion Characteristics..................................................................... 683
21.3.4 D/A Conversion Characteristics..................................................................... 684
21.3.5 Flash Memory Characteristics........................................................................ 685
21.4 Operational Timing......................................................................................................... 686
14
21.4.1 Bus Timing ..................................................................................................... 686
21.4.2 Refresh Controller Bus Timing....................................................................... 690
21.4.3 Control Signal Timing.................................................................................... 695
21.4.4 Clock Timing.................................................................................................. 697
21.4.5 TPC and I/O Port Timing................................................................................ 697
21.4.6 ITU Timing..................................................................................................... 698
21.4.7 SCI Input/Output Timing................................................................................ 699
21.4.8 DMAC Timing................................................................................................ 700
Appendix A Instruction Set............................................................................................ 703
A.1 Instruction List................................................................................................................ 703
A.2 Operation Code Map....................................................................................................... 718
A.3 Number of States Required for Execution...................................................................... 721
Appendix B Internal I/O Register................................................................................. 730
B.1 Addresses........................................................................................................................ 730
B.2 Function.......................................................................................................................... 738
Appendix C I/O Port Block Diagrams ........................................................................ 818
C.1 Port 1 Block Diagram..................................................................................................... 818
C.2 Port 2 Block Diagram..................................................................................................... 819
C.3 Port 3 Block Diagram..................................................................................................... 820
C.4 Port 4 Block Diagram..................................................................................................... 821
C.5 Port 5 Block Diagram..................................................................................................... 822
C.6 Port 6 Block Diagrams.................................................................................................... 823
C.7 Port 7 Block Diagrams.................................................................................................... 827
C.8 Port 8 Block Diagrams.................................................................................................... 828
C.9 Port 9 Block Diagrams.................................................................................................... 831
C.10 Port A Block Diagrams................................................................................................... 835
C.11 Port B Block Diagrams................................................................................................... 839
Appendix D Pin States..................................................................................................... 843
D.1 Port States in Each Mode................................................................................................ 843
D.2 Pin States at Reset........................................................................................................... 846
Appendix E
Timing of Transition to and Recovery from Hardware Standby Mode
.... 849
Appendix F Product Code Lineup............................................................................... 850
Appendix G Package Dimensions................................................................................ 852
Section 1 Overview
1.1 Overview
The H8/3048 Series is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities.
The four members of the H8/3048 Series are the H8/3048, the H8/3047, H8/3045, and the H8/3044. The H8/3048 has 128 kbytes of ROM and 4 kbytes of RAM. The H8/3047 has 96 kbytes of ROM and 4 kbytes of RAM. The H8/3045 has 64 kbytes of ROM and 2 kbytes of RAM. The H8/3044 has 32 kbytes of ROM and 2 kbytes of RAM.
Seven MCU operating modes offer a choice of data bus width and address space size. The modes (modes 1 to 7) include one single-chip mode and six expanded modes.
In addition to the masked-ROM versions of the H8/3048 Series, the H8/3048 has a ZTAT™*
1
version with user-programmable on-chip PROM and an F-ZTAT™*2version with on-chip flash memory that can be programmed on-board. These versions enable users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions.
Table 1-1 summarizes the features of the H8/3048 Series.
Notes: 1. ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.
2. F-ZTAT (Flexible ZTAT) is a trademark of Hitachi, Ltd.
1
Table 1-1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers (also usable as + eight 16-bit registers or eight 32-bit registers)
High-speed operation (flash memory version)
• Maximum clock rate: 16 MHz
• Add/subtract: 125 ns
• Multiply/divide: 875 ns
High-speed operation (masked ROM and PROM versions)
• Maximum clock rate: 18 MHz
• Add/subtract: 111 ns
• Multiply/divide: 778 ns
16-Mbyte address space Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits
× 8 bits, 16 bits × 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit positions
Memory H8/3048
• ROM: 128 kbytes
• RAM: 4 kbytes
H8/3047
• ROM: 96 kbytes
• RAM: 4 kbytes
H8/3045
• ROM: 64 kbytes
• RAM: 2 kbytes
H8/3044
• ROM: 32 kbytes
• RAM: 2 kbytes
Interrupt • Seven external interrupt pins: NMI, IRQ
0
to IRQ
5
controller • 30 internal interrupts
• Three selectable interrupt priority levels
Bus controller • Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Chip select output available for areas 0 to 7
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
• Bus arbitration function
2
Table 1-1 Features (cont)
Feature Description
Refresh DRAM refresh controller • Directly connectable to 16-bit-wide DRAM
• CAS-before-RAS refresh
• Self-refresh mode selectable Pseudo-static RAM refresh
• Self-refresh mode selectable Usable as an interval timer
DMA controller Short address mode (DMAC) • Maximum four channels available
• Selection of I/O mode, idle mode, or repeat mode
• Can be activated by compare match/input capture A interrupts from ITU channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, or external requests
Full address mode
• Maximum two channels available
• Selection of normal mode or block transfer mode
• Can be activated by compare match/input capture A interrupts from ITU channels 0 to 3, external requests, or auto-request
16-bit integrated • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10 timer unit (ITU) pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
• DMAC can be activated by compare match/input capture A interrupts (channels 0 to 3)
Programmable • Maximum 16-bit pulse output, using ITU as time base timing pattern • Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups) controller (TPC) • Non-overlap mode available
• Output data can be transferred by DMAC
Watchdog • Reset signal can be generated by overflow timer (WDT), • Reset signal can be output externally 1 channel • Usable as an interval timer
Serial • Selection of asynchronous or synchronous mode communication • Full duplex: can transmit and receive simultaneously interface (SCI), • On-chip baud-rate generator 2 channels • Smart card interface functions added (SCI0 only)
3
Table 1-1 Features (cont)
Feature Description
A/D converter • Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• A/D conversion can be externally triggered
D/A converter • Resolution: 8 bits
• Two channels
• D/A outputs can be sustained in software standby mode
I/O ports • 70 input/output pins
• 8 input-only pins
Operating modes Seven MCU operating modes
Mode Address Space Address Pins Initial Bus Width Max. Bus Width
Mode 1 1 Mbyte A19to A
0
8 bits 16 bits
Mode 2 1 Mbyte A19to A
0
16 bits 16 bits
Mode 3 16 Mbytes A23to A
0
8 bits 16 bits
Mode 4 16 Mbytes A23to A
0
16 bits 16 bits
Mode 5 1 Mbyte A19to A
0
8 bits 16 bits
Mode 6 16 Mbytes A23to A
0
8 bits 16 bits
Mode 7 1 Mbyte — — —
• On-chip ROM is disabled in modes 1 to 4
Power-down • Sleep mode state • Software standby mode
• Hardware standby mode
• Module standby function
• Programmable system clock frequency division
Other features • On-chip clock pulse generator Product lineup
Model (5-V) Model (3-V) Package ROM
HD64F3048TF HD64F3048VTF 100-pin TQFP (TFP-100B) Flash memory HD64F3048F HD64F3048VF 100-pin QFP (FP-100B) HD6473048TF HD6473048VTF 100-pin TQFP (TFP-100B) PROM HD6473048F HD6473048VF 100-pin QFP (FP-100B) HD6433048TF HD6433048VTF 100-pin TQFP (TFP-100B) Masked ROM HD6433048F HD6433048VF 100-pin QFP (FP-100B) HD6433047TF HD6433047VTF 100-pin TQFP (TFP-100B) Masked ROM HD6433047F HD6433047VF 100-pin QFP (FP-100B) HD6433045TF HD6433045VTF 100-pin TQFP (TFP-100B) Masked ROM HD6433045F HD6433045VF 100-pin QFP (FP-100B) HD6433044TF HD6433044VTF 100-pin TQFP (TFP-100B) Masked ROM HD6433044F HD6433044VF 100-pin QFP (FP-100B)
4
1.2 Block Diagram
Figure 1-1 shows an internal block diagram.
Figure 1-1 Block Diagram
VVVVVVVVV
CCCCCCSSSSSSSSSSSS
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
7654321
0
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
7654321
0
7654321
0
Port 3 Port 4
Port 5Port 9
P5 /A P5 /A P5 /A P5 /A
3 2 1 0
19 18 17 16
P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A P2 /A
7 6 5 4 3 2 1 0
P9 /SCK /IRQ P9 /SCK /IRQ P9 /RxD P9 /RxD P9 /TxD P9 /TxD
5 4 3 2 1 0
1
0 1 0 1 0
5 4
P7 /AN /DA
P7 /AN /DA
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /AN
7654321
0
1054321
0
Port 7
V
AV
AV
REF
CC
SS
PA
7
/TP
7
/TIOCB
2
/A
20
PA
6
/TP
6
/TIOCA
2
/A
21
/CS
4
PA
5
/TP
5
/TIOCB
1
/A
22
/CS
5
PA
4
/TP
4
/TIOCA
1
/A
23
/CS
6
PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TEND /TCLKB
PA /TP /TEND /TCLKA
Port A
3
2
0
0
3
2
1
0
1
0
PB /TP /DREQ /ADTRG
PB
6
/TP
14
/DREQ
0
/CS
7
PB /TP /TOCXB
PB /TP /TOCXA
PB /TP /TIOCB
PB /TP /TIOCA
PB /TP /TIOCB
PB /TP /TIOCA
15 17
44443
3
5
4
13
12
3
2
11
10
1
0
9
8
Port 8
P8 /CS P8 /CS /IRQ P8 /CS /IRQ P8 /CS /IRQ
P8 /RFSH/IRQ
40
3 2 1 0
1 2 3
3 2 1
0
MD MD MD
EXTAL
XTAL
ø
STBY
RES
V /RESO
NMI
2 1 0
H8/300H CPU
Clock pulse
generator
Interrupt controller
ROM
(masked ROM,
PROM, or flash
memory)
DMA controller
(DMAC)
Serial communication
interface
(SCI) 2 channels
×
Watchdog timer
(WDT)
Refresh
controller
1514131211109
8
Address bus
Data bus (upper)
Data bus (lower)
15 14 13 12 11 10 9 8
Port 2
P1 /A P1 /A P1 /A P1 /A P1 /A P1 /A P1 /A P1 /A
7 6 5 4 3 2 1 0
Port 1
7 6 5 4 3 2 1 0
7
6
1
0
P6 /LWR
P6 /HWR
P6 /RD
P6 /AS P6 /BACK P6 /BREQ
P6 /WAIT
6 5
4
3 2 1
0
RAM
16-bit integrated
timer unit
(ITU)
A/D converter
D/A converter
Port 6
Bus controller
Programmable
timing pattern
controller (TPC)
Port B
PP
*
Note: * V function is provided only for the flash memory version.
PP
5
1.3 Pin Description
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the H8/3048 Series.
Figure 1-2 Pin Arrangement (FP-100B or TFP-100B, Top View)
V TIOCA /TP /PB TIOCB /TP /PB
TIOCA /TP /PB
TIOCB /TP /PB TOCXA /TP /PB TOCXB /TP /PB
CS
7
/DREQ /TP /PB
ADTRG/DREQ /TP /PB
V /RESO
V TxD /P9 TxD /P9 RxD /P9 RxD /P9
IRQ /SCK /P9 IRQ /SCK /P9
D /P4 D /P4 D /P4 D /P4
V
D /P4 D /P4 D /P4
MD MD MD P6 /LWR P6 /HWR P6 /RD P6 /AS V XTAL EXTAL V NMI RES STBY ø P6 /BACK P6 /BREQ P6 /WAIT V P5 /A P5 /A P5 /A P5 /A P2 /A P2 /A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CC
0 1 2 3 4 5 6 7
SS
0 1 2 3 4 5 0 1 2 3
SS
4 5 6
8
9 10 11 12 13 14 15
0 1
0 1 0 1 0 1 0 1 2 3
4 5 6
4 5
2 1 0
2 1 0
3 2 1 0 7 6
PA /TP /TIOCB /A
PA /TP /TIOCA /A /CS4PA /TP /TIOCB /A /CS5PA /TP /TIOCA /A /CS6PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TEND /TCLKB
PA /TP /TEND /TCLKA
V
P8 /CS
P8 /CS /IRQ
P8 /CS /IRQ
P8 /CS /IRQ
P8 /RFSH/IRQ
7654321
0
AV
P7 /AN /DA
P7 /AN /DA
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /ANVAV
43210
7654321
0
7654321
0
012
3
1
0
321
7654321
0
D /P4
D /P3
D /P3
D /P3
D /P3
D /P3
D /P3
D /P3
D /P3
V
A /P1
A /P1
A /P1
A /P1
A /P1
A /P1
A /P1
A /P1
V
A /P2
A /P2
A /P2
A /P2
A /P2
A /P2
789
701234567CC0123456
7SS01234
5
Top view
(FP-100B, TFP-100B)
26272829303132333435363738394041424344454647484950
1011121314
15
0123456
7
8
9
101112
13
6 5 4 3
CC
SS
SS
19 18 17 16 15 14
100
9998979695949392919089888786858483828180797877
76
202122
23
SS
SS
REF
CC
0
1
0
3 3 4 4 4 4
22110
0
PP
*
Note: * V function is provided only for the flash memory version.
PP
6
1.3.2 Pin Assignments in Each Mode
Table 1-2 lists the pin assignments in each mode.
Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B)
Pin Name
PROM Mode
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
EPROM Flash
1 2 3 4 5 6 7 8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Notes: 1. In modes 1, 3, 5, and 6 the P40to P47functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
2. In modes 2 and 4 the D
0
to D7functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
3. Pins marked NC should be left unconnected.
4. For details about PROM mode see section 18, ROM.
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/ CS
7
PB7/TP15/DREQ1/ ADTRG
RESO V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
1
P41/D
1
*
1
P42/D
2
*
1
P43/D
3
*
1
V
SS
P44/D
4
*
1
P45/D
5
*
1
P46/D
6
*
1
P47/D
7
*
1
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/ CS
7
PB7/TP15/DREQ1/ ADTRG
RESO V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
2
P41/D
1
*
2
P42/D
2
*
2
P43/D
3
*
2
V
SS
P44/D
4
*
2
P45/D
5
*
2
P46/D
6
*
2
P47/D
7
*
2
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/ CS
7
PB7/TP15/DREQ1/ ADTRG
RESO V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
1
P41/D
1
*
1
P42/D
2
*
1
P43/D
3
*
1
V
SS
P44/D
4
*
1
P45/D
5
*
1
P46/D
6
*
1
P47/D
7
*
1
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/ CS
7
PB7/TP15/DREQ1/ ADTRG
RESO V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
2
P41/D
1
*
2
P42/D
2
*
2
P43/D
3
*
2
V
SS
P44/D
4
*
2
P45/D
5
*
2
P46/D
6
*
2
P47/D
7
*
2
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/ CS
7
PB7/TP15/DREQ1/ ADTRG
RESO V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
1
P41/D
1
*
1
P42/D
2
*
1
P43/D
3
*
1
V
SS
P44/D
4
*
1
P45/D
5
*
1
P46/D
6
*
1
P47/D
7
*
1
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/ CS
7
PB7/TP15/DREQ1/ ADTRG
RESO V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
1
P41/D
1
*
1
P42/D
2
*
1
P43/D
3
*
1
V
SS
P44/D
4
*
1
P45/D
5
*
1
P46/D
6
*
1
P47/D
7
*
1
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ
0
PB7/TP15/DREQ1/ ADTRG
RESO V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P4
0
P4
1
P4
2
P4
3
V
SS
P4
4
P4
5
P4
6
P4
7
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P3
6
VCCV
CC
NC NC NC NC NC NC NC NC NC NC NC NC NC NC
NC NC
VPPV
PP
VSSV
SS
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSSV
SS
NC NC NC NC NC NC NC NC EO0I/O
0
EO1I/O
1
EO2I/O
2
EO3I/O
3
EO4I/O
4
EO5I/O
5
EO6I/O
6
Pin No.
7
Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) (cont)
Pin Name
PROM Mode
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
EPROM Flash
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Notes: 1. In modes 1, 3, 5, and 6 the P40to P47functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
2. In modes 2 and 4 the D
0
to D7functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
3. Pins marked NC should be left unconnected.
4. For details about PROM mode see section 18, ROM.
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI V
SS
EXTAL XTAL V
CC
AS RD
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI V
SS
EXTAL XTAL V
CC
AS RD
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI V
SS
EXTAL XTAL V
CC
AS RD
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI V
SS
EXTAL XTAL V
CC
AS RD
D
15
V
CC
P10/A
0
P11/A
1
P12/A
2
P13/A
3
P14/A
4
P15/A
5
P16/A
6
P17/A
7
V
SS
P20/A
8
P21/A
9
P22/A
10
P23/A
11
P24/A
12
P25/A
13
P26/A
14
P27/A
15
P50/A
16
P51/A
17
P52/A
18
P53/A
19
V
SS
P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI V
SS
EXTAL XTAL V
CC
AS RD
D
15
V
CC
P10/A
0
P11/A
1
P12/A
2
P13/A
3
P14/A
4
P15/A
5
P16/A
6
P17/A
7
V
SS
P20/A
8
P21/A
9
P22/A
10
P23/A
11
P24/A
12
P25/A
13
P26/A
14
P27/A
15
P50/A
16
P51/A
17
P52/A
18
P53/A
19
V
SS
P60/WAIT P61/BREQ P62/BACK ø STBY RES NMI V
SS
EXTAL XTAL V
CC
AS RD
P3
7
V
CC
P1
0
P1
1
P1
2
P1
3
P1
4
P1
5
P1
6
P1
7
V
SS
P2
0
P2
1
P2
2
P2
3
P2
4
P2
5
P2
6
P2
7
P5
0
P5
1
P5
2
P5
3
V
SS
P6
0
P6
1
P6
2
ø STBY RES NMI V
SS
EXTAL XTAL V
CC
P6
3
P6
4
EO7I/O
7
VCCV
CC
EA0A
0
EA1A
1
EA2A
2
EA3A
3
EA4A
4
EA5A
5
EA6A
6
EA7A
7
VSSV
SS
EA8A
8
OE OE EA10A
10
EA11A
11
EA12A
12
EA13A
13
EA14A
14
CE CE VCCV
CC
VCCV
CC
NC NC NC NC VSSV
SS
EA15A
15
NC NC NC NC NC NC VSSV
CC
NC RES EA9A
9
VSSV
SS
NC
EXTAL NC XTAL VCCV
CC
NC A
16
NC NC
Pin No.
8
Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) (cont)
Pin Name
PROM Mode
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
EPROM Flash
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93
94
95
96
97
98
99
100 Notes: 1. In modes 1, 3, 5, and 6 the P40to P47functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
2. In modes 2 and 4 the D
0
to D7functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
3. Pins marked NC should be left unconnected.
4. For details about PROM mode see section 18, ROM.
NC V
CC
NC NC VSSV
SS
VSSV
SS
VSSV
SS
VCCV
CC
VCCV
CC
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSSV
SS
EA16NC PGM NC NC V
CC
NC WE NC NC VSSV
SS
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
Pin No.
9
HWR LWR MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/ TCLKA
PA1/TP1/TEND1/ TCLKB
PA2/TP2/TIOCA0/ TCLKC
PA3/TP3/TIOCB0/ TCLKD
PA4/TP4/TIOCA1/ CS
6
PA5/TP5/TIOCB1/ CS
5
PA6/TP6/TIOCA2/ CS
4
PA7/TP7/TIOCB
2
HWR LWR MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/ TCLKA
PA1/TP1/TEND1/ TCLKB
PA2/TP2/TIOCA0/ TCLKC
PA3/TP3/TIOCB0/ TCLKD
PA4/TP4/TIOCA1/ CS
6
PA5/TP5/TIOCB1/ CS
5
PA6/TP6/TIOCA2/ CS
4
PA7/TP7/TIOCB
2
HWR LWR MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/ TCLKA
PA1/TP1/TEND1/ TCLKB
PA2/TP2/TIOCA0/ TCLKC
PA3/TP3/TIOCB0/ TCLKD
PA4/TP4/TIOCA1/ CS
6
PA5/TP5/TIOCB1/ CS
5
PA6/TP6/TIOCA2/ CS
4
A
20
HWR LWR MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/ TCLKA
PA1/TP1/TEND1/ TCLKB
PA2/TP2/TIOCA0/ TCLKC
PA3/TP3/TIOCB0/ TCLKD
PA4/TP4/TIOCA1/ CS
6
PA5/TP5/TIOCB1/ CS
5
PA6/TP6/TIOCA2/ CS
4
A
20
HWR LWR MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/ TCLKA
PA1/TP1/TEND1/ TCLKB
PA2/TP2/TIOCA0/ TCLKC
PA3/TP3/TIOCB0/ TCLKD
PA4/TP4/TIOCA1/ CS
6
PA5/TP5/TIOCB1/ CS
5
PA6/TP6/TIOCA2/ CS
4
PA7/TP7/TIOCB
2
HWR LWR MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/ TCLKA
PA1/TP1/TEND1/ TCLKB
PA2/TP2/TIOCA0/ TCLKC
PA3/TP3/TIOCB0/ TCLKD
PA4/TP4/TIOCA1/ A23/CS
6
PA5/TP5/TIOCB1/ A22/CS
5
PA6/TP6/TIOCA2/ A21/CS
4
A
20
P6
5
P6
6
MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/IRQ
0
P81/IRQ
1
P82/IRQ
2
P83/IRQ
3
P8
4
V
SS
PA0/TP0/TEND0/ TCLKA
PA1/TP1/TEND1/ TCLKB
PA2/TP2/TIOCA0/ TCLKC
PA3/TP3/TIOCB0/ TCLKD
PA4/TP4/TIOCA
1
PA5/TP5/TIOCB
1
PA6/TP6/TIOCA
2
PA7/TP7/TIOCB
2
1.3.3 Pin Functions
Table 1-3 summarizes the pin functions.
Table 1-3 Pin Functions
Type Symbol Pin No. I/O Name and Function
Power V
CC
1, 35, 68 Input Power: For connection to the power supply.
Connect all V
CC
pins to the system power
supply.
V
SS
11, 22, 44, Input Ground: For connection to ground (0 V). 57, 65, 92 Connect all V
SS
pins to the 0-V system power
supply.
Clock XTAL 67 Input For connection to a crystal resonator.
For examples of crystal resonator and external clock input, see section 19, Clock Pulse Generator.
EXTAL 66 Input For connection to a crystal resonator or input of
an external clock signal. For examples of crystal resonator and external clock input, see section 19, Clock Pulse Generator.
ø 61 Output System clock: Supplies the system clock to
external devices.
Operating MD
2
to MD075 to 73 Input Mode 2 to mode 0: For setting the operating
mode control mode, as follows. Inputs at these pins must not
be changed during operation.
MD
2
MD
1
MD
0
Operating Mode
000— 0 0 1 Mode 1 0 1 0 Mode 2 0 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 1 1 0 Mode 6 1 1 1 Mode 7
10
Table 1-3 Pin Functions (cont)
Type Symbol Pin No. I/O Name and Function
System control RES 63 Input Reset input: When driven low, this pin resets
the chip
RESO 10 Output Reset output: Outputs a reset signal to
external devices
(RESO/V
PP
) Also used as a power supply for on-board
programming of the flash memory version.
STBY 62 Input Standby: When driven low, this pin forces
a transition to hardware standby mode
BREQ 59 Input Bus request: Used by an external bus master
to request the bus right
BACK 60 Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus master
Interrupts NMI 64 Input Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ
5
to 17, 16, Input Interrupt request 5 to 0: Maskable interrupt
IRQ
0
90 to 87 request pins
Address bus A
23
to A
0
97 to 100, Output Address bus: Outputs address signals 56 to 45, 43 to 36
Data bus D
15
to D034 to 23, Input/ Data bus: Bidirectional data bus
21 to 18 output
Bus control CS7to CS08, 97 to 99, Output Chip select: Select signals for areas 7 to 0
88 to 91
AS 69 Output Address strobe: Goes low to indicate valid
address output on the address bus
RD 70 Output Read: Goes low to indicate reading from the
external address space
HWR 71 Output High write: Goes low to indicate writing to the
external address space; indicates valid data on the upper data bus (D
15
to D8).
LWR 72 Output Low write: Goes low to indicate writing to the
external address space; indicates valid data on the lower data bus (D
7
to D0).
WAIT 58 Input Wait: Requests insertion of wait states in bus
cycles during access to the external address space
11
Table 1-3 Pin Functions (cont)
Type Symbol Pin No. I/O Name and Function
Refresh
RFSH 87 Output Refresh: Indicates a refresh cycle
controller
CS
3
88 Output Row address strobe RAS: Row address
strobe signal for DRAM connected to area 3
RD 70 Output Column address strobe CAS: Column
address
strobe signal for DRAM connected to
area
3; used with 2WE DRAM.
Write enable WE: Write enable signal for DRAM connected to area 3; used with 2CAS DRAM.
HWR 71 Output Upper write UW: Write enable signal for
DRAM connected to area 3; used with 2WE DRAM.
Upper column address strobe UCAS:
Column address strobe signal for DRAM connected to area 3; used with 2CAS DRAM.
LWR 72 Output Lower write LW: Write enable signal for DRAM
connected to area 3; used with 2WE DRAM.
Lower column address strobe LCAS:
Column address strobe signal for DRAM connected to area 3; used with 2CAS DRAM.
DREQ
1
, 9, 8 Input DMA request 1 and 0: DMAC activation
DREQ
0
requests
TEND
1
, 94, 93 Output Transfer end 1 and 0: These signals indicate
TEND
0
that the DMAC has ended a data transfer
TCLKD to 96 to 93 Input Clock input D to A: External clock inputs TCLKA
TIOCA
4
to 4, 2, 99, Input/ Input capture/output compare A4 to A0:
TIOCA
0
97, 95 output GRA4 to GRA0 output compare or input
capture, or PWM output
TIOCB4 to 5, 3, 100, Input/ Input capture/output compare B4 to B0: TIOCB
0
98, 96 output GRB4 to GRB0 output compare or input
capture, or PWM output
TOCXA
4
6 Output Output compare XA4: PWM output
TOCXB
4
7 Output Output compare XB4: PWM output
DMA controller (DMAC)
16-bit integrated timer unit (ITU)
12
Table 1-3 Pin Functions (cont)
Type Symbol Pin No. I/O Name and Function
Programmable TP
15
to 9 to 2, Output TPC output 15 to 0: Pulse output
timing pattern TP
0
100 to 93
controller (TPC)
TxD1, 13, 12 Output Transmit data (channels 0 and 1): SCI data TxD
0
output
RxD
1
, 15, 14 Input Receive data (channels 0 and 1): SCI data
RxD
0
input
SCK
1
, 17, 16 Input/ Serial clock (channels 0 and 1): SCI clock
SCK
0
output input/output
A/D converter AN
7
to AN085 to 78 Input Analog 7 to 0: Analog input pins
ADTRG 9 Input A/D trigger: External trigger input for starting
A/D conversion
D/A converter DA
1
, DA085, 84 Output Analog output: Analog output from the
D/A converter
A/D and D/A AV
CC
76 Input Power supply pin for the A/D and
converters D/A converters. Connect to the system power
supply (+5 V) when not using the A/D and D/A converters.
AV
SS
86 Input Ground pin for the A/D and D/A converters.
Connect to system ground (0 V).
V
REF
77 Input Reference voltage input pin for the A/D and
D/A converters. Connect to the system power supply (+5 V) when not using the A/D and D/A converters.
I/O ports P1
7
to P1043 to 36 Input/ Port 1: Eight input/output pins. The direction of
output each pin can be selected in the port 1 data
direction register (P1DDR).
P2
7
to P2052 to 45 Input/ Port 2: Eight input/output pins. The direction of
output each pin can be selected in the port 2 data
direction register (P2DDR).
P3
7
to P3034 to 27 Input/ Port 3: Eight input/output pins. The direction of
output each pin can be selected in the port 3 data
direction register (P3DDR).
P4
7
to P4026 to 23, Input/ Port 4: Eight input/output pins. The
21 to 18 output direction of each pin can be selected in the port
4 data direction register (P4DDR).
Serial com­munication interface (SCI)
13
Table 1-3 Pin Functions (cont)
Type Symbol Pin No. I/O Name and Function
I/O ports P5
3
to P5056 to 53 Input/ Port 5: Four input/output pins. The direction of
output each pin can be selected in the port 5 data
direction register (P5DDR).
P6
6
to P6072 to 69, Input/ Port 6: Seven input/output pins. The direction
60 to 58 output of each pin can be selected in the port 6 data
direction register (P6DDR).
P7
7
to P7085 to 78 Input Port 7: Eight input pins
P8
4
to P8091 to 87 Input/ Port 8: Five input/output pins. The direction of
output each pin can be selected in the port 8 data
direction register (P8DDR).
P9
5
to P9017 to 12 Input/ Port 9: Six input/output pins. The direction of
output each pin can be selected in the port 9 data
direction register (P9DDR).
PA
7
to PA0100 to 93 Input/ Port A: Eight input/output pins. The direction of
output each pin can be selected in the port A data
direction register (PADDR).
PB
7
to PB09 to 2 Input/ Port B: Eight input/output pins. The direction of
output each pin can be selected in the port B data
direction register (PBDDR).
14
Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1 Features
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-two basic instructions
— 8/16/32-bit data transfer and arithmetic and logic instructions — Multiply and divide instructions — Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct [Rn] — Register indirect [@ERn] — Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)] — Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] — Absolute address [@aa:8, @aa:16, or @aa:24] — Immediate [#xx:8, #xx:16, or #xx:32] — Program-counter relative [@(d:8, PC) or @(d:16, PC)] — Memory indirect [@@aa:8]
• 16-Mbyte linear address space
15
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