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Hitachi Single-Chip Microcomputer
H8/3048 Series
H8/3048
HD64F3048, HD6473048, HD6433048
H8/3047
HD6433047
H8/3045
HD6433045
H8/3044
HD6433044
Hardware Manual
ADE-602-073B
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查询64F3048F16供应商
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Preface
The H8/3048 Series is a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller
(DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been
expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to
reduce power consumption in battery-powered applications: individual modules can be placed in
standby, and the frequency of the system clock supplied to the chip can be divided down under
software control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.
With these features, the H8/3048 Series can be used to implement compact, high-performance
systems easily.
In addition to its masked-ROM versions, the H8/3048 Series has a ZTAT™*1version with userprogrammable on-chip PROM and an F-ZTAT™*2version with on-chip flash memory that can be
programmed on-board. These versions enable users to respond quickly and flexibly to changing
application specifications.
This manual describes the H8/3048 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Notes: 1. ZTAT™ (Zero Turn-Around-time) is a trademark of Hitachi, Ltd.
2. F-ZTAT™ (Flexible ZTAT) is a trademark of Hitachi, Ltd.
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Contents
Section 1 Overview...................................................................................................... 1
1.1 Overview......................................................................................................................... 1
1.2 Block Diagram................................................................................................................5
1.3 Pin Description ............................................................................................................... 6
1.3.1 Pin Arrangement............................................................................................. 6
1.3.2 Pin Assignments in Each Mode...................................................................... 7
1.3.3 Pin Functions.................................................................................................. 10
Section 2 CPU............................................................................................................... 15
2.1 Overview......................................................................................................................... 15
2.1.1 Features........................................................................................................... 15
2.1.2 Differences from H8/300 CPU....................................................................... 16
2.2 CPU Operating Modes.................................................................................................... 17
2.3 Address Space................................................................................................................. 18
2.4 Register Configuration.................................................................................................... 19
2.4.1 Overview......................................................................................................... 19
2.4.2 General Registers............................................................................................ 20
2.4.3 Control Registers............................................................................................ 21
2.4.4 Initial CPU Register Values............................................................................ 22
2.5 Data Formats................................................................................................................... 23
2.5.1 General Register Data Formats....................................................................... 23
2.5.2 Memory Data Formats.................................................................................... 25
2.6 Instruction Set................................................................................................................. 26
2.6.1 Instruction Set Overview................................................................................ 26
2.6.2 Instructions and Addressing Modes................................................................ 27
2.6.3 Tables of Instructions Classified by Function................................................. 28
2.6.4 Basic Instruction Formats............................................................................... 38
2.6.5 Notes on Use of Bit Manipulation Instructions.............................................. 39
2.7 Addressing Modes and Effective Address Calculation.................................................. 39
2.7.1 Addressing Modes.......................................................................................... 39
2.7.2 Effective Address Calculation........................................................................ 42
2.8 Processing States ............................................................................................................46
2.8.1 Overview......................................................................................................... 46
2.8.2 Program Execution State ................................................................................ 47
2.8.3 Exception-Handling State............................................................................... 47
2.8.4 Exception-Handling Sequences...................................................................... 49
2.8.5 Bus-Released State ......................................................................................... 50
2.8.6 Reset State ...................................................................................................... 50
2.8.7 Power-Down State .......................................................................................... 50
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2.9 Basic Operational Timing............................................................................................... 51
2.9.1 Overview......................................................................................................... 51
2.9.2 On-Chip Memory Access Timing................................................................... 51
2.9.3 On-Chip Supporting Module Access Timing................................................. 53
2.9.4 Access to External Address Space.................................................................. 54
Section 3 MCU Operating Modes........................................................................... 55
3.1 Overview......................................................................................................................... 55
3.1.1 Operating Mode Selection.............................................................................. 55
3.1.2 Register Configuration.................................................................................... 56
3.2 Mode Control Register (MDCR).................................................................................... 57
3.3 System Control Register (SYSCR)................................................................................. 58
3.4 Operating Mode Descriptions......................................................................................... 60
3.4.1 Mode 1............................................................................................................ 60
3.4.2 Mode 2............................................................................................................ 60
3.4.3 Mode 3............................................................................................................ 60
3.4.4 Mode 4............................................................................................................ 60
3.4.5 Mode 5............................................................................................................ 60
3.4.6 Mode 6 ........................................................................................................... 60
3.4.7 Mode 7 ........................................................................................................... 61
3.5 Pin Functions in Each Operating Mode.......................................................................... 61
3.6 Memory Map in Each Operating Mode.......................................................................... 61
Section 4 Exception Handling.................................................................................. 71
4.1 Overview......................................................................................................................... 71
4.1.1 Exception Handling Types and Priority.......................................................... 71
4.1.2 Exception Handling Operation....................................................................... 71
4.1.3 Exception Vector Table................................................................................... 72
4.2 Reset ............................................................................................................................... 73
4.2.1 Overview......................................................................................................... 73
4.2.2 Reset Sequence............................................................................................... 73
4.2.3 Interrupts after Reset....................................................................................... 76
4.3 Interrupts......................................................................................................................... 77
4.4 Trap Instruction............................................................................................................... 78
4.5 Stack Status after Exception Handling........................................................................... 79
4.6 Notes on Stack Usage..................................................................................................... 80
Section 5 Interrupt Controller................................................................................... 81
5.1 Overview......................................................................................................................... 81
5.1.1 Features........................................................................................................... 81
5.1.2 Block Diagram................................................................................................ 82
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5.1.3 Pin Configuration............................................................................................ 83
5.1.4 Register Configuration.................................................................................... 83
5.2 Register Descriptions...................................................................................................... 84
5.2.1 System Control Register (SYSCR)................................................................. 84
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)....................................... 85
5.2.3 IRQ Status Register (ISR) .............................................................................. 92
5.2.4 IRQ Enable Register (IER)............................................................................. 93
5.2.5 IRQ Sense Control Register (ISCR)............................................................... 94
5.3 Interrupt Sources............................................................................................................. 95
5.3.1 External Interrupts.......................................................................................... 95
5.3.2 Internal Interrupts ........................................................................................... 96
5.3.3 Interrupt Vector Table..................................................................................... 96
5.4 Interrupt Operation ......................................................................................................... 100
5.4.1 Interrupt Handling Process............................................................................. 100
5.4.2 Interrupt Sequence.......................................................................................... 105
5.4.3 Interrupt Response Time................................................................................. 106
5.5 Usage Notes.................................................................................................................... 107
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction................ 107
5.5.2 Instructions that Inhibit Interrupts.................................................................. 108
5.5.3 Interrupts during EEPMOV Instruction Execution......................................... 108
5.5.4 Notes on External Interrup to during Use....................................................... 108
Section 6 Bus Controller............................................................................................ 111
6.1 Overview......................................................................................................................... 111
6.1.1 Features........................................................................................................... 111
6.1.2 Block Diagram................................................................................................ 112
6.1.3 Input/Output Pins............................................................................................ 113
6.1.4 Register Configuration.................................................................................... 113
6.2 Register Descriptions...................................................................................................... 114
6.2.1 Bus Width Control Register (ABWCR)......................................................... 114
6.2.2 Access State Control Register (ASTCR)........................................................ 115
6.2.3 Wait Control Register (WCR)......................................................................... 116
6.2.4 Wait State Controller Enable Register (WCER)............................................. 117
6.2.5 Bus Release Control Register (BRCR)........................................................... 118
6.2.6 Chip Select Control Register (CSCR) ............................................................ 119
6.3 Operation ........................................................................................................................ 121
6.3.1 Area Division.................................................................................................. 121
6.3.2 Chip Select Signals......................................................................................... 123
6.3.3 Data Bus.......................................................................................................... 124
6.3.4 Bus Control Signal Timing............................................................................. 125
6.3.5 Wait Modes..................................................................................................... 133
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6.3.6 Interconnections with Memory (Example)..................................................... 139
6.3.7 Bus Arbiter Operation..................................................................................... 141
6.4 Usage Notes.................................................................................................................... 144
6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM................................ 144
6.4.2 Register Write Timing.................................................................................... 144
6.4.3 BREQ Input Timing........................................................................................ 144
6.4.4 Transition to Software Standby Mode............................................................ 146
Section 7 Refresh Controller .................................................................................... 147
7.1 Overview......................................................................................................................... 147
7.1.1 Features........................................................................................................... 147
7.1.2 Block Diagram................................................................................................ 148
7.1.3 Input/Output Pins............................................................................................ 149
7.1.4 Register Configuration.................................................................................... 149
7.2 Register Descriptions...................................................................................................... 150
7.2.1 Refresh Control Register (RFSHCR) ............................................................. 150
7.2.2 Refresh Timer Control/Status Register (RTMCSR)....................................... 153
7.2.3 Refresh Timer Counter (RTCNT)................................................................... 155
7.2.4 Refresh Time Constant Register (RTCOR) .................................................... 155
7.3 Operation ........................................................................................................................ 156
7.3.1 Overview......................................................................................................... 156
7.3.2 DRAM Refresh Control.................................................................................. 157
7.3.3 Pseudo-Static RAM Refresh Control.............................................................. 172
7.3.4 Interval Timing............................................................................................... 177
7.4 Interrupt Source.............................................................................................................. 183
7.5 Usage Notes.................................................................................................................... 183
Section 8 DMA Controller........................................................................................ 185
8.1 Overview......................................................................................................................... 185
8.1.1 Features........................................................................................................... 185
8.1.2 Block Diagram................................................................................................ 186
8.1.3 Functional Overview....................................................................................... 187
8.1.4 Input/Output Pins............................................................................................ 188
8.1.5 Register Configuration.................................................................................... 188
8.2 Register Descriptions (Short Address Mode)................................................................. 190
8.2.1 Memory Address Registers (MAR)................................................................ 190
8.2.2 I/O Address Registers (IOAR)........................................................................ 191
8.2.3 Execute Transfer Count Registers (ETCR)..................................................... 191
8.2.4 Data Transfer Control Registers (DTCR)....................................................... 193
8.3 Register Descriptions (Full Address Mode)................................................................... 196
8.3.1 Memory Address Registers (MAR)................................................................ 196
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8.3.2 I/O Address Registers (IOAR)........................................................................ 196
8.3.3 Execute Transfer Count Registers (ETCR)..................................................... 197
8.3.4 Data Transfer Control Registers (DTCR)....................................................... 199
8.4 Operation ........................................................................................................................ 205
8.4.1 Overview......................................................................................................... 205
8.4.2 I/O Mode......................................................................................................... 207
8.4.3 Idle Mode........................................................................................................ 209
8.4.4 Repeat Mode................................................................................................... 212
8.4.5 Normal Mode.................................................................................................. 215
8.4.6 Block Transfer Mode...................................................................................... 218
8.4.7 DMAC Activation........................................................................................... 223
8.4.8 DMAC Bus Cycle........................................................................................... 225
8.4.9 Multiple-Channel Operation........................................................................... 231
8.4.10 External Bus Requests, Refresh Controller, and DMAC................................ 232
8.4.11 NMI Interrupts and DMAC............................................................................ 233
8.4.12 Aborting a DMA Transfer.............................................................................. 234
8.4.13 Exiting Full Address Mode............................................................................. 235
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.................... 236
8.5 Interrupts......................................................................................................................... 237
8.6 Usage Notes.................................................................................................................... 238
8.6.1 Note on Word Data Transfer........................................................................... 238
8.6.2 DMAC Self-Access........................................................................................ 238
8.6.3 Longword Access to Memory Address Registers........................................... 238
8.6.4 Note on Full Address Mode Setup.................................................................. 238
8.6.5 Note on Activating DMAC by Internal Interrupts.......................................... 239
8.6.6 NMI Interrupts and Block Transfer Mode...................................................... 240
8.6.7 Memory and I/O Address Register Values ..................................................... 240
8.6.8 Bus Cycle when Transfer is Aborted.............................................................. 241
Section 9 I/O Ports....................................................................................................... 243
9.1 Overview......................................................................................................................... 243
9.2 Port 1............................................................................................................................... 246
9.2.1 Overview......................................................................................................... 246
9.2.2 Register Descriptions...................................................................................... 247
9.3 Port 2............................................................................................................................... 249
9.3.1 Overview......................................................................................................... 249
9.3.2 Register Descriptions...................................................................................... 250
9.4 Port 3............................................................................................................................... 253
9.4.1 Overview......................................................................................................... 253
9.4.2 Register Descriptions...................................................................................... 253
9.5 Port 4............................................................................................................................... 255
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9.5.1 Overview......................................................................................................... 255
9.5.2 Register Descriptions...................................................................................... 256
9.6 Port 5............................................................................................................................... 259
9.6.1 Overview......................................................................................................... 259
9.6.2 Register Descriptions...................................................................................... 259
9.7 Port 6............................................................................................................................... 262
9.7.1 Overview......................................................................................................... 262
9.7.2 Register Descriptions...................................................................................... 262
9.8 Port 7............................................................................................................................... 265
9.8.1 Overview......................................................................................................... 265
9.8.2 Register Description ....................................................................................... 266
9.9 Port 8............................................................................................................................... 267
9.9.1 Overview......................................................................................................... 267
9.9.2 Register Descriptions...................................................................................... 268
9.10 Port 9............................................................................................................................... 272
9.10.1 Overview......................................................................................................... 272
9.10.2 Register Descriptions...................................................................................... 272
9.11 Port A.............................................................................................................................. 276
9.11.1 Overview......................................................................................................... 276
9.11.2 Register Descriptions...................................................................................... 278
9.11.3 Pin Functions.................................................................................................. 279
9.12 Port B.............................................................................................................................. 284
9.12.1 Overview......................................................................................................... 284
9.12.2 Register Descriptions...................................................................................... 286
9.12.3 Pin Functions.................................................................................................. 288
Section 10 16-Bit Integrated Timer Unit (ITU)..................................................... 295
10.1 Overview......................................................................................................................... 295
10.1.1 Features........................................................................................................... 295
10.1.2 Block Diagrams.............................................................................................. 298
10.1.3 Input/Output Pins............................................................................................ 303
10.1.4 Register Configuration.................................................................................... 304
10.2 Register Descriptions...................................................................................................... 307
10.2.1 Timer Start Register (TSTR).......................................................................... 307
10.2.2 Timer Synchro Register (TSNC).................................................................... 308
10.2.3 Timer Mode Register (TMDR)....................................................................... 310
10.2.4 Timer Function Control Register (TFCR)...................................................... 313
10.2.5 Timer Output Master Enable Register (TOER).............................................. 315
10.2.6 Timer Output Control Register (TOCR)......................................................... 318
10.2.7 Timer Counters (TCNT)................................................................................. 319
10.2.8 General Registers (GRA, GRB) ..................................................................... 320
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10.2.9 Buffer Registers (BRA, BRB)........................................................................ 321
10.2.10 Timer Control Registers (TCR)...................................................................... 322
10.2.11 Timer I/O Control Register (TIOR)................................................................ 324
10.2.12 Timer Status Register (TSR)........................................................................... 326
10.2.13 Timer Interrupt Enable Register (TIER)......................................................... 329
10.3 CPU Interface ................................................................................................................. 331
10.3.1 16-Bit Accessible Registers............................................................................ 331
10.3.2 8-Bit Accessible Registers.............................................................................. 333
10.4 Operation ........................................................................................................................ 335
10.4.1 Overview......................................................................................................... 335
10.4.2 Basic Functions............................................................................................... 336
10.4.3 Synchronization.............................................................................................. 346
10.4.4 PWM Mode .................................................................................................... 348
10.4.5 Reset-Synchronized PWM Mode................................................................... 352
10.4.6 Complementary PWM Mode.......................................................................... 355
10.4.7 Phase Counting Mode..................................................................................... 365
10.4.8 Buffering......................................................................................................... 367
10.4.9 ITU Output Timing......................................................................................... 374
10.5 Interrupts......................................................................................................................... 376
10.5.1 Setting of Status Flags.................................................................................... 376
10.5.2 Clearing of Status Flags.................................................................................. 378
10.5.3 Interrupt Sources and DMA Controller Activation........................................ 379
10.6 Usage Notes.................................................................................................................... 380
Section 11 Programmable Timing Pattern Controller......................................... 395
11.1 Overview......................................................................................................................... 395
11.1.1 Features........................................................................................................... 395
11.1.2 Block Diagram................................................................................................ 396
11.1.3 TPC Pins......................................................................................................... 397
11.1.4 Registers ......................................................................................................... 398
11.2 Register Descriptions...................................................................................................... 399
11.2.1 Port A Data Direction Register (PADDR)...................................................... 399
11.2.2 Port A Data Register (PADR)......................................................................... 399
11.2.3 Port B Data Direction Register (PBDDR)...................................................... 400
11.2.4 Port B Data Register (PBDR)......................................................................... 400
11.2.5 Next Data Register A (NDRA)....................................................................... 401
11.2.6 Next Data Register B (NDRB)....................................................................... 403
11.2.7 Next Data Enable Register A (NDERA)........................................................ 405
11.2.8 Next Data Enable Register B (NDERB)......................................................... 406
11.2.9 TPC Output Control Register (TPCR)............................................................ 407
11.2.10 TPC Output Mode Register (TPMR).............................................................. 410
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11.3 Operation ........................................................................................................................... 412
11.3.1 Overview......................................................................................................... 412
11.3.2 Output Timing................................................................................................. 413
11.3.3 Normal TPC Output........................................................................................ 414
11.3.4 Non-Overlapping TPC Output........................................................................ 416
11.3.5 TPC Output Triggering by Input Capture....................................................... 418
11.4 Usage Notes.................................................................................................................... 419
11.4.1 Operation of TPC Output Pins........................................................................ 419
11.4.2 Note on Non-Overlapping Output.................................................................. 419
Section 12 Watchdog Timer........................................................................................ 421
12.1 Overview......................................................................................................................... 421
12.1.1 Features........................................................................................................... 421
12.1.2 Block Diagram................................................................................................ 422
12.1.3 Pin Configuration............................................................................................ 422
12.1.4 Register Configuration.................................................................................... 423
12.2 Register Descriptions...................................................................................................... 424
12.2.1 Timer Counter (TCNT)................................................................................... 424
12.2.2 Timer Control/Status Register (TCSR)........................................................... 425
12.2.3 Reset Control/Status Register (RSTCSR) ...................................................... 427
12.2.4 Notes on Register Access ............................................................................... 429
12.3 Operation ........................................................................................................................ 431
12.3.1 Watchdog Timer Operation............................................................................. 431
12.3.2 Interval Timer Operation................................................................................ 432
12.3.3 Timing of Setting of Overflow Flag (OVF).................................................... 433
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)............................. 434
12.4 Interrupts......................................................................................................................... 435
12.5 Usage Notes.................................................................................................................... 435
Section 13 Serial Communication Interface........................................................... 437
13.1 Overview......................................................................................................................... 437
13.1.1 Features........................................................................................................... 437
13.1.2 Block Diagram................................................................................................ 439
13.1.3 Input/Output Pins............................................................................................ 440
13.1.4 Register Configuration.................................................................................... 440
13.2 Register Descriptions...................................................................................................... 441
13.2.1 Receive Shift Register (RSR)......................................................................... 441
13.2.2 Receive Data Register (RDR)......................................................................... 441
13.2.3 Transmit Shift Register (TSR)........................................................................ 442
13.2.4 Transmit Data Register (TDR)........................................................................ 442
13.2.5 Serial Mode Register (SMR).......................................................................... 443
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13.2.6 Serial Control Register (SCR)........................................................................ 447
13.2.7 Serial Status Register (SSR)........................................................................... 451
13.2.8 Bit Rate Register (BRR)................................................................................. 455
13.3 Operation ........................................................................................................................ 464
13.3.1 Overview......................................................................................................... 464
13.3.2 Operation in Asynchronous Mode.................................................................. 466
13.3.3 Multiprocessor Communication ..................................................................... 475
13.3.4 Synchronous Operation .................................................................................. 482
13.4 SCI Interrupts.................................................................................................................. 491
13.5 Usage Notes.................................................................................................................... 492
Section 14 Smart Card Interface................................................................................ 497
14.1 Overview......................................................................................................................... 497
14.1.1 Features........................................................................................................... 497
14.1.2 Block Diagram................................................................................................ 498
14.1.3 Input/Output Pins............................................................................................ 499
14.1.4 Register Configuration.................................................................................... 499
14.2 Register Descriptions...................................................................................................... 500
14.2.1 Smart Card Mode Register (SCMR)............................................................... 500
14.2.2 Serial Status Register (SSR)........................................................................... 501
14.2.3 Serial Mode Register (SMR).......................................................................... 503
14.2.4 Serial Control Register (SCR)........................................................................ 504
14.3 Operation ........................................................................................................................ 505
14.3.1 Overview......................................................................................................... 505
14.3.2 Pin Connections.............................................................................................. 505
14.3.3 Data Format.................................................................................................... 506
14.3.4 Register Settings............................................................................................. 508
14.3.5 Clock............................................................................................................... 510
14.3.6 Transmitting and Receiving Data................................................................... 512
14.4 Usage Notes.................................................................................................................... 519
Section 15 A/D Converter............................................................................................ 523
15.1 Overview......................................................................................................................... 523
15.1.1 Features........................................................................................................... 523
15.1.2 Block Diagram................................................................................................ 524
15.1.3 Input Pins........................................................................................................ 525
15.1.4 Register Configuration.................................................................................... 526
15.2 Register Descriptions...................................................................................................... 527
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................ 527
15.2.2 A/D Control/Status Register (ADCSR).......................................................... 528
15.2.3 A/D Control Register (ADCR)....................................................................... 531
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15.3 CPU Interface ................................................................................................................. 532
15.4 Operation ........................................................................................................................ 533
15.4.1 Single Mode (SCAN = 0)............................................................................... 533
15.4.2 Scan Mode (SCAN = 1).................................................................................. 535
15.4.3 Input Sampling and A/D Conversion Time .................................................... 537
15.4.4 External Trigger Input Timing........................................................................ 538
15.5 Interrupts......................................................................................................................... 539
15.6 Usage Notes.................................................................................................................... 539
Section 16 D/A Converter............................................................................................ 545
16.1 Overview......................................................................................................................... 545
16.1.1 Features........................................................................................................... 545
16.1.2 Block Diagram................................................................................................ 545
16.1.3 Input/Output Pins............................................................................................ 546
16.1.4 Register Configuration.................................................................................... 546
16.2 Register Descriptions...................................................................................................... 547
16.2.1 D/A Data Registers 0 and 1 (DADR0/1)........................................................ 547
16.2.2 D/A Control Register (DACR) ....................................................................... 547
16.2.3 D/A Standby Control Register (DASTCR)..................................................... 549
16.3 Operation ........................................................................................................................ 550
16.4 D/A Output Control........................................................................................................ 551
16.5 Usage Notes.................................................................................................................... 551
Section 17 RAM............................................................................................................. 553
17.1 Overview......................................................................................................................... 553
17.1.1 Block Diagram................................................................................................ 553
17.1.2 Register Configuration.................................................................................... 554
17.2 System Control Register (SYSCR)................................................................................. 555
17.3 Operation ........................................................................................................................ 556
Section 18 ROM.............................................................................................................. 557
18.1 Overview......................................................................................................................... 557
18.1.1 Block Diagram................................................................................................ 558
18.2 PROM Mode................................................................................................................... 559
18.2.1 PROM Mode Setting ...................................................................................... 559
18.2.2 Socket Adapter and Memory Map.................................................................. 559
18.3 PROM Programming...................................................................................................... 562
18.3.1 Programming and Verification........................................................................ 562
18.3.2 Programming Precautions............................................................................... 567
18.3.3 Reliability of Programmed Data..................................................................... 568
18.4 Flash Memory Overview................................................................................................ 569
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18.4.1 Flash Memory Operation................................................................................ 569
18.4.2 Mode Programming and Flash Memory Address Space................................ 570
18.4.3 Features........................................................................................................... 570
18.4.4 Block Diagram................................................................................................ 572
18.4.5 Input/Output Pins............................................................................................ 573
18.4.6 Register Configuration.................................................................................... 573
18.5 Flash Memory Register Descriptions ............................................................................. 574
18.5.1 Flash Memory Control Register ..................................................................... 574
18.5.2 Erase Block Register 1.................................................................................... 577
18.5.3 Erase Block Register 2.................................................................................... 578
18.5.4 RAM Control Register (RAMCR).................................................................. 580
18.6 On-Board Programming Modes ..................................................................................... 582
18.6.1 Boot Mode...................................................................................................... 582
18.6.2 User Program Mode........................................................................................ 587
18.7 Programming and Erasing Flash Memory...................................................................... 589
18.7.1 Program Mode................................................................................................ 590
18.7.2 Program-Verify Mode..................................................................................... 590
18.7.3 Programming Flowchart and Sample Program............................................... 591
18.7.4 Erase Mode..................................................................................................... 593
18.7.5 Erase-Verify Mode.......................................................................................... 594
18.7.6 Erasing Flowchart and Sample Program ........................................................ 595
18.7.7 Prewrite-Verify Mode..................................................................................... 607
18.7.8 Protect Modes................................................................................................. 607
18.7.9 NMI Input Masking........................................................................................ 610
18.8 Flash Memory Emulation by RAM................................................................................ 611
18.9 PROM Mode................................................................................................................... 613
18.9.1 PROM Mode Setting ...................................................................................... 613
18.9.2 Socket Adapter and Memory Map.................................................................. 614
18.9.3 Operation in PROM Mode.............................................................................. 616
18.10 Flash Memory Programming and Erasing Precautions.................................................. 624
Section 19 Clock Pulse Generator............................................................................. 633
19.1 Overview......................................................................................................................... 633
19.1.1 Block Diagram................................................................................................ 633
19.2 Oscillator Circuit ............................................................................................................ 634
19.2.1 Connecting a Crystal Resonator ..................................................................... 634
19.2.2 External Clock Input....................................................................................... 636
19.3 Duty Adjustment Circuit................................................................................................. 639
19.4 Prescalers........................................................................................................................ 639
19.5 Frequency Divider.......................................................................................................... 639
19.5.1 Register Configuration.................................................................................... 639
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19.5.2 Division Control Register (DIVCR)............................................................... 639
19.5.3 Usage Notes.................................................................................................... 640
Section 20 Power-Down State.................................................................................... 641
20.1 Overview......................................................................................................................... 641
20.2 Register Configuration.................................................................................................... 643
20.2.1 System Control Register (SYSCR)................................................................. 643
20.2.2 Module Standby Control Register (MSTCR)................................................. 645
20.3 Sleep Mode..................................................................................................................... 647
20.3.1 Transition to Sleep Mode................................................................................ 647
20.3.2 Exit from Sleep Mode..................................................................................... 647
20.4 Software Standby Mode ................................................................................................. 648
20.4.1 Transition to Software Standby Mode............................................................ 648
20.4.2 Exit from Software Standby Mode................................................................. 648
20.4.3 Selection of Waiting Time for Exit from Software Standby Mode................ 649
20.4.4 Sample Application of Software Standby Mode............................................ 650
20.4.5 Note................................................................................................................. 650
20.5 Hardware Standby Mode................................................................................................ 651
20.5.1 Transition to Hardware Standby Mode........................................................... 651
20.5.2 Exit from Hardware Standby Mode................................................................ 651
20.5.3 Timing for Hardware Standby Mode.............................................................. 651
20.6 Module Standby Function............................................................................................... 652
20.6.1 Module Standby Timing................................................................................. 652
20.6.2 Read/Write in Module Standby...................................................................... 652
20.6.3 Usage Notes.................................................................................................... 652
20.7 System Clock Output Disabling Function...................................................................... 653
Section 21 Electrical Characteristics........................................................................ 649
21.1 Absolute Maximum Ratings........................................................................................... 649
21.2 Electrical Characteristics of Masked ROM and PROM Versions................................... 650
21.2.1 DC Characteristics.......................................................................................... 650
21.2.2 AC Characteristics.......................................................................................... 658
21.2.3 A/D Conversion Characteristics..................................................................... 666
21.2.4 D/A Conversion Characteristics..................................................................... 667
21.3 Electrical Characteristics of Flash Memory Version...................................................... 668
21.3.1 DC Characteristics.......................................................................................... 668
21.3.2 AC Characteristics.......................................................................................... 677
21.3.3 A/D Conversion Characteristics..................................................................... 683
21.3.4 D/A Conversion Characteristics..................................................................... 684
21.3.5 Flash Memory Characteristics........................................................................ 685
21.4 Operational Timing......................................................................................................... 686
14
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Page 15
21.4.1 Bus Timing ..................................................................................................... 686
21.4.2 Refresh Controller Bus Timing....................................................................... 690
21.4.3 Control Signal Timing.................................................................................... 695
21.4.4 Clock Timing.................................................................................................. 697
21.4.5 TPC and I/O Port Timing................................................................................ 697
21.4.6 ITU Timing..................................................................................................... 698
21.4.7 SCI Input/Output Timing................................................................................ 699
21.4.8 DMAC Timing................................................................................................ 700
Appendix A Instruction Set............................................................................................ 703
A.1 Instruction List................................................................................................................ 703
A.2 Operation Code Map....................................................................................................... 718
A.3 Number of States Required for Execution...................................................................... 721
Appendix B Internal I/O Register................................................................................. 730
B.1 Addresses........................................................................................................................ 730
B.2 Function.......................................................................................................................... 738
Appendix C I/O Port Block Diagrams ........................................................................ 818
C.1 Port 1 Block Diagram..................................................................................................... 818
C.2 Port 2 Block Diagram..................................................................................................... 819
C.3 Port 3 Block Diagram..................................................................................................... 820
C.4 Port 4 Block Diagram..................................................................................................... 821
C.5 Port 5 Block Diagram..................................................................................................... 822
C.6 Port 6 Block Diagrams.................................................................................................... 823
C.7 Port 7 Block Diagrams.................................................................................................... 827
C.8 Port 8 Block Diagrams.................................................................................................... 828
C.9 Port 9 Block Diagrams.................................................................................................... 831
C.10 Port A Block Diagrams................................................................................................... 835
C.11 Port B Block Diagrams................................................................................................... 839
Appendix D Pin States..................................................................................................... 843
D.1 Port States in Each Mode................................................................................................ 843
D.2 Pin States at Reset........................................................................................................... 846
Appendix E
Timing of Transition to and Recovery from Hardware Standby Mode
.... 849
Appendix F Product Code Lineup............................................................................... 850
Appendix G Package Dimensions................................................................................ 852
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Page 16
Section 1 Overview
1.1 Overview
The H8/3048 Series is a series of microcontrollers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory
access controller (DMAC), a refresh controller, and other facilities.
The four members of the H8/3048 Series are the H8/3048, the H8/3047, H8/3045, and the
H8/3044. The H8/3048 has 128 kbytes of ROM and 4 kbytes of RAM. The H8/3047 has 96 kbytes
of ROM and 4 kbytes of RAM. The H8/3045 has 64 kbytes of ROM and 2 kbytes of RAM. The
H8/3044 has 32 kbytes of ROM and 2 kbytes of RAM.
Seven MCU operating modes offer a choice of data bus width and address space size. The modes
(modes 1 to 7) include one single-chip mode and six expanded modes.
In addition to the masked-ROM versions of the H8/3048 Series, the H8/3048 has a ZTAT™*
1
version with user-programmable on-chip PROM and an F-ZTAT™*2version with on-chip flash
memory that can be programmed on-board. These versions enable users to respond quickly and
flexibly to changing application specifications, growing production volumes, and other conditions.
Table 1-1 summarizes the features of the H8/3048 Series.
Notes: 1. ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.
2. F-ZTAT (Flexible ZTAT) is a trademark of Hitachi, Ltd.
1
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Page 17
Table 1-1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also usable as + eight 16-bit registers or eight 32-bit registers)
High-speed operation (flash memory version)
• Maximum clock rate: 16 MHz
• Add/subtract: 125 ns
• Multiply/divide: 875 ns
High-speed operation (masked ROM and PROM versions)
• Maximum clock rate: 18 MHz
• Add/subtract: 111 ns
• Multiply/divide: 778 ns
16-Mbyte address space
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits
× 8 bits, 16 bits × 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit positions
Memory H8/3048
• ROM: 128 kbytes
• RAM: 4 kbytes
H8/3047
• ROM: 96 kbytes
• RAM: 4 kbytes
H8/3045
• ROM: 64 kbytes
• RAM: 2 kbytes
H8/3044
• ROM: 32 kbytes
• RAM: 2 kbytes
Interrupt • Seven external interrupt pins: NMI, IRQ
0
to IRQ
5
controller • 30 internal interrupts
• Three selectable interrupt priority levels
Bus controller • Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Chip select output available for areas 0 to 7
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
• Bus arbitration function
2
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Page 18
Table 1-1 Features (cont)
Feature Description
Refresh DRAM refresh
controller • Directly connectable to 16-bit-wide DRAM
• CAS-before-RAS refresh
• Self-refresh mode selectable
Pseudo-static RAM refresh
• Self-refresh mode selectable
Usable as an interval timer
DMA controller Short address mode
(DMAC) • Maximum four channels available
• Selection of I/O mode, idle mode, or repeat mode
• Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI
channel 0, or external requests
Full address mode
• Maximum two channels available
• Selection of normal mode or block transfer mode
• Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, external requests, or auto-request
16-bit integrated • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10
timer unit (ITU) pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
• DMAC can be activated by compare match/input capture A interrupts
(channels 0 to 3)
Programmable • Maximum 16-bit pulse output, using ITU as time base
timing pattern • Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
controller (TPC) • Non-overlap mode available
• Output data can be transferred by DMAC
Watchdog • Reset signal can be generated by overflow
timer (WDT), • Reset signal can be output externally
1 channel • Usable as an interval timer
Serial • Selection of asynchronous or synchronous mode
communication • Full duplex: can transmit and receive simultaneously
interface (SCI), • On-chip baud-rate generator
2 channels • Smart card interface functions added (SCI0 only)
3
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Page 19
Table 1-1 Features (cont)
Feature Description
A/D converter • Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• A/D conversion can be externally triggered
D/A converter • Resolution: 8 bits
• Two channels
• D/A outputs can be sustained in software standby mode
I/O ports • 70 input/output pins
• 8 input-only pins
Operating modes Seven MCU operating modes
Mode Address Space Address Pins Initial Bus Width Max. Bus Width
Mode 1 1 Mbyte A19to A
0
8 bits 16 bits
Mode 2 1 Mbyte A19to A
0
16 bits 16 bits
Mode 3 16 Mbytes A23to A
0
8 bits 16 bits
Mode 4 16 Mbytes A23to A
0
16 bits 16 bits
Mode 5 1 Mbyte A19to A
0
8 bits 16 bits
Mode 6 16 Mbytes A23to A
0
8 bits 16 bits
Mode 7 1 Mbyte — — —
• On-chip ROM is disabled in modes 1 to 4
Power-down • Sleep mode
state • Software standby mode
• Hardware standby mode
• Module standby function
• Programmable system clock frequency division
Other features • On-chip clock pulse generator
Product lineup
Model (5-V) Model (3-V) Package ROM
HD64F3048TF HD64F3048VTF 100-pin TQFP (TFP-100B) Flash memory
HD64F3048F HD64F3048VF 100-pin QFP (FP-100B)
HD6473048TF HD6473048VTF 100-pin TQFP (TFP-100B) PROM
HD6473048F HD6473048VF 100-pin QFP (FP-100B)
HD6433048TF HD6433048VTF 100-pin TQFP (TFP-100B) Masked ROM
HD6433048F HD6433048VF 100-pin QFP (FP-100B)
HD6433047TF HD6433047VTF 100-pin TQFP (TFP-100B) Masked ROM
HD6433047F HD6433047VF 100-pin QFP (FP-100B)
HD6433045TF HD6433045VTF 100-pin TQFP (TFP-100B) Masked ROM
HD6433045F HD6433045VF 100-pin QFP (FP-100B)
HD6433044TF HD6433044VTF 100-pin TQFP (TFP-100B) Masked ROM
HD6433044F HD6433044VF 100-pin QFP (FP-100B)
4
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Page 20
1.2 Block Diagram
Figure 1-1 shows an internal block diagram.
Figure 1-1 Block Diagram
VVVVVVVVV
CCCCCCSSSSSSSSSSSS
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
7654321
0
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
7654321
0
7654321
0
Port 3 Port 4
Port 5Port 9
P5 /A
P5 /A
P5 /A
P5 /A
3
2
1
0
19
18
17
16
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
7
6
5
4
3
2
1
0
P9 /SCK /IRQ
P9 /SCK /IRQ
P9 /RxD
P9 /RxD
P9 /TxD
P9 /TxD
5
4
3
2
1
0
1
0
1
0
1
0
5
4
P7 /AN /DA
P7 /AN /DA
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /AN
7654321
0
1054321
0
Port 7
V
AV
AV
REF
CC
SS
PA
7
/TP
7
/TIOCB
2
/A
20
PA
6
/TP
6
/TIOCA
2
/A
21
/CS
4
PA
5
/TP
5
/TIOCB
1
/A
22
/CS
5
PA
4
/TP
4
/TIOCA
1
/A
23
/CS
6
PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TEND /TCLKB
PA /TP /TEND /TCLKA
Port A
3
2
0
0
3
2
1
0
1
0
PB /TP /DREQ /ADTRG
PB
6
/TP
14
/DREQ
0
/CS
7
PB /TP /TOCXB
PB /TP /TOCXA
PB /TP /TIOCB
PB /TP /TIOCA
PB /TP /TIOCB
PB /TP /TIOCA
15 17
44443
3
5
4
13
12
3
2
11
10
1
0
9
8
Port 8
P8 /CS
P8 /CS /IRQ
P8 /CS /IRQ
P8 /CS /IRQ
P8 /RFSH/IRQ
40
3
2
1
0
1
2
3
3
2
1
0
MD
MD
MD
EXTAL
XTAL
ø
STBY
RES
V /RESO
NMI
2
1
0
H8/300H CPU
Clock pulse
generator
Interrupt controller
ROM
(masked ROM,
PROM, or flash
memory)
DMA controller
(DMAC)
Serial communication
interface
(SCI) 2 channels
×
Watchdog timer
(WDT)
Refresh
controller
1514131211109
8
Address bus
Data bus (upper)
Data bus (lower)
15
14
13
12
11
10
9
8
Port 2
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
7
6
5
4
3
2
1
0
Port 1
7
6
5
4
3
2
1
0
7
6
1
0
P6 /LWR
P6 /HWR
P6 /RD
P6 /AS
P6 /BACK
P6 /BREQ
P6 /WAIT
6
5
4
3
2
1
0
RAM
16-bit integrated
timer unit
(ITU)
A/D converter
D/A converter
Port 6
Bus controller
Programmable
timing pattern
controller (TPC)
Port B
PP
*
Note: * V function is provided only for the flash memory version.
PP
5
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Page 21
1.3 Pin Description
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the H8/3048 Series.
Figure 1-2 Pin Arrangement (FP-100B or TFP-100B, Top View)
V
TIOCA /TP /PB
TIOCB /TP /PB
TIOCA /TP /PB
TIOCB /TP /PB
TOCXA /TP /PB
TOCXB /TP /PB
CS
7
/DREQ /TP /PB
ADTRG/DREQ /TP /PB
V /RESO
V
TxD /P9
TxD /P9
RxD /P9
RxD /P9
IRQ /SCK /P9
IRQ /SCK /P9
D /P4
D /P4
D /P4
D /P4
V
D /P4
D /P4
D /P4
MD
MD
MD
P6 /LWR
P6 /HWR
P6 /RD
P6 /AS
V
XTAL
EXTAL
V
NMI
RES
STBY
ø
P6 /BACK
P6 /BREQ
P6 /WAIT
V
P5 /A
P5 /A
P5 /A
P5 /A
P2 /A
P2 /A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CC
0
1
2
3
4
5
6
7
SS
0
1
2
3
4
5
0
1
2
3
SS
4
5
6
8
9
10
11
12
13
14
15
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
4
5
2
1
0
2
1
0
3
2
1
0
7
6
PA /TP /TIOCB /A
PA /TP /TIOCA /A /CS4PA /TP /TIOCB /A /CS5PA /TP /TIOCA /A /CS6PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TEND /TCLKB
PA /TP /TEND /TCLKA
V
P8 /CS
P8 /CS /IRQ
P8 /CS /IRQ
P8 /CS /IRQ
P8 /RFSH/IRQ
7654321
0
AV
P7 /AN /DA
P7 /AN /DA
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /AN
P7 /ANVAV
43210
7654321
0
7654321
0
012
3
1
0
321
7654321
0
D /P4
D /P3
D /P3
D /P3
D /P3
D /P3
D /P3
D /P3
D /P3
V
A /P1
A /P1
A /P1
A /P1
A /P1
A /P1
A /P1
A /P1
V
A /P2
A /P2
A /P2
A /P2
A /P2
A /P2
789
701234567CC0123456
7SS01234
5
Top view
(FP-100B, TFP-100B)
26272829303132333435363738394041424344454647484950
1011121314
15
0123456
7
8
9
101112
13
6
5
4
3
CC
SS
SS
19
18
17
16
15
14
100
9998979695949392919089888786858483828180797877
76
202122
23
SS
SS
REF
CC
0
1
0
3
3
4
4
4
4
22110
0
PP
*
Note: * V function is provided only for the flash memory version.
PP
6
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Page 22
1.3.2 Pin Assignments in Each Mode
Table 1-2 lists the pin assignments in each mode.
Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B)
Pin Name
PROM Mode
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
EPROM Flash
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Notes: 1. In modes 1, 3, 5, and 6 the P40to P47functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
2. In modes 2 and 4 the D
0
to D7functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
3. Pins marked NC should be left unconnected.
4. For details about PROM mode see section 18, ROM.
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/
CS
7
PB7/TP15/DREQ1/
ADTRG
RESO
V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
1
P41/D
1
*
1
P42/D
2
*
1
P43/D
3
*
1
V
SS
P44/D
4
*
1
P45/D
5
*
1
P46/D
6
*
1
P47/D
7
*
1
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/
CS
7
PB7/TP15/DREQ1/
ADTRG
RESO
V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
2
P41/D
1
*
2
P42/D
2
*
2
P43/D
3
*
2
V
SS
P44/D
4
*
2
P45/D
5
*
2
P46/D
6
*
2
P47/D
7
*
2
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/
CS
7
PB7/TP15/DREQ1/
ADTRG
RESO
V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
1
P41/D
1
*
1
P42/D
2
*
1
P43/D
3
*
1
V
SS
P44/D
4
*
1
P45/D
5
*
1
P46/D
6
*
1
P47/D
7
*
1
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/
CS
7
PB7/TP15/DREQ1/
ADTRG
RESO
V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
2
P41/D
1
*
2
P42/D
2
*
2
P43/D
3
*
2
V
SS
P44/D
4
*
2
P45/D
5
*
2
P46/D
6
*
2
P47/D
7
*
2
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/
CS
7
PB7/TP15/DREQ1/
ADTRG
RESO
V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
1
P41/D
1
*
1
P42/D
2
*
1
P43/D
3
*
1
V
SS
P44/D
4
*
1
P45/D
5
*
1
P46/D
6
*
1
P47/D
7
*
1
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ0/
CS
7
PB7/TP15/DREQ1/
ADTRG
RESO
V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P40/D
0
*
1
P41/D
1
*
1
P42/D
2
*
1
P43/D
3
*
1
V
SS
P44/D
4
*
1
P45/D
5
*
1
P46/D
6
*
1
P47/D
7
*
1
D
8
D
9
D
10
D
11
D
12
D
13
D
14
V
CC
PB0/TP8/TIOCA
3
PB1/TP9/TIOCB
3
PB2/TP10/TIOCA
4
PB3/TP11/TIOCB
4
PB4/TP12/TOCXA
4
PB5/TP13/TOCXB
4
PB6/TP14/DREQ
0
PB7/TP15/DREQ1/
ADTRG
RESO
V
SS
P90/TxD
0
P91/TxD
1
P92/RxD
0
P93/RxD
1
P94/SCK0/IRQ
4
P95/SCK1/IRQ
5
P4
0
P4
1
P4
2
P4
3
V
SS
P4
4
P4
5
P4
6
P4
7
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P3
6
VCCV
CC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
VPPV
PP
VSSV
SS
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
VSSV
SS
NC NC
NC NC
NC NC
NC NC
EO0I/O
0
EO1I/O
1
EO2I/O
2
EO3I/O
3
EO4I/O
4
EO5I/O
5
EO6I/O
6
Pin
No.
7
www.DataSheet4U.com
Page 23
Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) (cont)
Pin Name
PROM Mode
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
EPROM Flash
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Notes: 1. In modes 1, 3, 5, and 6 the P40to P47functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
2. In modes 2 and 4 the D
0
to D7functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
3. Pins marked NC should be left unconnected.
4. For details about PROM mode see section 18, ROM.
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
P60/WAIT
P61/BREQ
P62/BACK
ø
STBY
RES
NMI
V
SS
EXTAL
XTAL
V
CC
AS
RD
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
P60/WAIT
P61/BREQ
P62/BACK
ø
STBY
RES
NMI
V
SS
EXTAL
XTAL
V
CC
AS
RD
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
P60/WAIT
P61/BREQ
P62/BACK
ø
STBY
RES
NMI
V
SS
EXTAL
XTAL
V
CC
AS
RD
D
15
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
V
SS
P60/WAIT
P61/BREQ
P62/BACK
ø
STBY
RES
NMI
V
SS
EXTAL
XTAL
V
CC
AS
RD
D
15
V
CC
P10/A
0
P11/A
1
P12/A
2
P13/A
3
P14/A
4
P15/A
5
P16/A
6
P17/A
7
V
SS
P20/A
8
P21/A
9
P22/A
10
P23/A
11
P24/A
12
P25/A
13
P26/A
14
P27/A
15
P50/A
16
P51/A
17
P52/A
18
P53/A
19
V
SS
P60/WAIT
P61/BREQ
P62/BACK
ø
STBY
RES
NMI
V
SS
EXTAL
XTAL
V
CC
AS
RD
D
15
V
CC
P10/A
0
P11/A
1
P12/A
2
P13/A
3
P14/A
4
P15/A
5
P16/A
6
P17/A
7
V
SS
P20/A
8
P21/A
9
P22/A
10
P23/A
11
P24/A
12
P25/A
13
P26/A
14
P27/A
15
P50/A
16
P51/A
17
P52/A
18
P53/A
19
V
SS
P60/WAIT
P61/BREQ
P62/BACK
ø
STBY
RES
NMI
V
SS
EXTAL
XTAL
V
CC
AS
RD
P3
7
V
CC
P1
0
P1
1
P1
2
P1
3
P1
4
P1
5
P1
6
P1
7
V
SS
P2
0
P2
1
P2
2
P2
3
P2
4
P2
5
P2
6
P2
7
P5
0
P5
1
P5
2
P5
3
V
SS
P6
0
P6
1
P6
2
ø
STBY
RES
NMI
V
SS
EXTAL
XTAL
V
CC
P6
3
P6
4
EO7I/O
7
VCCV
CC
EA0A
0
EA1A
1
EA2A
2
EA3A
3
EA4A
4
EA5A
5
EA6A
6
EA7A
7
VSSV
SS
EA8A
8
OE OE
EA10A
10
EA11A
11
EA12A
12
EA13A
13
EA14A
14
CE CE
VCCV
CC
VCCV
CC
NC NC
NC NC
VSSV
SS
EA15A
15
NC NC
NC NC
NC NC
VSSV
CC
NC RES
EA9A
9
VSSV
SS
NC
EXTAL
NC XTAL
VCCV
CC
NC A
16
NC NC
Pin
No.
8
www.DataSheet4U.com
Page 24
Table 1-2 Pin Assignments in Each Mode (FP-100B or TFP-100B) (cont)
Pin Name
PROM Mode
Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
EPROM Flash
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Notes: 1. In modes 1, 3, 5, and 6 the P40to P47functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
2. In modes 2 and 4 the D
0
to D7functions of pins P40/D0to P47/D7are selected after a reset, but they can be changed by software.
3. Pins marked NC should be left unconnected.
4. For details about PROM mode see section 18, ROM.
NC V
CC
NC NC
VSSV
SS
VSSV
SS
VSSV
SS
VCCV
CC
VCCV
CC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
VSSV
SS
EA16NC
PGM NC
NC V
CC
NC WE
NC NC
VSSV
SS
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
NC NC
Pin
No.
9
HWR
LWR
MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/
TCLKA
PA1/TP1/TEND1/
TCLKB
PA2/TP2/TIOCA0/
TCLKC
PA3/TP3/TIOCB0/
TCLKD
PA4/TP4/TIOCA1/
CS
6
PA5/TP5/TIOCB1/
CS
5
PA6/TP6/TIOCA2/
CS
4
PA7/TP7/TIOCB
2
HWR
LWR
MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/
TCLKA
PA1/TP1/TEND1/
TCLKB
PA2/TP2/TIOCA0/
TCLKC
PA3/TP3/TIOCB0/
TCLKD
PA4/TP4/TIOCA1/
CS
6
PA5/TP5/TIOCB1/
CS
5
PA6/TP6/TIOCA2/
CS
4
PA7/TP7/TIOCB
2
HWR
LWR
MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/
TCLKA
PA1/TP1/TEND1/
TCLKB
PA2/TP2/TIOCA0/
TCLKC
PA3/TP3/TIOCB0/
TCLKD
PA4/TP4/TIOCA1/
CS
6
PA5/TP5/TIOCB1/
CS
5
PA6/TP6/TIOCA2/
CS
4
A
20
HWR
LWR
MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/
TCLKA
PA1/TP1/TEND1/
TCLKB
PA2/TP2/TIOCA0/
TCLKC
PA3/TP3/TIOCB0/
TCLKD
PA4/TP4/TIOCA1/
CS
6
PA5/TP5/TIOCB1/
CS
5
PA6/TP6/TIOCA2/
CS
4
A
20
HWR
LWR
MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/
TCLKA
PA1/TP1/TEND1/
TCLKB
PA2/TP2/TIOCA0/
TCLKC
PA3/TP3/TIOCB0/
TCLKD
PA4/TP4/TIOCA1/
CS
6
PA5/TP5/TIOCB1/
CS
5
PA6/TP6/TIOCA2/
CS
4
PA7/TP7/TIOCB
2
HWR
LWR
MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/RFSH/IRQ
0
P81/CS3/IRQ
1
P82/CS2/IRQ
2
P83/CS1/IRQ
3
P84/CS
0
V
SS
PA0/TP0/TEND0/
TCLKA
PA1/TP1/TEND1/
TCLKB
PA2/TP2/TIOCA0/
TCLKC
PA3/TP3/TIOCB0/
TCLKD
PA4/TP4/TIOCA1/
A23/CS
6
PA5/TP5/TIOCB1/
A22/CS
5
PA6/TP6/TIOCA2/
A21/CS
4
A
20
P6
5
P6
6
MD
0
MD
1
MD
2
AV
CC
V
REF
P70/AN
0
P71/AN
1
P72/AN
2
P73/AN
3
P74/AN
4
P75/AN
5
P76/AN6/DA
0
P77/AN7/DA
1
AV
SS
P80/IRQ
0
P81/IRQ
1
P82/IRQ
2
P83/IRQ
3
P8
4
V
SS
PA0/TP0/TEND0/
TCLKA
PA1/TP1/TEND1/
TCLKB
PA2/TP2/TIOCA0/
TCLKC
PA3/TP3/TIOCB0/
TCLKD
PA4/TP4/TIOCA
1
PA5/TP5/TIOCB
1
PA6/TP6/TIOCA
2
PA7/TP7/TIOCB
2
www.DataSheet4U.com
Page 25
1.3.3 Pin Functions
Table 1-3 summarizes the pin functions.
Table 1-3 Pin Functions
Type Symbol Pin No. I/O Name and Function
Power V
CC
1, 35, 68 Input Power: For connection to the power supply.
Connect all V
CC
pins to the system power
supply.
V
SS
11, 22, 44, Input Ground: For connection to ground (0 V).
57, 65, 92 Connect all V
SS
pins to the 0-V system power
supply.
Clock XTAL 67 Input For connection to a crystal resonator.
For examples of crystal resonator and external
clock input, see section 19, Clock Pulse
Generator.
EXTAL 66 Input For connection to a crystal resonator or input of
an external clock signal. For examples of
crystal resonator and external clock input, see
section 19, Clock Pulse Generator.
ø 61 Output System clock: Supplies the system clock to
external devices.
Operating MD
2
to MD075 to 73 Input Mode 2 to mode 0: For setting the operating
mode control mode, as follows. Inputs at these pins must not
be changed during operation.
MD
2
MD
1
MD
0
Operating Mode
000—
0 0 1 Mode 1
0 1 0 Mode 2
0 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
1 1 0 Mode 6
1 1 1 Mode 7
10
www.DataSheet4U.com
Page 26
Table 1-3 Pin Functions (cont)
Type Symbol Pin No. I/O Name and Function
System control RES 63 Input Reset input: When driven low, this pin resets
the chip
RESO 10 Output Reset output: Outputs a reset signal to
external devices
(RESO/V
PP
) Also used as a power supply for on-board
programming of the flash memory version.
STBY 62 Input Standby: When driven low, this pin forces
a transition to hardware standby mode
BREQ 59 Input Bus request: Used by an external bus master
to request the bus right
BACK 60 Output Bus request acknowledge: Indicates that the
bus has been granted to an external bus
master
Interrupts NMI 64 Input Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ
5
to 17, 16, Input Interrupt request 5 to 0: Maskable interrupt
IRQ
0
90 to 87 request pins
Address bus A
23
to A
0
97 to 100, Output Address bus: Outputs address signals
56 to 45,
43 to 36
Data bus D
15
to D034 to 23, Input/ Data bus: Bidirectional data bus
21 to 18 output
Bus control CS7to CS08, 97 to 99, Output Chip select: Select signals for areas 7 to 0
88 to 91
AS 69 Output Address strobe: Goes low to indicate valid
address output on the address bus
RD 70 Output Read: Goes low to indicate reading from the
external address space
HWR 71 Output High write: Goes low to indicate writing to the
external address space; indicates valid data on
the upper data bus (D
15
to D8).
LWR 72 Output Low write: Goes low to indicate writing to the
external address space; indicates valid data on
the lower data bus (D
7
to D0).
WAIT 58 Input Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
11
www.DataSheet4U.com
Page 27
Table 1-3 Pin Functions (cont)
Type Symbol Pin No. I/O Name and Function
Refresh
RFSH 87 Output Refresh: Indicates a refresh cycle
controller
CS
3
88 Output Row address strobe RAS: Row address
strobe signal for DRAM connected to area 3
RD 70 Output Column address strobe CAS: Column
address
strobe signal for DRAM connected to
area
3; used with 2WE DRAM.
Write enable WE: Write enable signal for
DRAM connected to area 3; used with 2CAS
DRAM.
HWR 71 Output Upper write UW: Write enable signal for
DRAM connected to area 3; used with 2WE
DRAM.
Upper column address strobe UCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS DRAM.
LWR 72 Output Lower write LW: Write enable signal for DRAM
connected to area 3; used with 2WE DRAM.
Lower column address strobe LCAS:
Column address strobe signal for DRAM
connected to area 3; used with 2CAS DRAM.
DREQ
1
, 9, 8 Input DMA request 1 and 0: DMAC activation
DREQ
0
requests
TEND
1
, 94, 93 Output Transfer end 1 and 0: These signals indicate
TEND
0
that the DMAC has ended a data transfer
TCLKD to 96 to 93 Input Clock input D to A: External clock inputs
TCLKA
TIOCA
4
to 4, 2, 99, Input/ Input capture/output compare A4 to A0:
TIOCA
0
97, 95 output GRA4 to GRA0 output compare or input
capture, or PWM output
TIOCB4 to 5, 3, 100, Input/ Input capture/output compare B4 to B0:
TIOCB
0
98, 96 output GRB4 to GRB0 output compare or input
capture, or PWM output
TOCXA
4
6 Output Output compare XA4: PWM output
TOCXB
4
7 Output Output compare XB4: PWM output
DMA
controller
(DMAC)
16-bit
integrated
timer unit
(ITU)
12
www.DataSheet4U.com
Page 28
Table 1-3 Pin Functions (cont)
Type Symbol Pin No. I/O Name and Function
Programmable TP
15
to 9 to 2, Output TPC output 15 to 0: Pulse output
timing pattern TP
0
100 to 93
controller (TPC)
TxD1, 13, 12 Output Transmit data (channels 0 and 1): SCI data
TxD
0
output
RxD
1
, 15, 14 Input Receive data (channels 0 and 1): SCI data
RxD
0
input
SCK
1
, 17, 16 Input/ Serial clock (channels 0 and 1): SCI clock
SCK
0
output input/output
A/D converter AN
7
to AN085 to 78 Input Analog 7 to 0: Analog input pins
ADTRG 9 Input A/D trigger: External trigger input for starting
A/D conversion
D/A converter DA
1
, DA085, 84 Output Analog output: Analog output from the
D/A converter
A/D and D/A AV
CC
76 Input Power supply pin for the A/D and
converters D/A converters. Connect to the system power
supply (+5 V) when not using the A/D and
D/A converters.
AV
SS
86 Input Ground pin for the A/D and D/A converters.
Connect to system ground (0 V).
V
REF
77 Input Reference voltage input pin for the A/D and
D/A converters. Connect to the system power
supply (+5 V) when not using the A/D and
D/A converters.
I/O ports P1
7
to P1043 to 36 Input/ Port 1: Eight input/output pins. The direction of
output each pin can be selected in the port 1 data
direction register (P1DDR).
P2
7
to P2052 to 45 Input/ Port 2: Eight input/output pins. The direction of
output each pin can be selected in the port 2 data
direction register (P2DDR).
P3
7
to P3034 to 27 Input/ Port 3: Eight input/output pins. The direction of
output each pin can be selected in the port 3 data
direction register (P3DDR).
P4
7
to P4026 to 23, Input/ Port 4: Eight input/output pins. The
21 to 18 output direction of each pin can be selected in the port
4 data direction register (P4DDR).
Serial communication
interface (SCI)
13
www.DataSheet4U.com
Page 29
Table 1-3 Pin Functions (cont)
Type Symbol Pin No. I/O Name and Function
I/O ports P5
3
to P5056 to 53 Input/ Port 5: Four input/output pins. The direction of
output each pin can be selected in the port 5 data
direction register (P5DDR).
P6
6
to P6072 to 69, Input/ Port 6: Seven input/output pins. The direction
60 to 58 output of each pin can be selected in the port 6 data
direction register (P6DDR).
P7
7
to P7085 to 78 Input Port 7: Eight input pins
P8
4
to P8091 to 87 Input/ Port 8: Five input/output pins. The direction of
output each pin can be selected in the port 8 data
direction register (P8DDR).
P9
5
to P9017 to 12 Input/ Port 9: Six input/output pins. The direction of
output each pin can be selected in the port 9 data
direction register (P9DDR).
PA
7
to PA0100 to 93 Input/ Port A: Eight input/output pins. The direction of
output each pin can be selected in the port A data
direction register (PADDR).
PB
7
to PB09 to 2 Input/ Port B: Eight input/output pins. The direction of
output each pin can be selected in the port B data
direction register (PBDDR).
14
www.DataSheet4U.com
Page 30
Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1 Features
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-two basic instructions
— 8/16/32-bit data transfer and arithmetic and logic instructions
— Multiply and divide instructions
— Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct [Rn]
— Register indirect [@ERn]
— Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
— Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
— Absolute address [@aa:8, @aa:16, or @aa:24]
— Immediate [#xx:8, #xx:16, or #xx:32]
— Program-counter relative [@(d:8, PC) or @(d:16, PC)]
— Memory indirect [@@aa:8]
• 16-Mbyte linear address space
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• High-speed operation
— All frequently-used instructions execute in two to four states
— Maximum clock frequency: 18 MHz/16 MHz (flash memory version)
— 8/16/32-bit register-register add/subtract: 111 ns/125 ns (flash memory version)
—8 × 8-bit register-register multiply: 778 ns/875 ns (flash memory version)
— 16 ÷ 8-bit register-register divide: 778 ns/875 ns (flash memory version)
— 16 × 16-bit register-register multiply: 1.221 ns/1.375 ns (flash memory version)
— 32 ÷ 16-bit register-register divide: 1.221 ns/1.375 ns (flash memory version)
• Two CPU operating modes
— Normal mode (not available in the H8/3048 Series)
— Advanced mode
• Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
• More general registers
Eight 16-bit registers have been added.
• Expanded address space
— Advanced mode supports a maximum 16-Mbyte address space.
— Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
(Normal mode is not available in the H8/3048 Series.)
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
— Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
— Signed multiply/divide instructions and other instructions have been added.
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2.2 CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2-1.
The H8/3048 Series can be used only in advanced mode. (Information from this point on will
apply to advanced mode unless otherwise stated.)
Figure 2-1 CPU Operating Modes
CPU operating modes
Normal mode
Advanced mode
Maximum 64 kbytes, program
and data areas combined
Maximum 16 Mbytes, program
and data areas combined
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2.3 Address Space
The maximum address space of the H8/300H CPU is 16 Mbytes. The H8/3048 Series has various
operating modes (MCU modes), some providing a 1-Mbyte address space, the others supporting
the full 16 Mbytes.
Figure 2-2 shows the address ranges of the H8/3048 Series. For further details see section 3.6,
Memory Map in Each Operating Mode.
The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
Figure 2-2 Memory Map
H'00000
H'FFFFF
H'000000
H'FFFFFF
a. 1-Mbyte modes b. 16-Mbyte modes
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2.4 Register Configuration
2.4.1 Overview
The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers:
general registers and control registers.
Figure 2-3 CPU Internal Registers
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
0707015
(SP)
23 0
PC
7
CCR
6543210
IUIHUNZVC
General Registers (ERn)
Control Registers (CR)
Legend
SP:
PC:
CCR:
I:
UI:
H:
U:
N:
Z:
V:
C:
Stack pointer
Program counter
Condition code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
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2.4.2 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2-4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
Figure 2-4 Usage of General Registers
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
ER registers
ER0 to ER7
E registers
(extended registers)
E0 to E7
R registers
R0 to R7
RH registers
R0H to R7H
RL registers
R0L to R7L
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General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the
stack.
Figure 2-5 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so
the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details see section 5, Interrupt Controller.
Free area
Stack area
SP (ER7)
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Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,
the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an
MOV.L instruction executed immediately after a reset.
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2.5 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1,
2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as
two digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figures 2-6 and 2-7 show the data formats in general registers.
Figure 2-6 General Register Data Formats (1)
7
RnH
RnL
RnH
RnL
RnH
RnL
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
6543210
70
Don’t care
76543210
70
Don’t care
Don’t care
70
43
Lower digitUpper digit
7
43
Lower digitUpper digit
Don’t care
0
70
Don’t care
MSB LSB
Don’t care
70
MSB LSB
Data Type Data Format
General
Register
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Figure 2-7 General Register Data Formats (2)
Rn
En
ERn
Word data
Word data
Longword data
15 0
MSB LSB
General
RegisterData Type Data Format
15 0
MSB LSB
31 16
MSB
15 0
LSB
Legend
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
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2.5.2 Memory Data Formats
Figure 2-8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
Figure 2-8 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
76543210Address L
Address L
LSB
MSB
MSB
LSB
70
MSB LSB
1-bit data
Byte data
Word data
Longword data
AddressData Type Data Format
Address 2M
Address 2M + 1
Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3
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2.6 Instruction Set
2.6.1 Instruction Set Overview
The H8/300H CPU has 62 types of instructions, which are classified in table 2-1.
Table 2-1 Instruction Classification
Function Instruction Types
Data transfer MOV, PUSH
*
1
, POP
*
1
, MOVTPE
*
2
, MOVFPE
*
2
3
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, 18
MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU
Logic operations AND, OR, XOR, NOT 4
Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, 14
BIXOR, BLD, BILD, BST, BIST
Branch Bcc
*
3
, JMP, BSR, JSR, RTS 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9
Block data transfer EEPMOV 1
Total 62 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. Not available in the H8/3048 Series.
3. Bcc is a generic branching instruction.
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2.6.2 Instructions and Addressing Modes
Table 2-2 indicates the instructions available in the H8/300H CPU.
Table 2-2 Instructions and Addressing Modes
Addressing Modes
@@ @@
(d:16, (d:24, @ERn+/ @ @ @ (d:8, (d:16, @@
Function Instruction #xx Rn @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 PC) PC) aa:8 —
MOV BWL BWL BWL BWL BWL BWL B BWL BWL — — — —
POP, PUSH — — — — — — — — — — — — WL
MOVFPE, — — — — — — — B — — — — —
MOVTPE
ADD, CMP BWL BWL — — — — — — — — — — —
SUB WL BWL — — — — — — — — — — —
ADDX, SUBX B B — — — — — — — — — — —
ADDS, SUBS — L — — — — — — — — — — —
INC, DEC — BWL — — — — — — — — — — —
DAA, DAS — B — — — — — — — — — — —
MULXU, — BW — — — — — — — — — — —
MULXS,
DIVXU,
DIVXS
NEG — BWL — — — — — — — — — — —
EXTU, EXTS — WL — — — — — — — — — — —
Logic AND, OR, BWL BWL — — — — — — — — — — —
operations XOR
NOT —BWL— ——— — — — ————
Shift instructions — BWL — — — — — — — — — — —
Bit manipulation — B B — — — B — — — — — —
Branch Bcc, BSR — — — — — — — — —
oo——
JMP, JSR — —
o ——— ——o ——o —
RTS ——— — — — — — — — — —
o
TRAPA — — — — — — — — — — — — o
RTE ——— — — — — — — — — — o
SLEEP — — — — — — — — — — — — o
LDC B B W W W W — W W — — — —
STC — B W W W W — W W — — — —
ANDC, ORC, B — — — — — — — — — — — —
XORC
NOP — — — — — — — — — — — —
o
Block data transfer — — — — — — — — — — — — BW
Legend
B: Byte
W: Word
L: Longword
Data
transfer
Arithmetic
operations
System
control
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2.6.3 Tables of Instructions Classified by Function
Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation
used in these tables is defined next.
Operation Notation
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ AND logical
∨ OR logical
⊕ Exclusive OR logical
→ Move
¬ NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
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Table 2-3 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in the H8/3048 Series.
MOVTPE B Rs → (EAs)
Cannot be used in the H8/3048 Series.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W
Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2-4 Arithmetic Operation Instructions
Instruction Size* Function
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data cannot
be subtracted from data in a general register. Use the SUBX or ADD
instruction.)
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two general
registers, or on immediate data and data in a general register.
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands can
be incremented or decremented by 1 only.)
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
ADDX,
SUBX
INC,
DEC
ADD,
SUB
ADDS,
SUBS
DAA,
DAS
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Table 2-4 Arithmetic Operation Instructions (cont)
Instruction Size* Function
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
DIVXS B/W Rd ÷Rs → Rd
Performs signed division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register or
with immediate data, and sets CCR according to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a general
register.
EXTS W/L Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by extending the sign bit.
EXTU W/L Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data, or
extends word data in the lower 16 bits of a 32-bit register to longword data,
by padding with zeros.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2-5 Logic Operation Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another general
register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another general
register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and another
general register or immediate data.
NOT B/W/L ¬ Rd → Rd
Takes the one’s complement of general register contents.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2-6 Shift Instructions
Instruction Size* Function
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry bit.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
SHAL,
SHAR
SHLL,
SHLR
ROTL,
ROTR
ROTXL,
ROTXR
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Table 2-7 Bit Manipulation Instructions
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a general
register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit immediate
data or the lower 3 bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
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Table 2-7 Bit Manipulation Instructions (cont)
Instruction Size* Function
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general register or
memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD B ¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST B C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Size refers to the operand size.
B: Byte
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Table 2-8 Branching Instructions
Instruction Size Function
Bcc — Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
Bcc (BHS) Carry clear (high or same) C = 0
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
JMP — Branches unconditionally to a specified address
BSR — Branches to a subroutine at a specified address
JSR — Branches to a subroutine at a specified address
RTS — Returns from a subroutine
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Table 2-9 System Control Instructions
Instruction Size* Function
TRAPA — Starts trap-instruction exception handling
RTE — Returns from an exception-handling routine
SLEEP — Causes a transition to the power-down state
LDC B/W (EAs) → CCR
Moves the source operand contents to the condition code register. The
condition code register size is one byte, but in transfer from memory, data is
read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by word
access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data.
NOP — PC + 2 → PC
Only increments the program counter.
Note: * Size refers to the operand size.
B: Byte
W: Word
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Table 2-10 Block Transfer Instruction
Instruction Size Function
EEPMOV.B — if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until R4L = 0
else next;
EEPMOV.W — if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until R4 = 0
else next;
Transfers a data block according to parameters set in general registers R4L
or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5: Starting source address
ER6: Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
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2.6.4 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2-9 shows examples of instruction formats.
Figure 2-9 Instruction Formats
op
NOP, RTS, etc.
op rn rm
op rn rm
EA (disp)
Operation field only
ADD.B Rn, Rm, etc.
Operation field and register fields
MOV.B @(d:16, Rn), Rm
Operation field, register fields, and effective address extension
BRA d:8
Operation field, effective address extension, and condition field
op cc EA (disp)
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2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead
of time.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2-11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2-11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)
4 Register indirect with post-increment @ERn+
Register indirect with pre-decrement @–ERn
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8, PC)/@(d:16, PC)
8 Memory indirect @@aa:8
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1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the
resulting register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2-12 indicates the accessible
address ranges.
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Table 2-12 Absolute Address Access Ranges
Absolute
Address 1-Mbyte Modes 16-Mbyte Modes
8 bits (@aa:8) H'FFF00 to H'FFFFF H'FFFF00 to H'FFFFFF
(1048320 to 1048575) (16776960 to 16777215)
16 bits (@aa:16) H'00000 to H'07FFF, H'000000 to H'007FFF,
H'F8000 to H'FFFFF H'FF8000 to H'FFFFFF
(0 to 32767, 1015808 to 1048575) (0 to 32767, 16744448 to 16777215)
24 bits (@aa:24) H'00000 to H'FFFFF H'000000 to H'FFFFFF
(0 to 1048575) (0 to 16777215)
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The
first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2-10.
The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is
0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector
area. For further details see section 5, Interrupt Controller.
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Figure 2-10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2 Effective Address Calculation
Table 2-13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
Specified by @aa:8
Reserved
Branch address
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Table 2-13 Effective Address Calculation
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Register direct (Rn)
1
Operand is general
register contents
op rm rn
Register indirect (@ERn)
2
op r
General register contents
31 0
23 0
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
3
op r
General register contents
31 0
23 0
disp
Sign extension disp
Register indirect with post-increment
or pre-decrement
4
General register contents
31 0
23 0
1, 2, or 4
op r
General register contents
31 0
23 0
1, 2, or 4
op r
1 for a byte operand, 2 for a word
operand, 4 for a longword operand
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
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Table 2-13 Effective Address Calculation (cont)
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Absolute address
@aa:8
5
op
Program-counter relative
@(d:8, PC) or @(d:16, PC)
7
0
23 0
abs
23 087
@aa:16
op abs
23 016 15
H'FFFF
Sign
extension
@aa:24
op
23 0
abs
Immediate
#xx:8, #xx:16, or #xx:32
6
Operand is immediate data
op disp
23 0
PC contents
disp
op IMM
Sign
extension
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Table 2-13 Effective Address Calculation (cont)
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
8
Legend
r, rm, rn:
op:
disp:
IMM:
abs:
Register field
Operation field
Displacement
Immediate data
Absolute address
Memory indirect @@aa:8
8
op
23 0
abs
23 087
H'0000
0
abs
31
Memory contents
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2.8 Processing States
2.8.1 Overview
The H8/300H CPU has five processing states: the program execution state, exception-handling
state, power-down state, reset state, and bus-released state. The power-down state includes sleep
mode, software standby mode, and hardware standby mode. Figure 2-11 classifies the processing
states. Figure 2-13 indicates the state transitions.
Figure 2-11 Processing States
Processing states Program execution state
Bus-released state
Reset state
Power-down state
The CPU executes program instructions in sequence
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception
The external bus has been released in response to a bus request
signal from a bus master other than the CPU
The CPU and all on-chip supporting modules are initialized and halted
The CPU is halted to conserve power
Sleep mode
Software standby mode
Hardware standby mode
Exception-handling state
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2.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2-14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2-14 Exception Handling Types and Priority
Priority Type of Exception Detection Timing Start of Exception Handling
High Reset Synchronized with clock Exception handling starts immediately
when RES changes from low to high
Interrupt End of instruction When an interrupt is requested,
execution or end of exception handling starts at the end of
exception handling* the current instruction or current
exception-handling sequence
Trap instruction When TRAPA instruction Exception handling starts when a trap
Low is executed (TRAPA) instruction is executed
Note: * Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
immediately after reset exception handling.
Figure 2-12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
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Figure 2-12 Classification of Exception Sources
Figure 2-13 State Transitions
Exception
sources
Reset
Interrupt
Trap instruction
External interrupts
Internal interrupts (from on-chip supporting modules)
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End of bus release
Bus request
End of bus
release
Bus-released state
End of
exception
handling
Exception-handling state
RES = 1
Reset state
Notes: 1.2.From any state except hardware standby mode, a transition to the reset state occurs
whenever goes low.
From any state, a transition to hardware standby mode occurs when goes low.
*1
RES
Program execution state
Bus
request
Exception
Interrupt
NMI, IRQ , IRQ ,
or IRQ interrupt
2
STBY RES = 1, = 0
01
SLEEP
instruction
with SSBY = 0
Sleep mode
SLEEP instruction
with SSBY = 1
Software standby mode
Hardware standby mode
Power-down state
STBY
*2
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2.8.4 Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
the CPU fetches a start address from the exception vector table and execution branches to that
address.
Figure 2-14 shows the stack after the exception-handling sequence.
Figure 2-14 Stack Structure after Exception Handling
SP–4
SP–3
SP–2
SP–1
SP (ER7)
Before exception
handling starts
SP (ER7)
SP+1
SP+2
SP+3
SP+4
After exception
handling ends
Stack area
CCR
PC
Even
address
Pushed on stack
Legend
CCR:
SP:
Condition code register
Stack pointer
Notes: 1.2.PC is the address of the first instruction executed after the return from the
exception-handling routine.
Registers must be saved and restored by word access or longword access,
starting at an even address.
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2.8.5 Bus-Released State
In this state the bus is released to a bus master other than the CPU, in response to a bus request.
The bus masters other than the CPU are the DMA controller, the refresh controller, and an external
bus master. While the bus is released, the CPU halts except for internal operations. Interrupt
requests are not accepted. For details see section 6.3.7, Bus Arbiter Operation.
2.8.6 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The
I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 12,
Watchdog Timer.
2.8.7 Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and all clocks halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 20, Power-Down State.
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2.9 Basic Operational Timing
2.9.1 Overview
The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2-15 shows the on-chip memory access cycle. Figure 2-16 indicates the pin
states.
Figure 2-15 On-Chip Memory Access Cycle
T state
Bus cycle
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
ø
1
T state
2
Read data
Address
Write data
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Figure 2-16 Pin States during On-Chip Memory Access
T
, , ,AS
ø
1
T
2
Address bus
D to D
15 0
RD HWR LWR
High
Address
High impedance
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2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2-17 shows the on-chip supporting module
access timing. Figure 2-18 indicates the pin states.
Figure 2-17 Access Cycle for On-Chip Supporting Modules
Address bus
Internal read signal
Internal data bus
Internal write signal
Address
Internal data bus
ø
T state
Bus cycle
1
T state
2
T state
3
Read
access
Write
access
Write data
Read data
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Figure 2-18 Pin States during Access to On-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit bus, and whether it is accessed in
two or three states. For details see section 6, Bus Controller.
T
, , ,AS
ø
1
T
2
Address bus
D to D
15 0
RD HWR LWR
High
High impedance
T
3
Address
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Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Operating Mode Selection
The H8/3048 Series has seven operating modes (modes 1 to 7) that are selected by the mode pins
(MD2to MD0) as indicated in table 3-1. The input at these pins determines the size of the address
space and the initial bus mode.
Table 3-1 Operating Mode Selection
Description
Operating Initial Bus On-Chip On-Chip
Mode MD2MD1MD0Address Space Mode
*
1
ROM RAM
— 000 — — — —
Mode 1 0 0 1 Expanded mode 8 bits Disabled Enabled
*
2
Mode 2 0 1 0 Expanded mode 16 bits Disabled Enabled
*
2
Mode 3 0 1 1 Expanded mode 8 bits Disabled Enabled
*
2
Mode 4 1 0 0 Expanded mode 16 bits Disabled Enabled
*
2
Mode 5 1 0 1 Expanded mode 8 bits Enabled Enabled
*
2
Mode 6 1 1 0 Expanded mode 8 bits Enabled Enabled
*
2
Mode 7 1 1 1 Single-chip advanced — Enabled Enabled
mode
Notes: 1. In modes 1 to 6, an 8-bit or 16-bit data bus can be selected on a per-area basis by
settings made in the area bus width control register (ABWCR). For details see
section 6, Bus Controller.
2. If the RAME bit in SYSCR is cleared to 0, these addresses become external addresses.
For the address space size there are two choices: 1 Mbyte or 16 Mbytes. The external data bus is
either 8 or 16 bits wide depending on ABWCR settings. If 8-bit access is selected for all areas, the
external data bus is 8 bits wide. For details see section 6, Bus Controller.
Modes 1 to 4 are externally expanded modes that enable access to external memory and peripheral
devices and disable access to the on-chip ROM. Modes 1 and 2 support a maximum address space
of 1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes.
Mode Pins
MD
2
MD1MD
0
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Modes 5 and 6 are externally expanded modes that enable access to external memory and
peripheral devices and also enable access to the on-chip ROM. Mode 5 supports a maximum
address space of 1 Mbyte. Mode 6 supports a maximum address space of 16 Mbytes.
Mode 7 is a single-chip mode that operates using the on-chip ROM, RAM, and registers, and
makes all I/O ports available. Mode 7 supports a 1-Mbyte address space.
The H8/3048 Series can be used only in modes 1 to 7. The inputs at the mode pins must select one
of these seven modes. The inputs at the mode pins must not be changed during operation.
3.1.2 Register Configuration
The H8/3048 Series has a mode control register (MDCR) that indicates the inputs at the mode pins
(MD2to MD0), and a system control register (SYSCR). Table 3-2 summarizes these registers.
Table 3-2 Registers
Address* Name Abbreviation R/W Initial Value
H'FFF1 Mode control register MDCR R Undetermined
H'FFF2 System control register SYSCR R/W H'0B
Note: * The lower 16 bits of the address are indicated.
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3.2 Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the
H8/3048 Series.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
Bits 5 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD2to MD0(the current operating mode). MDS2 to MDS0 correspond to MD2to MD0. MDS2
to MDS0 are read-only bits. The mode pin (MD2to MD0) levels are latched into these bits when
MDCR is read.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—
R
*
2
MDS2
—
R
1
MDS1
— R**
Reserved bits Mode select 2 to 0
Bits indicating the current
operating mode
Reserved bits
Note: Determined by pins MD to MD .*
20
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3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3048 Series.
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 20, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7
SSBY Description
0 SLEEP instruction causes transition to sleep mode (Initial value)
1 SLEEP instruction causes transition to software standby mode
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
Software standby
Enables transition to software standby mode
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or an interrupt mask bit
NMI edge select
Selects the valid edge
of the NMI input
Reserved bit
RAM enable
Enables or
disables
on-chip RAM
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so
that the waiting time will be at least 7 ms at the system clock rate. For further information about
waiting time selection, see section 20.4.3, Selection of Waiting Time for Exit from Software
Standby Mode.
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
000Waiting time = 8,192 states (Initial value)
001Waiting time = 16,384 states
010Waiting time = 32,768 states
011Waiting time = 65,536 states
100Waiting time = 131,072 states
101Waiting time = 1,024 states
1 1 — Illegal setting
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as an interrupt mask bit
1 UI bit in CCR is used as a user bit (Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG Description
0 An interrupt is requested at the falling edge of NMI (Initial value)
1 An interrupt is requested at the rising edge of NMI
Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
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3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A19to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2 Mode 2
Ports 1, 2, and 5 function as address pins A19to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A23to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A23to A21are valid when 0 is written in bits 7 to 5 of the bus release control register
(BRCR). (In this mode A20is always used for address output.)
3.4.4 Mode 4
Ports 1, 2, and 5 and part of port A function as address pins A23to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access
to all areas. If all areas are designated for 8-bit access in ABWCR, the bus mode switches to
8 bits. A23to A21are valid when 0 is written in bits 7 to 5 of BRCR. (In this mode A20is always
used for address output.)
3.4.5 Mode 5
Ports 1, 2, and 5 can function as address pins A19to A0, permitting access to a maximum 1-Mbyte
address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.6 Mode 6
Ports 1, 2, and 5 and part of port A function as address pins A23to A0, permitting access to a
maximum 16-Mbyte address space, but following a reset they are input ports. To use ports 1, 2,
and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR,
and P5DDR) must be set to 1. For A23to A21output, clear bits 7 to 5 of BRCR to 0. (In this mode
A20is always used for address output.)
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least one area is
designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
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3.4.7 Mode 7
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are a vailable. Mode 7
supports a 1-Mbyte address space.
3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3-3
indicates their functions in each operating mode.
Table 3-3 Pin Functions in Each Mode
Port Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7
Port 1 A7to A
0
A7to A
0
A7to A
0
A7to A
0
P17to P1
0
*
2
P17to P1
0
*
2
P17to P1
0
Port 2 A15to A
8
A15to A
8
A15to A
8
A15to A
8
P27to P2
0
*
2
P27to P2
0
*
2
P27to P2
0
Port 3 D15to D
8
D15to D
8
D15to D
8
D15to D
8
D15to D
8
D15to D
8
P37to P3
0
Port 4 P47to P4
0
*
1
D7to D
0
*
1
P47to P4
0
*
1
D7to D
0
*
1
P47to P4
0
*
1
P47to P4
0
*
1
P47to P4
0
Port 5 A19to A
16
A19to A
16
A19to A
16
A19to A
16
P53to P5
0
*
2
P53to P5
0
*
2
P53to P5
0
Port A PA7to PA4PA7to PA4PA7to PA
5
*
3
, A20PA7to PA
5
*
3
, A20PA7to PA4PA7to PA5, A
20
*
3
PA7to PA
4
Notes: 1. Initial state. The bus mode can be switched by settings in ABWCR. These pins function
as P4
7
to P40in 8-bit bus mode, and as D7to D0in 16-bit bus mode.
2. Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
3. Initial state. A
20
is always an address output pin. PA7to PA5are switched over to A23to
A
21
output by writing 0 in bits 7 to 5 of BRCR.
3.6 Memory Map in Each Operating Mode
Figure 3-1 shows a memory map of the H8/3048. Figure 3-2 shows a memory map of the
H8/3047. Figure 3-3 shows a memory map of the H8/3044. Figure 3-4 shows a memory map of
the H8/3045. The address space is divided into eight areas.
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte modes
(modes 1, 2, 5, and 7) and 16-Mbyte modes (modes 3, 4, and 6). The address range specifiable by
the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs.
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Figure 3-1 H8/3048 Memory Map in Each Operating Mode
H'00000
H'000FF
H'07FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip RAM *
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Note: External addresses can be accessed by disabling on-chip RAM.*
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
On-chip RAM *
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FF8000
H'FFEF0F
H'FFEF10
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
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Figure 3-1 H8/3048 Memory Map in Each Operating Mode (cont)
H'00000
H'000FF
H'07FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Mode 7
(single-chip advanced mode)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip ROM
On-chip RAM *
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
H'00000
H'000FF
H'07FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
Vector area
On-chip ROM
On-chip RAM
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FEF10
H'FFF00
H'FFF0F
H'FFF1C
H'FFFFF
H'1FFFF
H'F8000
Note: External addresses can be accessed by disabling on-chip RAM.*
On-chip ROM
H'000000
H'0000FF
H'007FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 7
External
address
space
Vector area
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'01FFFF
H'020000
H'FFEF0F
H'FFEF10
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
On-chip RAM *
Area 6
H'FF8000
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Figure 3-2 H8/3047 Memory Map in Each Operating Mode
H'00000
H'000FF
H'07FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip RAM *
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Note: External addresses can be accessed by disabling on-chip RAM.*
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
On-chip RAM *
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FF8000
H'FFEF0F
H'FFEF10
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
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Figure 3-2 H8/3047 Memory Map in Each Operating Mode (cont)
H'00000
H'000FF
H'07FFF
H'17FFF
H'18000
Memory-indirect
branch addresses
16-bit absolute
addresses
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Mode 7
(single-chip advanced mode)
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip ROM
On-chip RAM
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
H'00000
H'000FF
H'07FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
Vector area
On-chip ROM
On-chip ROM
Reserved
*1
On-chip RAM
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FEF10
H'FFF00
H'FFF0F
H'FFF1C
H'FFFFF
H'17FFF
H'F8000
Notes:
H'1FFFF
H'20000
Reserved
*1
*2
1.2.Do not access the reserved area.
External addresses can be accessed by disabling on-chip RAM.
H'000000
H'0000FF
H'007FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 7
External
address
space
Vector area
On-chip RAM
*2
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'01FFFF
H'020000
H'FFEF0F
H'FFEF10
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'017FFF
H'018000
H'FF8000
Area 6
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Figure 3-3 H8/3044 Memory Map in Each Operating Mode
H'00000
H'000FF
H'07FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip RAM
*2
Reserved
*1
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'FEF10
H'FF70F
H'FF710
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
On-chip RAM
*2
Reserved
*1
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FF8000
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Notes:1.2.Do not access the reserved area.
External addresses can be accessed by disabling on-chip RAM.
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Figure 3-3 H8/3044 Memory Map in Each Operating Mode (cont)
H'00000
H'000FF
H'07FFF
H'08000
Memory-indirect
branch addresses
16-bit absolute
addresses
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Mode 7
(single-chip advanced mode)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip ROM
On-chip RAM
*2
Reserved
*1
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'DFFFF
H'E0000
H'FEF10
H'FF70F
H'FF710
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
H'00000
H'000FF
Memory-indirect
branch addresses
16-bit absolute
addresses
Vector area
On-chip ROM
On-chip RAM
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FF710
H'FFF00
H'FFF0F
H'FFF1C
H'FFFFF
H'07FFF
H'F8000
Notes:
Reserved
*1
1.2.Do not access the reserved area.
External addresses can be accessed by disabling on-chip RAM.
H'000000
H'0000FF
H'007FFF
H'008000
H'01FFFF
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
On-chip RAM
*2
Reserved
*1
On-chip ROM
Reserved
*1
H'FF8000
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Figure 3-4 H8/3045 Memory Map in Each Operating Mode
68
H'00000
H'000FF
H'07FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
Modes 1 and 2
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip RAM
*2
Reserved
*1
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'FEF10
H'FF70F
H'FF710
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Modes 3 and 4
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
On-chip RAM
*2
Reserved
*1
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FF8000
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Notes:1.2.Do not access the reserved area.
External addresses can be accessed by disabling on-chip RAM.
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Figure 3-4 H8/3045 Memory Map in Each Operating Mode (cont)
69
H'00000
H'000FF
H'07FFF
H'0FFFF
H'10000
Memory-indirect
branch addresses
16-bit absolute
addresses
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Mode 7
(single-chip advanced mode)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip ROM
On-chip RAM
*2
Reserved
*1
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'F8000
H'DFFFF
H'E0000
H'FEF10
H'FF70F
H'FF710
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
H'00000
H'000FF
Memory-indirect
branch addresses
16-bit absolute
addresses
Vector area
On-chip ROM
On-chip RAM
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FF710
H'FFF00
H'FFF0F
H'FFF1C
H'FFFFF
H'07FFF
H'0FFFF
H'F8000
Notes:
Reserved
*1
1.2.Do not access the reserved area.
External addresses can be accessed by disabling on-chip RAM.
H'000000
H'0000FF
H'007FFF
H'00FFFF
H'010000
H'01FFFF
H'020000
Memory-indirect
branch addresses
16-bit absolute
addresses
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
External
address
space
On-chip
registers
8-bit absolute addresses
16-bit absolute addresses
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
On-chip RAM
*2
Reserved
*1
On-chip ROM
Reserved
*1
H'FF8000
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Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4-1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the RES pin
Interrupt Interrupt requests are handled when execution of the current
instruction or handling of the current exception is completed
Low Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2. The CCR interrupt mask bit is set to 1.
3. A vector address corresponding to the exception source is generated, and program execution
starts from the address indicated in that address.
For a reset exception, steps 2 and 3 above are carried out.
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4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4-1. Different vectors are assigned to
different exception sources. Table 4-2 lists the exception sources and their vector addresses.
Figure 4-1 Exception Sources
Table 4-2 Exception Vector Table
Exception Source Vector Number Vector Address
*
1
Reset 0 H'0000 to H'0003
Reserved for system use 1 H'0004 to H'0007
2 H'0008 to H'000B
3 H'000C to H'000F
4 H'0010 to H'0013
5 H'0014 to H'0017
6 H'0018 to H'001B
External interrupt (NMI) 7 H'001C to H'001F
Trap instruction (4 sources) 8 H'0020 to H'0023
9 H'0024 to H'0027
10 H'0028 to H'002B
11 H'002C to H'002F
External interrupt IRQ
0
12 H'0030 to H'0033
External interrupt IRQ
1
13 H'0034 to H'0037
External interrupt IRQ
2
14 H'0038 to H'003B
External interrupt IRQ
3
15 H'003C to H'003F
External interrupt IRQ
4
16 H'0040 to H'0043
External interrupt IRQ
5
17 H'0044 to H'0047
Reserved for system use 18 H'0048 to H'004B
19 H'004C to H'004F
Internal interrupts
*
2
20 H'0050 to H'0053
to to
60 H'00F0 to H'00F3
Notes: 1. Lower 16 bits of the address.
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.
Exception
sources
• Reset
• Interrupts
• Trap instruction
External interrupts:
Internal interrupts:
NMI, IRQ to IRQ
30 interrupts from on-chip
supporting modules
0 5
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4.2 Reset
4.2.1 Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the
on-chip supporting modules. Reset exception handling begins when the RES pin changes from
low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer.
4.2.2 Reset Sequence
The chip enters the reset state when the RES pin goes low.
To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the
chip during operation, hold the RES pin low for at least 10 system clock (ø) cycles. See appendix
D.2, Pin States at Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows.
• The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
• The contents of the reset vector address (H'0000 to H'0003) are read, and program execution
starts from the address indicated in the vector address.
Figure 4-2 shows the reset sequence in modes 1 and 3. Figure 4-3 shows the reset sequence in
modes 2 and 4. Figure 4-4 shows the reset sequence in mode 6.
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Figure 4-2 Reset Sequence (Modes 1 and 3)
ø
Address
bus
RES
RD
HWR
D to D
15 8
Vector fetch
Internal
processing
Prefetch of
first program
instruction
(1), (3), (5), (7)
(2), (4), (6), (8)
(9)
(10)
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Address of reset vector: (1) = H'00000, (3) = H'00001, (5) = H'00002, (7) = H'00003
Start address (contents of reset vector)
Start address
First instruction of program
High
(1) (3) (5) (7)
(9)
(2) (4) (6) (8) (10)
LWR,
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Figure 4-3 Reset Sequence (Modes 2 and 4)
ø
Address bus
RES
RD
HWR
D to D
15 0
Vector fetch
Internal
processing
Prefetch of first
program instruction
(1), (3)
(2), (4)
(5)
(6)
Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
High
LWR,
Address of reset vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset vector)
Start address
First instruction of program
(2) (4)
(3)(1) (5)
(6)
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Figure 4-4 Reset Sequence (Mode 5, 6 and 7)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. The first instruction of the program is
always executed immediately after the reset state ends. This instruction should initialize the stack
pointer (example: MOV.L #xx:32, SP).
Vector fetch
Internal
processing
Prefetch of
first program
instruction
ø
Internal
address bus
RES
Internal
read signal
Internal
write signal
Internal
data bus
(16 bits wide)
(1) (3) (5)
(2) (4) (6)
(1), (3)
(2), (4)
(5)
(6)
Address of reset vector ((1) = H'000000, (2) = H'000002)
Start address (contents of reset vector)
Start address
First instruction of program
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4.3 Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ0to IRQ5) and
30 internal sources in the on-chip supporting modules. Figure 4-5 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),
refresh controller, 16-bit integrated timer unit (ITU), DMA controller (DMAC), serial
communication interface (SCI), and A/D converter. Each interrupt source has a separate vector
address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Figure 4-5 Interrupt Sources and Number of Interrupts
Interrupts
External interrupts
Internal interrupts
NMI (1)
IRQ to IRQ (6)
WDT (1)
Refresh controller (1)
ITU (15)
DMAC (4)
SCI (8)
A/D converter (1)
*1
*2
Notes: Numbers in parentheses are the number of interrupt sources.
1.2.When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
When the refresh controller is used as an interval timer, it generates an interrupt
request at compare match.
0 5
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4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
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4.5 Stack Status after Exception Handling
Figure 4-6 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Figure 4-6 Stack after Completion of Exception Handling
SP-4
SP-3
SP-2
SP-1
SP (ER7)
→
SP (ER7)
SP+1
SP+2
SP+3
SP+4
→
Before exception handling After exception handling
Stack area
CCR
PC
PC
PC
E
H
L
Even address
Pushed on stack
Legend
PCE:
PCH:
PCL:
CCR:
SP:
Notes: PC indicates the address of the first instruction that will be executed after return.
Registers must be saved in word or longword size at even addresses.
1.
2.
Bits 23 to 16 of program counter (PC)
Bits 15 to 8 of program counter (PC)
Bits 7 to 0 of program counter (PC)
Condition code register
Stack pointer
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4.6 Notes on Stack Usage
When accessing word data or longword data, the H8/3048 Series regards the lowest address bit as
0. The stack should always be accessed by word access or longword access, and the value of the
stack pointer (SP, ER7) should always be kept even. Use the following instructions to save
registers:
PUSH.W Rn (or MOV.W Rn, @–SP)
PUSH.L ERn (or MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4-7 shows an example of what
happens when the SP value is odd.
Figure 4-7 Operation when SP Value is Odd
TRAPA instruction executed
CCR
Legend
CCR:
PC:
R1L:
SP:
SP
PC
R1L
PC
SP
SP
MOV. B R1L, @-ER7
SP set to H'FFFEFF Data saved above SP CCR contents lost
Condition code register
Program counter
General register R1L
Stack pointer
Note: The diagram illustrates modes 3 and 4.
H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFF
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Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level masking by the I and UI bits in the CPU condition code register (CCR)
• Independent vector addresses
All interrupts are independently vectored; the interrupt service routine does not have to
identify the interrupt source.
• Seven external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ0to IRQ5, sensing of the falling edge or level sensing can be
selected independently.
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5.1.2 Block Diagram
Figure 5-1 shows a block diagram of the interrupt controller.
Figure 5-1 Interrupt Controller Block Diagram
ISCR IER IPRA, IPRB
.
.
.
OVF
TME
ADI
ADIE
.
.
.
.
.
.
.
CPU
CCR
I
UI
UE
SYSCR
ISCR:
IER:
ISR:
IPRA:
IPRB:
SYSCR:
NMI
input
IRQ input
IRQ input
section ISR
Interrupt controller
Priority
decision logic
Interrupt
request
Vector
number
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt priority register A
Interrupt priority register B
System control register
Legend
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5.1.3 Pin Configuration
Table 5-1 lists the interrupt pins.
Table 5-1 Interrupt Pins
Name Abbreviation I/O Function
Nonmaskable interrupt NMI Input Nonmaskable interrupt, rising edge or
falling edge selectable
External interrupt request 5 to 0 IRQ
5
to IRQ0Input Maskable interrupts, falling edge or
level sensing selectable
5.1.4 Register Configuration
Table 5-2 lists the registers of the interrupt controller.
Table 5-2 Interrupt Controller Registers
Address
*
1
Name Abbreviation R/W Initial Value
H'FFF2 System control register SYSCR R/W H'0B
H'FFF4 IRQ sense control register ISCR R/W H'00
H'FFF5 IRQ enable register IER R/W H'00
H'FFF6 IRQ status register ISR R/(W)
*
2
H'00
H'FFF8 Interrupt priority register A IPRA R/W H'00
H'FFF9 Interrupt priority register B IPRB R/W H'00
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
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5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
Software standby
Standby timer
select 2 to 0
User bit enable
Selects whether to use the UI bit in
CCR as a user bit or interrupt mask bit
NMI edge select
Selects the NMI input edge
Reserved bit
RAM enable
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as interrupt mask bit
1 UI bit in CCR is used as user bit (Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG Description
0 Interrupt is requested at falling edge of NMI input (Initial value)
1 Interrupt is requested at rising edge of NMI input
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
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Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which
interrupt priority levels can be set.
IPRA is initialized to H'00 by a reset and in hardware standby mode.
Bit
Initial value
Read/Write
7
IPRA7
0
R/W
6
IPRA6
0
R/W
5
IPRA5
0
R/W
4
IPRA4
0
R/W
3
IPRA3
0
R/W
0
IPRA0
0
R/W
2
IPRA2
0
R/W
1
IPRA1
0
R/W
Priority level A7
Selects the priority level of IRQ interrupt requests
Priority level A3
Selects the priority level of WDT and
refresh controller interrupt requests
Priority level A2
Selects the priority level of
ITU channel 0 interrupt requests
Priority level A1
Selects the priority level
of ITU channel 1
interrupt requests
Priority
level A0
Selects the
priority level
of ITU
channel 2
interrupt
requests
Selects the priority level of IRQ interrupt requests
Priority level A6
Selects the priority level of IRQ and IRQ interrupt requests
Priority level A5
Selects the priority level of IRQ and IRQ
interrupt requests
Priority level A4
0
1
23
45
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