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Hitachi Single-Chip Microcomputer
H8/3022 Series
H8/3022, H8/3021, H8/3020
TM
H8/3022 F-ZTAT
Hardware Manual
ADE-602-179
Rev. 1.0
12/6/99
Hitachi,Ltd
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
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Preface
The H8/3022 Series comprises high-performance single-chip microcomputers (MCUs) that
integrate system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities. Of the two SCI
channels, one has been expanded to support the ISO/IEC 7816-3 smart card interface. Functions
have also been added to reduce power consumption in battery-powered applications: individual
modules can be placed in standby, and the frequency of the system clock supplied to the chip can
be divided down under software control.
The five MCU operating modes offer a choice of expanded mode, single-chip mode, and address
space size, enabling the H8/3022 Series to adapt quickly and flexibly to a variety of conditions.
In addition to its masked-ROM versions, the H8/3022 Series has an F-ZTATTM* version with user
programmable on-chip flash memory that can be programmed on-board. These versions enable
users to respond quickly and flexibly to changing application specifications.
This manual describes the H8/3022 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.
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Contents
Section 1 Overview............................................................................................................ 1
1.1 Overview............................................................................................................................ 1
1.2 Block Diagram.................................................................................................................... 5
1.3 Pin Description................................................................................................................... 6
1.3.1 Pin Arrangement ................................................................................................... 6
1.3.2 Pin Functions......................................................................................................... 7
1.4 Pin Functions...................................................................................................................... 11
Section 2 CPU...................................................................................................................... 15
2.1 Overview............................................................................................................................ 15
2.1.1 Features ................................................................................................................. 15
2.1.2 Differences from H8/300 CPU.............................................................................. 16
2.2 CPU Operating Modes ....................................................................................................... 17
2.3 Address Space.................................................................................................................... 18
2.4 Register Configuration.......................................................................................................19
2.4.1 Overview............................................................................................................... 19
2.4.2 General Registers.................................................................................................. 20
2.4.3 Control Registers................................................................................................... 21
2.4.4 Initial CPU Register Values.................................................................................. 22
2.5 Data Formats...................................................................................................................... 23
2.5.1 General Register Data Formats ............................................................................. 23
2.5.2 Memory Data Formats .......................................................................................... 24
2.6 Instruction Set .................................................................................................................... 26
2.6.1 Instruction Set Overview ...................................................................................... 26
2.6.2 Instructions and Addressing Modes...................................................................... 27
2.6.3 Tables of Instructions Classified by Function....................................................... 29
2.6.4 Basic Instruction Formats...................................................................................... 39
2.6.5 Notes on Use of Bit Manipulation Instructions .................................................... 40
2.7 Addressing Modes and Effective Address Calculation...................................................... 41
2.7.1 Addressing Modes................................................................................................. 41
2.7.2 Effective Address Calculation............................................................................... 43
2.8 Processing States................................................................................................................ 47
2.8.1 Overview............................................................................................................... 47
2.8.2 Program Execution State....................................................................................... 48
2.8.3 Exception-Handling State ..................................................................................... 48
2.8.4 Exception-Handling Sequences ............................................................................ 50
2.8.5 Reset State............................................................................................................. 51
2.8.6 Power-Down State ................................................................................................ 51
2.9 Basic Operational Timing.................................................................................................. 52
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2.9.1 Overview............................................................................................................... 52
2.9.2 On-Chip Memory Access Timing......................................................................... 52
2.9.3 On-Chip Supporting Module Access Timing........................................................ 53
2.9.4 Access to External Address Space........................................................................ 54
Section 3 MCU Operating Modes................................................................................. 55
3.1 Overview............................................................................................................................ 55
3.1.1 Operating Mode Selection .................................................................................... 55
3.1.2 Register Configuration.......................................................................................... 56
3.2 Mode Control Register (MDCR)........................................................................................ 57
3.3 System Control Register (SYSCR).................................................................................... 58
3.4 Operating Mode Descriptions............................................................................................ 60
3.4.1 Mode 1 .................................................................................................................. 60
3.4.2 Mode 3 .................................................................................................................. 60
3.4.3 Mode 5 .................................................................................................................. 60
3.4.4 Mode 6 .................................................................................................................. 60
3.4.5 Mode 7 .................................................................................................................. 60
3.5 Pin Functions in Each Operating Mode.............................................................................. 61
3.6 Memory Map in Each Operating Mode.............................................................................. 61
Section 4 Exception Handling........................................................................................ 69
4.1 Overview............................................................................................................................ 69
4.1.1 Exception Handling Types and Priority................................................................ 69
4.1.2 Exception Handling Operation.............................................................................. 69
4.1.3 Exception Vector Table ........................................................................................ 70
4.2 Reset................................................................................................................................... 72
4.2.1 Overview............................................................................................................... 72
4.2.2 Reset Sequence...................................................................................................... 72
4.2.3 Interrupts after Reset............................................................................................. 74
4.3 Interrupts............................................................................................................................ 74
4.4 Trap Instruction.................................................................................................................. 75
4.5 Stack Status after Exception Handling............................................................................... 75
4.6 Notes on Stack Usage.........................................................................................................76
Section 5 Interrupt Controller......................................................................................... 77
5.1 Overview............................................................................................................................ 77
5.1.1 Features ................................................................................................................. 77
5.1.2 Block Diagram...................................................................................................... 78
5.1.3 Pin Configuration.................................................................................................. 79
5.1.4 Register Configuration.......................................................................................... 79
5.2 Register Descriptions.......................................................................................................... 80
5.2.1 System Control Register (SYSCR)....................................................................... 80
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB).............................................. 82
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5.2.3 IRQ Status Register (ISR)..................................................................................... 87
5.2.4 IRQ Enable Register (IER) ................................................................................... 88
5.2.5 IRQ Sense Control Register (ISCR)...................................................................... 89
5.3 Interrupt Sources................................................................................................................ 90
5.3.1 External Interrupts................................................................................................. 90
5.3.2 Internal Interrupts.................................................................................................. 91
5.3.3 Interrupt Vector Table........................................................................................... 91
5.4 Interrupt Operation............................................................................................................. 94
5.4.1 Interrupt Handling Process.................................................................................... 94
5.4.2 Interrupt Sequence ................................................................................................ 99
5.4.3 Interrupt Response Time....................................................................................... 100
5.5 Usage Notes........................................................................................................................ 101
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction....................... 101
5.5.2 Instructions that Inhibit Interrupts......................................................................... 102
5.5.3 Interrupts during EEPMOV Instruction Execution............................................... 102
5.5.4 Usage Notes .......................................................................................................... 102
Section 6 Bus Controller.................................................................................................. 105
6.1 Overview............................................................................................................................ 105
6.1.1 Features ................................................................................................................. 105
6.1.2 Block Diagram...................................................................................................... 106
6.1.3 Pin Configuration.................................................................................................. 107
6.1.4 Register Configuration.......................................................................................... 107
6.2 Register Descriptions.......................................................................................................... 108
6.2.1 Access State Control Register (ASTCR) .............................................................. 108
6.2.2 Wait Control Register (WCR)............................................................................... 109
6.2.3 Wait State Controller Enable Register (WCER)................................................... 110
6.2.4 Address Control Register (ADRCR)..................................................................... 111
6.3 Operation............................................................................................................................ 113
6.3.1 Area Division........................................................................................................ 113
6.3.2 Bus Control Signal Timing ................................................................................... 115
6.3.3 Wait Modes........................................................................................................... 117
6.3.4 Interconnections with Memory (Example)............................................................ 123
6.4 Usage Notes........................................................................................................................ 125
6.4.1 Register Write Timing .......................................................................................... 125
6.4.2 Precautions on setting ASTCR and ABWCR*..................................................... 125
Section 7 I/O Ports ............................................................................................................. 127
7.1 Overview............................................................................................................................ 127
7.2 Port 1.................................................................................................................................. 131
7.2.1 Overview............................................................................................................... 131
7.2.2 Register Descriptions............................................................................................ 131
7.2.3 Pin Functions in Each Mode ................................................................................. 133
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7.3 Port 2.................................................................................................................................. 135
7.3.1 Overview............................................................................................................... 135
7.3.2 Register Descriptions............................................................................................ 136
7.3.3 Pin Functions in Each Mode ................................................................................. 138
7.3.4 Input Pull-Up Transistors...................................................................................... 140
7.4 Port 3.................................................................................................................................. 141
7.4.1 Overview............................................................................................................... 141
7.4.2 Register Descriptions............................................................................................ 141
7.4.3 Pin Functions in Each Mode ................................................................................. 143
7.5 Port 5.................................................................................................................................. 144
7.5.1 Overview............................................................................................................... 144
7.5.2 Register Descriptions............................................................................................ 144
7.5.3 Pin Functions in Each Mode ................................................................................. 147
7.5.4 Input Pull-Up Transistors...................................................................................... 148
7.6 Port 6.................................................................................................................................. 149
7.6.1 Overview............................................................................................................... 149
7.6.2 Register Descriptions............................................................................................ 149
7.6.3 Pin Functions in Each Mode ................................................................................. 152
7.7 Port 7.................................................................................................................................. 155
7.7.1 Overview............................................................................................................... 155
7.7.2 Register Description.............................................................................................. 155
7.8 Port 8.................................................................................................................................. 156
7.8.1 Overview............................................................................................................... 156
7.8.2 Register Descriptions............................................................................................ 157
7.8.3 Pin Functions......................................................................................................... 158
7.9 Port 9.................................................................................................................................. 159
7.9.1 Overview............................................................................................................... 159
7.9.2 Register Descriptions............................................................................................ 159
7.9.3 Pin Functions......................................................................................................... 160
7.10 Port A.................................................................................................................................. 163
7.10.1 Overview ............................................................................................................... 163
7.10.2 Register Descriptions ............................................................................................ 164
7.10.3 Pin Functions......................................................................................................... 166
7.11 Port B.................................................................................................................................. 173
7.11.1 Overview ............................................................................................................... 173
7.11.2 Register Descriptions ............................................................................................ 173
7.11.3 Pin Functions......................................................................................................... 175
Section 8 16-Bit Integrated Timer Unit (ITU)........................................................... 181
8.1 Overview............................................................................................................................ 181
8.1.1 Features ................................................................................................................. 181
8.1.2 Block Diagrams..................................................................................................... 184
8.1.3 Pin Configuration.................................................................................................. 189
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8.1.4 Register Configuration.......................................................................................... 191
8.2 Register Descriptions.......................................................................................................... 194
8.2.1 Timer Start Register (TSTR)................................................................................. 194
8.2.2 Timer Synchro Register (TSNC) .......................................................................... 195
8.2.3 Timer Mode Register (TMDR) ............................................................................. 197
8.2.4 Timer Function Control Register (TFCR) ............................................................ 200
8.2.5 Timer Output Master Enable Register (TOER).................................................... 202
8.2.6 Timer Output Control Register (TOCR)............................................................... 205
8.2.7 Timer Counters (TCNT)........................................................................................ 206
8.2.8 General Registers (GRA, GRB)............................................................................ 207
8.2.9 Buffer Registers (BRA, BRB) .............................................................................. 208
8.2.10 Timer Control Registers (TCR) ............................................................................ 209
8.2.11 Timer I/O Control Register (TIOR)...................................................................... 212
8.2.12 Timer Status Register (TSR)................................................................................. 214
8.2.13 Timer Interrupt Enable Register (TIER) ............................................................... 216
8.3 CPU Interface..................................................................................................................... 218
8.3.1 16-Bit Accessible Registers .................................................................................. 218
8.3.2 8-Bit Accessible Registers .................................................................................... 220
8.4 Operation............................................................................................................................ 221
8.4.1 Overview............................................................................................................... 221
8.4.2 Basic Functions..................................................................................................... 222
8.4.3 Synchronization .................................................................................................... 232
8.4.4 PWM Mode........................................................................................................... 234
8.4.5 Reset-Synchronized PWM Mode.......................................................................... 238
8.4.6 Complementary PWM Mode................................................................................ 241
8.4.7 Phase Counting Mode ........................................................................................... 251
8.4.8 Buffering ............................................................................................................... 253
8.4.9 ITU Output Timing ............................................................................................... 260
8.5 Interrupts............................................................................................................................ 262
8.5.1 Setting of Status Flags........................................................................................... 262
8.5.2 Clearing of Status Flags........................................................................................ 264
8.5.3 Interrupt Sources ................................................................................................... 265
8.6 Usage Notes........................................................................................................................ 266
Section 9 Programmable Timing Pattern Controller................................................ 281
9.1 Overview............................................................................................................................ 281
9.1.1 Features ................................................................................................................. 281
9.1.2 Block Diagram...................................................................................................... 282
9.1.3 Pin Configuration.................................................................................................. 283
9.1.4 Register Configuration.......................................................................................... 284
9.2 Register Descriptions.......................................................................................................... 285
9.2.1 Port A Data Direction Register (PADDR)............................................................ 285
9.2.2 Port A Data Register (PADR)............................................................................... 285
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9.2.3 Port B Data Direction Register (PBDDR) ............................................................ 286
9.2.4 Port B Data Register (PBDR)................................................................................ 286
9.2.5 Next Data Register A (NDRA) ............................................................................. 287
9.2.6 Next Data Register B (NDRB).............................................................................. 289
9.2.7 Next Data Enable Register A (NDERA)............................................................... 291
9.2.8 Next Data Enable Register B (NDERB) ............................................................... 292
9.2.9 TPC Output Control Register (TPCR).................................................................. 293
9.2.10 TPC Output Mode Register (TPMR).................................................................... 296
9.3 Operation............................................................................................................................ 298
9.3.1 Overview............................................................................................................... 298
9.3.2 Output Timing....................................................................................................... 299
9.3.3 Normal TPC Output.............................................................................................. 300
9.3.4 Non-Overlapping TPC Output.............................................................................. 302
9.4 Usage Notes........................................................................................................................ 305
9.4.1 Operation of TPC Output Pins.............................................................................. 305
9.4.2 Note on Non-Overlapping Output......................................................................... 305
Section 10 Watchdog Timer.............................................................................................. 307
10.1 Overview............................................................................................................................ 307
10.1.1 Features ................................................................................................................. 307
10.1.2 Block Diagram ...................................................................................................... 308
10.1.3 Pin Configuration.................................................................................................. 308
10.1.4 Register Configuration.......................................................................................... 309
10.2 Register Descriptions.......................................................................................................... 310
10.2.1 Timer Counter (TCNT) ......................................................................................... 310
10.2.2 Timer Control/Status Register (TCSR)................................................................. 311
10.2.3 Reset Control/Status Register (RSTCSR)............................................................. 313
10.2.4 Notes on Register Access...................................................................................... 315
10.3 Operation............................................................................................................................ 317
10.3.1 Watchdog Timer Operation .................................................................................. 317
10.3.2 Interval Timer Operation ...................................................................................... 318
10.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 319
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ................................... 320
10.4 Interrupts ............................................................................................................................ 321
10.5 Usage Notes........................................................................................................................ 321
Section 11 Serial Communication Interface................................................................. 323
11.1 Overview............................................................................................................................ 323
11.1.1 Features ................................................................................................................. 323
11.1.2 Block Diagram...................................................................................................... 325
11.1.3 Pin Configuration.................................................................................................. 326
11.1.4 Register Configuration.......................................................................................... 326
11.2 Register Descriptions.......................................................................................................... 327
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11.2.1 Receive Shift Register (RSR)................................................................................ 327
11.2.2 Receive Data Register (RDR) ............................................................................... 327
11.2.3 Transmit Shift Register (TSR) .............................................................................. 328
11.2.4 Transmit Data Register (TDR).............................................................................. 328
11.2.5 Serial Mode Register (SMR)................................................................................. 329
11.2.6 Serial Control Register (SCR)............................................................................... 333
11.2.7 Serial Status Register (SSR).................................................................................. 337
11.2.8 Bit Rate Register (BRR)........................................................................................ 341
11.3 Operation............................................................................................................................ 350
11.3.1 Overview ............................................................................................................... 350
11.3.2 Operation in Asynchronous Mode ........................................................................ 352
11.3.3 Multiprocessor Communication............................................................................ 361
11.3.4 Synchronous Operation......................................................................................... 368
11.4 SCI Interrupts ..................................................................................................................... 377
11.5 Usage Notes........................................................................................................................ 378
Section 12 Smart Card Interface ...................................................................................... 383
12.1 Overview............................................................................................................................ 383
12.1.1 Features ................................................................................................................. 383
12.1.2 Block Diagram...................................................................................................... 384
12.1.3 Pin Configuration.................................................................................................. 385
12.1.4 Register Configuration.......................................................................................... 385
12.2 Register Descriptions.......................................................................................................... 386
12.2.1 Smart Card Mode Register (SCMR)..................................................................... 386
12.2.2 Serial Status Register (SSR).................................................................................. 388
12.3 Operation............................................................................................................................ 390
12.3.1 Overview............................................................................................................... 390
12.3.2 Pin Connections .................................................................................................... 390
12.3.3 Data Format........................................................................................................... 392
12.3.4 Register Settings.................................................................................................... 394
12.3.5 Clock ..................................................................................................................... 396
12.3.6 Data Transfer Operations...................................................................................... 398
12.4 Usage Note ......................................................................................................................... 404
Section 13 A/D Converter.................................................................................................. 407
13.1 Overview............................................................................................................................ 407
13.1.1 Features ................................................................................................................. 407
13.1.2 Block Diagram ...................................................................................................... 408
13.1.3 Pin Configuration.................................................................................................. 409
13.1.4 Register Configuration.......................................................................................... 410
13.2 Register Descriptions.......................................................................................................... 411
13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 411
13.2.2 A/D Control/Status Register (ADCSR) ................................................................ 412
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13.2.3 A/D Control Register (ADCR).............................................................................. 415
13.3 CPU Interface..................................................................................................................... 416
13.4 Operation............................................................................................................................ 417
13.4.1 Single Mode (SCAN = 0)...................................................................................... 417
13.4.2 Scan Mode (SCAN = 1)........................................................................................ 419
13.4.3 Input Sampling and A/D Conversion Time .......................................................... 421
13.4.4 External Trigger Input Timing.............................................................................. 422
13.5 Interrupts ............................................................................................................................ 423
13.6 Usage Notes .......................................................................................................................... 423
Section 14 RAM.................................................................................................................... 429
14.1 Overview............................................................................................................................ 429
14.1.1 Block Diagram ...................................................................................................... 430
14.1.2 Register Configuration.......................................................................................... 430
14.2 System Control Register (SYSCR) .................................................................................... 431
14.3 Operation............................................................................................................................ 432
Section 15 ROM.................................................................................................................... 433
15.1 Features .............................................................................................................................. 433
15.2 Overview............................................................................................................................ 434
15.2.1 Block Diagram...................................................................................................... 434
15.2.2 Mode Transitions .................................................................................................. 435
15.2.3 On-Board Programming Modes............................................................................ 436
15.2.4 Flash Memory Emulation in RAM........................................................................ 438
15.2.5 Differences between Boot Mode and User Program Mode.................................. 439
15.2.6 Block Configuration.............................................................................................. 440
15.3 Pin Configuration ............................................................................................................... 440
15.4 Register Configuration ....................................................................................................... 441
15.5 Register Descriptions.......................................................................................................... 441
15.5.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 441
15.5.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 444
15.5.3 Erase Block Register 1 (EBR1) ............................................................................ 445
15.5.4 Erase Block Register 2 (EBR2) ............................................................................ 446
15.5.5 RAM Emulation Register (RAMER).................................................................... 447
15.5.6 Differences from H8/3039 F-ZTAT Series........................................................... 449
15.6 On-Board Programming Modes ......................................................................................... 450
15.6.1 Boot Mode............................................................................................................. 451
15.6.2 User Program Mode.............................................................................................. 456
15.7 Programming/Erasing Flash Memory ................................................................................ 458
15.7.1 Program Mode....................................................................................................... 459
15.7.2 Program-Verify Mode........................................................................................... 460
15.7.3 Notes on Program/Program-Verify Procedure...................................................... 460
15.7.4 Erase Mode............................................................................................................ 465
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15.7.5 Erase-Verify Mode................................................................................................ 465
15.8 Protection............................................................................................................................ 467
15.8.1 Hardware Protection.............................................................................................. 467
15.8.2 Software Protection............................................................................................... 468
15.8.3 Error Protection..................................................................................................... 469
15.8.4 NMI Input Disable Conditions.............................................................................. 471
15.9 Flash Memory Emulation in RAM..................................................................................... 472
15.10 Flash Memory PROM Mode.............................................................................................. 474
15.10.1 Socket Adapters and Memory Map ...................................................................... 474
15.10.2 Notes on Use of PROM Mode .............................................................................. 475
15.11 Notes on Flash Memory Programming/Erasing................................................................. 476
15.12 Overview of Mask ROM.................................................................................................... 482
15.12.1 Block Diagram...................................................................................................... 482
15.13 Notes on Ordering Mask ROM Version Chips.................................................................. 483
15.14 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions 484
Section 16 Clock Pulse Generator ................................................................................... 485
16.1 Overview............................................................................................................................ 485
16.1.1 Block Diagram ...................................................................................................... 486
16.2 Oscillator Circuit................................................................................................................ 487
16.2.1 Connecting a Crystal Resonator............................................................................ 487
16.2.2 External Clock Input ............................................................................................. 489
16.3 Duty Adjustment Circuit.................................................................................................... 492
16.4 Prescalers............................................................................................................................ 492
16.5 Frequency Divider.............................................................................................................. 492
16.5.1 Register Configuration.......................................................................................... 492
16.5.2 Division Control Register (DIVCR) ..................................................................... 493
16.5.3 Usage Notes .......................................................................................................... 493
Section 17 Power-Down State.......................................................................................... 495
17.1 Overview............................................................................................................................ 495
17.2 Register Configuration ....................................................................................................... 497
17.2.1 System Control Register (SYSCR) ....................................................................... 497
17.2.2 Module Standby Control Register (MSTCR)........................................................ 499
17.3 Sleep Mode......................................................................................................................... 501
17.3.1 Transition to Sleep Mode...................................................................................... 501
17.3.2 Exit from Sleep Mode ........................................................................................... 501
17.4 Software Standby Mode ..................................................................................................... 502
17.4.1 Transition to Software Standby Mode .................................................................. 502
17.4.2 Exit from Software Standby Mode........................................................................ 502
17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode... 503
17.4.4 Sample Application of Software Standby Mode................................................... 504
17.4.5 Usage Note............................................................................................................ 504
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17.5 Hardware Standby Mode.................................................................................................... 505
17.5.1 Transition to Hardware Standby Mode................................................................. 505
17.5.2 Exit from Hardware Standby Mode...................................................................... 505
17.5.3 Timing for Hardware Standby Mode.................................................................... 505
17.6 Module Standby Function.................................................................................................. 506
17.6.1 Module Standby Timing........................................................................................ 506
17.6.2 Read/Write in Module Standby............................................................................. 506
17.6.3 Usage Notes .......................................................................................................... 506
17.7 System Clock Output Disabling Function.......................................................................... 507
Section 18 Electrical Characteristics............................................................................... 509
18.1 Electrical characteristics of Masked ROM Version........................................................... 509
18.1.1 Absolute Maximum Ratings.................................................................................. 509
18.1.2 DC Characteristics ................................................................................................ 510
18.1.3 AC Characteristics ................................................................................................ 514
18.1.4 A/D Conversion Characteristics............................................................................ 519
18.2 Electrical characteristics of Flash Memory Version .......................................................... 520
18.2.1 Absolute Maximum Ratings.................................................................................. 520
18.2.2 DC Characteristics ................................................................................................ 521
18.2.3 AC Characteristics ................................................................................................ 525
18.2.4 A/D Conversion Characteristics............................................................................ 530
18.2.5 Flash Memory Characteristics .............................................................................. 531
18.3 Operational Timing ............................................................................................................ 532
18.3.1 Bus Timing............................................................................................................ 532
18.3.2 Control Signal Timing .......................................................................................... 536
18.3.3 Clock Timing ........................................................................................................ 538
18.3.4 TPC and I/O Port Timing...................................................................................... 538
18.3.5 ITU Timing ........................................................................................................... 539
18.3.6 SCI Input/Output Timing...................................................................................... 540
Appendix A Instruction Set............................................................................................... 541
A.1 Instruction List.................................................................................................................... 541
A.2 Operation Code Maps......................................................................................................... 556
A.3 Number of States Required for Execution.......................................................................... 559
Appendix B Internal I/O Register Field........................................................................ 569
B.1 Addresses............................................................................................................................ 569
B.2 Function.............................................................................................................................. 576
Appendix C I/O Block Diagrams.................................................................................... 635
C.1 Port 1 Block Diagram......................................................................................................... 635
C.2 Port 2 Block Diagram......................................................................................................... 636
C.3 Port 3 Block Diagram......................................................................................................... 637
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C.4 Port 5 Block Diagram......................................................................................................... 638
C.5 Port 6 Block Diagrams ....................................................................................................... 639
C.6 Port 7 Block Diagram......................................................................................................... 641
C.7 Port 8 Block Diagrams ....................................................................................................... 642
C.8 Port 9 Block Diagrams ....................................................................................................... 644
C.9 Port A Block Diagrams...................................................................................................... 648
C.10 Port B Block Diagrams ...................................................................................................... 651
Appendix D Pin States........................................................................................................ 654
D.1 Port States in Each Mode ................................................................................................... 654
D.2 Pin States at Reset .............................................................................................................. 656
Appendix E Timing of Transition to and Recovery
from Hardware Standby Mode
................................................................ 659
Appendix F Product Code Lineup.................................................................................. 660
Appendix G Package Dimensions................................................................................... 661
Appendix H Comparison of H8/300H Series Product Specifications.................. 663
H.1 Differences between H8/3039F and H8/3022F.................................................................. 663
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Section 1 Overview
1.1 Overview
The H8/3022 Series comprises microcomputers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core featuring an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities.
The H8/3022 Series consists of four models: the H8/3022 with 256 kbytes of ROM and 8 kbytes
of RAM, the H8/3021 with 192 kbytes of ROM and 8 kbytes of RAM, and the H8/3020 with 128
kbytes of ROM and 4 kbytes of RAM.
The five MCU operating modes offer a choice of expanded mode, single-chip mode and address
space size.
In addition to the masked-ROM version of the H8/3022 Series, an F-ZTATTM* version with an onchip flash memory that can be freely programmed and reprogrammed by the user after the board is
installed is also available. This version enables users to respond quickly and flexibly to changing
application specifications, growing production volumes, and other conditions.
Table 1-1 summarizes the features of the H8/3022 Series.
Note: * F-ZTAT (Flexible ZTAT) is a trademark of Hitachi, Ltd.
1
Page 16
Table 1-1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 18 MHz
• Add/subtract: 111 ns
• Multiply/divide: 778 ns
Two CPU operating modes
• Normal mode (64-kbyte address space)*
• Advanced mode (16-Mbyte address space)
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit positions
Memory H8/3022
• ROM: 256 kbytes
• RAM: 8 kbytes
H8/3021
• ROM: 192 kbytes
• RAM: 8 kbytes
H8/3020
• ROM: 128 kbytes
• RAM: 4 kbytes
Interrupt
controller
• Five external interrupt pins: NMI, IRQ0, IRQ1, IRQ4, IRQ
• 25 internal interrupts
• Three selectable interrupt priority levels
Bus controller
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
5
2
Page 17
Feature Description
16-bit integrated
timer unit (ITU)
• Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10
pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
Programmable
timing pattern
controller (TPC)
Watchdog timer
(WDT), 1 channel
Serial
communication
interface (SCI),
2 channels
A/D converter
I/O ports
• Maximum 15-bit pulse output, using ITU as time base
• Up to three 4-bit pulse output groups and one 3-bit pulse output group (or one 15-
bit group, one 8-bit group, or one 7-bit group)
• Non-overlap mode available
• Reset signal can be generated by overflow
• Reset signal can be output externally (However, not available with the F-ZTAT
version.)
• Usable as an interval timer
• Selection of asynchronous or synchronous mode
• Full duplex: can transmit and receive simultaneously
• On-chip baud-rate generator
• Smart card interface functions added (SCI0 only)
• Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• Can be externally triggered
• 55 input/output pins
• 8 input-only pins
Operating modes Five MCU operating modes
Mode
Mode 1 1 Mbyte A0 to A
Mode 3 16 Mbytes A0 to A
Mode 5 1 Mbyte A0 to A
Mode 6 16 Mbytes A0 to A
Mode 7 1 Mbyte — —
• On-chip ROM is disabled in modes 1 and 3
Address
Space
Address
Pins
19
23
19
23
Bus
Width
8 bits
8 bits
8 bits
8 bits
3
Page 18
Feature Description
Power-down
state
• Sleep mode
• Software standby mode
• Hardware standby mode
• Module standby function
• Programmable System clock frequency division
Other features
Product lineup Model (3V) Package ROM
• On-chip clock oscillator
HD64F3022F 80-pin QFP (FP-80A) Flash memory
HD64F3022TE 80-pin TQFP (TFP-80C)
HD6433022F 80-pin QFP (FP-80A) Mask ROM
HD6433022TE 80-pin TQFP (TFP-80C)
HD6433021F 80-pin QFP (FP-80A) Mask ROM
HD6433021TE 80-pin TQFP (TFP-80C)
HD6433020F 80-pin QFP (FP-80A) Mask ROM
HD6433020TE 80-pin TQFP (TFP-80C)
Note: * Normal mode cannot be used with this LSI.
4
Page 19
1.2 Block Diagram
y
Figure 1-1 shows an internal block diagram of the H8/3022 Series.
7
6
5
4
3
/D
/D
/D
/D
5
4
3
P3
P3
P3
P3
Port 3
Data bus (upper)
Bus
controller
MD2
MD
MD
EXTAL
XTAL
STBY
RES
RESO/FWE*
NMI
P65/WR
/RD
P6
4
/AS
P6
3
/WAIT
P6
0
/IRQ
P8
1
P80/IRQ
/D
/D
7
6
P3
P3
Data bus (lower)
VSSVSSV
SS
H8/300H CPU
CC
VCCV
1
0
ø
Clock osc.
ROM
(Flash memory,
Interrupt
controller
masked ROM)
Watchdog
RAM
timer
(WDT)
16-bit
1
0
Port 8 Port 6
integrated
timer unit
(ITU)
Serial
communication
interface
(SCI) × 2 channel
2
1
0
/D
/D
2
1
0
P3
P3
Address bus
Port 5
Port 2Port 1
P53/A
P52/A
P51/A
P50/A
P27/A
P26/A
P25/A
P24/A
P23/A
P22/A
P21/A
P20/A
P17/A
P16/A
P15/A
P14/A
P13/A
P12/A
P11/A
P10/A
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Programmable
timing pattern
controller (TPC)
4
4
4
4
3
3
/A
/TIOCB
/TIOCA
/TIOCB
/ADTRG
/TOCXB
/TOCXA
15
13
/TP
/TP
/TP
7
5
PB
PB
PB
12
/TP
4
PB
/TIOCA
9
10
/TP
2
PB
/TP
1
PB
8
/TP
0
PB
/TIOCB
/TP
11
3
PA
Note: * Masked ROM : RESO
Flash memor
: FWE
Figure 1-1 Block Diagram
20
/A
2
/TIOCA
7
/TP
7
PA
21
22
/A
2
1
/TIOCB
6
5
/TP
6
5
PA
23
/A
1
/TCLKD
0
/TIOCA
4
/TIOCB
/TP
3
4
/TP
PA
3
PA
A/D converter
/TCLKB
/TCLKA
/TCLKC
1
0
0
/TP
/TP
1
0
PA
PA
/TIOCA
2
/TP
2
PA
CC
AV
SS
AV
7
/AN
7
P7
6
/AN
6
P7
Port 7Port APort B
5
/AN
5
P7
4
/AN
4
P7
3
/AN
3
P7
2
/AN
2
P7
1
/AN
1
P7
0
/AN
0
P7
Port 9
P95/SCK1/IRQ
P94/SCK0/IRQ
P93/RxD
P92/RxD
P91/TxD
P90/TxD
1
0
1
0
5
4
5
Page 20
1.3 Pin Description
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the H8/3022 Series.
1
0
/AN
P95/IRQ5/SCK
PA0/TP0/TCLKA
/TP1/TCLKB
PA
1
PA
/TP2/TIOCA0/TCLKC
2
/TP3/TIOCB0/TCLKD
PA
3
PA
/TP4/TIOCA1/A
4
PA5/TP5/TIOCB1/A
PA6/TP6/TIOCA2A
PA7/TP7/TIOCB2/A
P7
/AN
2
P73/AN
P74/AN
P75/AN
P76/AN
P77/AN
AV
P80/IRQ
P81/IRQ
P91/TxD
P93/RxD
CC
/AN
1
0
P7
P7
AVSSRESO/FWE*
60
59
61
2
62
3
63
4
64
5
65
6
66
7
58
67
68
0
69
1
70
1
71
1
72
1
73
74
75
76
77
23
78
22
79
21
80
20
1
2
3
57
4
/WR
5
P6
56
5
/RD
4
P6
55
6
/AS
3
CC
XTAL
52
EXTAL
51
P6
54
V
53
Top view
(FP-80A, TFP-80C)
7
8
9
10
VSSNMI
50
11
49
12
RES
48
13
STBY
47
14
ø
MD1MD0P6
46
45
15
16
44
17
/WAIT
0
43
18
19
/A
3
P5
42
19
18
/A
2
P5
41
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
/P5
17
A16/P5
A15/P2
A14/P2
A13/P2
A12/P2
A11/P2
A10/P2
A9/P2
A8/P2
V
SS
A7/P1
A6/P1
A5/P1
A4/P1
A3/P1
A2/P1
A1/P1
A0/P1
V
CC
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
/PB
/PB
8
9
/TP
/TP
3
3
TIOCA
TIOCB
Note: * Masked ROM: RESO
Flash memory: FWE
Figure 1-2 Pin Arrangement (FP-80A, TFP-80C Top View)
6
2
3
/PB
/PB
10
11
/TP
/TP
4
4
TIOCA
TIOCB
4
5
/PB
/PB
12
13
/TP
/TP
4
4
TOCXA
TOCXB
2
MD
7
/PB
15
ADTRG/TP
0
/P9
0
TxD
2
/P9
0
RxD
4
/P9
0
/SCK
4
IRQ
0
1
2
3
4
5
6
SS
V
/P3
/P3
/P3
/P3
/P3
0
1
2
D
D
3
D
D
/P3
4
5
D
D
/P3
6
D
7
/P3
7
D
Page 21
1.3.2 Pin Functions
Pin Assignments in Each Mode: Table 1-2 lists the FP-80A and TFP-80C pin assignments in
each mode.
Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode
Pin Name
Pin No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7
1PB
2PB
3PB
4PB
5PB
6PB
/TP8/
0
TIOCA
/TP9/
1
TIOCB
/TP10/
2
TIOCA
/TP11/
3
TIOCB
/TP12/
4
TOCXA
/TP13/
5
TOCXB
PB0/TP8/
3
TIOCA
PB1/TP9/
3
TIOCB
PB2/TP10/
4
TIOCA
PB3/TP11/
4
TIOCB
PB4/TP12/
4
TOCXA
PB5/TP13/
4
TOCXB
7MD2MD
8PB
9P9
10 P92/RxD
/TP15/
7
ADTRG
/TxD
0
PB7/TP15/
ADTRG
0
0
P90/TxD
P92/RxD
PB0/TP8/
3
TIOCA
3
PB1/TP9/
3
TIOCB
3
PB2/TP10/
4
TIOCA
4
PB3/TP11/
4
TIOCB
4
PB4/TP12/
4
TOCXA
4
PB5/TP13/
4
2
TOCXB
MD
2
4
PB7/TP15/
ADTRG
0
0
P90/TxD
P92/RxD
0
0
PB0/TP8/
TIOCA
3
PB1/TP9/
TIOCB
3
PB2/TP10/
TIOCA
4
PB3/TP11/
TIOCB
4
PB4/TP12/
TOCXA
4
PB5/TP13/
TOCXB
MD
4
2
PB7/TP15/
ADTRG
P90/TxD
P92/RxD
PB0/TP8/
TIOCA
3
PB1/TP9/
TIOCB
3
PB2/TP10/
TIOCA
4
PB3/TP11/
TIOCB
4
PB4/TP12/
TOCXA
4
PB5/TP13/
TOCXB
MD
4
2
PB7/TP15/
ADTRG
0
0
P90/TxD
P92/RxD
0
0
11 P94/SCK0/
IRQ
4
12 V
13 D
14 D
15 D
16 D
17 D
18 D
19 D
20 D
SS
0
1
2
3
4
5
6
7
P94/SCK0/
IRQ
4
V
SS
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
P94/SCK0/
IRQ
4
V
SS
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
P94/SCK0/
IRQ
4
V
SS
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
P94/SCK0/
IRQ
4
V
SS
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P3
6
P3
7
7
Page 22
Pin Name
Pin No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7
21 V
22 A
23 A
24 A
25 A
26 A
27 A
28 A
29 A
30 V
31 A
32 A
33 A
34 A
35 A
CC
0
1
2
3
4
5
6
7
SS
8
9
10
11
12
V
CC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
A
8
A
9
A
10
A
11
A
12
V
CC
P10/A
P11/A
P12/A
P13/A
P14/A
P15/A
P16/A
P17/A
V
SS
P20/A
P21/A
P22/A
P23/A
P24/A
V
CC
0
1
2
3
4
5
6
7
8
9
10
11
12
P10/A
P11/A
P12/A
P13/A
P14/A
P15/A
P16/A
P17/A
V
SS
P20/A
P21/A
P22/A
P23/A
P24/A
0
1
2
3
4
5
6
7
8
9
10
11
12
V
P1
P1
P1
P1
P1
P1
P1
P1
V
P2
P2
P2
P2
P2
CC
0
1
2
3
4
5
6
7
SS
0
1
2
3
4
36 A
37 A
38 A
39 A
40 A
41 A
42 A
13
14
15
16
17
18
19
43 P60/WAIT P60/WAIT P60/WAIT P60/WAIT P6
44 MD
45 MD
0
1
A
13
A
14
A
15
A
16
A
17
A
18
A
19
MD
MD
P25/A
P26/A
P27/A
P50/A
P51/A
P52/A
P53/A
0
1
MD
MD
13
14
15
16
17
18
19
0
1
P25/A
P26/A
P27/A
P50/A
P51/A
P52/A
P53/A
MD
0
MD
1
13
14
15
16
17
18
19
P2
P2
P2
P5
P5
P5
P5
MD
MD
5
6
7
0
1
2
3
0
0
1
46шшшшш
47 STBY STBY STBY STBY STBY
48 RES RES RES RES RES
49 NMI NMI NMI NMI NMI
50 V
SS
V
SS
V
SS
V
SS
V
SS
8
Page 23
Pin Name
Pin No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7
51 EXTAL EXTAL EXTAL EXTAL EXTAL
52 XTAL XTAL XTAL XTAL XTAL
53 V
CC
V
CC
V
CC
V
CC
V
54 AS AS AS AS P6
55 RD RD RD RD P6
56 WR WR WR WR P6
57 RESO/
FWE*
58 AV
SS
59 P70/AN
60 P71/AN
61 P72/AN
62 P73/AN
63 P74/AN
64 P75/AN
65 P76/AN
66 P77/AN
0
1
2
3
4
5
6
7
RESO/
FWE*
AV
SS
P70/AN
P71/AN
P72/AN
P73/AN
P74/AN
P75/AN
P76/AN
P77/AN
RESO/
FWE*
AV
SS
0
1
2
3
4
5
6
7
P70/AN
P71/AN
P72/AN
P73/AN
P74/AN
P75/AN
P76/AN
P77/AN
0
1
2
3
4
5
6
7
RESO/
FWE*
AV
SS
P70/AN
P71/AN
P72/AN
P73/AN
P74/AN
P75/AN
P76/AN
P77/AN
RESO/
FWE*
AV
0
1
2
3
4
5
6
7
P70/AN
P71/AN
P72/AN
P73/AN
P74/AN
P75/AN
P76/AN
P77/AN
CC
3
4
5
SS
0
1
2
3
4
5
6
7
67 AV
68 P80/IRQ
69 P81/IRQ
70 P91/TxD
71 P93/RxD
CC
0
1
1
1
72 P95/SCK1/
IRQ
5
73 PA0/TP0/
TCLKA
74 PA1/TP1/
TCLKB
75 PA2/TP2/
TIOCA
/
0
TCLKC
AV
CC
P80/IRQ
P81/IRQ
P91/TxD
P93/RxD
0
1
1
1
P95/SCK1/
IRQ
5
PA0/TP0/
TCLKA
PA1/TP1/
TCLKB
/TP2/
PA
2
TIOCA
/
0
TCLKC
AV
CC
P80/IRQ
P81/IRQ
P91/TxD
P93/RxD
0
1
1
1
P95/SCK1/
IRQ
5
PA0/TP0/
TCLKA
PA1/TP1/
TCLKB
/TP2/
PA
2
TIOCA
/
0
TCLKC
AV
CC
P80/IRQ
P81/IRQ
P91/TxD
P93/RxD
0
1
1
1
P95/SCK1/
IRQ
5
PA0/TP0/
TCLKA
PA1/TP1/
TCLKB
/TP2/
PA
2
TIOCA
/
0
TCLKC
AV
CC
P80/IRQ
P81/IRQ
P91/TxD
P93/RxD
0
1
1
1
P95/SCK1/
IRQ
5
PA0/TP0/
TCLKA
PA1/TP1/
TCLKB
/TP2/
PA
2
TIOCA
/
0
TCLKC
9
Page 24
Pin Name
Pin No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7
76 PA3/TP3/
TIOCB
0
TCLKD
77 PA4/TP4/
TIOCA
1
78 PA5/TP5/
TIOCB
1
79 PA6/TP6/
TIOCA
2
80 PA7/TP7/
TIOCB
2
PA
/TP3/
3
/
TIOCB
/
0
TCLKD
PA4/TP4/
TIOCA
1/A23
PA5/TP5/
TIOCB
1/A22
PA6/TP6/
TIOCA
A
2/A21
20
PA
/TP3/
3
TIOCB
TCLKD
PA4/TP4/
TIOCA
PA5/TP5/
TIOCB
PA6/TP6/
TIOCA
PA7/TP7/
TIOCB
Notes: Pins marked NC should be left unconnected.
* Masked ROM: RESO
Flash Memory: FWE
PA
/TP3/
3
/
0
TIOCB
/
0
TCLKD
PA4/TP4/
1
TIOCA
1/A23
PA5/TP5/
1
TIOCB
1/A22
PA6/TP6/
2
2
TIOCA
A
20
2/A21
PA
/TP3/
3
TIOCB
0
TCLKD
PA4/TP4/
TIOCA
1
PA5/TP5/
TIOCB
1
PA6/TP6/
TIOCA
2
PA7/TP7/
TIOCB
2
/
10
Page 25
1.4 Pin Functions
Table 1-3 summarizes the pin functions.
Table 1-3 Pin Functions
Type Symbol Pin No. I/O Name and Function
Power V
CC
21,
53
Input Power: For connection to the power
supply. Connect all V
pins to the system
CC
power supply.
V
SS
12,
30,
50
Input Ground: For connection to ground (0 V).
Connect all V
pins to the 0-V system
SS
power supply.
Clock XTAL 52 Input For connection to a crystal resonator
For examples of crystal resonator and
external clock input, see section 16, Clock
Pulse Generator.
EXTAL 51 Input For connection to a crystal resonator or
input of an external clock signal. For
examples of crystal resonator and external
clock input, see section 16, Clock Pulse
Generator.
ø 46 Output System clock: Supplies the system clock
to external devices
Operating
mode
control
MD2,
MD
MD
7,
,
1
0
45,
44
Input Mode 2 to mode 0: For setting the
operating mode, as follows. These pins
should not be changed during operation.
Operating
MD
MD
2
MD
1
Mode
0
000—
0 0 1 Mode 1
010—
0 1 1 Mode 3
100—
1 0 1 Mode 5
1 1 0 Mode 6
1 1 1 Mode 7
11
Page 26
Type Symbol Pin No. I/O Name and Function
System
control
RES 48 Input Reset input: When driven low, this pin
resets the chip
RESO/
FWE
57 Output/
Input
Reset output (Masked ROM version):
Outputs WDT-generated reset signal to an
external device.
Write enable signal (F-ZTAT version):
Flash memory write control signal.
STBY 47 Input Standby: When driven low, this pin forces a
transition to hardware standby mode
Interrupts NMI 49 Input Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ
, IRQ
5
IRQ
, IRQ
1
Address bus A23 to A20,
A
to A8,
19
A
to A
7
0
Data bus D7 to D
0
72, 11,
4
69, 68
0
77 to 80,
42 to 31,
29 to 22
20 to 13 Input/
Input Interrupt request 5, 4, 1, 0: Maskable
interrupt request pins
Output Address bus: Outputs address signals
Data bus: Bidirectional data bus
output
Bus control AS 54 Output Address strobe: Goes low to indicate valid
address output on the address bus
RD 55 Output Read: Goes low to indicate reading from the
external address space.
WR 56 Output Write: Goes low to indicate writing to the
external address space indicates valid data
on the data bus.
WAIT 43 Input Wait: Requests insertion of wait states in
bus cycles during access to the external
address space
16-bit
integrated
timer unit
(ITU)
TCLKD to
TCLKA
TIOCA4 to
TIOCA
0
76 to 73 Input Clock input A to D: External clock inputs
3, 1, 79,
77, 75
Input/
Output
Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
TIOCB4 to
TIOCB
0
4, 2, 80,
78, 76
Input/
output
Input capture/output compare B4 to B0
GRB4 to GRB0 output compare or input
capture, or PWM output
TOCXA
TOCXB
4
4
5 Output Output compare XA4: PWM output
6 Output Output compare XB4: PWM output
12
Page 27
Type Symbol Pin No. I/O Name and Function
Programmable timing
pattern
TP
TP
,
15
to
13
0
8, 6 to 1
80 to 73
Output TPC output 15, 13 to 0 : Pulse output
TP
controller
(TPC)
Serial communication
interface
(SCI)
TxD1,
TxD
RxD1,
RxD
SCK1,
SCK
A/D
converter
AN7 to
AN
ADTRG 8 Input A/D trigger: External trigger input for
AV
AV
I/O ports P1
0
0
0
0
CC
SS
to P1
7
70, 9 Output Transmit data:(channels 0 and 1): SCI
data output
71, 10 Input Receive data:(channels 0 and 1): SCI
data input
72, 11 Input/
output
Serial clock:(channels 0 and 1): SCI clock
input/output
66 to 59 Input Analog 7 to 0: Analog input pins
starting A/D conversion
67 Input Power supply pin and reference voltage
input pin for the A/D converter Connect to
the system power supply when not using
the A/D converter
58 Input Ground pin for the A/D converter. Connect
to system power-supply (0 V).
29 to 22 Input/
0
output
Port 1: Eight input/output pins. The
direction of each pin can be selected in the
port 1 data direction register (P1DDR).
P27 to P2
P37 to P3
P53 to P5
P65 to P63,
P6
0
P77 to P7
P81, P8
0
38 to 31 Input/
0
output
Port 2: Eight input/output pins. The
direction of each pin can be selected in the
port 2 data direction register (P2DDR).
20 to 13 Input/
0
output
Port 3: Eight input/output pins. The
direction of each pin can be selected in the
port 3 data direction register (P3DDR).
42 to 39 Input/
0
output
Port 5: Four input/output pins. The
direction of each pin can be selected in the
port 5 data direction register (P5DDR).
56 to 54,43Input/
output
Port 6: Four input/output pins. The
direction of each pin can be selected in the
port 6 data direction register (P6DDR).
66 to 59 Input Port 7: Eight input pins
0
69, 68 Input/
output
Port 8: Two input/output pins. The
direction of each pin can be selected in the
port 8 data direction register (P8DDR).
13
Page 28
Type Symbol Pin No. I/O Name and Function
I/O ports P9
P9
PA7 to
PA
PB7, PB
to PB
5
0
0
to
72, 11
71, 10
70, 9
80 to 73 Input/
Input/
output
output
Port 9: Six input/output pins. The direction
of each pin can be selected in the port 9
data direction register (P9DDR).
Port A: Eight input/output pins. The
direction of each pin can be selected in the
port A data direction register (PADDR).
8, 6 to 1 Input/
5
0
output
Port B: Seven input/output pins. The
direction of each pin can be selected in the
port B data direction register (PBDDR).
14
Page 29
Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1 Features
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 series object programs without alteration
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-two basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, or @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8, PC) or @(d:16, PC)]
Memory indirect [@@aa:8]
• 16-Mbyte linear address space
15
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• High-speed operation
All frequently-used instructions execute in two to four states
Maximum clock frequency: 18 MHz
8/16/32-bit register-register add/subtract: 111 ns
8 × 8-bit register-register multiply: 778 ns
16 ÷ 8-bit register-register divide: 778 ns
16 × 16-bit register-register multiply: 1222 ns
32 ÷ 16-bit register-register divide: 1222 ns
• Two CPU operating modes
Normal mode (cannot be used with this LSI)
Advanced mode
• Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
• More general registers
Eight 16-bit registers have been added.
• Expanded address space
Advanced mode supports a maximum 16-Mbyte address space.
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
Signed multiply/divide instructions and other instructions have been added.
16
Page 31
2.2 CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2-1.
Unless specified otherwise, all descriptions in this manual refer to advanced mode.
Normal mode
CPU operating modes
Advanced mode
Note: * Normal mode cannot be used with this LSI.
Figure 2-1 CPU Operating Modes
*
Maximum 64 kbytes, program
and data areas combined
Maximum 16 Mbytes, program
and data areas combined
17
Page 32
2.3 Address Space
The maximum address space of the H8/300H CPU is 16 Mbytes. This LSI allows selection of a
normal mode and advanced mode 1-Mbyte mode or 16-Mbyte mode for the address space
depending on the MCU operation mode. Figure 2-2 shows the address ranges of the H8/3022
Series. For further details see section 3.6, Memory Map in Each Operating Mode.
The 1-Mbyte operating mode uses 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
H'00000
H'FFFFF
(64-Kbyte mode)
H'00000
H'FFFFF
2. Advanced mode1. Normal mode
*
H'000000
H'FFFFFF
(b) 16-Mbyte mode(a) 1-Mbyte mode
Note: * Normal mode cannot be used with this LSI.
18
Figure 2-2 Memory Map
Page 33
2.4 Register Configuration
2.4.1 Overview
The H8/300H CPU has the internal registers shown in figure 2-3. There are two types of registers:
general registers and control registers.
General Registers (ERn)
0707015
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
Control Registers (CR)
PC
Legend
SP:
PC:
CCR:
I:
UI:
H:
U:
N:
Z:
V:
C:
Stack pointer
Program counter
Condition code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
E0
E1
E2
E3
E4
E5
E6
E7
23 0
(SP)
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
CCR
7
IUIHUNZVC
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
6543210
Figure 2-3 CPU Registers
19
Page 34
2.4.2 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 2-4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
E registers
(extended registers)
E0 to E7
ER registers
ER0 to ER7
R registers
R0 to R7
RH registers
R0H to R7H
RL registers
R0L to R7L
Figure 2-4 Usage of General Registers
20
Page 35
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2-5 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 2-5 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU
will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so
the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is
regarded as 0.
Condition Code Register (CCR): This 8-bit register contains internal CPU status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details see section 5, Interrupt Controller.
21
Page 36
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit
in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular,
the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an
MOV.L instruction executed immediately after a reset.
22
Page 37
2.5 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figures 2-6 and 2-7 show the data formats in general registers.
General
Data Type Data Format
1-bit data
1-bit data
Register
RnH
RnL
70
7
6543210
Don’t care
Don’t care
70
76543210
4-bit BCD data
4-bit BCD data
Byte data
Byte data
Legend
RnH:
RnL:
General register RH
General register RL
70
RnH
RnL
70
RnH
MSB LSB
RnL
43
Lower digitUpper digit
Don’t care
Don’t care
Figure 2-6 General Register Data Formats
Don’t care
7
70
MSB LSB
43
Lower digitUpper digit
Don’t care
0
23
Page 38
Word data
General
RegisterData Type Data Format
15 0
Rn
MSB LSB
15 0
Word data
Longword data
Legend
ERn:
En:
Rn:
MSB:
LSB:
General register
General register E
General register R
Most significant bit
Least significant bit
En
ERn
MSB LSB
31 16
MSB
15 0
LSB
Figure 2-7 General Register Data Formats
2.5.2 Memory Data Formats
Figure 2-8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
24
Page 39
AddressData T ype Data Format
70
1-bit data
Byte data
Word data
Longword data
76543210Address
Address
Address 2m
MSB LSB
MSB
Address 2m + 1
Address 2n
MSB
Address 2n + 1
Address 2n + 2
Address 2n + 3
Figure 2-8 Memory Data Formats
LSB
LSB
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
25
Page 40
2.6 Instruction Set
2.6.1 Instruction Set Overview
The H8/300H CPU has 62 types of instructions, which are classified as shown in table 2-1.
Table 2-1 Instruction Classification
Function Instruction Types
Data transfer MOV, PUSH*
1
, POP*1 , MOVTPE*2 , MOVFPE*
2
3
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,
MULXU, DIVXU, MULXS, DIVXS, CMP, NEG, EXTS, EXTU
Logic operations AND, OR, XOR, NOT 4
Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR,
BIXOR, BLD, BILD, BST, BIST
Branch Bcc*3 , JMP, BSR, JSR, RTS 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9
Block data transfer EEPMOV 1
Total 62 types
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. These instructions are not available on the H8/3022 Series.
3. Bcc is a generic branching instruction.
18
14
26
Page 41
2.6.2 Instructions and Addressing Modes
Table 2-2 indicates the instructions available in the H8/300H CPU.
Table 2-2 Instructions and Addressing Modes
Addressing Modes
@
@
(d:16,
(d:24,
@ERn+/
Function Instruction #xx Rn@ERn
Data MOV BWL BWL BWL BWL BWL BWL B BWL BWL — — — —
transfer POP, PUSH — — — — — — — — — — — — WL
ERn)
ERn)
@–ERn@aa:8@aa:16@aa:24
@
(d:8,
PC)
@
(d:16,
PC)
@@
aa:8 Implied
MOVFPE,
MOVTPE
Arithmetic ADD, CMP BWL BWL — — — — — — — — — — —
operations SUB WL BWL — — — — — — — — — — —
ADDX,
SUBX
ADDS,
SUBS
INC, DEC — BWL — — — — — — — — — — —
DAA, DAS — B — — — — — — — — — — —
MULXU,
MULXS,
DIVXU,
DIVXS
NEG — BWL — — — — — — — — — — —
EXTU,
EXTS
——— ——— —B — ————
BB— ——— —— — ————
—L— ——— —— — ————
—BW— ——— —— — ————
—WL— ——— —— — ————
Logic
operations
Shift instructions — BWL — — — — — — — — — — —
Bit manipulation — B B — — — B — — — — — —
Branch Bcc, BSR — — — — — — — — — ——
AND, OR,
XOR
NOT — BWL — — — — — — — — — — —
JMP, JSR — — ——— —— —— —
RTS ——— ——— —— — ———
BWL BWL — — — — — — — — — — —
27
Page 42
Addressing Modes
@
@
(d:16,
(d:24,
@ERn+/
Function Instruction #xx Rn@ERn
System TRAPA — — — — — — — — — — — —
control RTE — — — — — — — — — — — —
SLEEP — — — — — — — — — — — —
LDC B B W W W W — W W — — — —
STC — B W W W W — W W — — — —
ERn)
ERn)
@–ERn@aa:8@aa:16@aa:24
@
(d:8,
PC)
@
(d:16,
PC)
@@
aa:8 Implied
ANDC,
ORC,
XORC
NOP ——— ——— —— — ———
Block data transfer — — — — — — — — — — — — BW
B—— ——— —— — ————
Legend
B: Byte
W: Word
L: Longword
28
Page 43
2.6.3 Tables of Instructions Classified by Function
Tables 2-3 to 2-10 summarize the instructions in each functional category. The operation notation
used in these tables is defined as follows.
Operation Notation
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Exclusive logical OR
→ Move
¬ NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
29
Page 44
Table 2-3 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in the H8/3022 Series.
MOVTPE B Rs → (EAs)
Cannot be used in the H8/3022 Series.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L
@SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L
ERn, @–SP.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
30
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Table 2-4 Arithmetic Operation Instructions
Instruction Size* Function
ADD,
SUB
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data
cannot be subtracted from data in a general register. Use the SUBX or
ADD instruction.)
ADDX,
SUBX
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
INC,
DEC
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS,
SUBS
DAA,
DAS
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register
by referring to CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
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Instruction Size* Function
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16bit quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR according to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a
general register.
EXTS W/L Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by extending the sign bit.
EXTU W/L Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by padding with zeros.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
32
Page 47
Table 2-5 Logic Operation Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ¬ Rd → Rd
Takes the one’s complement of general register contents.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2-6 Shift Instructions
Instruction Size* Function
SHAL,
SHAR
SHLL,
SHLR
ROTL,
ROTR
ROTXL,
ROTXR
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry bit.
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Table 2-7 Bit Manipulation Instructions
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The
bit number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower 3 bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Instruction Size* Function
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD B ¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST B C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: *Size refers to the operand size.
B: Byte
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Table 2-8 Branching Instructions
Instruction Size Function
Bcc — Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
Bcc (BHS) Carry clear (high or same) C = 0
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
JMP — Branches unconditionally to a specified address
BSR — Branches to a subroutine at a specified address
JSR — Branches to a subroutine at a specified address
RTS — Returns from a subroutine
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Table 2-9 System Control Instructions
Instruction Size* Function
TRAPA — Starts trap-instruction exception handling
RTE — Returns from an exception-handling routine
SLEEP — Causes a transition to the power-down state
LDC B/W (EAs) → CCR
Moves the source operand contents to the condition code register. The
condition code register size is one byte, but in transfer from memory,
data is read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is written
by word access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data.
NOP — PC + 2 → PC
Only increments the program counter.
Note: *Size refers to the operand size.
B: Byte
W: Word
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Table 2-10 Block Transfer Instruction
Instruction Size Function
EEPMOV.B — if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until R4L = 0
else next;
EEPMOV.W — if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until R4 = 0
else next;
Transfers a data block according to parameters set in general registers
R4L or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5: Starting source address
ER6: Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
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2.6.4 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2-9 shows examples of instruction formats.
Operation field only
op
Operation field and register fields
op rn rm
Operation field, register fields, and effective address extension
op rn rm
EA (disp)
Operation field, effective address extension, and condition field
op cc EA (disp)
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
BRA d:8
Figure 2-9 Instruction Formats
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2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
Step Description
1 Read Read one data byte at the specified address
2 Modify Modify one bit in the data byte
3 Write Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (PADDR) under
the following conditions.
PA7, PA6: Input pins
PA5 – PA0: Output pins
The intended purpose of this BCLR instruction is to switch PA0 from output to input.
Before Execution of BCLR Instruction
PA
7
Input/output Input Input Output Output Output Output Output Output
DDR 00111111
PA
6
PA
5
PA
4
PA
3
PA
2
PA
1
PA
0
Execution of BCLR Instruction
BCLR #0, @PADDR ;Clear bit 0 in data direction register
After Execution of BCLR Instruction
PA
7
Input/output Output Output Output Output Output Output Output Input
DDR 11111110
PA
6
PA
5
PA
4
PA
3
PA
2
PA
1
PA
0
Explanation: To execute the BCLR instruction, the CPU begins by reading PADDR. Since
PADDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to PADDR to complete the BCLR instruction.
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As a result, PA0DDR is cleared to 0, making PA0 an input pin. In addition, PA7DDR and
PA6DDR are set to 1, making PA7 and PA6 output pins.
The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead
of time.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2-11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2-11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16, ERn)/@d:24, ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8, PC)/@(d:16, PC)
8 Memory indirect @@aa:8
@ERn+
@–ERn
1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
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3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the resulting
register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2-12 indicates the accessible
address ranges.
Table 2-12 Absolute Address Access Ranges
Absolute
Address 1-Mbyte Modes 16-Mbyte Modes
8 bits (@aa:8) H'FFF00 to H'FFFFF
(1,048,320 to 1,048,575)
16 bits (@aa:16) H'00000 to H'07FFF,
H'F8000 to H'FFFFF
(0 to 32,767, 1,015,808 to
1,048,575)
24 bits (@aa:24) H'00000 to H'FFFFF
(0 to 1,048,575)
H'FFFF00 to H'FFFFFF
(16,776,960 to 16,777,215)
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
(0 to 32,767, 16,744,448 to
16,777,215)
H'000000 to H'FFFFFF
(0 to 16,777,215)
6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
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The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The first
byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2-10. The
upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to
255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area.
For further details see section 5, Interrupt Controller.
Specified by @aa:8
Reserved
Branch address
Figure 2-10 Memory-Indirect Branch Address Specification
When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2 Effective Address Calculation
Table 2-13 explains how an effective address is calculated in each addressing mode. In the
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
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23 0
Operand is general
register contents
23 0
23 0
23 0
General register contents
31 0
General register contents
31 0
Sign extension disp
disp
1, 2, or 4
General register contents
31 0
General register contents
31 0
1, 2, or 4
1 for a byte operand, 2 for a word
operand, 4 for a longword operand
op rm rn
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Register direct (Rn)
Table 2-13 Effective Address Calculation
1
Register indirect (@ERn)
2
44
op r
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
3
op r
Register indirect with post-increment
4
op r
or pre-decrement
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@–ERn
op r
Page 59
23 087
H'FFFF
23 016 15
Sign
extension
23 0
23 0
Operand is immediate data
0
disp
PC contents
Sign
23 0
extension
abs
op abs
op
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Absolute address
@aa:8
@aa:16
5
op
@aa:24
abs
op IMM
Program-counter relative
Immediate
#xx:8, #xx:16, or #xx:32
6
@(d:8, PC) or @(d:16, PC)
7
op disp
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16 15
H'00Memory contents
23 0
23 0
abs
23 087
H'0000
abs
15 0
23 087
H'0000
Memory contents
31 0
*
abs
op
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Memory indirect
@@aa:8
Normal mode
8
46
abs
op
Advanced mode
Register field
Operation field
Displacement
Legend
r, rm, rn:
op:
disp:
Immediate data
Absolute address
IMM:
abs:
Note: * Normal mode cannot be used with this LSI.
Page 61
2.8 Processing States
2.8.1 Overview
The H8/300H CPU has four processing states: the program execution state, exception-handling
state, power-down state, and reset state. The power-down state includes sleep mode, software
standby mode, and hardware standby mode. Figure 2-11 classifies the processing states.
Figure 2-13 indicates the state transitions.
Processing states Program execution state
The CPU executes program instructions in sequence
Exception-handling state
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception
Reset state
The CPU and all on-chip supporting modules are initialized and halted
Power-down state
The CPU is halted to conserve power
Sleep mode
Software standby mode
Hardware standby mode
Figure 2-11 Processing States
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2.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception handling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2-14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2-14 Exception Handling Types and Priority
Type of
Priority
High Reset Synchronized with clock Exception handling starts
Low
Note: *Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
Exception Detection Timing Start of Exception Handling
immediately when RES changes
from low to high
Interrupt End of instruction execution
or end of exception handling*
Trap instruction When TRAPA instruction is
executed
immediately after reset exception handling.
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Exception handling starts when
a trap (TRAPA) instruction is
executed
Figure 2-12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
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Exception
sources
Reset
External interrupts
Interrupt
Internal interrupts (from on-chip supporting modules)
Trap instruction
Figure 2-12 Classification of Exception Sources
Program execution state
SLEEP
instruction
with SSBY = 0
End of
exception
handling
Exception
Sleep mode
Interrupt
NMI, IRQ , IRQ ,
Exception-handling state
RES high
Reset state
Notes: 1.2.From any state except hardware standby mode, a transition to the reset state occurs
whenever goes low.
From any state, a transition to hardware standby mode occurs when goes low.
*1
RES
or IRQ interrupt
STBY high, RES low
01
2
SLEEP instruction
with SSBY = 1
Software standby mode
Hardware standby mode
Power-down state
STBY
*2
Figure 2-13 State Transitions
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2.8.4 Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets this set to 1, the CPU sets the I bit in the condition code
register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition
code register to 1. Then the CPU fetches a start address from the exception vector table and
execution branches to that address.
Figure 2-14 shows the stack after the exception-handling sequence.
SP–4
SP–3
SP–2
SP–1
SP (ER7)
Legend
CCR:
SP:
Notes: 1.2.PC is the address of the first instruction executed after the return from the
Condition code register
Stack pointer
exception-handling routine.
Registers must be saved and restored by word access or longword access,
starting at an even address.
Stack area
Before exception
handling starts
SP (ER7)
SP+1
SP+2
SP+3
SP+4
Pushed on stack
CCR
PC
After exception
handling ends
Even
address
Figure 2-14 Stack Structure after Exception Handling
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2.8.5 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 10,
Watchdog timer.
2.8.6 Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and clock halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 17, Power-Down State.
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2.9 Basic Operational Timing
2.9.1 Overview
The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the
system clock to the next rise is referred to as a “state.” A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memory, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus controller.
2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and
word access. Figure 2-15 shows the on-chip memory access cycle. Figure 2-16 indicates the pin
states.
Bus cycle
ø
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Figure 2-15 On-Chip Memory Access Cycle
T state
1
Address
Read data
Write data
T state
2
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T
1
T
2
ø
Address bus
, , AS
RD WR
Address
High
High impedance
D
to D0
7
Figure 2-16 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2-17 shows the on-chip supporting module
access timing. Figure 2-18 indicates the pin states.
Bus cycle
Read
access
Write
access
ø
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Internal data bus
T state
1
T state
2
Address
Read data
Write data
Figure 2-17 Access Cycle for On-Chip Supporting Modules
T state
3
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T
1
T
2
T
3
ø
Address bus
RD WR
, , AS
Address
High
High impedance
to D
D
7
0
Figure 2-18 Pin States during Access to On-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area accessed in two or three states. For details see section 6, Bus
Controller.
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Section 3 MCU Operating Modes
3.1 Overview
3.1.1 Operating Mode Selection
The H8/3022 Series has five operating modes (modes 1, 3, 5 to7) that are selected by the mode
pins (MD2 and MD0) as indicated in table 3-1. The input at these pins determines expanded mode
or single-chip mode.
Table 3-1 Operating Mode Selection
Mode Pins Description
Operating
Mode MD
—000— ———
Mode 1 0 0 1 Expanded mode 8 bits Disabled Enabled*
Mode 2 0 1 0 — — — —
Mode 3 0 1 1 Expanded mode 8 bits Disabled Enabled*
Mode 4 1 0 0 — — — —
Mode 5 1 0 1 Expanded mode 8 bits Enabled Enabled*
Mode 6 1 1 0 Expanded mode 8 bits Enabled Enabled*
Mode 7 1 1 1 Single-chip advanced mode — Enabled Enabled*
MD
2
MD
1
0
Address Space
Initial Bus
Mode*
1
On-Chip
ROM
On-Chip
RAM
1
1
1
1
2
Notes: 1. If the RAM enable bit (RAME) in the system control register (SYSCR) is cleared to 0,
these addresses become external addresses.
2. In mode 7, clearing bit RAME in SYSCR to 0 and reading the on-chip RAM always
return H’FF, and write access is ignored. For details, see section 14.3, Operation.
For the address space size there are two choices: 1 Mbyte, or 16 Mbytes.
Modes 1 and 3 are on-chip ROM disable expanded modes capable of accessing external memory
and peripheral devices.
Mode 1 supports a maximum address space of 1 Mbyte. Mode 3 supports a maximum address
space of 16 Mbytes.
Modes 5 and 6 are externally expanded mode that enables access to external memory and
peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum
address space of 1 Mbyte.
Mode 6 supports a maximum address space of 16 Mbyte.
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Mode 7 is single-chip modes that operate using the on-chip ROM, RAM, and registers. All I/O
ports are available. Mode 7 is an advanced mode with a maximum address space of 1 Mbyte.
The H8/3022 Series can be used only in modes 1, 3, or 5 to 7. The inputs at the mode pins must
select one of these seven modes. The inputs at the mode pins must not be changed during
operation.
3.1.2 Register Configuration
The H8/3022 Series has a mode control register (MDCR) that indicates the inputs at the mode pins
(MD2 and MD0), and a system control register (SYSCR). Table 3-2 summarizes these registers.
Table 3-2 Registers
Address* Name Abbreviation R/W Initial Value
H'FFF1 Mode control register MDCR R Undetermined
H'FFF2 System control register SYSCR R/W H'0B
Note: *The lower 16 bits of the address are indicated.
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3.2 Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3022
Series.
Bit
Initial value
Read/Write
Note: Determined by pins MD to MD .
7
—
1
—
6
—
1
—
5
—
0
—
Reserved bits
2
0
4
—
0
—
3
—
0
—
2
MDS2
—
R
Mode select 2 to 0
Bits indicating the current
operating mode
1
MDS1
— R***
MDS0
0
—
R
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS1 and
MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched when MDCR is read.
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3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3022 Series.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
5
STS1
0
R/W
4
STS0
0
R/W
User bit enable
Selects whether to use UI bit in CCR
as a user bit or an interrupt mask bit
3
UE
1
R/W
2
NMIEG
0
R/W
NMI edge select
Selects the valid edge
of the NMI input
1
—
1
—
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
0
RAME
1
R/W
Software standby
Enables transition to software standby mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information about software standby mode see section 17, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit7
SSBY Description
0 SLEEP instruction causes transition to sleep mode (Initial value)
1 SLEEP instruction causes transition to software standby mode
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at
least 7 ms at the system clock rate. For further information about waiting time selection, see
section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode.
Bit6
STS2
0 0 0 Waiting time = 8,192 states (Initial value)
0 0 1 Waiting time = 16,384 states
0 1 0 Waiting time = 32,768 states
0 1 1 Waiting time = 65,536 states
1 0 0 Waiting time = 131,072 states
1 0 1 Waiting time = 1,024 states
1 1 — Illegal setting
Bit5
STS1
Bit4
STS0 Description
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as an interrupt mask bit
1 UI bit in CCR is used as a user bit (Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit2
NMIEG Description
0 An interrupt is requested at the falling edge of NMI (Initial value)
1 An interrupt is requested at the rising edge of NMI
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
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3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.2 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register
(BRCR). (In this mode A20 is always used for address output.)
3.4.3 Mode 5
Ports 1, 2, and 5 can function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The address bus width can be selected freely by setting DDR of ports 1, 2, and 5. The initial
bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.4 Mode 6
Ports 1, 2, and 5, and port A (PA7 to PA4) function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space, but following a reset these pins, except for A20, are input ports.
To use ports 1, 2, and 5 as address bus pins A19 to A0, the corresponding bits in their data direction
registers (P1DDR, P2DDR, and P5DDR) must be set to 1 to select output mode. A23 to A21 are
enabled by writing 0 to bits 7 to 5 in the address control register (ADRCR). The address bus
width can be selected freely (excluding A20) by setting DDR of ports 1, 2, and 5, and ADRCR.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.5 Mode 7
This mode is an advanced mode with a 1-Mbyte address space which operates using the on-chip
ROM, RAM, and registers. All I/O ports are available.
Note: The H8/3022 Series cannot be used in mode 2 and 4.
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3.5 Pin Functions in Each Operating Mode
The pin functions of ports 1 to 3, port 5 and port A vary depending on the operating mode. Table
3-3 indicates their functions in each operating mode.
Table 3-3 Pin Functions in Each Mode
Port Mode 1 Mode 2*1Mode 3 Mode 4*1Mode 5 Mode 6 Mode 7
Port 1 A
Port 2 A
to A
7
to A
15
Port 3 D7 to D
Port 5 A19 to A
Port A PA7 to PA4—PA
—A
0
—A
8
—D
0
—A
16
A
to A
7
to A
15
to D
7
to A
19
to PA4*3,
6
20
0
8
0
16
—P1
—P2
—D
—P5
—PA
to P10*2P17 to P10*2P17 to P1
7
to P20*2P27 to P20*2P27 to P2
7
to D
7
0
to P50*2P53 to P50*2P53 to P5
3
to PA4PA6 to PA4*3,
7
D7 to D
A
20
0
P37 to P3
PA7 to PA
Notes: 1. H8/3022 Series cannot be used in these modes.
2. Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
3. Initial state A
A
output by writing 0 in bits 7 to 5 of ADRCR.
21
is always an address output pin. PA6 to PA4 are switched over to A23 to
20
3.6 Memory Map in Each Operating Mode
Figure 3-1 shows a memory map of the H8/3022. Figure 3-2 shows a memory map of the
H8/3021. Figure 3-3 shows a memory map of the H8/3020. The address space is divided into eight
areas.
0
0
0
0
4
Modes 1, 3, 5, and 6 are the 8-bit bus mode.
The address locations of the on-chip RAM and internal I/O registers differ between the 1-Mbyte
modes (modes 1, 5, and 7) and 16-Mbyte modes (mode 3 and 6). The address range specifiable by
the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs.
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Page 76
Mode 1
(1-Mbyte expanded modes with
on-chip ROM disabled)
Mode 3
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'00000
H'000FF
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'F8000
H'FDF0F
H'FDF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Vector area
External address
space
On-chip RAM *
External
address
space
Ineternal I/O
registers
H'000000
H'0000FF
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
H'007FFF
Area 0
Area 1
H'1FFFFF
H'200000
Area 2
Area 3
H'3FFFFF
H'400000
Area 4
Area 5
H'5FFFFF
H'600000
Area 6
Area 7
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
16-bit absolute addresses
(second half)
8-bit absolute addresses
H'FF8000
H'FFDF0F
H'FFDF10
Vector area
External
address
space
On-chip RAM *
8-bit memory-indirect
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
16-bit absolute
addresses (first half)
addresses
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3-1 H8/3022 Memory Map in Each Operating Mode (1)
62
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
External
address
space
Internal I/O
registers
16-bit absolute addresses
(second half)
8-bit absolute addresses
Page 77
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Mode 7
(single-chip advanced mode)
H'00000
H'000FF
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'F8000
Vector area
On-chip ROM
External address
space
8-bit memory-indirect
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'000000
H'0000FF
addresses
16-bit absolute
addresses (first half)
H'007FFF
H'03FFFF
H'040000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Vector area
On-chip ROM
External address
space
8-bit memory-indirect
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'00000
H'000FF
addresses
16-bit absolute
addresses (first half)
H'07FFF
H'3FFFF
H'F8000
Vector area
On-chip ROM
8-bit memory-indirect
addresses
16-bit absolute
addresses (first half)
H'FDF0F
H'FDF10
On-chip RAM *
H'FFDF0F
H'FFDF10
H'FFFF00
On-chip RAM *
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
External
address
space
Internal I/O
registers
8-bit absolute addresses
H'FFFF0F
H'FFFF10
External
address
H'FFFF1B
H'FFFF1C
16-bit absolute addresses
(second half)
space
Internal I/O
registers
H'FFFFFF
Note: * External addresses can be accessed by disabling on-chip RAM.
H'FDF10
On-chip RAM
H'FFF00
H'FFF0F
H'FFF1C
16-bit absolute addresses
(second half)
8-bit absolute addresses
H'FFFFF
Internal I/O
registers
16-bit absolute addresses
(second half)
8-bit absolute addresses
Figure 3-1 H8/3022 Memory Map in Each Operating Mode (2)
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Page 78
Mode 1
(1-Mbyte expanded modes with
on-chip ROM disabled)
Mode 3
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'00000
H'000FF
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'F8000
H'FDF0F
H'FDF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Vector area
External address
space
On-chip RAM
External
address
space
Internal I/O
registers
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
*
16-bit absolute addresses
(second half)
8-bit absolute addresses
H'000000
H'0000FF
H'007FFF
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'FF8000
H'FFDF0F
H'FFDF10
Vector area
External
address
space
On-chip RAM
8-bit memory-indirect
addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
*
16-bit absolute
addresses (first half)
Note: * External addresses can be accessed by disabling on-chip RAM.
Figure 3-2 H8/3021 Memory Map in Each Operating Mode (1)
64
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
External
address
space
Internal I/O
registers
16-bit absolute addresses
(second half)
8-bit absolute addresses
Page 79
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Mode 7
(single-chip advanced mode)
H'00000
H'000FF
H'07FFF
H'1FFFF
H'20000
H'2FFFF
H'30000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Vector area
On-chip ROM
Reserved
External address
*1
space
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'000000
H'0000FF
H'007FFF
H'02FFFF
H'030000
H'03FFFF
H'040000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Vector area
On-chip ROM
Reserved
External address
*1
space
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'00000
H'000FF
H'07FFF
H'2FFFF
Vector area
On-chip ROM
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
H'F8000
H'FDF0F
H'FDF10
On-chip RAM
*2
H'FFF00
H'FFF0F
H'FFF10
External
address
H'FFF1B
space
H'FFF1C
Internal I/O
registers
H'FFFFF
1.2.Do not access the reserved area.
Notes:
External addresses can be accessed by disabling on-chip RAM.
H'FFDF0F
H'FFDF10
On-chip RAM
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
16-bit absolute addresses
(second half)
8-bit absolute addresses
H'FFFFFF
External
address
space
Internal I/O
registers
*2
16-bit absolute addresses
8-bit absolute addresses
H'F8000
H'FDF10
H'FFF00
H'FFF0F
H'FFF1C
(second half)
H'FFFFF
On-chip RAM
Internal I/O
registers
16-bit absolute addresses
(second half)
8-bit absolute addresses
Figure 3-2 H8/3021 Memory Map in Each Operating Mode (2)
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Page 80
Mode 1
(1-Mbyte expanded modes with
on-chip ROM disabled)
Mode 3
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'00000
H'000FF
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'F8000
H'FDF0F
H'FDF10
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Vector area
External address
space
Reserved
*1
On-chip RAM
External
address
space
Internal I/O
registers
16-bit absolute
8-bit memory-indirect
addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
*2
16-bit absolute addresses
8-bit absolute addresses
H'000000
Vector area
H'0000FF
addresses (first half)
H'007FFF
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'FF8000
(second half)
H'FFDF0F
H'FFDF10
H'FFEF0F
H'FFEF10
On-chip RAM
External
address
space
Reserved
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
*1
*2
Notes:1.2.Do not access the reserved area.
External addresses can be accessed by disabling on-chip RAM.
Figure 3-3 H8/3020 Memory Map in Each Operating Mode (1)
66
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
External
address
space
Internal I/O
registers
16-bit absolute addresses
(second half)
8-bit absolute addresses
Page 81
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled)
Mode 6
(16-Mbyte expanded mode with
on-chip ROM enabled)
Mode 7
(single-chip advanced mode)
H'00000
H'000FF
H'07FFF
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Vector area
On-chip ROM
Reserved
External address
*1
space
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'000000
H'0000FF
H'007FFF
H'01FFFF
H'020000
H'03FFFF
H'040000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Vector area
On-chip ROM
Reserved
External address
*1
space
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'00000
H'000FF
H'07FFF
H'1FFFF
Vector area
On-chip ROM
16-bit absolute
8-bit memory-indirect
addresses (first half)
addresses
H'F8000
H'FDF0F
H'FDF10
H'FEF0F
H'FEF10
Reserved
On-chip RAM
*1
*2
H'FFF00
H'FFF0F
H'FFF10
External
address
H'FFF1B
space
H'FFF1C
Internal I/O
registers
H'FFFFF
1.2.Do not access the reserved area.
Notes:
External addresses can be accessed by disabling on-chip RAM.
H'FFDF0F
H'FFDF10
H'FFEF0F
H'FFEF10
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
16-bit absolute addresses
(second half)
8-bit absolute addresses
H'FFFFFF
On-chip RAM
Reserved
External
address
space
Internal I/O
registers
H'F8000
*1
*2
H'FEF10
On-chip RAM
H'FFF00
H'FFF0F
H'FFF1C
16-bit absolute addresses
(second half)
8-bit absolute addresses
H'FFFFF
Internal I/O
registers
16-bit absolute addresses
(second half)
8-bit absolute addresses
Figure 3-3 H8/3020 Memory Map in Each Operating Mode (2)
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Page 82
Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4-1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the
RES pin
Interrupt Interrupt requests are handled when execution of the
current instruction or handling of the current exception is
completed
Low Trap instruction (TRAPA) Started by execution of a trap instruction (TRAPA)
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2. The CCR interrupt mask bit is set to 1.
3. A vector address corresponding to the exception source is generated, and program execution
starts from the address indicated in the vector address.
For a reset exception, steps 2 and 3 above are carried out.
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Page 83
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4-1. Different vectors are assigned to
different exception sources. Table 4-2 lists the exception sources and their vector addresses.
• Reset
Exception
sources
External interrupts:
• Interrupts
NMI, IRQ , IRQ , IRQ , IRQ
0 1 4 5
• Trap instruction
Figure 4-1 Exception Sources
Internal interrupts:
25 interrupts from on-chip
supporting modules
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Page 84
Table 4-2 Exception Vector Table
Vector Address*
1
Exception Source Vector Number Normal Mode Advanced Mode
Reset 0 H'0000 to H'0001 H'0000 to H'0003
Reserved for system use 1 H'0002 to H'0003 H'0004 to H'0007
2 H'0004 to H'0005 H'0008 to H'000B
3 H'0006 to H'0007 H'000C to H'000F
4 H'0008 to H'0009 H'0010 to H'0013
5 H'000A to H'000B H'0014 to H'0017
6 H'000C to H'000D H'0018 to H'001B
External interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F
Trap instruction (4 sources) 8 H'0010 to H'0011 H'0020 to H'0023
9 H'0012 to H'0013 H'0024 to H'0027
10 H'0014 to H'0015 H'0028 to H'002B
11 H'0016 to H'0017 H'002C to H'002F
External interrupt IRQ
IRQ
0
1
12 H'0018 to H'0019 H'0030 to H'0033
13 H'001A to H'001B H'0034 to H'0037
Reserved for system use 14 H'001C to H'001D H'0038 to H'003B
15 H'001E to H'001F H'003C to H'003F
External interupt IRQ
IRQ
4
5
16 H'0020 to H'0021 H'0040 to H'0043
17 H'0022 to H'0023 H'0044 to H'0047
Reserved for system use 18 H'0024 to H'0025 H'0048 to H'004B
19 H'0026 to H'0027 H'004C to H'004F
Internal interrupts*
2
20
to
60
H'0028 to H'0029
to
H'0078 to H'0079
H'0050 to H'0053
to
H'00F0 to H'00F3
Notes: 1. Lower 16 bits of the address.
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.
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4.2 Reset
4.2.1 Overview
A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the
H8/3022 Series enters the reset state. A reset initializes the internal state of the CPU and the
registers of the on-chip supporting modules. Reset exception handling begins when the RES pin
changes from low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 10,
Watchdog Timer.
4.2.2 Reset Sequence
The H8/3022 Series enters the reset state when the RES pin goes low.
To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the
chip during operation, hold the RES pin low for at least 10 system clock (ø) cycles. When using
the flash memory version, hold at "Low" level for a least 1usec. See appendix D.2, Pin States at
Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the H8/3022 Series chip
starts reset exception handling as follows.
• The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
• The contents of the reset vector address (H'0000 to H'0003 in advanced mode) are read, and
program execution starts from the address indicated in the vector address.
Figure 4-2 shows the reset sequence in modes 5 and 7.
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Prefetch of
first program
instruction
Internal
processing
(5)(3)(1)
Vector fetch
ø
Figure 4-2 Reset Sequence (Modes 5 and 7)
RES
Internal
address bus
Internal read
signal
Internal write
signal
(2) (4) (6)
Address of reset vector: (1) = H'000000, (3) = H'000002
Internal data bus
(16-bit width)
(1), (3)
Start address (contents of reset vector)
Start address
First instruction of program
(2), (4)
(5)
(6)
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4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. The first instruction of the program is
always executed immediately after the reset state ends. This instruction should initialize the stack
pointer (example: MOV.L #xx:32, SP).
4.3 Interrupts
Interrupt exception handling can be requested by five external sources (NMI, IRQ0, IRQ1, IRQ4,
IRQ5) and 25 internal sources in the on-chip supporting modules. Figure 4-3 classifies the interrupt
sources and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
integrated timer unit (ITU), serial communication interface (SCI), and A/D converter. Each
interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
NMI (1)
IRQ , IRQ , IRQ , IRQ (4)
0 1 4 5
WDT* (1)
ITU (15)
SCI (8)
A/D converter (1)
Notes:
External interrupts
Interrupts
Internal interrupts
Numbers in parentheses are the number of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates
an interrupt request at every counter overflow.
Figure 4-3 Interrupt Sources and Number of Interrupts
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4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5 Stack Status after Exception Handling
Figure 4-4 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7)
Legend
PCE:
PCH:
PCL:
CCR:
SP:
Notes: PC indicates the address of the first instruction that will be executed after return.
→
Before exception handling After exception handling
Bits 23 to 16 of program counter (PC)
Bits 15 to 8 of program counter (PC)
Bits 7 to 0 of program counter (PC)
Condition code register
Stack pointer
1.
Saving and restoring of registers must be conducted at even addresses in word-size
2.
or longword-size units.
Stack area
SP (ER7)
SP+1
SP+2
SP+3
SP+4
Save on stack
→
CCR
PC
PC
PC
E
H
L
Even address
Figure 4-4 Stack after Completion of Exception Handling (Advanced Mode)
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4.6 Notes on Stack Usage
When accessing word data or longword data, the H8/3022 Series regards the lowest address bit as
0. The stack should always be accessed by word access or longword access, and the value of the
stack pointer (SP, ER7) should always be kept even. Use the following instructions to save
registers:
PUSH.W Rn (or MOV.W Rn, @–SP)
PUSH.L ERn (or MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4-5 shows an example of what
happens when the SP value is odd.
SP
Legend
CCR:
PC:
R1L:
SP:
CCR
SP
PC
TRAPA instruction executed
SP set to H'FFEFF Data saved above SP CCR contents lost
Condition code register
Program counter
General register R1L
Stack pointer
MOV. B R1L, @-ER7
SP
R1L
PC
H'FFEFA
H'FFEFB
H'FFEFC
H'FFEFD
H'FFEFF
Note: The diagram illustrates modes 1, 3, 5, 6, and 7.
Figure 4-5 Operation when SP Value is Odd
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Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level masking by the I and UI bits in the CPU condition code register (CCR)
• Independent vector addresses
All interrupts are independently vectored; the interrupt service routine does not have to identify
the interrupt source.
• Five external interrupt pins
NMI has the highest priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ0 , IRQ1, IRQ4, and IRQ5, sensing of the falling edge or level sensing
can be selected independently.
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5.1.2 Block Diagram
Figure 5-1 shows a block diagram of the interrupt controller.
ISCR IER IPRA, IPRB
NMI
input
CPU
IRQ input
OVF
TME
.
.
.
.
.
.
.
ADI
ADIE
Legend
I:
IER:
IPRA:
IPRB:
ISCR:
ISR:
SYSCR:
UE:
UI:
IRQ input
section ISR
.
.
.
Interrupt controller
Interrupt mask bit
IRQ enable register
Interrupt priority register A
Interrupt priority register B
IRQ sense control register
IRQ status register
System control register
User bit enable
User bit/interrupt mask bit
Priority
decision logic
Interrupt
request
Vector
number
I
CCR
UI
UE
SYSCR
Figure 5-1 Interrupt Controller Block Diagram
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5.1.3 Pin Configuration
Table 5-1 lists the interrupt pins.
Table 5-1 Interrupt Pins
Name Abbreviation I/O Function
Nonmaskable interrupt NMI Input Nonmaskable interrupt, rising edge or
falling edge selectable
External interrupt
request 5, 4, 1, and 0
IRQ
, IRQ4 ,
5
and IRQ
, IRQ
1
Input Maskable interrupts, falling edge or level
0
sensing selectable
5.1.4 Register Configuration
Table 5-2 lists the registers of the interrupt controller.
Table 5-2 Interrupt Controller Registers
Address*
H'FFF2 System control register SYSCR R/W H'0B
H'FFF4 IRQ sense control register ISCR R/W H'00
H'FFF5 IRQ enable register IER R/W H'00
H'FFF6 IRQ status register ISR R/(W)*
H'FFF8 Interrupt priority register A IPRA R/W H'00
H'FFF9 Interrupt priority register B IPRB R/W H'00
1
Name Abbreviation R/W Initial Value
2
H'00
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
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5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
Software standby
6
STS2
0
R/W
Standby timer
select 2 to 0
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
NMI edge select
Selects the NMI input edge
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or interrupt mask bit
2
NMIEG
0
R/W
1
—
1
—
RAM enable
Reserved bit
0
RAME
1
R/W
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as interrupt mask bit
1 UI bit in CCR is used as user bit (Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Bit 2
NMIEG Description
0 Interrupt is requested at falling edge of NMI input (Initial value)
1 Interrupt is requested at rising edge of NMI input
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5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)
IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority.
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
Initial value
Read/Write
7
IPRA7
0
R/W
6
IPRA6
0
R/W
5
—
0
R/W
4
IPRA4
0
R/W
3
IPRA3
0
R/W
2
IPRA2
0
R/W
1
IPRA1
0
R/W
0
IPRA0
0
R/W
Priority
level A0
Selects the
priority level
of ITU
channel 2
interrupt
requests
Priority level A1
Selects the priority level
of ITU channel 1
interrupt requests
Priority level A2
Selects the priority level of
ITU channel 0 interrupt requests
Priority level A3
Selects the priority level of
WDT interrupt requests
Priority level A4
Selects the priority level of IRQ4 and IRQ
interrupt requests
Reserved bit
Priority level A6
Selects the priority level of IRQ1 interrupt requests
Priority level A7
Selects the priority level of IRQ interrupt requests
0
IPRA is initialized to H'00 by a reset and in hardware standby mode.
5
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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests.
Bit7
IPRA7 Description
0 IRQ0 interrupt requests have priority level 0 (low priority) (Initial value)
1 IRQ0 interrupt requests have priority level 1 (high priority)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.
Bit6
IPRA6 Description
0 IRQ1 interrupt requests have priority level 0 (low priority) (Initial value)
1 IRQ1 interrupt requests have priority level 1 (high priority)
Bit 5—Reserved bit: This bit can be written and read, but it does not affect interrupt priority.
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ
interrupt
5
requests.
Bit4
IPRA4 Description
0 IRQ4, IRQ
interrupt requests have priority level 0 (low priority) (Initial value)
5
1 IRQ4, IRQ5 interrupt requests have priority level 1 (high priority)
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT interrupt requests.
Bit3
IPRA3 Description
0 WDT interrupt requests have priority level 0 (low priority) (Initial value)
1 WDT interrupt requests have priority level 1 (high priority)
Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests.
Bit2
IPRA2 Description
0 ITU channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 0 interrupt requests have priority level 1 (high priority)
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Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.
Bit1
IPRA1 Description
0 ITU channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 1 interrupt requests have priority level 1 (high priority)
Bit 0—Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests.
Bit0
IPRA0 Description
0 ITU channel 2 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 2 interrupt requests have priority level 1 (high priority)
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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which
interrupt priority levels can be set.
Bit
Initial value
Read/Write
7
IPRB7
0
R/W
6
IPRB6
0
R/W
5
—
0
R/W
4
—
0
R/W
3
IPRB3
0
R/W
Priority level B3
Selects the priority level of SCI
channel 0 interrupt requests
2
IPRB2
0
R/W
Priority level B1
Selects the priority level
of A/D converter
interrupt request
Priority level B2
Selects the priority level of SCI
channel 1 interrupt requests
1
IPRB1
0
R/W
Reserved bit
0
—
0
R/W
Reserved bits
Priority level B6
Selects the priority level of ITU channel 4 interrupt requests
Priority level B7
Selects the priority level of ITU channel 3 interrupt requests
IPRB is initialized to H'00 by a reset and in hardware standby mode.
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Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests.
Bit7
IPRB7 Description
0 ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 3 interrupt requests have priority level 1 (high priority)
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Bit6
IPRB6 Description
0 ITU channel 4 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 4 interrupt requests have priority level 1 (high priority)
Bits 5 and 4—Reserved: These bits can be written and read, but it does not affect interrupt
priority.
Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests.
Bit3
IPRB3 Description
0 SCI channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1 SCI channel 0 interrupt requests have priority level 1 (high priority)
Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit2
IPRB2 Description
0 SCI channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1 SCI channel 1 interrupt requests have priority level 1 (high priority)
Bit 1—Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests.
Bit1
IPRB1 Description
0 A/D converter interrupt requests have priority level 0 (low priority) (Initial value)
1 A/D converter interrupt requests have priority level 1 (high priority)
Bit 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.
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5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ0, IRQ1, IRQ4, and IRQ
interrupt requests.
Bit
Initial value
Read/Write
*
Note: Only 0 can be written, to clear flags.
7
—
0
—
Reserved bits Reserved bits
6
—
0
—
5
IRQ5F
0
R/(W)*
IRQ to IRQ flags
54
These bits indicate IRQ5 and IRQ4
interrupt request status
4
IRQ4F
0
R/(W) *
3
—
0
—
2
—
0
—
1
IRQ1F
0
R/(W) *
IRQ , IRQ flags
1
These bits indicates IRQ1 and IRQ0
interrupt request status
0
IRQ0F
0
R/(W) *
0
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7, 6, 3 and 2—Reserved: These bits cannot be modified and are always read as 0.
5
Bits 5, 4, 1 and 0—IRQ5, IRQ4, IRQ1 and IRQ0 Flags (IRQ5F, IRQ4F, IRQ1F, and IRQ0F):
These bits indicate the status of IRQ5, IRQ4, IRQ1 and IRQ0 interrupt requests.
Bits 5, 4, 1, and 0
IRQ5F, IRQ4F, IRQ1F,
and IRQ0F Description
0 [Clearing conditions] (Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is
carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1 [Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5, 4, 1 and 0
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