Hitachi H8/300L Programming Manual

H8/300L Series

Programming Manual

Notice

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Contents

Preface....... .....................................................................................................1

Section 1. CPU.................................................................................................3

1.1 Overview.........................................................................................................................3

1.1.1 Features..............................................................................................................3

1.1.2 Data Structure..................................................................................................... 4

1.1.3 Address Space.....................................................................................................6

1.1.4 Register Configuration........................................................................................ 6

1.2 Registers..........................................................................................................................7

1.2.1 General Registers................................................................................................ 7

1.2.2 Control Registers................................................................................................ 7

1.2.3 Initial Register Values ........................................................................................ 8

1.3 Instructions......................................................................................................................9

1.3.1 Types of Instructions...........................................................................................9

1.3.2 Instruction Functions .......................................................................................... 9

1.3.3 Basic Instruction Formats ................................................................................... 20

1.3.4 Addressing Modes and Effective Address Calculation ........................................ 25

Section 2. Instruction Set..................................................................................31

2.1 Explanation Format..........................................................................................................31

ADD (add binary) (byte)..............................................................................................31

2.2 Instructions......................................................................................................................36

2.2.1(1) ADD (add binary) (byte) ................................................................................ 36

2.2.1 (2) ADD (add binary) (word) ..............................................................................37

2.2.2 ADDS (add with sign extension).........................................................................38

2.2.3 ADDX (add with extend carry)........................................................................... 39

2.2.4 AND (AND logical)............................................................................................ 40

2.2.5 ANDC (AND control register) ............................................................................41

2.2.6 BAND (bit AND)................................................................................................42

2.2.7 Bcc (branch conditionally).................................................................................. 44

2.2.8 BCLR (bit clear).................................................................................................47

2.2.9 BIAND (bit invert AND) ....................................................................................49

2.2.10 BILD (bit invert load)....................................................................................... 51

2.2.11 BIOR (bit invert inclusive OR) .........................................................................53

2.2.12 BIST (bit invert store).......................................................................................55

2.2.13 BIXOR (bit invert exclusive OR)......................................................................57

2.2.14 BLD (bit load) ..................................................................................................59

2.2.15 BNOT (bit NOT) .............................................................................................. 61

2.2.16 BOR (bit inclusive OR).....................................................................................63

i

2.2.17 BSET (bit set)...................................................................................................65

2.2.18 BSR (branch to subroutine)............................................................................... 67

2.2.19 BST (bit store).................................................................................................. 68

2.2.20 BTST (bit test).................................................................................................. 70

2.2.21 BXOR (bit exclusive OR)................................................................................. 72

2.2.22 (1) CMP (compare) (byte) CMP........................................................................ 74

2.2.22 (2) CMP (compare) (word)................................................................................75

2.2.23 DAA (decimal adjust add) ................................................................................ 76

2.2.24 DAS (decimal adjust subtract) .......................................................................... 78

2.2.25 DEC (decrement)..............................................................................................79

2.2.26 DIVXU (divide extend as unsigned)..................................................................80

2.227 EEPMOV (move date to EEPROM)...................................................................83

2.2.28 INC (increment.................................................................................................85

2.2.29 JMP (jump)....................................................................................................... 86

2.2.30 JSR (Jump to subroutine).................................................................................. 87

2.2.31 LDC (load to control register)...........................................................................88

2.2.32 (1) MOV (move data) (byte)............................................................................. 89

2.2.32(2) MOV (move data) (word)............................................................................. 90

2.2.32(3) MOV (move data) (byte).............................................................................. 91

2.2.32(4) MOV (move data) (word)............................................................................. 93

2.2.32(5) MOV (move) data) (byte).............................................................................95

2.2.32(6) MOV (move data) (word)............................................................................. 96

2.2.33 MULXU (multiply extend as unsigned) ............................................................ 98

2.2.34 NEG (negate).................................................................................................... 99

2.2.35 NOP (no operation)........................................................................................... 100

2.2.36 NOT (NOT = logical complement)................................................................... 101

2.2.37 OR (inclusive OR logical)................................................................................. 102

2.2.38 ORC (inclusive OR control register)................................................................. 103

2.2.39 POP (pop data)..................................................................................................104

2.2.40 PUSH (push data) ............................................................................................. 105

2.2.41 ROTL (rotate left)............................................................................................. 106

2.2.42 ROTR (rotate right) .......................................................................................... 107

2.2.43 ROTXL (rotate with extend carry left)..............................................................108

2.2.44 ROTXR (rotate with extend carry right)............................................................ 109

2.2.45 RTE (return from exception)............................................................................. 110

2.2.46 RTS (return from subroutine)............................................................................ 111

2.2.47 SHAL (shift arithmetic left).............................................................................. 112

2.2.48 SHAR (shift arithmetic right)............................................................................ 113

2.2.49 SHLL (shift logical left)....................................................................................115

2.2.50 SHLR (shift logical right) .................................................................................117

2.2.51 SLEEP (sleep) .................................................................................................. 119

2.2.52 STC (store from control register) ......................................................................120

2.2.53(1) SUB (subtract binary) (byte)......................................................................... 121

ii

2.2.53(2) SUB (subtract binary) (word)........................................................................123

2.2.54 SUBS (subtract with sign extension)................................................................. 124

2.2.55 SUBX (subtract with extend carry) ................................................................... 125

2.2.56 XOR (exclusive OR logical) .............................................................................126

2.2.57 XORC (exclusive OR control register)..............................................................127

2.3 Operation Code Map........................................................................................................128

2.4 List of Instructions...........................................................................................................130

2.5 Number of Execution States............................................................................................. 138

Section 3. CPU Operation States......................................................................145

3.1 Program Execution State.................................................................................................. 146

3.2 Exception Handling States ...............................................................................................146

3.2.1 Types and Priorities of Exception Handling........................................................ 146

3.2.2 Exception Sources and Vector Table...................................................................148

3.2.3 Outline of Exception Handling Operation........................................................... 148

3.3 Reset State.......................................................................................................................149

3.4 Power-Down State ...........................................................................................................149

Section 4. Basic Operation Timing...................................................................151

4.1 On-chip Memory (RAM, ROM)....................................................................................... 151

4.2 On-chip Peripheral Modules and External Devices...........................................................152

iii

iv

Preface

The H8/300L Series of single-chip microcomputers is built around the high-speed H8/300L
CPU, with an architecture featuring eight 16-bit (or sixteen 8-bit) general registers and a concise,
optimized instruction set.

This manual gives detailed descriptions of the H8/300L instructions. The descriptions apply to
all chips in the H8/300L Series. Assembly-language programmers should also read the separate
H8/300 Series Cross Assembler User's Manual.

For hardware details, refer to the hardware manual of the specific chip.

1

2

Section 1. CPU

1.1 Overview

The H8/300L CPU at the heart of the H8/300L Series features 16 general registers of 8 bits each
(or 8 registers of 16-bits each), and a concise, optimized instruction set geared to high-speed
operation.

1.1.1 Features

The H8/300L CPU has the following features.

• General register configuration
16 8-bit registers (can be used as 8 16-bit registers)

• 55 basic instructions
 Multiply and divide instructions
 Powerful bit manipulation instructions

• 8 addressing modes
 Register direct (Rn)
 Register indirect (@Rn)
 Register indirect with displacement (@(d: 16, Rn))
 Register indirect with post-increment/pre-decrement (@Rn+/@-Rn)
 Absolute address (@aa:8/@aa:16)
 Immediate (#xx:8/#xx:16)
 Program-counter relative (@(d:8, PC))
 Memory indirect (@@aa:8)

• 64-kbyte address space

• High-speed operation
 All frequently used instructions are executed in 2 to 4 states
 High-speed operating frequency: 5 MHz

• Add/subtract between 8/1 6-bit registers: 0.4 µs

8 × 8-bit multiply: 2.8 µs
16 ÷ 8-bit divide: 2.8 µs

• Low-power operation
Transition to power-down state using SLEEP instruction

3

1.1.2 Data Structure

The H8/300L CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 1 6-bit
(word) data.

• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a

byte operand.

• All operational instructions except ADDS and SUBS can operate on byte data.

• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.

• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in

packed BCD form. Each 4-bit of the byte is treated as a decimal digit.

Data Structure in General Registers: Data of all the sizes above can be stored in general
registers as shown in figure 1-1.

Data type Register No. Data format

1-Bit data RnH

1-Bit data RnL

Don't - care

07

Don't - care76543210

67 452301

07

Byte data RnH

Byte data RnL

Word data Rn

4-Bit BCD data RnH

07

M
S
B

L
S
B

Don't - care

70

Don't - care

M
S
B

L
S
B

15 0

M
S
B

L
S
B

70

Upper Lower

Don't - care

4

Data Structure in Memory: Figure 1-2 shows the structure of data in memory. The H8/300L
CPU is able to access word data in memory (MOV.W instruction), but only if the word data
starts from an even-numbered address. If an odd address is designated, no address error occurs,
but the access is performed starting from the previous even address, with the least significant bit
of the address regarded as 0.* The same applies to instruction codes.

* Note that the LSIs in the H8/300L Series also contain on-chip peripheral modules for

which access in word size is not possible. Details are given in the applicable hardware
manual.

Data Type Data FormatAddress

07

1-Bit data Address n

765 43210

Word data

Byte data (CCR) on stack

Word data on stack

Address nByte data

Even address
Odd address

Even address
Odd address

Even address
Odd address

M
S
B

L
S
B

Upper 8 bits
Lower 8 bits

CCR
CCR*

5

1.1.3 Address Space

The H8/300L CPU supports a 64-Kbyte address space (program code + data). The memory map
differs depending on the particular chip in the H8/300L Series and its operating mode. See the
applicable hardware manual for details.

1.1.4 Register Configuration

Figure 1-3 shows the register configuration of the H8/300L CPU. There are 16 8-bit general
registers (R0H, R0L, ..., R7H, R7L), which can also be accessed as eight 16-bit registers (R0 to
R7). There are two control registers: the 16-bit program counter (PC) and the 8-bit condition
code register (CCR).

General Registers (Rn)

Control Registers (CR)

7

R0H R0L

R4H

15 0

700

R1LR1H
R2LR2H
R3LR3H
R4L
R5LR5H

R6LR6H
R7LR7H (SP)

PC

47561230

CCR

I

UH U N

ZVC

SP: Stack Pointer

Program Counter

Condition Code Register

Carry flag
Overflow flag
Zero flag
Negative flag

Half-carry flag
Interrupt mask bit

User bit

Figure 1-3. CPU Registers

6

1.2 Registers

1.2.1 General Registers

All the general registers can be used as both data registers and address registers. When used as
address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as
data registers, they can be accessed as 16-bit registers (R0 to R7), or the high (R0H to R7H) and
low (R0L to R7L) bytes can be accessed separately as 8-bit registers. The register length is
determined by the instruction.

R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and
subroutine calls. In assembly language, the letters SP can be coded as a synonym for R7. As
indicated in figure 1-4, R7 (SP) points to the top of the stack.

Unused area

SP (R7)

Stack area

Figure 1-4. Stack Pointer

1.2.2 Control Registers

The CPU has a 16-bit program counter (PC) and an 8-bit condition code register (CCR).

(1) Program Counter (PC):

CPU will execute. Instructions are fetched by 16-bit (word) access, so the least significant bit
of the PC is ignored (always regarded as 0).

(2) Condition Code Register (CCR):

with an interrupt mask (I) bit and five flag bits: half-carry (H), negative (N), zero (Z),
overflow (V), and carry (C) flags. The two unused bits are available to the user. The bit
configuration of the condition code register is shown below.

This 16-bit register indicates the address of the next instruction the

This 8-bit register indicates the internal status of the CPU

7

Bit

76543210

I UHUNZVC

Initial value
Read/Write

Not fixed

*

1

R/W

*

R/W R/W R/W R/W R/W R/W R/W

*

****

*

Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked.
This bit is set to I automatically at the start of interrupt handling.

Bits 6 and 4--User Bits (U): These bits can be written and read by software for its own purposes
using LDC, STC, ANDC, ORC, and XORC instructions.

Bit 5--Half-Carry (H): This bit is used by add, subtract, and compare instructions to indicate a
borrow or carry out of bit 3 or bit 11. It is referenced by the decimal adjust instructions.

Bit 3--Negative (N): This bit indicates the value of the most significant bit (sign bit) of the
result of an instruction.

Bit 2--Zero (Z): This bit is set to 1 to indicate a zero result and cleared to 0 to indicate a
nonzero result.

Bit 1--Overflow (V): This bit is set to 1 when an arithmetic overflow occurs, and cleared to 0 at
other times.

Bit 0--Carry (C): This bit is used by:

• Add, subtract, and compare instructions, to indicate a carry or borrow at the most significant
bit

•

8

1.3 Instructions

Features:

• The H8/300L CPU has a concise set of 55 instructions.

• A general-register architecture is adopted.

• All instructions are 2 or 4 bytes long.

• Fast multiply/divide instructions and extensive bit manipulation instructions are supported.

• Eight addressing modes are supported.

1.3.1 Types of Instructions

Table 1-1 classifies the H8/300L instructions by type. Section 2, Instruction Set, gives detailed
descriptions.

Table 1-1. Instruction Classification

Function Instructions Types

Data transfer MOV, POP*, PUSH* 1
Arithmetic

operations
Logic operations AND, OR, XOR, NOT 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR

Branch Bcc**, JMP, BSR, JSR, RTS 5
System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8
Block data transfer EEPMOV 1

* POP Rn is equivalent to MOV.W @SP+, Rn.

PUSH Rn is equivalent to MOV.W Rn, @-SP.

** Bcc is a conditional branch instruction in which cc represents a condition.

ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS,
DAA, DAS, MULXU, DIVXU, CMP, NEG,

ROTXR

BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST

Total 55

14

8

14

1.3.2 Instruction Functions

Tables 1-2 to 1-9 give brief descriptions of the instructions in each functional group. The
following notation is used.

9

Notation

Rd General register (destination)
Rs General register (source)
Rn General register
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) bit of CCR
Z Z (zero) bit of CCR
V V (overflow) bit of CCR
C C (carry) bit of CCR
PC Program counter
SP Stack pointer (R7)
#Imm Immediate data
op Operation field
disp Displacement
+ Addition

- Subtraction

× Multiplication
÷ Division
∧ AND logical
∨ OR logical
⊕ Exclusive OR logical
→ Move
¬ Not

:3, :8, :16 3-bit, 8-bit, or 16-bit length

10

Table 1-2. Data Transfer Instructions

Instruction Size* Function

MOV B/W (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @-Rn, and @Rn+
addressing modes are available for byte or word data. The @aa:8
addressing mode is available for byte data only.
The @-R7 and @R7+ modes require word operands. Do not specify byte
size for these two modes.

POP W @SP+ → Rn

Pops a 16-bit general register from the stack.
Equivalent to MOV.W @SP+, Rn.

PUSH W Rn → @-SP

Pushes a 16-bit general register onto the stack.
Equivalent to MOV.W Rn, @-SP.

* Size: Operand size

B: Byte
W: Word

11

Table 1-3. Arithmetic Instructions

Instruction Size* Function

ADD
SUB

ADDX
SUBX

INC
DEC

ADDS
SUBS

DAA
DAS

MULXU B Rd × Rs → Rd

DIVXU B Rd ÷ Rs → Rd

CMP B/W Rd - Rs, Rd-#Imm

NEG B 0 - Rd → Rd

* Size: Operand size

B: Byte
W: Word

B/W Rd ± Rs → Rd, Rd + #Imm → Rd

Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register.
Immediate data cannot be subtracted from data in a general
register.
Word data can be added or subtracted only when both words are in
general registers.

B Rd ± Rs ± C → Rd, Rd ± #Imm ± C → Rd

Performs addition or subtraction with carry or borrow on byte data
in two general registers, or addition or subtraction on immediate
data and data in a general register.

B Rd ± 1 → Rd

Increments or decrements a general register.

W Rd ± 1 → Rd, Rd ± 2 → Rd

Adds or subtracts immediate data to or from data in a general
register. The immediate data must be 1 or 2.

B Rd decimal adjust → Rd

Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the condition code
register.

Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.

Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.

Compares data in a general register with data in another general
register or with immediate data. Word data can be compared only
between two general registers.

Obtains the two's complement (arithmetic complement) of data in a
general register.

12

Table 1-4. Logic operation Instructions

Instruction Size* Function

AND B Rd ∧ Rs → Rd, Rd ∧ #Imm → Rd

Performs a logical AND operation on a general register and another
general register or immediate data.

OR B Rd ∨ Rs → Rd, Rd ∨ #Imm → Rd

Performs a logical OR operation on a general register and another
general register or immediate data.

XOR B Rd ⊕ Rs → Rd, Rd ⊕ #Imm → Rd

Performs a logical exclusive OR operation on a general register and
another general register or immediate data.

NOT B ¬ Rd → Rd

Obtains the one's complement (logical complement) of general register
contents.

* Size: Operand size

B: Byte

Table 1-5. Shift Instructions

Instruction Size* Function

SHAL
SHAR

SHLL
SHLR

ROTL
ROTR

ROTXL
ROTXR

* Size: Operand size

B Rd shift → Rd

Performs an arithmetic shift operation on general register contents.

B Rd shift → Rd

Performs a logical shift operation on general register contents.

B Rd rotate → Rd

Rotates general register contents.

B Rd rotate through carry → Rd

Rotates general register contents through the C (carry) bit.

B: Byte

13

Table 1-6. Bit Manipulation Instructions

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

BCLR B 0 → (<bit-No.> of <EAd>)

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

BTST B ¬ (<bit-No.> of <EAd>) → Z

BAND

BIAND

BOR

BIOR

BXOR

BIXOR

BLD

BILD

BST

BIST

B

B

B

B

B

B

B

B

B

B

* Size: Operand size

B: Byte

Sets a specified bit in a general register or memory to 1. The bit is specified by a bit
number, given in 3-bit immediate data or the lower three bits of a general register.

Clears a specified bit in a general register or memory to 0. The bit is specified by a
bit number, given in 3-bit immediate data or the lower three bits of a general
register.

Inverts a specified bit in a general register or memory. The bit is specified by a bit
number, given in 3-bit immediate data or the lower three bits of a general register.

Tests a specified bit in a general register or memory and sets or clears the Z flag
accordingly. The bit is specified by a bit number, given in 3-bit immediate data or the
lower three bits of a general register.

C ∧ (<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory.
C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general register or memory.
The bit number is specified by 3-bit immediate data.

C ∨ (<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory.
C ∨ [¬(<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general register or memory.
The bit number is specified by 3-bit immediate data.

C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the C flag with a specified bit in a general register or memory.
C ⊕ [¬(<bit-No.> of <EAd>)] → C
Exclusive-ORs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.

(<bit-No.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C flag.
¬(<bit-No.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or memory to the C flag.
The bit number is specified by 3-bit immediate data.

C → (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
¬C → (<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general register or memory.
The bit number is specified by 3-bit immediate data.

14

Table 1-7. Branching Instructions

Instruction Size Function

Bcc -- Branches if condition cc is true. The branching conditions are as follows.

Mnemonic Description Condition

BRA (BT) Always (True) Always
BRN (BF) Never (False) Never
BHI High C ∨ Z = 0
BLS Low or Same C ∨ Z = 1
BCC (BHS) Carry Clear (High

or Same)
BCS (BLO) Carry Set (Low) C = 1
BNE Not Equal Z = 0
BEQ Equal Z = 1
BVC Overflow Clear V = 0
BVS Overflow Set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or Equal N ⊕ V = 0
BLT Less Than N ⊕ V = 1
BGT Greater Than Z ∨ (N ⊕ V) = 0
BLE Less or Equal Z ∨ (N ⊕ V) = 1

JMP -- Branches unconditionally to a specified address.
BSR -- Branches to a subroutine at a specified displacement from the current

address.

JSR -- Branches to a subroutine at a specified address.
RTS -- Returns from a subroutine.

C = 0

15

Table 1-8. System Control Instructions

Instruction Size* Function

RTE -- Returns from an exception handling routine.
SLEEP -- Causes a transition to power-down state.
LDC B Rs → CCR, #Imm → CCR

Moves immediate data or general register contents to the condition code
register.

STC B CCR → Rd

Copies the condition code register to a specified general register.

ANDC B CCR ∧ #Imm → CCR

Logically ANDs the condition code register with immediate data.

ORC B CCR ∨ #Imm → CCR

Logically ORs the condition code register with immediate data.

XORC B CCR ⊕ #Imm → CCR

Logically exclusive-ORs the condition code register with immediate data.

NOP -- PC + 2 → PC

Only increments the program counter.

* Size: Operand size

B: Byte

Table 1-9. Block Data Transfer Instruction

Instruction Size Function

EEPMOV -- if R4L ≠ 0 then

repeat @RS+ → @R6+

R4L - 1 → R4L

until R4L = 0
else next;
Moves a data block according to parameters set in general registers

R4L, R5, and R6.
R4L: size of block (bytes)
R5: starting source address
R6: starting destination address

Execution of the next instruction starts as soon as the block transfer is completed.

This instruction is for writing to the large-capacity EEPROM provided on chip with some
models in the H8/300L Series. For details see the applicable hardware manual.

16

Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read­modify-write instructions. They read a byte of data, modify one bit in the byte, then write the
byte back. Care is required when these instructions are applied to registers with write-only bits
and to the I/O port registers.

Sequence Operation

1 Read Read one data byte at the specified address
2 Modify Modify one bit in the data byte
3 Write Write the modified data byte back to the specified address

Example 1: BCLR is executed to clear bit 0 in port control register 4 (PCR4) under the
following conditions.

P47: Input pin, Low

P46: Input pin, High

P45 - P40: Output pins, Low

The intended purpose of this BCLR instruction is to switch P40 from output to input.

Before Execution of BCLR Instruction

P47 P46 P45 P44 P43 P42 P41 P40

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
PCR4 0 0 111111
PDR4 1 0 000000

Execution of BCLR Instruction

BCLR #0 @PCR4 ;clear bit 0 in PCR4

After Execution of BCLR Instruction

P47 P46 P45 P44 P43 P42 P41 P40

Input/output Output Output Output Output Output Output Output Input
Pin state Low High Low Low Low Low Low High
PCR4 11111110
PDR4 10000000

17

Explanation: To execute the BCLR instruction, the CPU begins by reading PCR4. Since PCR4
is a write-only register, it is read as H'FF, even though its true value is H'3F.

Next the CPU clears bit 0 of the read data, changing the value to H'FE.

Finally, the CPU writes this value (H'FE) back to PCR4 to complete the BCLR instruction.

As a result, bit 0 in PCR4 is cleared to 0, making P40 an input pin. In addition, bits 7 and 6 in
PCR4 are set to 1, making P47 and P46 output pins.

Example 2: BSET is executed to set bit 0 in the port 4 port data register (PDR4) under the
following conditions.

P47: Input pin, Low

P46: Input pin, High

P45 P40: Output pins, Low

The intended purpose of this BSET instruction is to switch the output level at P40 from Low to
High.

Before Execution of BSET Instruction

P47 P46 P45 P44 P43 P42 P41 P40

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
PCR4 0 0 1 1 1 1 1 1
PDR4 1 0 0 0 0 0 0 0

Execution of BSET Instruction

BSET #0 @PDR4 ;set bit 0 in port 4 port data register

After Execution of BSET Instruction

P47 P46 P45 P44 P43 P42 P41 P40

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low High
PCR4 0 0 1 1 1 1 1 1
PDR4 0 1 0 0 0 0 0 1

18

Explanation: To execute the BSET instruction, the CPU begins by reading port 4. Since P47
and P46 are input pins, the CPU reads the level of these pins directly, not the value in the port
data register. It reads P47 as Low (0) and P46 as High (1).

Since P45 to P40 are output pins, for these pins the CPU reads the value in PDR4. The CPU
therefore reads the value of port 4 as H'40, although the actual value in PDR4 is H'80.

Next the CPU sets bit 0 of the read data to 1, changing the value to H'41.

Finally, the CPU writes this value (H'41) back to PDR4 to complete the BSET instruction.

As a result, bit 0 in PDR4 is set to 0, switching pin P40 to High output. However, bits 7 and 6 in
PDR4 change their values.

19

1.3.3 Basic Instruction Formats

(1) Format of Data Transfer Instructions

Figure 1-5 shows the format used for data transfer instructions.

15 8 7 0

op

15 780

15 780

op

15

op

15

r

n

15

15

r

n

15

op

r

m

r

mn

r

mn

disp.

78

r

mn

7op8

7op80

abs.

78

78

IMM

r

n

r

r

r

abs.

r

n

IMMop Rn# xx:8

r

n

MOV

Rn

Rm

Rn @Rm, or @Rm Rn op

@(d:16,Rm) Rn, or
Rn @(d:16,Rm)

0

@ Rm+ Rn, or Rn @-Rm

0

@ aa :8 Rn, or Rn @ aa :8

@ aa :16 Rn, or 
Rn @ aa :16

0

0

# xx:16 Rn

20

15

op

780

Notation
op : Operation field
r , r : Register field

m

n

disp. : Displacement
abs. : Absolute address
IMM : Immediate data

Figure 1-5.Instruction Format of Data Transfer Instructions

r

n

POP, PUSH

(2) Format of Arithmetic, Logic Operation, and Shift Instructions

Figure 1-6 shows the format used for arithmetic, logic operation, and shift instructions.

15 8 7 0

o p

r

m

r

n

ADD, SUB, CMP(Rm)
ADDX, SUBX (Rm)

15 7

op

15 780

op

15

op

15

op

15

op IMM

15

op

Notation
op : Operation field
r , r : Register field

m

n

IMM : Immediate data

80

r

n

r

m

7

8

r

n

7

8

r

m

7

8

r

n

7

8

IMM

r

n

r

n

r

n

ADDS, SUBS, INC, DEC, DAA,
DAS, NEG, NOT

MULXU, DIVXU

0

ADD, ADDX, SUBX, CMP
(#xx :8)

0

AND, OR, XOR (Rm)

0

AND, OR, XOR (#xx:8)

0

SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR

Figure 1-6. Instruction Format of Arithmetic, Logic, and Shift Instructions

21

(3) Format of Bit Manipulation Instructions

Figure 1-7 shows the format used for bit manipulation instructions.

15

op

15 8 7 0

op

15 7op80

15

op
op

15

op

op

15

op

op

15

op

15

op

op

15

op
op

78

78

78

78

78

78

78

IMM n

r

m

r

n

r

n

r

m

IMM

IMM

r

m

r

n

IMM

IMM

abs.

abs

abs

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 00 0

0 0 0 0

r

r

n

0 0 0 0

r

n

0 0

BSET, BCLR, BNOT, BTST

0

Operand: register direct (Rn)
Bit No.: immediate (#xx:3)

Operand: register direct (Rn)
Bit No.: register direct (Rm)

Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)

0 0 0 0 IMMop

0

Operand: register indirect (@Rn)
Bit No.: register direct (Rm)

0

Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)

0

Operand: absolute (@aa:8)
Bit No.: register direct (Rm)

BAND, BOR, BXOR, BLD, BST

0

Operand: register direct (Rn)
Bit No.: immediate (#xx:3)

Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)

0 0

0

Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)

22

Notation
op : Operation field
r , r : Register field

m

n

abs. : Absolute address
IMM : Immediate data

Figure 1-7. Instruction Format of Bit Manipulation Instructions

15 8 7 0

op

15 7op80

IMM n

r

n

r

0 0 0 0

BIAND, BIOR, BIXOR, BILD, BIST

Operand: register direct (Rn)
Bit No.: immediate (#xx:3)

Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)

0 0 0 0 IMMop

15

op
op

Notation
op : Operation field
r , r : Register field

m

n

abs. : Absolute address
IMM : Immediate data

Figure 1-7. Instruction Format of Bit Manipulation Instructions (Cont.)

78

abs.

IMM

0 0 0 0

0

Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)

23

(4) Format of Branching Instructions

Figure 1-8 shows the format used for branching instructions.

15 8 7 0

op disp.

cc Bcc

15 7

op

80

r

m

000

0

JMP (@Rm)

15 780

op

JMP (@aa:16)

JMP (@@aa:8)

BSR

15

op

15

op

15

15

abs.

78

0

abs.

7

8

0

disp.

7

8

r

m

7

80

0
0000op JSR (@Rm)

op

JSR (@aa:16)

JSR (@@aa:8)

15

op

abs.

8

7

0

abs.

15

78

op

Notation
op : Operation field
cc : Condition field
r : Register field

m

disp. : Displacement 
abs. : Absolute address

Figure 1-8. Instruction Format of Branching Instructions

24

0

RTS