Hitachi H8/300H Programming Manual

Download

Page 1

H8/300H Series

Programming Manual

HITACHI

ADE-602-053A

Page 2

Major Revisions and Additions in this Version

Page Item Description P27 Figure 1-12 Instruction Formats Figure (4) amended P33 Table 1-6 Effective Address Calculation (8) Table amended P51 2.2.6 BAND Notes added P58 2.2.11 BIOR Operand Format and Number of Register direct 1st byte

States Required for Execution amended P67 2.2.18 BSR Notes description added P74 2.2.22 (3) CMP (L) Operand Format and Number of Operands amended

States Required for Execution P86 2.2.26 (3) DIVXS Description amended P87 DIVXS Example 2 Example 2 added P106 2.2.33 JSR Cautions Description added P108 2.2.34 (1) LDC (B) Description amended

/added

P110 2.2.34 (2) LDC (W) Operand Format and Number of Mnemonic amended

States Required for Execution P114 2.2.35 (4) MOV (B) Description Description amended P117 2.2.35 (5) MOV (W) Operand Format and Number of Table contents amended

States Required for Execution P119 2.2.35 (6) MOV (L) Operand Format and Number of Table contents amended

States Required for Execution P123 2.2.35 (8) MOV (W) Operand Format and Number of Table contents amended

States Required for Execution P125 2.2.35 (9) MOV (L) Operand Format and Number of Table contents amended

States Required for Execution P129 2.2.38 (2) MULXS (W) Figure amended P144 2.2.45 (2) POP (L) Number of execution states

amended

P146 2.2.46 (2) PUSH (L) Number of execution states

amended P160 2.2.52 RTS Figure amended P174 2.2.58 (1) STC (B) Assembly-Language Format Assembler format amended

2.2.58 (1) STC (B) Operand Format and Number of Mnemonic amended States Required for Execution

Page 3

Page Item Description P175 2.2.58 (2) STC (W) Instruction amended

2.2.58 (2) STC (W) Assembler Format Assembler format amended

P176 2.2.58 (2) STC (W) Operand Format and Number of Mnemonic amended

States Required for Execution P180 2.2.60 SUBS Operation Operation amended P189 (1) Data Transfer Instructions MOV.W @ERs+,Rd Operation amended

(1) Data Transfer Instructions MOV.W Rs,@ERd Operation amended (1) Data Transfer Instructions MOV.W Rs,@(d:24,ERd) Number of execution states

amended

(1) Data Transfer Instructions MOV.L #xx:32,ERd Operation and number of

execution states amended

P190 (1) Data Transfer Instructions MOV.L @ERs+,ERd Operation amended

(1) Data Transfer Instructions POP.L ERn Number of execution states

amended

(1) Data Transfer Instructions PUSH.L ERn Number of execution states

amended P191 (2) Arithmetic Operation Instructions DAA Rd Condition code amended P192 (2) Arithmetic Operation Instructions CMP.L #xx:32,ERd Number of execution states

amended P196 (5) Bit Manipulation Instructions Table amended P197, (6) Branch Instructions Added

P198 P198 (7) System Control Instructions LDC @ERs,CCR Operation amended

(7) System Control Instructions LDC @(d:16,ERs),CCR Operation amended (7) System Control Instructions LDC @(d:24,ERs),CCR Operation amended

(7) System Control Instructions LDC @ERs+,CCR Operation amended P204 Table 2-3 Instruction Codes (4) MOV.B@aa:16,Rd Instruction format amended P231 Table 2-8 Bus States BSR d:16 Execution order nos.2 to

5 amended

P234, Table 2-8 Bus States POP.W Rn to PUSH.L ERn Instruction added P235

P240 Figure 3-2 State Transitions Figure amended

Page 4

Section 1 CPU................................................................................................................... 1

1.1 Overview......................................................................................................................... 1

1.1.1 Features............................................................................................................... 1

1.1.2 Differences from H8/300 CPU........................................................................... 2

1.2 CPU Operating Modes.................................................................................................... 3

1.3 Address Space................................................................................................................. 7

1.4 Register Configuration.................................................................................................... 8

1.4.1 Overview............................................................................................................. 8

1.4.2 General Registers................................................................................................ 9

1.4.3 Control Registers................................................................................................ 10

1.4.4 Initial Register Values......................................................................................... 11

1.5 Data Formats................................................................................................................... 12

1.5.1 General Register Data Formats........................................................................... 12

1.5.2 Memory Data Formats........................................................................................ 13

1.6 Instruction Set................................................................................................................. 15

1.6.1 Overview............................................................................................................. 15

1.6.2 Instructions and Addressing Modes.................................................................... 16

1.6.3 Tables of Instructions Classified by Function .................................................... 18

1.6.4 Basic Instruction Formats................................................................................... 27

1.6.5 Addressing Modes and Effective Address Calculation...................................... 28

Section 2 Instruction Descriptions.............................................................................. 35

2.1 Tables and Symbols........................................................................................................ 35

2.1.1 Assembler Format............................................................................................... 36

2.1.2 Operation ............................................................................................................ 37

2.1.3 Condition Code................................................................................................... 38

2.1.4 Instruction Format .............................................................................................. 38

2.1.5 Register Specification......................................................................................... 39

2.1.6 Bit Data Access in Bit Manipulation Instructions.............................................. 40

2.2 Instruction Descriptions.................................................................................................. 41

2.2.1 (1) ADD (B) ........................................................................................................ 42

2.2.1 (2) ADD (W) ....................................................................................................... 43

2.2.1 (3) ADD (L) ........................................................................................................ 44

2.2.2 ADDS............................................................................................................ 45

2.2.3 ADDX............................................................................................................ 46

2.2.4 (1) AND (B) ........................................................................................................ 47

2.2.4 (2) AND (W) ....................................................................................................... 48

2.2.4 (3) AND (L) ........................................................................................................ 49

2.2.5 ANDC............................................................................................................ 50

Page 5

2.2.6 BAND............................................................................................................ 51

2.2.7 Bcc................................................................................................................. 52

2.2.8 BCLR............................................................................................................. 54

2.2.9 BIAND .......................................................................................................... 56

2.2.10 BILD.............................................................................................................. 57

2.2.11 BIOR.............................................................................................................. 58

2.2.12 BIST .............................................................................................................. 59

2.2.13 BIXOR........................................................................................................... 60

2.2.14 BLD............................................................................................................... 61

2.2.15 BNOT............................................................................................................ 62

2.2.16 BOR............................................................................................................... 64

2.2.17 BSET ............................................................................................................. 65

2.2.18 BSR................................................................................................................ 67

2.2.19 BST................................................................................................................ 68

2.2.20 BTST ............................................................................................................. 69

2.2.21 BXOR............................................................................................................ 71

2.2.22 (1) CMP (B) ........................................................................................................ 72

2.2.22 (2) CMP (W)....................................................................................................... 73

2.2.22 (3) CMP (L)......................................................................................................... 74

2.2.23 DAA .............................................................................................................. 75

2.2.24 DAS............................................................................................................... 77

2.2.25 (1) DEC (B)......................................................................................................... 79

2.2.25 (2) DEC (W)........................................................................................................ 80

2.2.25 (3) DEC (L)......................................................................................................... 81

2.2.26 (1) DIVXS (B)..................................................................................................... 82

2.2.26 (2) DIVXS (W) ................................................................................................... 84

2.2.26 (3) DIVXS .......................................................................................................... 86

2.2.27 (1) DIVXU (B).................................................................................................... 90

2.2.27 (2) DIVXU (W)................................................................................................... 91

2.2.28 (1) EEPMOV (B) ................................................................................................ 95

2.2.28 (2) EEPMOV (W)............................................................................................... 96

2.2.29 (1) EXTS (W)...................................................................................................... 98

2.2.29 (2) EXTS (L)....................................................................................................... 99

2.2.30 (1) EXTU (W)..................................................................................................... 100

2.2.30 (2) EXTU (L) ...................................................................................................... 101

2.2.31 (1) INC (B).......................................................................................................... 102

2.2.31 (2) INC (W)......................................................................................................... 103

2.2.31 (3) INC (L).......................................................................................................... 104

2.2.32 JMP................................................................................................................ 105

2.2.33 JSR................................................................................................................. 106

2.2.34 (1) LDC (B)......................................................................................................... 108

Page 6

2.2.34 (2) LDC (W)........................................................................................................ 109

2.2.35 (1) MOV (B) ....................................................................................................... 111

2.2.35 (2) MOV (W) ...................................................................................................... 112

2.2.35 (3) MOV (L)........................................................................................................ 113

2.2.35 (4) MOV (B) ....................................................................................................... 114

2.2.35 (5) MOV (W) ...................................................................................................... 116

2.2.35 (6) MOV (L)........................................................................................................ 118

2.2.35 (7) MOV (B) ....................................................................................................... 120

2.2.35 (8) MOV (W) ...................................................................................................... 122

2.2.35 (9) MOV (L)........................................................................................................ 124

2.2.36 MOVFPE....................................................................................................... 126

2.2.37 MOVTPE....................................................................................................... 127

2.2.38 (1) MULXS (B)................................................................................................... 128

2.2.38 (2) MULXS (W).................................................................................................. 129

2.2.39 (1) MULXU (B).................................................................................................. 130

2.2.39 (2) MULXU (W)................................................................................................. 131

2.2.40 (1) NEG (B)......................................................................................................... 132

2.2.40 (2) NEG (W) ....................................................................................................... 133

2.2.40 (3) NEG (L)......................................................................................................... 134

2.2.41 NOP............................................................................................................... 135

2.2.42 (1) NOT (B)......................................................................................................... 136

2.2.42 (2) NOT (W) ....................................................................................................... 137

2.2.42 (3) NOT (L)......................................................................................................... 138

2.2.43 (1) OR (B)........................................................................................................... 139

2.2.43 (2) OR (W).......................................................................................................... 140

2.2.43 (3) OR (L) ........................................................................................................... 141

2.2.44 ORC............................................................................................................... 142

2.2.45 (1) POP (W) ........................................................................................................ 143

2.2.45 (2) POP (L).......................................................................................................... 144

2.2.46 (1) PUSH (W) ..................................................................................................... 145

2.2.46 (2) PUSH (L)....................................................................................................... 146

2.2.47 (1) ROTL (B) ...................................................................................................... 147

2.2.47 (2) ROTL (W)..................................................................................................... 148

2.2.47 (3) ROTL (L)....................................................................................................... 149

2.2.48 (1) ROTR (B)...................................................................................................... 150

2.2.48 (2) ROTR (W)..................................................................................................... 151

2.2.48 (3) ROTR (L) ...................................................................................................... 152

2.2.49 (1) ROTXL (B) ................................................................................................... 153

2.2.49 (2) ROTXL (W) .................................................................................................. 154

2.2.49 (3) ROTXL (L).................................................................................................... 155

2.2.50 (1) ROTXR (B)................................................................................................... 156

Page 7

2.2.50 (2) ROTXR (W).................................................................................................. 157

2.2.50 (3) ROTXR (L) ................................................................................................... 158

2.2.51 RTE................................................................................................................ 159

2.2.52 RTS................................................................................................................ 160

2.2.53 (1) SHAL (B) ...................................................................................................... 161

2.2.53 (2) SHAL (W)..................................................................................................... 162

2.2.53 (3) SHAL (L)....................................................................................................... 163

2.2.54 (1) SHAR (B)...................................................................................................... 164

2.2.54 (2) SHAR (W)..................................................................................................... 165

2.2.54 (3) SHAR (L) ...................................................................................................... 166

2.2.55 (1) SHLL (B)....................................................................................................... 167

2.2.55 (2) SHLL (W)...................................................................................................... 168

2.2.55 (3) SHLL (L)....................................................................................................... 169

2.2.56 (1) SHLR (B)....................................................................................................... 170

2.2.56 (2) SHLR (W) ..................................................................................................... 171

2.2.56 (3) SHLR (L)....................................................................................................... 172

2.2.57 SLEEP ........................................................................................................... 173

2.2.58 (1) STC (B) ......................................................................................................... 174

2.2.58 (2) STC (W) ........................................................................................................ 175

2.2.59 (1) SUB (B)......................................................................................................... 177

2.2.59 (2) SUB (W)........................................................................................................ 178

2.2.59 (3) SUB (L)......................................................................................................... 179

2.2.60 SUBS............................................................................................................. 180

2.2.61 SUBX ............................................................................................................ 181

2.2.62 TRAPA .......................................................................................................... 182

2.2.63 (1) XOR (B) ........................................................................................................ 183

2.2.63 (2) XOR (W)....................................................................................................... 184

2.2.63 (3) XOR (L)......................................................................................................... 185

2.2.64 XORC............................................................................................................ 186

2.3 Instruction Set Summary ................................................................................................ 187

2.4 Instruction Codes............................................................................................................ 200

2.5 Operation Code Map....................................................................................................... 209

2.6 Number of States Required for Instruction Execution ................................................... 212

2.7 Condition Code Modification......................................................................................... 221

2.8 Bus cycles During Instruction Execution ....................................................................... 226

Section 3 Processing States........................................................................................... 239

3.1 Overview......................................................................................................................... 239

3.2 Program Execution State ................................................................................................ 241

3.3 Exception-Handling State............................................................................................... 241

3.3.1 Types of Exception Handling and Their Priority................................................ 241

Page 8

3.3.2 Exception-Handling Sequences.......................................................................... 242

3.4 Bus-Released State ......................................................................................................... 244

3.5 Reset State ...................................................................................................................... 244

3.6 Power-Down State .......................................................................................................... 244

3.6.1 Sleep Mode........................................................................................................... 244

3.6.2 Software Standby Mode ....................................................................................... 244

3.6.3 Hardware Standby Mode...................................................................................... 244

Section 4 Basic Timing .................................................................................................. 245

4.1 Overview......................................................................................................................... 245

4.2 On-Chip Memory (RAM, ROM).................................................................................... 245

4.3 On-Chip Supporting Modules......................................................................................... 247

4.4 External Data Bus ........................................................................................................... 248

Page 9

Section 1 CPU

1.1 Overview

The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

1.1.1 Features

The H8/300H CPU has the following features.

• Upward-compatible with H8/300 CPU

— Can execute H8/300 object programs

• General-register architecture

— Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit

registers)

• Sixty-two basic instructions

— 8/16/32-bit arithmetic and logic instructions — Multiply and divide instructions — Powerful bit-manipulation instructions

• Eight addressing modes

— Register direct [Rn] — Register indirect [@ERn] — Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] — Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn] — Absolute address [@aa:8, @aa:16, or @aa:24] — Immediate [#xx:8, #xx:16, or #xx:32] — Program-counter relative [@(d:8,PC) or @(d:16,PC)] — Memory indirect [@@aa:8]

• 16-Mbyte address space

• High-speed operation

— All frequently-used instructions execute in two to four states — Maximum clock frequency: 16 MHz

Page 10

— 8/16/32-bit register-register add/subtract: 125 ns —8 ×8-bit register-register multiply: 875 ns — 16 ÷ 8-bit register-register divide: 875 ns — 16 × 16-bit register-register multiply: 1375 ns — 32 ÷ 16-bit register-register divide: 1375 ns

• Two CPU operating modes

— Normal mode — Advanced mode

• Low-power mode

— Transition to power-down state by SLEEP instruction

1.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8/300H CPU has the following enhancements.

• More general registers

Eight 16-bit registers have been added.

• Expanded address space

Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

Advanced mode supports a maximum 16-Mbyte address space.

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.

• Enhanced instructions

Signed multiply/divide instructions and other instructions have been added.

Page 11

1.2 CPU Operating Modes

The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. The mode is selected at the mode pins of the microcontroller. For further information, refer to the relevant hardware manual.

Normal mode

CPU operating modes

Advanced mode

Maximum 64 kbytes, program and data areas combined

Maximum 16 Mbytes, program and data areas combined

Figure 1-1 CPU Operating Modes

(1) Normal Mode: The exception vector table and stack have the same structure as in the H8/300

CPU.

Address Space: A maximum address space of 64 kbytes can be accessed, as in the H8/300 CPU.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit data registers,

or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (R0 to R7) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register will be affected.

Instruction Set: All additional instructions and addressing modes of the H8/300 CPU can be used. If a 24-bit effective address (EA) is specified, only the lower 16 bits are used.

Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 1-2). The exception vector table differs depending on the microcontroller, so see the microcontroller hardware manual for further information.

Page 12

H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009

Reset exception vector

Reserved for system use

Exception vector 1

Exception vector 2

Exception vector table

Figure 1-2 Exception Vector Table (normal mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table.

Stack Structure: When the program counter (PC) is pushed on the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed on the stack in exception handling, they are stored in the same way as in the H8/300 CPU. See figure 1-3.

(a) Subroutine branch (b) Exception handling

Note: * Ignored at return.

(16 bits)

CCR

CCR*

(16 bits)

Figure 1-3 Stack Structure (normal mode)

Page 13

(2) Advanced Mode: In advanced mode the exception vector table and stack structure differ from the H8/300 CPU.

Address Space: Up to 16 Mbytes can be accessed linearly.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit data registers,

or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers. When a 32-bit register is used as an address register, the upper 8 bits are ignored.

Instruction Set: All additional instructions and addressing modes of the H8/300H can be used.

Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top

area starting at H'000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 1-4). The exception vector table differs depending on the microcontroller, so see the relevant hardware manual for further information.

H'000000

H'000003 H'000004

H'00000B H'00000C

Don’t care

Reset exception vector

Exception vector table

Reserved for system use

Don’t care

Exception vector

Figure 1-4 Exception Vector Table (advanced mode)

Page 14

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, of which the lower 24 bits are the branch address. Branch addresses can be stored in the top area from H'000000 to H'0000FF. Note that this area is also used for the exception vector table.

Stack Structure:When the program counter (PC) is pushed on the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed on the stack in exception handling, they are stored as shown in figure 1-5.

(a) Subroutine branch (b) Exception handling

Reserved

(24 bits)

Figure 1-5 Stack Structure (advanced mode)

CCR

(24 bits)

Page 15

1.3 Address Space

Figure 1-6 shows a memory map of the H8/300H CPU.

(a) Normal mode (b) Advanced mode

H'0000

H'FFFF

H'000000

H'FFFFFF

Figure 1-6 Memory Map

Page 16

1.4 Register Configuration

1.4.1 Overview

The H8/300H CPU has the internal registers shown in figure 1-7. There are two types of registers: general and extended registers, and control registers.

General registers (Rn) and extended registers (En)

15 07 07 0

E0 E1 E2 E3 E4 E5 E6

Control registers (CR)

R0H R1H R2H R3H R4H R5H R6H R7H

23 0

R0L R1L R2L R3L R4L R5L R6L R7L

Legend

Stack pointer

SP:

Program counter

PC:

Condition code register

CCR:

Interrupt mask bit

User bit or interrupt mask bit

Half-carry flag

Negative flag

Zero flag

Overflow flag

Carry flag

76543210

I UHUNZVCCCR

Figure 1-7 CPU Registers

Page 17

1.4.2 General Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers.

Figure 1-8 illustrates the usage of the general registers. The usage of each register can be selected independently.

Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

RH registers

(R0H to R7H)

R registers (R0 to R7)

RL registers

(R0L to R7L)

Figure 1-8 Usage of General Registers

Page 18

General register ER7 has the function of stack pointer (SP) in addition to its general-register



function, and is used implicitly in exception handling and subroutine calls. Figure 1-9 shows the stack.

Free area

SP (ER7)

Stack area

Figure 1-9 Stack

1.4.3 Control Registers

The control registers are the 24-bit program counter (PC) and the 8-bit condition-code register (CCR).

(1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.

(2) Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence.

Bit 6—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see the relevant microcontroller hardware manual.

Page 19

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.

Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction.

Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to store the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.

1.4.4 Initial Register Values

When the CPU is reset, the program counter (PC) is loaded from the vector table and the I bit in the condition-code register (CCR) is set to 1. The other CCR bits and the general registers and extended registers are not initialized. In particular, the stack pointer (extended register E7 and general register R7) is not initialized. The stack pointer must therefore be initialized by an MOV.L instruction executed immediately after a reset.

Page 20

1.5 Data Formats

The H8/300H CPU can process 1-bit, 4-bit, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

1.5.1 General Register Data Formats

Figure 1-10 shows the data formats in general registers.

Data type Register number Data format

1-bit data

4-bit BCD data

Byte data

RnH

RnL

RnH

RnL

RnH

RnL

76543210 Don’t care

Don’t care 76543210

MSB LSB

Don’t care

MSB

Figure 1-10 General Register Data Formats

Don’t careUpper Lower

Upper

Don’t care

Lower

LSB

Page 21

Word data

MSB LSB

Longword data

MSB

Legend

ERn:

General register ER

En:

General register E

Rn:

General register R

RnH:

General register RH

RnL:

General register RL

MSB:

Most significant bit

LSB:

Least significant bit

ERn

En Rn

LSB

Figure 1-10 General Register Data Formats (cont)

1.5.2 Memory Data Formats

Figure 1-11 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.

Page 22

Data type Data format

Address

1-bit data

Address L

76543210

Byte data

Word data

Longword data

Address L

Address 2M

Address 2M + 1

Address 2N Address 2N + 1 Address 2N + 2

Address 2N + 3

MSB LSB

MSB

LSB

MSB

LSB

Figure 1-11 Memory Data Formats

When ER7 is used as an address register to access the stack, the operand size should be word size or longword size.

Page 23

1.6 Instruction Set

1.6.1 Overview

The H8/300H CPU has 62 types of instructions, which are classified by function in table 1-1. For a detailed description of each instruction see section 2.2, Instruction Descriptions.

Table 1-1 Instruction Classification

Function Instructions Number

Data transfer MOV, PUSH

Arithmetic ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, 18 operations DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS,

EXTU Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, 8

ROTXR Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, 14

BXOR, BIXOR, BLD, BILD, BST, BIST

Branch Bcc

, JMP, BSR, JSR, RTS 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9 Block data transfer EEPMOV 1

Notes: The shaded instructions are not present in the H8/300 instruction set.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @–SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @–SP.

2. Bcc is the generic designation of a conditional branch instruction.

, POP

, MOVTPE, MOVFPE 3

Total 62 types

Page 24

1.6.2 Instructions and Addressing Modes

Table 1-2 indicates the instructions available in the H8/300H CPU.

Table 1-2 Instruction Set Overview

Function Instruction

Data transfer

Arithmetic operations

Logic operations

Shift

Bit manipulation

MOV POP, PUSH MOVFPE, MOVTPE ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS AND, OR, XOR NOT

#xx Rn @ERn @(d:16,ERn) @(d:24,ERn) @ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 —

BWL — —

BWL WL B

—

— — — —

—

— BWL

— — —

BWL — —

BWL BWL B

BWL B BW

BWL WL BWL

BWL BWL B

BWL — —

— — —

—

— — —

—

— — —

— — B

BWL — —

— — —

—

— — —

—

— — —

BWL — —

— — —

—

— — —

—

— — —

Addressing Modes

BWL — —

— — —

—

— — —

—

— — —

BWL

—

— — —

—

— — —

—

— — —

—

— — —

—

— — —

—

— — —

—

— — —

— WL —

— — —

—

— — —

—

— — —

Page 25

Table 1-2 Instruction Set Overview (cont)

Addressing Modes

Function Instruction

Branch

System control

Block data transfer

Bcc, BSR JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP EEPMOV.B EEPMOV.W

Legend

B: Byte W: Word L: Longword

: Newly added instruction in H8/300H CPU

Notes: 1. The operand size of the ADDS and SUBS instructions of the H8/300H CPU has been changed to longword size. (In the

H8/300 CPU it was word size.)

2. Because of its larger address space, the H8/300H CPU uses a 24-bit absolute address for the JMP and JSR instructions. (The H8/300 CPU used 16 bits.)

#xx Rn @ERn @(d:16,ERn) @(d:24,ERn) @ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 —

—

— — — — — — W W —

— — —

— — — — — — W W —

— — —

— — — — — — W W —

— — —

—

— — — — — W W —

— — —

—

— — — — — — — —

— — —

—

— — — — — — —

— — —

— —

— — —

Page 26

1.6.3 Tables of Instructions Classified by Function

Table 1-3 summarizes the instructions in each functional category. The notation used in table 1-3 is defined next.

Operation Notation

Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) bit of CCR Z Z (zero) bit of CCR V V (overflow) bit of CCR C C (carry) bit of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division

∧ AND logical ∨ OR logical ⊕ Exclusive OR logical → Move

¬ Not :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H/R0L to R7H/R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Page 27

Table 1-3 Instructions Classified by Function

Type Instruction Size* Function

Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.

MOVFPE B (EAs) → Rd

Moves external memory contents (addressed by @aa:16) to a general register in synchronization with an E clock.

MOVTPE B Rs → (EAd)

Moves general register contents to an external memory location (addressed by @aa:16) in synchronization with an E clock.

POP W/L @SP+ → Rn

Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.

Note: * Size refers to the operand size.

B: Byte W: Word L: Longword

Page 28

Table 1-3 Instructions Classified by Function (cont)

Type Instruction Size* Function

Arithmetic operations

Note: * Size refers to the operand size.

B: Byte W: Word L: Longword

ADD SUB

ADDX SUBX

INC DEC

ADDS SUBS

DAA DAS

MULXS B/W Rd × Rs → Rd

MULXU B/W Rd × Rs → Rd

DIVXS B/W Rd ÷ Rs → Rd

B/W/L Rd ±Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.)

B Rd ± Rs ±C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register.

B/W/L Rd ±1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ±4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data.

Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →16-bit quotient and 16-bit remainder.

Page 29

Table 1-3 Instructions Classified by Function (cont)

Type Instruction Size* Function

Arithmetic operations

Logic operations AND B/W/L Rd∧ Rs → Rd, Rd ∧ #IMM → Rd

Note: * Size refers to the operand size.

B: Byte W: Word L: Longword

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register or with immediate data, and sets the CCR according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two’s complement (arithmetic complement) of data in a general register.

EXTS W/L Rd (sign extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit.

EXTU W/L Rd (zero extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros.

Performs a logical AND operation on a general register and another general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and another general register or immediate data.

NOT B/W/L ¬ (Rd) → (Rd)

Takes the one’s complement of general register contents.

Page 30

Table 1-3 Instructions Classified by Function (cont)

Type Instruction Size* Function

Shift operations B/W/L Rd (shift) → Rd

Bit-manipulation instructions

Note: * Size refers to the operand size.

B: Byte W: Word L: Longword

SHAL SHAR

SHLL SHLR

ROTL ROTR

ROTXL ROTXR

BSET B 1 → (<bit-No.> of <EAd>)

BCLR B 0 → (<bit-No.> of <EAd>)

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

BTST B ¬ (<bit-No.> of <EAd>) → Z

BAND B C ∧ (<bit-No.> of <EAd>) → C

BIAND B C ∧ ¬ (<bit-No.> of <EAd>) → C

B/W/L Rd (shift) → Rd

B/W/L Rd (rotate) → Rd

Performs an arithmetic shift on general register contents.

Performs a logical shift on general register contents.

Rotates general register contents.

Rotates general register contents through the carry bit.

Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

Page 31

Table 1-3 Instructions Classified by Function (cont)

Type Instruction Size* Function

Bit-manipulation instructions

Note: * Size refers to the operand size.

B: Byte

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C

ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.

BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C

Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory operand to the carry flag.

BILD B ¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general register or memory operand to the carry flag.

The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a general register or memory operand.

BIST B ¬ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand.

The bit number is specified by 3-bit immediate data.

Page 32

Table 1-3 Instructions Classified by Function (cont)

Type Instruction Size* Function

Branching Bcc — Branches to a specified address if a specified condition instructions is true. The branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always BRN(BF) Never (false) Never BHI High C ∨ Z = 0 BLS Low or same C ∨ Z = 1 Bcc(BHS) Carry clear C = 0

(high or same) BCS(BLO) Carry set (low) C = 1 BNE Not equal Z = 0 BEQ Equal Z = 1 BVC Overflow clear V = 0 BVS Overflow set V = 1 BPL Plus N = 0 BMI Minus N = 1 BGE Greater or equal N ⊕ V = 0 BLT Less than N ⊕ V = 1 BGT Greater than Z ∨ (N ⊕ V) = 0 BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP — Branches unconditionally to a specified address. BSR — Branches to a subroutine at a specified address. JSR — Branches to a subroutine at a specified address. RTS — Returns from a subroutine.

Note: * Size refers to the operand size.

Page 33

Table 1-3 Instructions Classified by Function (cont)

Type Instruction Size* Function

System control instructions

Note: * Size refers to the operand size.

B: Byte W: Word

TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to the power-down state. LDC B/W (EAs) → CCR

Moves the source operand contents to the condition code register. Byte transfer is performed in the #xx:8, Rs addressing mode and word transfer in other addressing modes.

STC B/W CCR → (EAd)

Transfers the CCR contents to a destination location. Byte transfer is performed in the Rd addressing mode and word transfer in other addressing modes.

ANDC B CCR ∧ #IMM → CCR

Logically ANDs the condition code register with immediate data.

ORC B CCR ∨ #IMM → CCR

Logically ORs the condition code register with immediate data.

XORC B CCR ⊕ #IMM → CCR

Logically exclusive-ORs the condition code register with immediate data.

NOP — PC + 2 → PC

Only increments the program counter.

Page 34

Table 1-3 Instructions Classified by Function (cont)

Type Instruction Size* Function

Block data transfer instruction

Note: * Size refers to the operand size.

EEPMOV.B — if R4L ≠ 0 then

Repeat @ER5 +→ @ER6 +

R4L – 1→R4L

Until R4L = 0

else next;

EEPMOV.W — if R4 ≠ 0 then

Repeat @ER5 +→ @ER6 +

R4 – 1→R4L

Until R4 = 0

else next; Transfers a data block according to parameters set in

general registers R4L or R4, ER5, and R6. R4L or R4: size of block (bytes)

ER5: starting source address R6: starting destination address

Execution of the next instruction begins as soon as the transfer is completed.

Page 35

1.6.4 Basic Instruction Formats

The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc).

Operation Field: Indicates the function of the instruction, the effective address, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields.

Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.

Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or a displacement is treated as 32-bit data in which the first 8 bits are 0.

Condition Field: Specifies the branching condition of Bcc instructions.

Figure 1-12 shows examples of instruction formats.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp)

rn rm

NOP, RTS, etc.

ADD. Rn, Rm, etc.

MOV @(d:16, Rn), Rm

BRA @(d:8, PC)

Figure 1-12 Instruction Formats

Page 36

1.6.5 Addressing Modes and Effective Address Calculation

(1) Addressing Modes: The H8/300H CPU supports the eight addressing modes listed in table 1-

4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute (8-bit) addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 1-4 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn) 4 Register indirect with post-increment @ERn+

Register indirect with pre-decrement @–ERn 5 Absolute address @aa:8/@aa:16/@aa:24 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8

1 Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.

2 Register Indirect—@ERn: The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of a memory operand.

3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit displacement contained in the instruction is added to an address register (an extended register paired with a general register) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended when added.

Page 37

4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even.

• Register indirect with pre-decrement—@–ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the resulting register value should be even.

5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. Table 1-5 indicates the accessible address ranges.

Table 1-5 Absolute Address Access Ranges

Normal Mode Advanced Mode

8 bits H'FF00 to H'FFFF H'FFFF00 to H'FFFFF (@aa:8) (65,280 to 65,535) (16,776,960 to 16,777,215)

16 bits H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (@aa:16) (0 to 65,535) (0 to 32,767, 16,744,448 to 16,777,215)

24 bits H'0000 to H'FFFF H'00000 to H'FFFFF (@aa:24) (0 to 65,535) (0 to 16,777,215)

For further details on the accessible range, see the relevant microcontroller hardware manual.

6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in the second byte of the instruction, specifying a vector address.

Page 38

7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit program counter (PC) contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number.

8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction specifies a memory operand by an 8-bit absolute address. This memory operand contains a branch address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is 0 to 255 (H’0000 to H’00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand. The first byte is ignored and the branch address is 24 bits long. Note that the first part of the address range is also the exception vector area. For further details see the relevant microcontroller hardware manual.

Specified by @aa:8

Branch address

(a) Normal mode (b) Advanced mode

Specified by @aa:8

Reserved

Branch address

Figure 1-13 Branch Address Specification in Memory Indirect Mode

If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing access to be performed at the address preceding the specified address. [See (2) Memory Data Formats in section 1.5.2 for further information.]

(2) Effective Address Calculation: Table 1-6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Page 39

Table 1-6 Effective Address Calculation

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

(1) Register direct Rn

op Regm Regn

Operands are contents of regm and regn

op reg

(3)

@(d:16, ERn)

op reg

(4)

• Register indirect with post-increment @ERn+

reg

• Register indirect with pre-decrement @–ERn

op reg

disp

31 0 23 0

31 0

23 0

31 0

Sign extension

31 0

Operand Size Added Value

Byte Word Longword

1 2 4

disp

23 0

1, 2, or 4

23 0

1, 2, or 4

Page 40

Table 1-6 Effective Address Calculation (cont)

No. Addressing Mode and Instruction Format Effective Address Calculation

Absolute address

(5)

@aa:8

op abs

@aa:16

@aa:24

Immediate #xx:8/#xx:16/#xx:32

(6)

abs

IMM

Effective Address (EA)

23 08 7

H'FFFF

23 016 15

Sign

extension

23 0

Operand is immediate data.

Page 41

Table 1-6 Effective Address Calculation (cont)

(7)

Program-counter relative @(d:8, PC)/@(d:16, PC)

dispop

(8)

Memory indirect @@aa:8 Normal mode

absop

Effective Address Calculation Effective Address (EA)No. Addressing Mode and Instruction Format

Sign

extension

PC contents

23 0

disp

Advanced mode

H'0000 abs

absop

H'0000 abs

31 0

Memory contents

8 7

Memory contents

8 7

023

23 016 15

H'00

23 0

Page 42

Legend

reg, regm, regn: General registers op: Operation field disp: Displacement abs: Absolute address IMM: Immediate data

Page 43

Section 2 Instruction Descriptions

2.1 Tables and Symbols

This section explains how to read the tables describing each instruction. Note that the descriptions of some instructions extend over two pages or more.

Mnemonic (full name): Gives the full and mnemonic names of the instruction.

Type: Indicates the type of instruction.

Operation: Describes the instruction in symbolic notation. (See section 2.1.2, Operation.)

Assembly-Language Format: Indicates the assembly-language format of the instruction. (See

section 2.1.1, Assembler Format.)

Operand Size: Indicates the available operand sizes.

Condition Code: Indicates the effect of instruction execution on the flag bits in the CCR. (See

section 2.1.3, Condition Code.)

Description: Describes the operation of the instruction in detail.

Available Registers: Indicates which registers can be specified in the register field of the

instruction.

Operand Format and Number of States Required for Execution: Shows the addressing modes and instruction format together with the number of states required for execution.

Notes: Gives notes concerning execution of the instruction.

Page 44

2.1.1 Assembler Format

Example: ADD. B <EAs>, Rd

Destination operand

Source operand

Size

Mnemonic

The operand size is byte (B), word (W), or longword (L). Some instructions are restricted to a limited set of operand sizes.

The symbol <EA> indicates that two or more addressing modes can be used. The H8/300H CPU supports the eight addressing modes listed next. Effective address calculation is described in section 1.7, Effective Address Calculation.

Symbol Addressing Mode

Rn Register direct @ERn Register indirect @(d:16, ERn)/@(d:24, ERn) Register indirect with displacement (16-bit or 24-bit) @ERn+, @–ERn Register indirect with post-increment or pre-decrement @aa:8/16/24 Absolute address (8-bit, 16-bit, or 24-bit) #xx:8/16/32 Immediate (8-bit, 16-bit, or 32-bit) @(d:8, PC)/@(d:16, PC) Program-counter relative (8-bit or 16-bit) @@aa:8 Memory indirect

Page 45

2.1.2 Operation

The symbols used in the operation descriptions are defined as follows.

Symbol Meaning

Rd General destination register* Rs General source register* Rn General register* ERd General destination register (address register or 32-bit register) ERs General source register (address register or 32-bit register) ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand PC Program counter SP Stack pointer CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR disp Displacement → Transfer from the operand on the left to the operand on the right, or transition

from the state on the left to the state on the right + Addition of the operands on both sides – Subtraction of the operand on the right from the operand on the left × Multiplication of the operands on both sides ÷ Division of the operand on the left by the operand on the right

∧ Logical AND of the operands on both sides ∨ Logical OR of the operands on both sides ⊕ Logical exclusive OR of the operands on both sides

¬ Logical NOT (logical complement) ( ) < > Contents of effective address of the operand Note: * General registers include 8-bit registers (R0H to R7H and R0L to R7L), 16-bit registers

(R0 to R7 ad E0 to E7) and 32-bit registers.

Page 46

2.1.3 Condition Code

The symbols used in the condition-code description are defined as follows.

Symbol Meaning

↕ Changes according to the result of the instruction

* Undetermined (no guaranteed value)

0 Always cleared to 0 – Not affected by execution of the instruction ∆ Varies depending on conditions; see the notes.

2.1.4 Instruction Format

The symbols used in the instruction format descriptions are listed below.

Symbol Meaning

IMM Immediate data (2, 3, 8, 16, or 32 bits) abs Absolute address (8, 16, or 24 bits) disp Displacement (8, 16, or 24 bits) rs, rd, rn Register number (4 bits. The symbol rs corresponds to operand symbols such

as Rs. The symbol rd corresponds to operand symbols such as Rd. The symbol rn corresponds to the operand symbol Rn.)

ers, erd, ern Register number (3 bits. The symbol ers corresponds to operand symbols such

as ERs. The symbol erd corresponds to operand symbols such as ERd and @ERd. The symbol ern corresponds to the operand symbol ERn.)

Page 47

2.1.5 Register Specification

Address Register Specification: When a general register is used as an address register [@ERn,

@(d:16, ERn), @(d:24, ERn), @ERn+, or @–ERn], the register is specified by a 3-bit register field (ers or erd). The lower 24 bits of the register are valid.

Data Register Specification: A general register can be used as a 32-bit, 16-bit, or 8-bit data register, which is specified by a 3-bit register number. When a 32-bit register (ERn) is used as a longword data register, it is specified by a 3-bit register field (ers, erd, or ern). When a 16-bit register is used as a word data register, it is specified by a 4-bit register field (rs, rd, or rn). The lower 3 bits specify the register number. The upper bit is set to 1 to specify an extended register (En) or cleared to 0 to specify a general register (Rn). When an 8-bit register is used as a byte data register, it is specified by a 4-bit register field (rs, rd, or rn). The lower 3 bits specify the register number. The upper bit is set to 1 to specify a low register (RnL) or cleared to 0 to specify a high register (RnH). This is shown next.

Address Register 32-bit Register 16-bit Register 8-bit Register

000 ER0 0000 R0 0000 R0H 001 ER1 0001 R1 0001 R1H

111 ER7 0111 R7 0111 R7H

1000 E0 1000 E0L 1001 E1 1001 E1L

1111 E7 1111 E7L

Page 48

2.1.6 Bit Data Access in Bit Manipulation Instructions

Bit data is accessed as the n-th bit (n = 0, 1, 2, 3, …, 7) of a byte operand in a general register or memory. The bit number is given by 3-bit immediate data, or by the lower 3 bits of a general register value.

Example 1: To set bit 3 in R2H to 1

BSET R1L, R2H

R1L

R2H

Don’t care

011

Bit number

001

10110

Set to 1

Example 2: To load bit 5 at address H'FFFF02 into the bit accumulator

BLD #5, @FFFF02

H'FF02

Load

00101

110

The operand size and addressing mode are as indicated for register or memory operand data.

Page 49

2.2 Instruction Descriptions

The instructions are described starting in section 2.2.1.

Page 50

2.2.1 (1) ADD (B)

ADD (ADD binary) Add Binary

Operation

Rd + (EAs) → Rd

Assembly-Language Format

ADD.B <EAs>, Rd

Operand Size

Condition Code

IUIHUNZVC

—— ↕ — ↕↕↕↕

H: Set to 1 if there is a carry at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

Byte

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 7;

otherwise cleared to 0.

Description

This instruction adds the source operand to the contents of an 8-bit register Rd (destination operand) and stores the result in the 8-bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate ADD.B #xx:8, Rd 8 rd IMM 2 Register direct ADD.B Rs, Rd 0 8 rs rd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 51

2.2.1 (2) ADD (W)

ADD (ADD binary) Add Binary

Operation

Rd + (EAs) → Rd

Assembly-Language Format

ADD.W <EAs>, Rd

Operand Size

Condition Code

IUIHUNZVC

—— ↕ — ↕↕↕↕

H: Set to 1 if there is a carry at bit 11;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

Word

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 15;

otherwise cleared to 0.

Description

This instruction adds the source operand to the contents of a 16-bit register Rd (destination operand) and stores the result in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate ADD.W #xx:16, Rd 7 9 1 rd IMM 4 Register direct ADD.W Rs, Rd 0 9 rs rd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 52

2.2.1 (3) ADD (L)

ADD (ADD binary) Add Binary Operation

ERd + (EAs) → ERd

Assembly-Language Format

ADD.L <EAs>, ERd

Operand Size

Condition Code

IUIHUNZVC

—— ↕ — ↕↕↕↕

H: Set to 1 if there is a carry at bit 27;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

Longword

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 31;

otherwise cleared to 0.

Description

This instruction adds the source operand to the contents of a 32-bit register ERd (destination operand) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7 ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate ADD.L #xx:32, ERd 7 A 1 0 erd IMM 6 Register direct ADD.L Rs, ERd 0 A 1 ers 0 erd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

Instruction Format

Notes

No. of States

Page 53

2.2.2 ADDS

ADDS (ADD with Sign extension) Add Binary Address Data

Operation

Rd + 1 → ERd Rd + 2 → ERd Rd + 4 → ERd

Assembly-Language Format

ADDS #1, ERd ADDS #2, ERd ADDS #4, ERd

Condition Code

IUIHUNZVC

————————

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged. C: Previous value remains unchanged.

Operand Size

Longword

Description

This instruction adds the immediate value 1, 2, or 4 to the contents of a 32-bit register ERd. Differing from the ADD instruction, it does not affect the condition code flags.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode

Register direct ADDS #1, ERd 0 B 0 0 erd 2 Register direct ADDS #2, ERd 0 B 8 0 erd 2 Register direct ADDS #4, ERd 0 B 9 0 erd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 54

2.2.3 ADDX

ADDX (ADD with eXtend carry) Add with Carry

Operation

Rd + (EAs) + C → Rd

Assembly-Language Format

ADDX <EAs>, Rd

Operand Size

Condition Code

IUIHUNZVC

—— ↕ — ↕↕↕↕

H: Set to 1 if there is a carry at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

Byte

cleared to 0.

Z: Previous value remains unchanged if the

result is zero; otherwise cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a carry at bit 7;

otherwise cleared to 0.

Description

This instruction adds the source operand and carry flag to the contents of an 8-bit register Rd (destination register) and stores the result in the 8-bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate ADDX #xx:8, Rd 9 rd IMM 2 Register direct ADDX Rs, Rd 0 E rs rd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 55

2.2.4 (1) AND (B)

AND (AND logical) Logical AND

Operation

Rd ∧ (EAs) →Rd

Assembly-Language Format

AND.B <EAs>, Rd

Operand Size

Condition Code

IUIHUNZVC

———— ↕↕0—

H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise

cleared to 0.

Byte

Z: Set to 1 if the result is zero; otherwise

cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents of an 8-bit register Rd (destination register) and stores the result in the 8-bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate AND.B #xx:8, Rd E rd IMM 2 Register direct AND.B Rs, Rd 1 6 rs rd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 56

2.2.4 (2) AND (W)

AND (AND logical) Logical AND

Operation

Rd ∧ (EAs) →Rd

Assembly-Language Format

AND.W <EAs>, Rd

Operand Size

Condition Code

IUIHUNZVC

———— ↕↕0—

H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise

cleared to 0.

Word

Z: Set to 1 if the result is zero; otherwise

cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents of a 16-bit register Rd (destination register) and stores the result in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate AND.W #xx:16, Rd 7 9 6 rd IMM 4 Register direct AND.W Rs, Rd 6 6 rs rd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 57

2.2.4 (3) AND (L)

AND (AND logical) Logical AND

Operation

ERd ∧ (EAs) →ERd

Assembly-Language Format

AND.L <EAs>, ERd

Operand Size

Condition Code

IUIHUNZVC

———— ↕↕0—

H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise

cleared to 0.

Longword

Z: Set to 1 if the result is zero; otherwise

cleared to 0. V: Always cleared to 0. C: Previous value remains unchanged.

Description

This instruction ANDs the source operand with the contents of a 32-bit register ERd (destination register) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7 ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate AND.L #xx:32, ERd 7 A 6 0 erd IMM 6 Register direct AND.L Rs, ERd 0 1 F 0 6 6 0 ers 0 erd 4

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

Instruction Format

Notes

No. of States

Page 58

2.2.5 ANDC

ANDC (AND Control register) Logical AND with CCR

Operation

CCR ∧ #IMM →CCR

Assembly-Language Format

ANDC #xx:8, CCR

Operand Size

Condition Code

IUIHUNZVC

↕↕↕↕↕↕↕↕

I: Stores the corresponding bit of the result. UI: Stores the corresponding bit of the result H: Stores the corresponding bit of the result.

Byte

U: Stores the corresponding bit of the result N: Stores the corresponding bit of the result. Z: Stores the corresponding bit of the result. V: Stores the corresponding bit of the result. C: Stores the corresponding bit of the result.

Description

This instruction ANDs the contents of the condition-code register (CCR) with immediate data and stores the result in the condition-code register. No interrupt requests, including NMI, are accepted immediately after execution of this instruction.

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate ANDC #xx:8, CCR 0 6 IMM 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 59

2.2.6 BAND

BAND (Bit AND) Bit Logical AND

Operation

C ∧ (<bit No.> of <EAd>) →C

Assembly-Language Format

BAND #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

——————— ↕

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Stores the result of the operation.

Description

This instruction ANDs a specified bit in the destination operand with the carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

∧

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BAND #xx:3.Rd 7 6 0 Register indirect BAND #xx:3.@ERd 7 C 0 erd 0 7 6 0 Absolute address BAND #xx:3.@aa:8 7 E abs 7 6 0

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

IMM

rd 2

IMM IMM

Notes

See the corresponding LSI hardware manual for details on the access range for @aa : 8.

No. of

States

06 06

Page 60

2.2.7 Bcc

Bcc (Branch conditionally) Conditional Branch

Operation

If condition is true, then

PC + disp → PC

else next;

Assembly-Language Format

Bcc disp

→ Condition field

Operand Size

Condition Code

IUIHUNZVC

————————

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged. C: Previous value remains unchanged.

—

Description

If the condition specified in the condition field (cc) is true, a displacement is added to the program counter (PC) and execution branches to the resulting address. The PC value used in the address calculation is the starting address of the instruction immediately following the Bcc instruction. The displacement is a signed 8-bit or 16-bit value. The branch destination address can be located in the range from –126 to +128 bytes or –32766 to +32768 bytes from the Bcc instruction.

Mnemonic Meaning cc Condition Signed/Unsigned*

BRA (BT) Always (true) 0000 True BRn (BF) Never (false) 0001 False BHI HIgh 0010 C∨Z = 0 X > Y (unsigned) BLS Low or Same 0011 C∨Z = 1 X ≤ Y (unsigned) BCC (BHS) Carry Clear (High or Same) 0100 C = 0 X ≥ Y (unsigned) BCS (BLO) Carry Set (LOw) 0101 C = 1 X < Y (unsigned) BNE Not Equal 0110 Z = 0 X ≠ Y (unsigned or signed) BEQ EQual 0111 Z = 1 X > Y (unsigned or signed) BVC oVerflow Clear 1000 V = 0 BVS oVerflow Set 1001 V = 1 BPL PLus 1010 N = 0 BMI Minus 1011 N = 1 BGE Greater or Equal 1100 N⊕V = 0 X ≥ Y (signed) BLT Less Than 1101 N⊕V = 1 X < Y (signed) BGT Greater Than 1110 Z∨(N⊕V) = 0 X > Y (signed) BLE Less or Equal 1111 Z∨(N⊕V) = 1 X ≤ Y (signed)

Note: * If the immediately preceding instruction is a CMP instruction, X is the destination operand

and Y is the source operand.

Page 61

Bcc (Branch conditionally) Conditional Branch Operand Format and Number of States Required for Execution

Addressing

Mode

Program-counter relative

Mnemonic Operands

BRA (BT)

BRN (BF)

BHI

BLS

Bcc (BHS)

BCS (BLO)

BNE

BEQ

BVC

BVS

BPL

BMI

BGE

BLT

BGT

BLE

d:8 4 0 disp 4 d:16 5 8 0 0 disp 6 d:8 4 1 disp 4 d:16 5 8 1 0 disp 6 d:8 4 2 disp 4 d:16 5 8 2 0 disp 6 d:8 4 3 disp 4 d:16 5 8 3 0 disp 6 d:8 4 4 disp 4 d:16 5 8 4 0 disp 6 d:8 4 5 disp 4 d:16 5 8 5 0 disp 6 d:8 4 6 disp 4 d:16 5 8 6 0 disp 6 d:8 4 7 disp 4 d:16 5 8 7 0 disp 6 d:8 4 8 disp 4 d:16 5 8 8 0 disp 6 d:8 4 9 disp 4 d:16 5 8 9 0 disp 6 d:8 4 A disp 4 d:16 5 8 A 0 disp 6 d:8 4 B disp 4 d:16 5 8 B 0 disp 6 d:8 4 C disp 4 d:16 5 8 C 0 disp 6 d:8 4 D disp 4 d:16 5 8 D 0 disp 6 d:8 4 E disp 4 d:16 5 8 E 0 disp 6 d:8 4 F disp 4 d:16 5 8 F 0 disp 6

Instruction Format

1st byte 2nd byte 3rd byte 4th byte

No. of

States

Notes

1. The branch destination address must be even.

2. In machine language BRA, BRN, BCC, and BCS are identical to BT, BF, BHS, and BLO, respectively. The number of execution states for BRn (BF) is the same as for two NOP instructions.

Page 62

2.2.8 BCLR

BCLR (Bit CLeaR) Bit Clear

Operation

0 → (<bit No.> of <EAd>)

Assembly-Language Format

BCLR #xx:3, <EAd> BCLR Rn, <EAd>

Operand Size

Condition Code

IUIHUNZVC

————————

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged.

Byte

C: Previous value remains unchanged.

Description

This instruction clears a specified bit in the destination operand to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register (Rn). The specified bit is not tested. The condition-code flags are not altered.

Specified by #xx:3 or Rn

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H Rn: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Page 63

BCLR (Bit CLeaR) Bit Clear

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BCLR #xx:3, Rd 7 2 0 IMM rd 2 Register indirect BCLR Absolute address BCLR Register direct BCLR Rn, Rd 6 2 rn rd 2 Register indirect BCLR Rn, @ERd 7 D 0 erd 0 6 2 rn 0 8 Absolute address BCLR Rn, @aa:8 7 F abs 6 2 rn 0 8

Mnemonic Operands

#xx:3, @ERd #xx:3, @aa:8

1st byte 2nd byte 3rd byte 4th byte

7 D 0 erd 0 7 2 0 IMM 0 8 7 F abs 7 2 0 IMM 0 8

Instruction Format

No. of

States

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 64

2.2.9 BIAND

BIAND (Bit Invert AND) Bit Logical AND

Operation

C ∧ [¬ (<bit No.> of <EAd>)] → C

Assembly-Language Format

BIAND #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

——————— ↕

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Stores the result of the operation.

Description

This instruction ANDs the inverse of a specified bit in the destination operand with the carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

Invert

∧

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BIAND #xx:3.Rd 7 6 1 IMM rd 2 Register indirect BIAND #xx:3.@ERd 7 C 0 erd 0 7 6 1 IMM 0 6 Absolute address BIAND #xx:3.@aa:8 7 E abs 7 6 1 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 65

2.2.10 BILD

BILD (Bit Invert LoaD) Bit Load

Operation

¬ (<bit No.> of <EAd>) →C

Assembly-Language Format

BILD #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

——————— ↕

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Loaded with the inverse of the specified bit.

Description

This instruction loads the inverse of a specified bit from the destination operand into the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

Invert

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BILD #xx:3.Rd 7 7 1 IMM rd 2 Register indirect BILD #xx:3.@ERd 7 C 0 erd 0 7 7 1 IMM 0 6 Absolute address BILD #xx:3.@aa:8 7 E abs 7 7 1 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 66

2.2.11 BIOR

BIOR (Bit Invert inclusive OR) Bit Logical OR

Operation

C ∨ [¬ (<bit No.> of <EAd>)] →C

Assembly-Language Format

BIOR #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

——————— ↕

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Stores the result of the operation.

Description

This instruction ORs the inverse of a specified bit in the destination operand with the carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

Invert

∨

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BIOR #xx:3.Rd 7 4 1 IMM rd 2 Register indirect BIOR #xx:3.@ERd 7 C 0 erd 0 7 4 1 IMM 0 6 Absolute address BIOR #xx:3.@aa:8 7 E abs 7 4 1 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 67

2.2.12 BIST

BIST (Bit Invert STore) Bit Store

Operation

¬C→(<bit No.> of <EAd>)

Assembly-Language Format

BIST #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

————————

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Previous value remains unchanged.

Description

This instruction stores the inverse of the carry bit in a specified bit location in the destination operand. The bit number is specified by 3-bit immediate data. Other bits in the destination operand remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

Invert

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BIST #xx:3,Rd 6 7 1 IMM rd 2 Register indirect BIST #xx:3,@ERd 7 D 0 erd 0 6 7 1 IMM 0 8 Absolute address BIST #xx:3,@aa:8 7 F abs 6 7 1 IMM 0 8

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 68

2.2.13 BIXOR

BIXOR (Bit Invert eXclusive OR) Bit Exclusive Logical OR

Operation

C ⊕ [¬ (<bit No.> of <EAd>)] →C

Assembly-Language Format

BIXOR #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

——————— ↕

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Stores the result of the operation.

Description

This instruction exclusively ORs the inverse of a specified bit in the destination operand with the carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

Invert

⊕

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BIXOR #xx:3,Rd 7 5 1 IMM rd 2 Register indirect BIXOR #xx:3,@ERd 7 C 0 erd 0 7 5 1 IMM 0 6 Absolute address BIXOR #xx:3,@aa:8 7 E abs 7 5 1 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 69

2.2.14 BLD

BLD (Bit LoaD) Bit Load

Operation

(<Bit No.> of <EAd>) → C

Assembly-Language Format

BLD #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

——————— ↕

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Loaded from the specified bit.

Description

This instruction loads a specified bit from the destination operand into the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

07Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BLD #xx:3,Rd 7 7 0 IMM rd 2 Register indirect BLD #xx:3,@ERd 7 C 0 erd 0 7 7 0 IMM 0 6 Absolute address BLD #xx:3,@aa:8 7 E abs 7 7 0 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 70

2.2.15 BNOT

BNOT (Bit NOT) Bit NOT

Operation

¬ (<bit No.> of <EAd>)→ (<bit No.> of <EAd>)

Condition Code

IUIHUNZVC

————————

Assembly-Language Format

BNOT #xx:3, <EAd> BNOT Rn, <EAd>

Operand Size

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged. C: Previous value remains unchanged.

Byte

Description

This instruction inverts a specified bit in the destination operand. The bit number is specified by 3-bit immediate data or by the lower 3 bits of a general register. The specified bit is not tested. The condition code remains unchanged.

Specified by #xx:3 or Rn

70Bit No.

<EAd>

Invert

Available Registers

Rd: R0L to R7L, R0H to R7H Rn: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Page 71

BNOT (Bit NOT) Bit NOT

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BNOT #xx:3, Rd 7 1 0 IMM rd 2 Register indirect BNOT #xx:3, @ERd 7 D 0 erd 0 7 1 0 IMM 0 8 Absolute address BNOT #xx:3, @aa:8 7 F abs 7 1 0 IMM 0 8 Register direct BNOT Rn, Rd 6 1 rn rd 2 Register indirect BNOT Rn, @ERd 7 D 0 erd 0 6 1 rn 0 8 Absolute address BNOT Rn, @aa:8 7 F abs 6 1 rn 0 8

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 72

2.2.16 BOR

BOR (bit inclusive OR) Bit Logical OR

Operation

C ∨ [(<bit No.> of <EAd>)] → C

Assembly-Language Format

BOR #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

——————— ↕

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Stores the result of the operation.

Description

This instruction ORs a specified bit in the destination operand with the carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

∨

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BOR #xx:3,Rd 7 4 0 IMM rd 2 Register indirect BOR #xx:3,@ERd 7 C 0 erd 0 7 4 0 IMM 0 6 Absolute address BOR #xx:3,@aa:8 7 E abs 7 4 0 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 73

2.2.17 BSET

BSET (Bit SET) Bit Set

Operation

1 → (<bit No.> of <EAd>)

Assembly-Language Format

BSET #xx:3, <EAd> BSET Rn, <EAd>

Operand Size

Condition Code

IUIHUNZVC

————————

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged.

Byte

C: Previous value remains unchanged.

Description

This instruction sets a specified bit in the destination operand to 1. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The specified bit is not tested. The condition code flags are not altered.

Specified by #xx:3 or Rn

70Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H Rn: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Page 74

BSET (Bit SET) Bit Set

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BSET #xx:3, Rd 7 0 0 IMM rd 2 Register indirect BSET #xx:3, @ERd 7 D 0 erd 0 7 0 0 IMM 0 8 Absolute address BSET #xx:3, @aa:8 7 F abs 7 0 0 IMM 0 8 Register direct BSET Rn, Rd 6 0 rn rd 2 Register indirect BSET Rn, @ERd 7 D 0 erd 0 6 0 rn 0 8 Absolute address BSET Rn, @aa:8 7 F abs 6 0 rn 0 8

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

States

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual. <EAd> is byte data in a register or on memory.

No. of

Page 75

2.2.18 BSR

BSR (Branch to SubRoutine) Branch to Subroutine

Operation

PC → @–SP PC + disp → PC

Condition Code

IUIHUNZVC

————————

Assembly-Language Format

BSR disp

Operand Size

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged. V: Previous value remains unchanged.

—

C: Previous value remains unchanged.

Description

This instruction branches to a subroutine at a specified address. It pushes the program counter (PC) value onto the stack as a restart address, then adds a specified displacement to the PC value and branches to the resulting address. The PC value pushed onto the stack is the address of the instruction following the BSR instruction. The displacement is a signed 8-bit or 16-bit value, so the possible branching range is –126 to +128 bytes or –32766 to +32768 bytes from the address of the BSR instruction.

Operand Format and Number of States Required for Execution

Addressing

Mode

Program-counter relative

Mnemonic Operands

BSR

d:8 5 5 disp 6 8 d:16 5 C 0 0 disp 8 10

1st byte 2nd byte 3rd byte 4th byte Normal Advanced

Instruction Format No. of States

Notes

The stack structure differs between normal mode and advanced mode. In normal mode only the lower 16 bits of the program counter are pushed on the stack.

Reserved

23 16 15 8 7 0

Normal mode

23 16 15 8 7 0

Advanced mode

The branch address must be even.

Page 76

2.2.19 BST

BST (Bit STore) Bit Store

Operation

C → (<bit No.> of <EAd>)

Assembly-Language Format

BST #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

————————

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Previous value remains unchanged.

Description

This instruction stores the carry bit in a specified bit location in the destination operand. The bit number is specified by 3-bit immediate data. Other bits in the destination operand remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BST #xx:3,Rd 6 7 0 IMM rd 2 Register indirect BST #xx:3,@ERd 7 D 0 erd 0 6 7 0 IMM 0 8 Absolute address BST #xx:3,@aa:8 7 F abs 6 7 0 IMM 0 8

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 77

2.2.20 BTST

BTST (Bit TeST) Bit Test

Operation

¬ (<Bit No.> of <EAd>) →Z

Assembly-Language Format

Condition Code

IUIHUNZVC

————— ↕ ——

BTST #xx:3, <EAd> BTST Rn, <EAd>

H: Previous value remains unchanged. N: Previous value remains unchanged.

Operand Size

Byte

Z: Set to 1 if the specified bit is zero;

otherwise cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged.

Description

This instruction tests a specified bit in the destination operand and sets or clears the Z flag according to the result. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The destination operand remains unchanged.

Specified by #xx:3 or Rn

70Bit No.

<EAd>

Test

Available Registers

Rd: R0L to R7L, R0H to R7H Rn: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Page 78

BTST (Bit TeST) Bit Test

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BTST #xx:3, Rd 7 3 0 IMM rd 2 Register indirect BTST #xx:3, @ERd 7 C 0 erd 0 7 3 0 IMM 0 6 Absolute address BTST #xx:3, @aa:8 7 E abs 7 3 0 IMM 0 6 Register direct BTST Rn, Rd 6 3 rn rd 2 Register indirect BTST Rn, @ERd 7 C 0 erd 0 6 3 rn 0 6 Absolute address BTST Rn, @aa:8 7 E abs 6 3 rn 0 6

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

States

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

No. of

Page 79

2.2.21 BXOR

BXOR (Bit eXclusive OR) Bit Exclusive Logical OR

Operation

C ⊕ (<bit No.> of <EAd>) → C

Assembly-Language Format

BXOR #xx:3, <EAd>

Operand Size

Condition Code

IUIHUNZVC

——————— ↕

H: Previous value remains unchanged. N: Previous value remains unchanged. Z: Previous value remains unchanged.

Byte

V: Previous value remains unchanged. C: Stores the result of the operation.

Description

This instruction exclusively ORs a specified bit in the destination operand with the carry bit and stores the result in the carry bit. The bit number is specified by 3-bit immediate data. The destination operand contents remain unchanged.

Specified by #xx:3

Bit No.

<EAd>

⊕

Available Registers

Rd: R0L to R7L, R0H to R7H ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Register direct BXOR #xx:3,Rd 7 5 0 IMM rd 2 Register indirect BXOR #xx:3,@ERd 7 C 0 erd 0 7 5 0 IMM 0 6 Absolute address BXOR #xx:3,@aa:8 7 E abs 7 5 0 IMM 0 6

Note: * The addressing mode is the addressing mode of the destination operand <EAd>.

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Notes

For the @aa:8 access range, refer to the relevant microcontroller hardware manual.

Page 80

2.2.22 (1) CMP (B)

CMP (CoMPare) Compare

Operation

Rd – (EAs), set or clear CCR

Assembly-Language Format

CMP.B <EAs>, Rd

Operand Size

Condition Code

IUIHUNZVC

—— ↕ — ↕↕↕↕

H: Set to 1 if there is a borrow at bit 3;

otherwise cleared to 0.

N: Set to 1 if the result is negative; otherwise

Byte

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 7;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of an 8-bit register Rd (destination register) and sets or clears the CCR bits according to the result. The destination register contents remain unchanged.

Available Registers

Rd: R0L to R7L, R0H to R7H Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate CMP.B #xx:8, Rd A rd IMM 2 Register direct CMP.B Rs, Rd 1 C rs rd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 81

2.2.22 (2) CMP (W)

CMP (CoMPare) Compare

Operation

Rd – (EAs), set CCR

Assembly-Language Format

CMP.W <EAs>, Rd

Operand Size

Condition Code

IUIHUNZVC

—— ↕ — ↕↕↕↕

H: Set to 1 if there is a borrow at bit 11;

otherwise cleared to 0. N: Set to 1 if the result is negative; otherwise

Word

cleared to 0. Z: Set to 1 if the result is zero; otherwise

cleared to 0. V: Set to 1 if an overflow occurs; otherwise

cleared to 0. C: Set to 1 if there is a borrow at bit 15;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of a 16-bit register Rd (destination register) and sets or clears the CCR bits according to the result. The contents of the 16-bit register Rd remain unchanged.

Available Registers

Rd: R0 to R7, E0 to E7 Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate CMP.W #xx:16, Rd 7 9 2 rd IMM 4 Register direct CMP.W Rs, Rd 1 D rs rd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 82

2.2.22 (3) CMP (L)

CMP (CoMPare) Compare

Operation

ERd – (EAs), set CCR

Assembly-Language Format

CMP.L <EAs>, ERd

Operand Size

Condition Code

IHNZVC

—— ↕ — ↕↕↕↕

I: Previous value remains unchanged. H: Set to 1 if there is a borrow at bit 27;

otherwise cleared to 0.

Longword

N: Set to 1 if the result is negative; otherwise

cleared to 0.

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Set to 1 if there is a borrow at bit 31;

otherwise cleared to 0.

Description

This instruction subtracts the source operand from the contents of a 32-bit register ERd (destination register) and sets or clears the CCR bits according to the result. The contents of the 32-bit register ERd remain unchanged.

Available Registers

ERd: ER0 to ER7 ERs: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode

Immediate CMP.L #xx:32, ERd 7 A 2 0 erd IMM 6 Register direct CMP.L ERs, ERd 1 F 1 ers 0 erd 2

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte

Instruction Format

Notes

No. of States

Page 83

2.2.23 DAA

DAA (Decimal Adjust Add) Decimal Adjust

Operation

Rd (decimal adjust) → Rd

Assembly-Language Format

Condition Code

IUIHUNZVC

——*—↕↕*↕

DAA Rd

H: Undetermined (no guaranteed value).

Operand Size

Byte

N: Set to 1 if the adjusted result is negative;

otherwise cleared to 0. Z: Set to 1 if the adjusted result is zero;

otherwise cleared to 0. V: Undetermined (no guaranteed value). C: Set to 1 if there is a carry at bit 7;

otherwise left unchanged.

Description

Given that the result of an addition operation performed by an ADD.B or ADDX instruction on 4-bit BCD data is contained in an 8-bit register Rd (destination register) and the carry and halfcarry flags, the DAA instruction adjusts the general register contents by adding H'00, H'06, H'60, or H'66 according to the table below.

C Flag Upper 4 Bits H Flag Lower 4 Bits C Flag before before before before after

Adjustment Adjustment Adjustment Adjustment Adjustment

0 0 to 9 0 0 to 9 00 0 0 0 to 8 0 A to F 06 0 0 0 to 9 1 0 to 3 06 0 0 A to F 0 0 to 9 60 1 0 9 to F 0 A to F 66 1 0 A to F 1 0 to 3 66 1 1 1 to 2 0 0 to 9 60 1 1 1 to 2 0 A to F 66 1 1 1 to 3 1 0 to 3 66 1

Value Added (hexadecimal)

Page 84

DAA (Decimal Adjust Add) Decimal Adjust

Available Registers

Rd: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Addressing

Mode

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above.

No. of

States

Page 85

2.2.24 DAS

DAS (Decimal Adjust Subtract) Decimal Adjust

Operation

Rd (decimal adjust) → Rd

Assembly-Language Format

DAS Rd

Operand Size

Condition Code

IUIHUNZVC

——*—↕↕*—

H: Undetermined (no guaranteed value). N: Set to 1 if the adjusted result is negative;

otherwise cleared to 0.

Byte

Z: Set to 1 if the adjusted result is zero;

otherwise cleared to 0. V: Undetermined (no guaranteed value). C: Previous value remains unchanged.

Description

Given that the result of a subtraction operation performed by a SUB.B, SUBX.B, or NEG.B instruction on 4-bit BCD data is contained in an 8-bit register Rd (destination register) and the carry and half-carry flags, the DAS instruction adjusts the general register contents by adding H'00, H'FA, H'A0, or H'9A according to the table below.

C Flag Upper 4 Bits H Flag Lower 4 Bits C Flag before before before before after

Adjustment Adjustment Adjustment Adjustment Adjustment

0 0 to 9 0 0 to 9 00 0 0 0 to 8 1 6 to F FA 0 1 7 to F 0 0 to 9 A0 1 1 6 to F 1 6 to F 9A 1

Value Added (hexadecimal)

Available Registers

Rd: R0L to R7L, R0H to R7H

Page 86

DAS (Decimal Adjust Subtract) Decimal Adjust

Operand Format and Number of States Required for Execution

Addressing

Mode

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

Valid results (8-bit register Rd contents and C, V, Z, N, and H flags) are not assured if this instruction is executed under conditions other than those described above.

No. of

States

Page 87

2.2.25 (1) DEC (B)

DEC (DECrement) Decrement

Operation

Rd – 1 → Rd

Assembly-Language Format

DEC.B Rd

Operand Size

Condition Code

IUIHUNZVC

———— ↕↕↕—

H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise

cleared to 0.

Byte

Z: Set to 1 if the result is zero; otherwise

cleared to 0. V: Set to 1 if an overflow occurs (the

previous value in Rd was H'80);

otherwise cleared to 0. C: Previous value remains unchanged.

Description

This instruction decrements an 8-bit register Rd (destination register) and stores the result in the 8-bit register Rd.

Available Registers

Rd: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Addressing

Mode

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

An overflow is caused by the operation H'80 – 1 → H'7F.

No. of

States

Page 88

2.2.25 (2) DEC (W)

DEC (DECrement) Decrement

Operation

Rd – 1 → Rd Rd – 2 → Rd

Condition Code

IUIHUNZVC

———— ↕↕↕—

Assembly-Language Format

DEC.W #1, Rd DEC.W #2, Rd

H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise

cleared to 0.

Operand Size

Word

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs (the

previous value in Rd was H'8000); otherwise cleared to 0.

C: Previous value remains unchanged.

Description

This instruction subtracts the immediate value 1 or 2 from the contents of a 16-bit register Rd (destination register) and stores the result in the 16-bit register Rd.

Available Registers

Rd: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Addressing

Mode

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

An overflow is caused by the operations H'8000 – 1 → H'7FFF, H'8000 – 2 → H'7FFE, and H'8001 – 2 → H'7FFF.

No. of

States

Page 89

2.2.25 (3) DEC (L)

DEC (DECrement) Decrement

Operation

ERd – 1 → ERd ERd – 2 → ERd

Condition Code

IUIHUNZVC

———— ↕↕↕—

Assembly-Language Format

DEC.L #1, ERd DEC.L #2, ERd

H: Previous value remains unchanged. N: Set to 1 if the result is negative; otherwise

cleared to 0.

Operand Size

Longword

Z: Set to 1 if the result is zero; otherwise

cleared to 0.

V: Set to 1 if an overflow occurs; otherwise

cleared to 0.

C: Previous value remains unchanged.

Description

This instruction subtracts the immediate value 1 or 2 from the contents of a 32-bit register ERd (destination register) and stores the result in the 32-bit register ERd.

Available Registers

ERd: ER0 to ER7

Operand Format and Number of States Required for Execution

Addressing

Mode*

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Notes

An overflow is caused by the operations H'80000000 – 1 → H'7FFFFFFF, H'80000000 – 2 → H'7FFFFFFE, and H'80000001 – 2 → H'7FFFFFFF.

Page 90

2.2.26 (1) DIVXS (B)

DIVXS (DIVide eXtend as Signed) Divide Signed

Operation

Rd ÷ Rs → Rd

Assembly-Language Format

DIVXS.B Rs, Rd

Operand Size

Condition Code

IUIHUNZVC

———— ↕↕——

H: Previous value remains unchanged. N: Set to 1 if the quotient is negative;

otherwise cleared to 0.

Byte

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged.

Description

This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division is signed. The operation performed is 16 bits ÷ 8 bits →8-bit quotient and 8-bit remainder. The quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd.

Rd Rs Rd

Dividend ÷ Divisor → Remainder Quotient

16 bits 8 bits 8 bits 8 bits

Valid results are not assured if division by zero is attempted or an overflow occurs. For information on avoiding overflow, see DIVXS Instruction, Zero Divide, and Overflow.

Available Registers

Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H

Page 91

DIVXS (B)

DIVXS (DIVide eXtend as Signed) Divide Signed Operand Format and Number of States Required for Execution

Addressing

Mode

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Notes

The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign. The N flag may therefore be set to 1 when the quotient is zero.

Page 92

2.2.26 (2) DIVXS (W)

DIVXS (DIVide eXtend as Signed) Divide Signed Operation

ERd ÷ Rs →ERd

Assembly-Language Format

DIVXS.W Rs, ERd

Operand Size

Condition Code

IUIHUNZVC

———— ↕↕——

H: Previous value remains unchanged. N: Set to 1 if the quotient is negative;

otherwise cleared to 0.

Word

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged.

Description

This instruction divides the contents of a 32-bit register ERd (destination register) by the contents of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The division is signed. The operation performed is 32 bits ÷ 16 bits →16-bit quotient and 16-bit remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The remainder is placed in the upper 16 bits (Ed).

ERd Rs ERd

Dividend ÷ Divisor → Remainder Quotient

32 bits 16 bits 16 bits 16 bits

Valid results are not assured if division by zero is attempted or an overflow occurs. For information on avoiding overflow, see DIVXS Instruction, Zero Divide, and Overflow.

Available Registers

ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7

Page 93

DIVXS (W)

DIVXS (DIVide eXtend as Signed) Divide Signed

Operand Format and Number of States Required for Execution

Addressing

Mode

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Notes

The N flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign. The N flag may therefore be set to 1 when the quotient is zero.

Page 94

2.2.26 (3) DIVXS

DIVXS (DIVide eXtend as Signed) Divide Signed

DIVXS instruction, Division by Zero, and Overflow

Since the DIVXS instruction does not detect division by zero or overflow, applications should detect and handle division by zero and overflow using techniques similar to those used in the following program.

1. Programming solution for DIVXS.B R0L, R1 Example 1: Convert dividend and divisor to non-negative numbers, then use DIVXU

programming solution for zero divide and overflow

MOV.B R0L, R0L ; Test divisor BEQ ZERODIV ; Branch to ZERODIV if R0L = 0 ANDC #AF, CCR ; Clear CCR user bits (bits 6 and 4) to 0 BPL L1 ; Branch to L1 if N flag = 0 (positive divisor) NEG.B R0L ; Take 2’s complement of R0L to make sign positive ORC #10, CCR ; Set CCR bit 4 to 1

L1: MOV.W R1.R1 ; Test dividend

BPL L2 ; Branch to L2 if N flag = 0 (positive dividend) NEG.W R1 ; Take 2’s complement of R1 to make sign positive XORC #50, CCR ; Invert CCR bits 6 and 4

L2: MOV.B R1H, R2L ;

EXTU.W R2 ; DIVXU.B R0L, R2 ; Use DIVXU.B instruction to divide non-negative dividend MOV.B R2H, R1H ; by positive divisor DIVXU.B R0L, R1 ; 16 bits ÷ 8 bits → quotient (16 bits) and remainder (8 bits) MOV.B R2L, R2H ; (See DIVXU Instruction, Zero Divide, and Overflow) MOV.B R1L, R2L ;

STC CCR, R1L ; Copy CCR contents to R1L BTST #6, R1L ; Test CCR bit 6 BEQ L3 ; Branch to L3 if bit 6 = 1 NEG.B R1H ; Take 2’s complement of R1H to make sign of remainder negative

L3: BTST #4, R1L ; Test CCR bit 4

BEQ L4 ; Branch to L4 if bit 4 = 1 NEG.W R2 ; Take 2’s complement of R2 to make sign of quotient negative

L4: RTS ZERODIV:

; Zero-divide handling routine

This program leaves a 16-bit quotient in R2 and an 8-bit remainder in R1H.

R1H R2

R0L

Dividend

Remainder

Quotient

Divisor

Page 95

DIVXS

DIVXS (DIVide eXtend as Signed) Divide Signed

Example 2: Sign extend the 8-bit divisor to 16 bits, sign extend the 16-bit dividend to 32 bits, and

then use DIVXS to divide

EXTS.W R0 BEQ ZERODIV EXTS.L ER1 DIVXS.L R0,ER1 RTS

ZERODIV:

This program leaves the 16-bit quotient in R1 and the 8-bit remainder in E1 (in a 16-bit sign extended format).

ER1

ROL

R0L

Dividend

Sign extension

DividendSign extension

QuotientRemainder

Divisor

Page 96

DIVXS

DIVXS (DIVide eXtend as Signed) Divide Signed

2. Programming solution for DIVXS.W R0, ER1 Example: Convert dividend and divisor to non-negative numbers, then use DIVXU programming

solution for zero divide and overflow

MOV.W R0, R0 ; Test divisor BEQ ZERODIV ; Branch to ZERODIV if R0 = 0 ANDC #AF, CCR ; Clear CCR user bits (bits 6 and 4) to 0 BPL L1 ; Branch to L1 if N flag = 0 (positive divisor) NEG.W R0 ; Take 2’s complement of R0 to make sign positive ORC #10, CCR ; Set CCR bit 4 to 1

L1: MOV.L ER1,ER1 ; Test dividend

BPL L2 ; Branch to L2 if N flag = 0 (positive dividend) NEG.L ER1 ; Take 2’s complement of ER1 to make sign positive XORC #50,CCR ; Invert CCR bits 6 and 4

L2: MOV.W E1, R2 ;

EXTU.L ER2 ; DIVXU.W R0, E2 ; Use DIVXU.W instruction to divide non-negative dividend MOV.W E2, R1 ; by positive divisor DIVXU.W R0, ER1 ; 32 bits ÷ 16 bits → quotient (32 bits) and remainder MOV.W R2, E2 (16 bits) MOV.W R1, R2 (See DIVXU Instruction, Zero Divide, and Overflow)

STC CCR, R1L ; Copy CCR contents to R1L BTST #6, R1L ; Test CCR bit 6 BEQ L3 ; Branch to L3 if bit 6 = 1 NEG.W E1 ; Take 2’s complement of E1 to make sign of remainder negative

L3: BTST #4, R1L ; Test CCR bit 4

BEQ L4 ; Branch to L4 if bit 4 = 1 NEG.L ER2 ; Take 2’s complement of ER2 to make sign of quotient negative

L4: RTS ZERODIV:

; Zero-divide handling routine

This program leaves a 32-bit quotient in ER2 and a 16-bit remainder in E1.

ER1

E1 ER2

Dividend

Remainder

Quotient

Divisor

Page 97

DIVXS (W)

DIVXS (DIVide eXtend as Signed) Divide Signed

The preceding two examples flag the status of the divisor and dividend in the UI and U bits in the CCR, and modify the sign of the quotient and remainder in the unsigned division result of the DIVXU instruction as shown next.

UI U Divisor Dividend Remainder Quotient Sign Modification

0 0 Positive Positive Positive Positive No sign modification 0 1 Negative Positive Positive Negative Sign of quotient is reversed 1 0 Negative Negative Negative Positive Sign of remainder is reversed 1 1 Positive Negative Negative Negative Signs of quotient and remainder

are both reversed

Page 98

2.2.27 (1) DIVXU (B)

DIVXU (DIVide eXtend as Unsigned) Divide

Operation

Rd ÷ Rs → Rd

Assembly-Language Format

Condition Code

IUIHUNZVC

———— ↕↕——

DIVXU.B Rs, Rd

H: Previous value remains unchanged.

Operand Size

Byte

N: Set to 1 if the divisor is negative;

otherwise cleared to 0. Z: Set to 1 if the divisor is zero; otherwise

cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged.

Description

This instruction divides the contents of a 16-bit register Rd (destination register) by the contents of an 8-bit register Rs (source register) and stores the result in the 16-bit register Rd. The division is unsigned. The operation performed is 16 bits ÷ 8 bits →8-bit quotient and 8-bit remainder. The quotient is placed in the lower 8 bits of Rd. The remainder is placed in the upper 8 bits of Rd.

Rd Rs Rd

Dividend ÷ Divisor → Remainder Quotient

16 bits 8 bits 8 bits 8 bits

Valid results are not assured if division by zero is attempted or an overflow occurs. For information on avoiding overflow, see DIVXU Instruction, Zero Divide, and Overflow.

Available Registers

Rd: R0 to R7, E0 to E7 Rs: R0L to R7L, R0H to R7H

Operand Format and Number of States Required for Execution

Addressing

Mode

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

Notes

No. of

States

Page 99

2.2.27 (2) DIVXU (W)

DIVXU (DIVide eXtend as Unsigned) Divide

Operation

ERd ÷ Rs → ERd

Assembly-Language Format

DIVXU.W Rs, ERd

Operand Size

Condition Code

IUIHUNZVC

———— ↕↕——

H: Previous value remains unchanged. N: Set to 1 if the divisor is negative;

otherwise cleared to 0.

Word

Z: Set to 1 if the divisor is zero; otherwise

cleared to 0. V: Previous value remains unchanged. C: Previous value remains unchanged.

Description

This instruction divides the contents of a 32-bit register ERd (destination register) by the contents of a 16-bit register Rs (source register) and stores the result in the 32-bit register ERd. The division is unsigned. The operation performed is 32 bits ÷ 16 bits →16-bit quotient and 16-bit remainder. The quotient is placed in the lower 16 bits (Rd) of the 32-bit register ERd. The remainder is placed in the upper 8 bits of (Ed).

ERd Rs ERd

Dividend ÷ Divisor → Remainder Quotient

32 bits 16 bits 16 bits 16 bits

Valid results are not assured if division by zero is attempted or an overflow occurs. For information on avoiding overflow, see DIVXU Instruction, Zero Divide, and Overflow.

Available Registers

ERd: ER0 to ER7 Rs: R0 to R7, E0 to E7

Operand Format and Number of States Required for Execution

Addressing

Mode

Mnemonic Operands

1st byte 2nd byte 3rd byte 4th byte

Instruction Format

No. of

States

Notes

Page 100

DIVXU

DIVXU (DIVide eXtend as Unsigned) Divide

DIVXU Instruction, Zero Divide, and Overflow

Zero divide and overflow are not detected in the DIVXU instruction. A program like the following can detect zero divisors and avoid overflow.

1. Programming solutions for DIVXU.B R0L, R1 Example 1: Divide upper 8 bits and lower 8 bits of 16-bit dividend separately and obtain 16-bit

quotient

CMP.B #0, R0L ; R0L = 0? (Zero divisor?) BEQ ZERODIV ; Branch to ZERODIV if R0L = 0 MOV.B R1H,R2L ; Copy upper 8 bits of dividend to R2L and EXTU.W R2 (*1). ; zero-extend to 16 bits DIVXU.B R0L, R2 (*2) ; Divide upper 8 bits of dividend MOV.B R2H, R1H (*3) ; R2H → R1H (store partial remainder in R1H) DIVXU.B R0L, R1 (*4) ; Divide lower 8 bits of dividend (including repeated division of

MOV.B R2L, R2H ; Store upper part of quotient in R2H

upper 8 bits)

MOV.B R1L, R2L (*5) ; Store lower part of quotient in R2L RTS

ZERODIV: ; Zero-divide handling routine

The resulting operation is 16 bits ÷ 8 bits →quotient (16 bits) and remainder (8 bits), and no overflow occurs. The 16-bit quotient is stored in R2, the 8-bit remainder in R1H.

R0L

Sign extension Dividend (high)

Remainder (part) Quotient (high)

Remainder (part) Dividend (low)

R1 R2

Remainder Quotient (low)

Remainder

Dividend

Quotient (low)

Quotient

Divisor

( 1)*

( 2)*

( 3)*

( 4)*

( 5)*