H8/300H Series
Programming Manual
HITACHI
ADE-602-053A
Major Revisions and Additions in this Version
Page Item Description
P27 Figure 1-12 Instruction Formats Figure (4) amended
P33 Table 1-6 Effective Address Calculation (8) Table amended
P51 2.2.6 BAND Notes added
P58 2.2.11 BIOR Operand Format and Number of Register direct 1st byte
States Required for Execution amended
P67 2.2.18 BSR Notes description added
P74 2.2.22 (3) CMP (L) Operand Format and Number of Operands amended
States Required for Execution
P86 2.2.26 (3) DIVXS Description amended
P87 DIVXS Example 2 Example 2 added
P106 2.2.33 JSR Cautions Description added
P108 2.2.34 (1) LDC (B) Description amended
/added
P110 2.2.34 (2) LDC (W) Operand Format and Number of Mnemonic amended
States Required for Execution
P114 2.2.35 (4) MOV (B) Description Description amended
P117 2.2.35 (5) MOV (W) Operand Format and Number of Table contents amended
States Required for Execution
P119 2.2.35 (6) MOV (L) Operand Format and Number of Table contents amended
States Required for Execution
P123 2.2.35 (8) MOV (W) Operand Format and Number of Table contents amended
States Required for Execution
P125 2.2.35 (9) MOV (L) Operand Format and Number of Table contents amended
States Required for Execution
P129 2.2.38 (2) MULXS (W) Figure amended
P144 2.2.45 (2) POP (L) Number of execution states
amended
P146 2.2.46 (2) PUSH (L) Number of execution states
amended
P160 2.2.52 RTS Figure amended
P174 2.2.58 (1) STC (B) Assembly-Language Format Assembler format amended
2.2.58 (1) STC (B) Operand Format and Number of Mnemonic amended
States Required for Execution
Page Item Description
P175 2.2.58 (2) STC (W) Instruction amended
2.2.58 (2) STC (W) Assembler Format Assembler format amended
P176 2.2.58 (2) STC (W) Operand Format and Number of Mnemonic amended
States Required for Execution
P180 2.2.60 SUBS Operation Operation amended
P189 (1) Data Transfer Instructions MOV.W @ERs+,Rd Operation amended
(1) Data Transfer Instructions MOV.W Rs,@ERd Operation amended
(1) Data Transfer Instructions MOV.W Rs,@(d:24,ERd) Number of execution states
amended
(1) Data Transfer Instructions MOV.L #xx:32,ERd Operation and number of
execution states amended
P190 (1) Data Transfer Instructions MOV.L @ERs+,ERd Operation amended
(1) Data Transfer Instructions POP.L ERn Number of execution states
amended
(1) Data Transfer Instructions PUSH.L ERn Number of execution states
amended
P191 (2) Arithmetic Operation Instructions DAA Rd Condition code amended
P192 (2) Arithmetic Operation Instructions CMP.L #xx:32,ERd Number of execution states
amended
P196 (5) Bit Manipulation Instructions Table amended
P197, (6) Branch Instructions Added
P198
P198 (7) System Control Instructions LDC @ERs,CCR Operation amended
(7) System Control Instructions LDC @(d:16,ERs),CCR Operation amended
(7) System Control Instructions LDC @(d:24,ERs),CCR Operation amended
(7) System Control Instructions LDC @ERs+,CCR Operation amended
P204 Table 2-3 Instruction Codes (4) MOV.B@aa:16,Rd Instruction format amended
P231 Table 2-8 Bus States BSR d:16 Execution order nos.2 to
5 amended
P234, Table 2-8 Bus States POP.W Rn to PUSH.L ERn Instruction added
P235
P240 Figure 3-2 State Transitions Figure amended
Contents
Section 1 CPU................................................................................................................... 1
1.1 Overview......................................................................................................................... 1
1.1.1 Features............................................................................................................... 1
1.1.2 Differences from H8/300 CPU........................................................................... 2
1.2 CPU Operating Modes.................................................................................................... 3
1.3 Address Space................................................................................................................. 7
1.4 Register Configuration.................................................................................................... 8
1.4.1 Overview............................................................................................................. 8
1.4.2 General Registers................................................................................................ 9
1.4.3 Control Registers................................................................................................ 10
1.4.4 Initial Register Values......................................................................................... 11
1.5 Data Formats................................................................................................................... 12
1.5.1 General Register Data Formats........................................................................... 12
1.5.2 Memory Data Formats........................................................................................ 13
1.6 Instruction Set................................................................................................................. 15
1.6.1 Overview............................................................................................................. 15
1.6.2 Instructions and Addressing Modes.................................................................... 16
1.6.3 Tables of Instructions Classified by Function .................................................... 18
1.6.4 Basic Instruction Formats................................................................................... 27
1.6.5 Addressing Modes and Effective Address Calculation...................................... 28
Section 2 Instruction Descriptions.............................................................................. 35
2.1 Tables and Symbols........................................................................................................ 35
2.1.1 Assembler Format............................................................................................... 36
2.1.2 Operation ............................................................................................................ 37
2.1.3 Condition Code................................................................................................... 38
2.1.4 Instruction Format .............................................................................................. 38
2.1.5 Register Specification......................................................................................... 39
2.1.6 Bit Data Access in Bit Manipulation Instructions.............................................. 40
2.2 Instruction Descriptions.................................................................................................. 41
2.2.1 (1) ADD (B) ........................................................................................................ 42
2.2.1 (2) ADD (W) ....................................................................................................... 43
2.2.1 (3) ADD (L) ........................................................................................................ 44
2.2.2 ADDS............................................................................................................ 45
2.2.3 ADDX............................................................................................................ 46
2.2.4 (1) AND (B) ........................................................................................................ 47
2.2.4 (2) AND (W) ....................................................................................................... 48
2.2.4 (3) AND (L) ........................................................................................................ 49
2.2.5 ANDC............................................................................................................ 50
2.2.6 BAND............................................................................................................ 51
2.2.7 Bcc................................................................................................................. 52
2.2.8 BCLR............................................................................................................. 54
2.2.9 BIAND .......................................................................................................... 56
2.2.10 BILD.............................................................................................................. 57
2.2.11 BIOR.............................................................................................................. 58
2.2.12 BIST .............................................................................................................. 59
2.2.13 BIXOR........................................................................................................... 60
2.2.14 BLD............................................................................................................... 61
2.2.15 BNOT............................................................................................................ 62
2.2.16 BOR............................................................................................................... 64
2.2.17 BSET ............................................................................................................. 65
2.2.18 BSR................................................................................................................ 67
2.2.19 BST................................................................................................................ 68
2.2.20 BTST ............................................................................................................. 69
2.2.21 BXOR............................................................................................................ 71
2.2.22 (1) CMP (B) ........................................................................................................ 72
2.2.22 (2) CMP (W)....................................................................................................... 73
2.2.22 (3) CMP (L)......................................................................................................... 74
2.2.23 DAA .............................................................................................................. 75
2.2.24 DAS............................................................................................................... 77
2.2.25 (1) DEC (B)......................................................................................................... 79
2.2.25 (2) DEC (W)........................................................................................................ 80
2.2.25 (3) DEC (L)......................................................................................................... 81
2.2.26 (1) DIVXS (B)..................................................................................................... 82
2.2.26 (2) DIVXS (W) ................................................................................................... 84
2.2.26 (3) DIVXS .......................................................................................................... 86
2.2.27 (1) DIVXU (B).................................................................................................... 90
2.2.27 (2) DIVXU (W)................................................................................................... 91
2.2.28 (1) EEPMOV (B) ................................................................................................ 95
2.2.28 (2) EEPMOV (W)............................................................................................... 96
2.2.29 (1) EXTS (W)...................................................................................................... 98
2.2.29 (2) EXTS (L)....................................................................................................... 99
2.2.30 (1) EXTU (W)..................................................................................................... 100
2.2.30 (2) EXTU (L) ...................................................................................................... 101
2.2.31 (1) INC (B).......................................................................................................... 102
2.2.31 (2) INC (W)......................................................................................................... 103
2.2.31 (3) INC (L).......................................................................................................... 104
2.2.32 JMP................................................................................................................ 105
2.2.33 JSR................................................................................................................. 106
2.2.34 (1) LDC (B)......................................................................................................... 108
2.2.34 (2) LDC (W)........................................................................................................ 109
2.2.35 (1) MOV (B) ....................................................................................................... 111
2.2.35 (2) MOV (W) ...................................................................................................... 112
2.2.35 (3) MOV (L)........................................................................................................ 113
2.2.35 (4) MOV (B) ....................................................................................................... 114
2.2.35 (5) MOV (W) ...................................................................................................... 116
2.2.35 (6) MOV (L)........................................................................................................ 118
2.2.35 (7) MOV (B) ....................................................................................................... 120
2.2.35 (8) MOV (W) ...................................................................................................... 122
2.2.35 (9) MOV (L)........................................................................................................ 124
2.2.36 MOVFPE....................................................................................................... 126
2.2.37 MOVTPE....................................................................................................... 127
2.2.38 (1) MULXS (B)................................................................................................... 128
2.2.38 (2) MULXS (W).................................................................................................. 129
2.2.39 (1) MULXU (B).................................................................................................. 130
2.2.39 (2) MULXU (W)................................................................................................. 131
2.2.40 (1) NEG (B)......................................................................................................... 132
2.2.40 (2) NEG (W) ....................................................................................................... 133
2.2.40 (3) NEG (L)......................................................................................................... 134
2.2.41 NOP............................................................................................................... 135
2.2.42 (1) NOT (B)......................................................................................................... 136
2.2.42 (2) NOT (W) ....................................................................................................... 137
2.2.42 (3) NOT (L)......................................................................................................... 138
2.2.43 (1) OR (B)........................................................................................................... 139
2.2.43 (2) OR (W).......................................................................................................... 140
2.2.43 (3) OR (L) ........................................................................................................... 141
2.2.44 ORC............................................................................................................... 142
2.2.45 (1) POP (W) ........................................................................................................ 143
2.2.45 (2) POP (L).......................................................................................................... 144
2.2.46 (1) PUSH (W) ..................................................................................................... 145
2.2.46 (2) PUSH (L)....................................................................................................... 146
2.2.47 (1) ROTL (B) ...................................................................................................... 147
2.2.47 (2) ROTL (W)..................................................................................................... 148
2.2.47 (3) ROTL (L)....................................................................................................... 149
2.2.48 (1) ROTR (B)...................................................................................................... 150
2.2.48 (2) ROTR (W)..................................................................................................... 151
2.2.48 (3) ROTR (L) ...................................................................................................... 152
2.2.49 (1) ROTXL (B) ................................................................................................... 153
2.2.49 (2) ROTXL (W) .................................................................................................. 154
2.2.49 (3) ROTXL (L).................................................................................................... 155
2.2.50 (1) ROTXR (B)................................................................................................... 156
2.2.50 (2) ROTXR (W).................................................................................................. 157
2.2.50 (3) ROTXR (L) ................................................................................................... 158
2.2.51 RTE................................................................................................................ 159
2.2.52 RTS................................................................................................................ 160
2.2.53 (1) SHAL (B) ...................................................................................................... 161
2.2.53 (2) SHAL (W)..................................................................................................... 162
2.2.53 (3) SHAL (L)....................................................................................................... 163
2.2.54 (1) SHAR (B)...................................................................................................... 164
2.2.54 (2) SHAR (W)..................................................................................................... 165
2.2.54 (3) SHAR (L) ...................................................................................................... 166
2.2.55 (1) SHLL (B)....................................................................................................... 167
2.2.55 (2) SHLL (W)...................................................................................................... 168
2.2.55 (3) SHLL (L)....................................................................................................... 169
2.2.56 (1) SHLR (B)....................................................................................................... 170
2.2.56 (2) SHLR (W) ..................................................................................................... 171
2.2.56 (3) SHLR (L)....................................................................................................... 172
2.2.57 SLEEP ........................................................................................................... 173
2.2.58 (1) STC (B) ......................................................................................................... 174
2.2.58 (2) STC (W) ........................................................................................................ 175
2.2.59 (1) SUB (B)......................................................................................................... 177
2.2.59 (2) SUB (W)........................................................................................................ 178
2.2.59 (3) SUB (L)......................................................................................................... 179
2.2.60 SUBS............................................................................................................. 180
2.2.61 SUBX ............................................................................................................ 181
2.2.62 TRAPA .......................................................................................................... 182
2.2.63 (1) XOR (B) ........................................................................................................ 183
2.2.63 (2) XOR (W)....................................................................................................... 184
2.2.63 (3) XOR (L)......................................................................................................... 185
2.2.64 XORC............................................................................................................ 186
2.3 Instruction Set Summary ................................................................................................ 187
2.4 Instruction Codes............................................................................................................ 200
2.5 Operation Code Map....................................................................................................... 209
2.6 Number of States Required for Instruction Execution ................................................... 212
2.7 Condition Code Modification......................................................................................... 221
2.8 Bus cycles During Instruction Execution ....................................................................... 226
Section 3 Processing States........................................................................................... 239
3.1 Overview......................................................................................................................... 239
3.2 Program Execution State ................................................................................................ 241
3.3 Exception-Handling State............................................................................................... 241
3.3.1 Types of Exception Handling and Their Priority................................................ 241
3.3.2 Exception-Handling Sequences.......................................................................... 242
3.4 Bus-Released State ......................................................................................................... 244
3.5 Reset State ...................................................................................................................... 244
3.6 Power-Down State .......................................................................................................... 244
3.6.1 Sleep Mode........................................................................................................... 244
3.6.2 Software Standby Mode ....................................................................................... 244
3.6.3 Hardware Standby Mode...................................................................................... 244
Section 4 Basic Timing .................................................................................................. 245
4.1 Overview......................................................................................................................... 245
4.2 On-Chip Memory (RAM, ROM).................................................................................... 245
4.3 On-Chip Supporting Modules......................................................................................... 247
4.4 External Data Bus ........................................................................................................... 248
Section 1 CPU
1.1 Overview
The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
1.1.1 Features
The H8/300H CPU has the following features.
• Upward-compatible with H8/300 CPU
— Can execute H8/300 object programs
• General-register architecture
— Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
• Sixty-two basic instructions
— 8/16/32-bit arithmetic and logic instructions
— Multiply and divide instructions
— Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct [Rn]
— Register indirect [@ERn]
— Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
— Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
— Absolute address [@aa:8, @aa:16, or @aa:24]
— Immediate [#xx:8, #xx:16, or #xx:32]
— Program-counter relative [@(d:8,PC) or @(d:16,PC)]
— Memory indirect [@@aa:8]
• 16-Mbyte address space
• High-speed operation
— All frequently-used instructions execute in two to four states
— Maximum clock frequency: 16 MHz
1
— 8/16/32-bit register-register add/subtract: 125 ns
—8 ×8-bit register-register multiply: 875 ns
— 16 ÷ 8-bit register-register divide: 875 ns
— 16 × 16-bit register-register multiply: 1375 ns
— 32 ÷ 16-bit register-register divide: 1375 ns
• Two CPU operating modes
— Normal mode
— Advanced mode
• Low-power mode
— Transition to power-down state by SLEEP instruction
1.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H CPU has the following enhancements.
• More general registers
Eight 16-bit registers have been added.
• Expanded address space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Signed multiply/divide instructions and other instructions have been added.
2
1.2 CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. The mode is
selected at the mode pins of the microcontroller. For further information, refer to the relevant
hardware manual.
Normal mode
CPU operating modes
Advanced mode
Maximum 64 kbytes, program
and data areas combined
Maximum 16 Mbytes, program
and data areas combined
Figure 1-1 CPU Operating Modes
(1) Normal Mode: The exception vector table and stack have the same structure as in the H8/300
CPU.
Address Space: A maximum address space of 64 kbytes can be accessed, as in the H8/300 CPU.
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit data registers,
or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers.
When En is used as a 16-bit register it can contain any value, even when the corresponding
general register (R0 to R7) is used as an address register. If the general register is referenced in the
register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a
carry or borrow occurs, however, the value in the corresponding extended register will be affected.
Instruction Set: All additional instructions and addressing modes of the H8/300 CPU can be
used. If a 24-bit effective address (EA) is specified, only the lower 16 bits are used.
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16
bits (figure 1-2). The exception vector table differs depending on the microcontroller, so see the
microcontroller hardware manual for further information.
3
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
Reset exception vector
Reserved for system use
Exception vector 1
Exception vector 2
Exception
vector table
Figure 1-2 Exception Vector Table (normal mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address to specify a memory operand that contains a branch address. In normal
mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses
can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the
exception vector table.
Stack Structure: When the program counter (PC) is pushed on the stack in a subroutine call, and
the PC and condition-code register (CCR) are pushed on the stack in exception handling, they are
stored in the same way as in the H8/300 CPU. See figure 1-3.
(a) Subroutine branch (b) Exception handling
SP
Note: * Ignored at return.
PC
(16 bits)
SP
CCR
CCR*
(16 bits)
Figure 1-3 Stack Structure (normal mode)
4
PC
(2) Advanced Mode: In advanced mode the exception vector table and stack structure differ from
the H8/300 CPU.
Address Space: Up to 16 Mbytes can be accessed linearly.
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit data registers,
or they can be combined with the general registers (R0 to R7) for use as 32-bit data registers.
When a 32-bit register is used as an address register, the upper 8 bits are ignored.
Instruction Set: All additional instructions and addressing modes of the H8/300H can be used.
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top
area starting at H'000000 is allocated to the exception vector table in units of 32 bits. In each 32
bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 1-4).
The exception vector table differs depending on the microcontroller, so see the relevant hardware
manual for further information.
H'000000
H'000003
H'000004
H'00000B
H'00000C
Don’t care
Reset exception vector
Exception vector table
Reserved for system use
Don’t care
Exception vector
Figure 1-4 Exception Vector Table (advanced mode)
5
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address to specify a memory operand that contains a branch address. In advanced
mode the operand is a 32-bit longword operand, of which the lower 24 bits are the branch address.
Branch addresses can be stored in the top area from H'000000 to H'0000FF. Note that this area is
also used for the exception vector table.
Stack Structure:When the program counter (PC) is pushed on the stack in a subroutine call, and
the PC and condition-code register (CCR) are pushed on the stack in exception handling, they are
stored as shown in figure 1-5.
(a) Subroutine branch (b) Exception handling
SP
Reserved
PC
(24 bits)
SP
Figure 1-5 Stack Structure (advanced mode)
CCR
PC
(24 bits)
6
1.3 Address Space
Figure 1-6 shows a memory map of the H8/300H CPU.
(a) Normal mode (b) Advanced mode
H'0000
H'FFFF
H'000000
H'FFFFFF
Figure 1-6 Memory Map
7
1.4 Register Configuration
1.4.1 Overview
The H8/300H CPU has the internal registers shown in figure 1-7. There are two types of registers:
general and extended registers, and control registers.
General registers (Rn) and extended registers (En)
15 07 07 0
E0
E1
E2
E3
E4
E5
E6
SP
Control registers (CR)
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
23 0
PC
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
Legend
Stack pointer
SP:
Program counter
PC:
Condition code register
CCR:
Interrupt mask bit
I:
User bit or interrupt mask bit
U:
Half-carry flag
H:
Negative flag
N:
Zero flag
Z:
Overflow flag
V:
Carry flag
C:
76543210
I UHUNZVCCCR
Figure 1-7 CPU Registers
8
1.4.2 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
Figure 1-8 illustrates the usage of the general registers. The usage of each register can be selected
independently.
Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 1-8 Usage of General Registers
9
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 1-9 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 1-9 Stack
1.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition-code register
(CCR).
(1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the
CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits,
so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC
bit is regarded as 0.
(2) Condition Code Register (CCR): This 8-bit register contains internal CPU status
information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z),
overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence.
Bit 6—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions. This bit can also be used as an interrupt mask bit. For details see the
relevant microcontroller hardware manual.
10
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions. Some
instructions leave some or all of the flag bits unchanged. For the action of each instruction on the
flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
1.4.4 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the I bit in
the condition-code register (CCR) is set to 1. The other CCR bits and the general registers and
extended registers are not initialized. In particular, the stack pointer (extended register E7 and
general register R7) is not initialized. The stack pointer must therefore be initialized by an MOV.L
instruction executed immediately after a reset.
11
1.5 Data Formats
The H8/300H CPU can process 1-bit, 4-bit, 8-bit (byte), 16-bit (word), and 32-bit (longword)
data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of
byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of
4-bit BCD data.
1.5.1 General Register Data Formats
Figure 1-10 shows the data formats in general registers.
Data type Register number Data format
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
RnH
RnL
RnH
RnL
RnH
RnL
70
76543210 Don’t care
70
Don’t care 76543210
70
70
MSB LSB
43
70
Don’t care
70
Don’t care
MSB
Figure 1-10 General Register Data Formats
Don’t careUpper Lower
Upper
Don’t care
43
Lower
LSB
12
Word data
Word data
15
MSB LSB
Rn
En
0
15
MSB LSB
0
Longword data
31
MSB
Legend
ERn:
General register ER
En:
General register E
Rn:
General register R
RnH:
General register RH
RnL:
General register RL
MSB:
Most significant bit
LSB:
Least significant bit
ERn
15
16
En Rn
0
LSB
Figure 1-10 General Register Data Formats (cont)
1.5.2 Memory Data Formats
Figure 1-11 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, no address error occurs but
the least significant bit of the address is regarded as 0, so the access starts at the preceding
address. This also applies to instruction fetches.
13
Data type Data format
Address
70
1-bit data
Address L
76543210
Byte data
Word data
Longword data
Address L
Address 2M
Address 2M + 1
Address 2N
Address 2N + 1
Address 2N + 2
Address 2N + 3
MSB LSB
MSB
LSB
MSB
LSB
Figure 1-11 Memory Data Formats
When ER7 is used as an address register to access the stack, the operand size should be word size
or longword size.
14
1.6 Instruction Set
1.6.1 Overview
The H8/300H CPU has 62 types of instructions, which are classified by function in table 1-1. For
a detailed description of each instruction see section 2.2, Instruction Descriptions.
Table 1-1 Instruction Classification
Function Instructions Number
1
Data transfer MOV, PUSH
*
Arithmetic ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, 18
operations DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS,
EXTU
Logic operations AND, OR, XOR, NOT 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, 8
ROTXR
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, 14
BXOR, BIXOR, BLD, BILD, BST, BIST
2
*
Branch Bcc
, JMP, BSR, JSR, RTS 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9
Block data transfer EEPMOV 1
Notes: The shaded instructions are not present in the H8/300 instruction set.
1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @–SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@–SP.
2. Bcc is the generic designation of a conditional branch instruction.
, POP
2
*
, MOVTPE, MOVFPE 3
Total 62 types
15
1.6.2 Instructions and Addressing Modes
Table 1-2 indicates the instructions available in the H8/300H CPU.
Table 1-2 Instruction Set Overview
Function Instruction
Data
transfer
Arithmetic
operations
Logic
operations
Shift
Bit manipulation
MOV
POP, PUSH
MOVFPE,
MOVTPE
ADD, CMP
SUB
ADDX,
SUBX
ADDS,
SUBS
INC, DEC
DAA, DAS
MULXU,
DIVXU
MULXS,
DIVXS
NEG
EXTU, EXTS
AND, OR,
XOR
NOT
#xx Rn @ERn @(d:16,ERn) @(d:24,ERn) @ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 —
BWL
—
—
BWL
WL
B
—
—
—
—
—
—
—
BWL
—
—
—
BWL
—
—
BWL
BWL
B
*
L
BWL
B
BW
BW
BWL
WL
BWL
BWL
BWL
B
BWL
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
B
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Addressing Modes
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
BWL
BWL
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
Table 1-2 Instruction Set Overview (cont)
Addressing Modes
Function Instruction
Branch
System
control
Block data
transfer
Bcc, BSR
JMP, JSR
RTS
TRAPA
RTE
SLEEP
LDC
STC
ANDC,
ORC,
XORC
NOP
EEPMOV.B
EEPMOV.W
Legend
B: Byte
W: Word
L: Longword
: Newly added instruction in H8/300H CPU
Notes: 1. The operand size of the ADDS and SUBS instructions of the H8/300H CPU has been changed to longword size. (In the
H8/300 CPU it was word size.)
2. Because of its larger address space, the H8/300H CPU uses a 24-bit absolute address for the JMP and JSR instructions.
(The H8/300 CPU used 16 bits.)
#xx Rn @ERn @(d:16,ERn) @(d:24,ERn) @ERn+/@–ERn @aa:8 @aa:16 @aa:24 @(d:8,PC) @(d:16,PC) @@aa:8 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
B
B
W
B
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
—
W
—
—
—
—
—
—
—
—
—
2
*
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17
1.6.3 Tables of Instructions Classified by Function
Table 1-3 summarizes the instructions in each functional category. The notation used in table 1-3
is defined next.
Operation Notation
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) bit of CCR
Z Z (zero) bit of CCR
V V (overflow) bit of CCR
C C (carry) bit of CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ AND logical
∨ OR logical
⊕ Exclusive OR logical
→ Move
¬ Not
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H/R0L to R7H/R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit registers (ER0 to ER7).
18
Table 1-3 Instructions Classified by Function
Type Instruction Size* Function
Data transfer MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between
a general register and memory, or moves immediate
data to a general register.
MOVFPE B (EAs) → Rd
Moves external memory contents (addressed by
@aa:16) to a general register in synchronization with
an E clock.
MOVTPE B Rs → (EAd)
Moves general register contents to an external memory
location (addressed by @aa:16) in synchronization with
an E clock.
POP W/L @SP+ → Rn
Pops a register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L
@SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a register onto the stack. PUSH.W Rn is
identical to MOV.W Rn, @–SP. PUSH.L ERn is
identical to MOV.L ERn, @–SP.
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
19
Table 1-3 Instructions Classified by Function (cont)
Type Instruction Size* Function
Arithmetic
operations
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
ADD
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXS B/W Rd × Rs → Rd
MULXU B/W Rd × Rs → Rd
DIVXS B/W Rd ÷ Rs → Rd
B/W/L Rd ±Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general
registers, or on immediate data and data in a general
register. (Immediate byte data cannot be subtracted
from data in a general register. Use the SUBX or ADD
instruction.)
B Rd ± Rs ±C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow
on byte data in two general registers, or on immediate
data and data in a general register.
B/W/L Rd ±1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2.
(Byte operands can be incremented or decremented by
1 only.)
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ±4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in
a 32-bit register.
B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a
general register by referring to the CCR to produce
4-bit BCD data.
Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16
bits → 32 bits.
Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16
bits → 32 bits.
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and
8-bit remainder or 32 bits ÷ 16 bits →16-bit quotient
and 16-bit remainder.
20
Table 1-3 Instructions Classified by Function (cont)
Type Instruction Size* Function
Arithmetic
operations
Logic operations AND B/W/L Rd∧ Rs → Rd, Rd ∧ #IMM → Rd
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and
16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in
another general register or with immediate data, and
sets the CCR according to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of
data in a general register.
EXTS W/L Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register
to word data, or extends word data in the lower 16 bits
of a 32-bit register to longword data, by extending the
sign bit.
EXTU W/L Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register
to word data, or extends word data in the lower 16 bits
of a 32-bit register to longword data, by padding with
zeros.
Performs a logical AND operation on a general register
and another general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate
data.
NOT B/W/L ¬ (Rd) → (Rd)
Takes the one’s complement of general register
contents.
21
Table 1-3 Instructions Classified by Function (cont)
Type Instruction Size* Function
Shift operations B/W/L Rd (shift) → Rd
Bit-manipulation
instructions
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
SHAL
SHAR
SHLL
SHLR
ROTL
ROTR
ROTXL
ROTXR
BSET B 1 → (<bit-No.> of <EAd>)
BCLR B 0 → (<bit-No.> of <EAd>)
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
BTST B ¬ (<bit-No.> of <EAd>) → Z
BAND B C ∧ (<bit-No.> of <EAd>) → C
BIAND B C ∧ ¬ (<bit-No.> of <EAd>) → C
B/W/L Rd (shift) → Rd
B/W/L Rd (rotate) → Rd
B/W/L Rd (rotate) → Rd
Performs an arithmetic shift on general register
contents.
Performs a logical shift on general register contents.
Rotates general register contents.
Rotates general register contents through the carry bit.
Sets a specified bit in a general register or memory
operand to 1. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
Clears a specified bit in a general register or memory
operand to 0. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
Inverts a specified bit in a general register or memory
operand. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
Tests a specified bit in a general register or memory
operand and sets or clears the Z flag accordingly. The
bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
ANDs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
ANDs the carry flag with the inverse of a specified bit in
a general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
22
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