Hitachi DVP-345-E, DVP-345-UK Service manual
SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH
CAUTION:
Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.
No. 9403
DV-P345UK
DV-P345E
Data contained within this Service
manual is subject to alteration for
improvement.
ATTENTION:
Avant d’effectuer l’entretien du châassis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.
Les données fournies dans le présent
manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.
Die in diesem Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
Digital Versatile Disk
August 2004
2
1. GENERAL DESCRIPTION
1.1 ZR36768
The ZR36768 Disc Loader Controller and Decoder Device can control disc loaders and read
bitstreams using the following media: DVD-ROM, DVDRW, CD-DA, CD-ROM, CD-R and CD-R/W
discs. The device can decode bitstreams and process navigation data of the following formats:
DVD-Video, DVD-Audio, CD-DA, VCD (Video-CD), SVCD (Super Video-CD) and MP3.
The features of this chip can be listed as follows:
Disc loader control and bitstream processing
• 8 analog inputs (low frequency) for servo errors and RF signals envelope monitoring
• 11 actuators drive or control outputs. Two analog outputs through 11 bits DACs (e.g. for the
tracking and focus coils), and 9 PWM outputs divided into two type groups: High frequency,
“uniform” type PWMs (e.g. for the spindle and sled motor drives), and lower frequency
“regular” type PWMs, which can be used e.g. for programmed tray motion or RF amplifier
parameter setting.
• Processing of spindle and sled position read-back devices
• All servo loop closure, closed loop control and error handling.
• Bitstream extraction using AGC, bit clock frequency detection and phase lock loop, adaptive
threshold calculations, Viterbi bit decision, defect detection, frame sync detection and EFM/P
conversion.
• CD sub-code extraction and processing.
• CD ECC for all CD types. CD EDC for Mode 1 discs
• DVD ECC and EDC.
• Track buffer and re-try management
Decoding
• Single chip solution for playback of DVD-Video, DVD-Audio Video-CD, Super Video-CD, CD-
DA, and MP3 from CD-ROM, CD-R or CD-R/W.
• Decoding and display of high resolution MPEG 1 and MPEG 2 still image sequences
(including ASVs from DVD-Audio but without the transition effects).
• Decoding of Dolby AC-3, DTS or MLP multi-channel audio.
• Decoding of MPEG 1 or MPEG 2 layer II mono, stereo, or multi-channel audio. Decoding of
MPEG 1 or MPEG 2 Layer 3 (MP3) mono and stereo audio.
• PCM and LPCM audio playback from DVD-Video, DVD-Audio, Video-CD and CD-DA.
• Decoding and playback of sub-picture (including Highlight), and closed captions (“line 21”)
data from DVD-Video discs.
• Interlaced digital and analog video output or progressive analog video output.
• NTSC and PAL standards. PAL playback of NTSC discs and NTSC playback of PAL discs.
• Special modes support like pause, slow motion, fast forward and reverse.
Post Processing
• Audio down mixing, sample rate conversion, Dolby's pro-logic and 3D enhancement.
• Karaoke mixing of decoded audio and two channels of input audio.
• On-chip OSD engine with 32 color (24-bit YUV) palette, up to 8 levels of transparency; and
capability of blinking regions and vertical scrolling.
• On-screen and off-screen OSD memory regions for animation support.
• 1/4 pixel and 1/4 line pan&scan
• Horizontal and vertical up- and down-scaling with polyphase two-tap vertical and horizontal
interpolation.
3
• Letterbox and Pan-scan display aspect ratio conversion (16:9 to 4:3)
• Automatic frame rate conversion (e.g., 3/2 pull down) and format conversion (16:9, 4:3, 1:1).
• EIA-608 compatible modulation of line 21 (NTSC) or line 22 (PAL) closed captions data over
the video output.
• Edge adaptive, two fields, de-interlacing generating a progressive analog video output.
Interfaces
• 8-bit YUV 4:2:2 digital interlaced video output.
• Composite, Y/C, YUV or RGB interlaced analog video output or component progressive
analog video output (using 10 bits on-chip DACs)
• Internally generated video sync signals and internally generated audio port clock signals.
• 6/18/20/24-bit I2S or EIAJ serial audio outputs. 16 bit I2S EIAJ serial audio input
• 2 to 8 channels audio output. 2 channels audio input
• S/PDIF output for compressed audio (including DTS) or reconstructed audio (according to
IEC 958 and its extensions).
• Single 64-Mbit, single 16-Mbits and dual 16 Mbits SDRAMs (16 bits data)
• Direct interface (through RF and servo amplifiers) to several types of disc loaders.
• SW controlled GPIO to interface to IR remote control receiver, front panel concentrator, audio
DACs and ADC, etc.’, e.g. using I2C, SPI and other protocols.
• 3 line serial general purpose slave interface (SSC)
• 2 UART interfaces for CPU SW debug
• JTAG interfaces for CPU, ADP and DSP SW debug
Physical Features
• Dual supply: 1.8V for the core and PLL, and 3.3V for the I/O and DACs.
• 208 pin, PQFP package.
• TTL I/O levels. 5V tolerance on many inputs.
• Single 27MHz crystal/clock input.
• 5 layer metal, 0.18 micron technology.
• Less than 1.6 W power consumption during operation.
• Several power-down modes
1.2 MEMORY
1.2.1 SDRAM Memory Interface
The ZR36768 provides 16-bit interface to DRAM memory devices used as OSD, MPEG
stream and video buffer memory for a DVD player. The maximum amount of memory supported
is 8 MB of Synchronous DRAM (SDRAM). The memory interface is configurable in depth to
support 64-Mb addressing.
1.3 DRIVE INTERFACES
The ZR36768 supports direct interface (through RF and servo amplifiers) to several types
of disc loaders.
1.4 FRONT PANEL
The front panel is based around a Futaba VFD and a Princeton front panel controller
chip, (PT6311). The ZR36768 controls the PT16311 using several control signals, (clock, data,
chip select). The infrared remote control signal is passed directly to the ZR36768 for decoding.
4
1.5 REAR PANEL
A typical rear panel supports:
- Six channel or two channel audio outputs
- Optical and coax S/PDIF outputs.
- Composite, S-Video, and SCART outputs
Outputs provided by ZR36768 are Composite, Y/C, YUV or RGB interlaced analog video output
or component progressive analog video output (using 10 bits on-chip DACs). DVD6110 rear
panel has Composite and S-video otputs on it.
ZR36768 provides 2 to 8 channels audio output. DVD6110 has 2 channels audio output on its
rear panel. The rear panel has S/PDIF serial stream and optical output generated by the
ZR36768. CS4392 Audio DACs are used for two channel audio output with ZR36768.
2. SYSTEM BLOCK DIAGRAM and ZR36768 PIN DESCRIPTION
2.1 ZR36768 PIN DESCRIPTION
Pin No Pin Functions Direction
CPU Interface (15 pins)
DUPTD0 // O // First debug UART data output //
153 GPCI/O[36] I/O General purpose input/output pin, monitored/controlled by the CPU or DSP
DUPRD0 // I // First debug UART data input //
152 GPCI/O[35] I/O General purpose input/output pin, monitored/controlled by the CPU or DSP
DUPTD1 // O // Second debug UART data output //
156 GPCI/O[38] I/O General purpose input/output pin, monitored/controlled by the CPU or DSP
DUPRD1 // I // Second debug UART data input //
155 GPCI/O[37] I/O General purpose input/output pin, monitored/controlled by the CPU or DSP
GPCI/O[20] I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
106 CPUNMI // I // CPU non-maskable interrupt input //
SDATA[0] // I // SERVO channel sample data input for AFE by-pass //
PM[0] O Probe mux data output
ICGPCI/O[0] I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
108
AOUT[3] // O // Serial output of digital stereo audio //
SDATA[1] // // SERVO channel sample data input for AFE by-pass //
PM[1] O Probe mux data output
IDGPCI/O[0] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
109
SW
SW
SW
SW
SW //
SW. When input, the pin can be used as general purpose external interrupt
to the CPU //
SW. When input, the pin can be used as general purpose external interrupt
to the DSP //
Description
5
SDATA[2] // I // SERVO channel sample data input for AFE by-pass //
PM[2] O Probe mux data output
149,147 GPCI/O[34-31] I/O General purpose input/output pins, monitored/controlled by the CPU or DSP
145,136
ICGPCI/O[5,4] I/O General purpose input/output pins monitored/controlled by the CPU or DSP
148,146
IDGPCI/O[3] I/O General purpose input/output pins, monitored/controlled by the CPU or DSP
150
PLL Signals (4 pins)
139 RESET# ID Reset input (active low)
142 GCLKP ID 27.000MHz clock or crystal input for main processing clock generation.
141 XO AO Output to a crystal that is connected to GCLK. If a crystal is not used at
143 GCLKA ID 27.000MHz clock input for audio master clock generation. In normal operation
Analog Video Port, (5 pins)
CVBS/G/Y AO When the I64 outputs composite video, this line is CVBS
158 (DAC A)
Y/R/V/C AO When the I64 outputs the composite video, this line is Y
161 (DAC B)
C/B/U AO When the I64 outputs the composite video, this line is C
162 (DAC C)
159 CVBS/C/Y AO The output on this line can be either CVBS or C or Y
(DAC D)
163 RSET AI Resistive load for gain adjustment of the DACs
SW.
SW. When input, the pins can be used as general purpose external interrupts
to the CPU
SW. When input, the pins can be used as general purpose external interrupts
to the DSP
GCLK, XO must be left not connected.
must be connected to GCLKP
When the I64 outputs RGB, this line is the Green output
When the I64 outputs YUV, this line is the Y output
When the I64 outputs RGB, this line is the Red output
When the I64 outputs YUV, this line is the V output
When the I64 outputs SCART, this line is the C output
When the I64 outputs RGB, this line is the Blue output
When the I64 outputs YUV, this line is the U output
The selection is independent of the selection of the other three DACs.
Digital Video Port, CPU, DSP and ADP de-bug (11 pins)
VID[7] // O // Digital video luma/chroma output, multiplexed in time according to the
ICETMS // I // ADP debug interface //
128 DJTMS // I // DSP debug interface //
GPCI/O[26] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
DACTEST[7] I DACs test input
VID[6] // O // Digital video luma/chroma output, multiplexed in time according to the
ICETDI // I // ADP debug interface //
129 DJTDI // I // DSP debug interface //
ICGPCI/O[2]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
CCIR656 standard (for interlaced video) or luma (for progressive) //
SW //
CCIR656 standard (for interlaced video) or luma (for progressive) //
SW. When input, the pin can be used as general purpose external interrupt
to the CPU//
6
DACTEST[6] I DACs test input
VID[5] // O // Digital video luma/chroma output, multiplexed in time according to the
ICETDO // O // ADP debug interface //
130 DJTDO // O // DSP debug interface //
IDGPCI/O[1]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
DACTEST[5] I DACs test input
VID[4] // O // Digital video luma/chroma output, multiplexed in time according to the
ICETCK // I // ADP debug interface /
131 DJTCK // I // DSP debug interface //
GPCI/O[27]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
DACTEST[4] I DACs test input
VID[3] // O // Digital video luma/chroma output, multiplexed in time according to the
DJTMS // I // DSP debug interface //
132 GPCI/O[28]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
DACTEST[3] // I // DACs test input //
SERVOCLK O SERVO channel clock output for AFE by-pass
VID[2] // O // Digital video luma/chroma output, multiplexed in time according to the
DJTDI // I // DSP debug interface //
133 GPCI/O[29]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
DACTEST[2] // I // DACs test input //
SSEL[0] O SERVO channel select output for AFE by-pass
VID[1] // O // Digital video luma/chroma output, multiplexed in time according to the
DJTDO // O // DSP debug interface //
134 GPCI/O[30]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
DACTEST[1] // I // DACs test input //
SSEL[1] O SERVO channel select output for AFE by-pass
VID[0] // O // Digital video luma/chroma output, multiplexed in time according to the
DJTCK // I // DSP debug interface //
135 ICGPCI/O[3]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
DACTEST[0] // I // DACs test input //
SSEL[2] O SERVO channel select output for AFE by-pass
VCLKx2 // O // Digital video clock output. 27.000MHz //
COSYNC // O // Composite sync output. Active only when component analog output is
ICGPCI/O[1]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
CCIR656 standard (for interlaced video) or luma (for progressive) //
SW. When input, the pin can be used as general purpose external interrupt
to the DSP//
CCIR656 standard (for interlaced video) or luma (for progressive) //
SW //
CCIR656 standard (for interlaced video) or luma (for progressive) //
SW //
CCIR656 standard (for interlaced video) or luma (for progressive) //
SW //
CCIR656 standard (for interlaced video) or luma (for progressive) //
SW //
CCIR656 standard (for interlaced video) or luma (for progressive) //
SW. When input, the pin can be used as general purpose external interrupt
to the CPU //
selected //
7
126
CJTMS // I // CPU debug interface //
DACTEST[10] // I // DACs test input //
PM[11] O Probe mux data output
HSYNC# // O // Digital video horizontal sync signal//
GPCI/O[25]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
124
CJTDO // O // CPU debug interface //
DACTEST[8] // I // DACs test input //
PM[10] O Probe mux data output
VSYNC# // O // Digital video vertical sync signal//
GPCI/O[24]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
122
CJTDI // I // CPU debug interface //
DACTEST[9] // I // DACs test input //
PM[9] O Probe mux data output
Digital Audio Port and CPU de-bug (9 pins)
AIN // I // Serial input of digital stereo audio //
GPCI/O[23]// I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
120
CJTCK // I // CPU debug interface //
PM[8] O Probe mux data output
118 AMCLK I/O Audio Master Clock input/output. 128, 192, 256 or 384 times the sampling
S/PDIF // O // S/PDIF transmitter output for digital coded or reconstructed audio data //
110 SDATA[3] // I // SERVO channel sample data input for AFE by-pass //
PM[3] O Probe mux data output
AOUT[2,1] // O // Serial outputs of digital stereo audio //
GPCI/O[21,22] I/O // General purpose input/output pin, monitored/ controlled by the CPU or DSP
111,112
SDATA[4,5] I // SERVO channel sample data inputs for AFE by-pass //
PM[4,5] O Probe mux data outputs
AOUT[0] // O Serial output of digital stereo audio //
113 SDATA[6] //
PM[6]
115 ALRCLK O Digital audio left/right select output for the audio port. Square wave, at the
116 ABCLK O Digital audio bit-clock output. Data on AOUT and AIN is output or latched,
GPAI/O // I/O // General purpose input/output pin, monitored/controlled by the ADP SW //
114 AOUT[3] // O // Serial output of digital stereo audio //
SDATA[7] // I // SERVO channel sample data input for AFE by-pass //
PM[7] O Probe mux data output
SW. When input, the pin can be used as general purpose external interrupt
to the CPU //
SW //
SW //
SW //
frequency (programmable).
SW //
SERVO channel sample data input for AFE by -pass //
Probe mux data outputs
sampling frequency. Programmable polarity
respectively, with the rising or falling (programmable) edge of this clock.
Loader interface, RF amplifier interface, AV bitstream interface (28 pins)
185,184 VBIASS[1,0] AI Servo analog signal reference voltage inputs
169,167 DACDRIVE[1,0] AO Drive DACs output signals
8
PWMACT[0] O // PWM0 output signal //
GPCI/O[39] I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
187
DVDDAT[0] I // DVD-DSP data input for FE by-pass //
NRZDATA I NRZ data input for AFE and DRC by-pass
PWMACT[1] O // PWM1 output signal //
GPCI/O[40] I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
188
DVDDAT[1] I // DVD-DSP data input for FE by-pass //
NRZCLK I NRZ clock input for AFE and DRC by-pass
SLEDPULSE I // Sled optical encoder input //
IDGPCI/O[6] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
205
DVDSOS I AV start of sector indication input for FE by-pass. Programmable polarity
SPINDLE I // Spindle optical encoder input //
PULSE //
206 IDGPCI/O[7] I/O General purpose input/output pin, monitored/controlled by the CPU or DSP
172 RFINP AI RF positive input signal (differential input) // RF input signal (single ended)
173 RFINN AI RF negative input signal (differential input) // RF reference input signal
ADCIN[7] // AI // SERVO ADC input signal from RF amplifier //
124 AFETESTN AI/O AFE test differential signal, input or output. AFETESTN carries the negative
ADCIN[6] // AI // SERVO ADC input signal from RF amplifier //
125 AFETESTP AI/O AFE test differential signal, input or output. AFETESTP carries the positive
178-183 ADCIN[5-0] AI SERVO ADC input signals from RF amplifier
PWMCO[0] // O // PWM2 output signal //
GPCI/O[41] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
189
DVDDAT[2] // I // DVD-DSP data input for FE by-pass //
NRZLOCK I NRZ lock input for AFE and DRC by-pass
PWMCO[1] // O // PWM3 output signal //
GPCI/O[42] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
191
DVDDAT[3] // I // DVD-DSP data input for FE by-pass //
NRZDFCT I NRZ defect input for AFE and DRC by-pass
PWMCO[5-2] O // PWM4 to PWM7 output signals //
198,196, GPCI/O[46-43] I/O // General purpose input/output pins, monitored/controlled by the CPU or DSP
194,193
DVDDAT[7-4] I // DVD-DSP data inputs for FE by -pass //
RFDAT[3-0] I RF channel sample data inputs for AFE by -pass
PWMCO[6] // O // PWM8 output signal //
IDGPCI/O[4] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
199
DVDREQ // O // DVD-DSP data request output for FE by-pass. Programmable polarity //
SW //
SW //
SW. When input, the pin can be used as general purpose external interrupt
to the DSP //
SW. When input, the pin can be used as general purpose external interrupt
to the DSP
Signal
Signal
SW //
SW //
SW //
SW. When input, the pin can be used as general purpose external interrupt
to the DSP //
9
RFDAT[4] O RF channel sample data inputs for AFE by-pass
ICGPCI/O[7] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
203
DVDERR // I // DVD-DSP error input for FE by-pass. Programmable polarity//
RFCLK // O // RF channel sampling clock output for AFE by-pass //
PM[12] O Probe mux data output
DEFECT // I/O // Disc defect input or output signal //
IDGPCI/O[5] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
200
DVDSTRB // O // AV data bit strobe (clock) input for FE by-pass. Programmable polarity //
RFDAT[5] I RF channel sample data inputs for AFE by-pass
ICGPCI/O[6] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
201
DVDVALID // I // AV data valid input for FE by-pass. Programmable polarity //
PM[16] O Probe mux data output
SDRAM Interface (36 pins)
103,100,
98,94,90
,88,85,8
2,84,86,
89,92,96
,99,102,
104
RAMDAT[15-0] I/O SDRAM bidirectional data bus
SW. When input, the pin can be used as general purpose external interrupt
to the CPU //
SW. When input, the pin can be used as general purpose external interrupt
to the DSP //
SW. When input, the pin can be used as general purpose external interrupt
to the CPU //
69,65,67
,63,60,5
7,55,53,
54,56,59
SSC Interface (3 pins)
208 GPCI/O[16] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
RAMADD[11-0] O SDRAM address bus output
,61
74 RAMRAS# O SDRAM row select (active low) output
75 RAMCAS# O SDRAM column select (active low) output
80 PCLK O SDRAM clock output (same as internal processing clock).
78 RAMDQM O SDRAM data masking (active high) output
71 RAMBA[0] O SDRAM bank select output
70 RAMCS[0]# // O SDRAM chip select (active low) //
RAMBA[1]
73 RAMCS[1]# O SDRAM chip select (active low) output
77 RAMWE# O SDRAM write enable (active low) output.
SSCTXD // O // SSC data output signal //
PM[14] O Probe mux data output
SSCRXD // I // SSC data input. //
1 GPCI/O[17] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
SDRAM bank select output
SW //
10
PM[15] O Probe mux data output
SSCCLK // I/O // SSC clock input signal or output //
207 GPCI/O[47] // I/O // General purpose input/output pin, monitored/controlled by the CPU or DSP
PM[13] O Probe mux data output
PNVM/SRAM Interface (41 pins)
9,14,18,
22,26,30
,35,39,1
1,16,19,
24,27,33
,37,42
31,34,5,
15,17,36
,38,40,4
3,45,46
48,49
MEMDA[15-0] I/O PNVM/SRAM bidirectional data bus
MEMAD[20] // O // PNVM/SRAM address bus outputs //
20 MEMCS[2]# // O // PNVM/SRAM chip select (active low) output//
GPCI/O[19] I/O General purpose input/output pin, monitored/controlled by the CPU or DSP
MEMAD[19] // O // PNVM/SRAM address bus outputs //
28 PLLSEL I PLL frequency selection - 108 MHz (low) or 135 MHz (high). Level sampled
MEMAD[18-14] O PNVM/SRAM address bus outputs
4,6
MEMAD[13] // O // PNVM/SRAM address bus output //
7 AFETESTEN I Audio PLL configuration input. Level sampled during RESET. In normal
MEMAD[12] // O // PNVM/SRAM address bus output //
8 PLLCFGA I AFE test mode enable input. Level sampled during RESET. In normal operation
MEMAD[11] // O // PNVM/SRAM address bus output //
10 PLLCFGP I Process PLL configuration input. Level sampled during RESET. In normal
MEMAD[10] // O // PNVM/SRAM address bus output //
13 TESTMODE I Operational mode selection. Level sampled during RESET. In normal operation
MEMAD[9-2] O PNVM/SRAM address bus outputs
MEMAD[1,0] // O // PNVM/SRAM address bus outpu t //
BOOTSEL[2,1] I CPU SW boot (and execute) source selection:
MEMAD[0] // O // PNVM/SRAM address bus output //
49 BOOTSEL1 I CPU SW boot (and execute) source selection - Flash (low) or first debug
23 MEMWR# O PNVM/SRAM write enable (active low) output.
44 MEMRD# O PNVM/SRAM read enable (active low) output.
SW //
SW //
SW
during RESET
operation the pin must be low during RESET
the pin must be low during RESET
operation the pin must be low during RESET
the pin must be low during RESET.
(high, high) - For production testing;
(high, low) - Flash+SRAM (for debug monitor);
(low, high) - First debug UART; (low, low) - Flash (low) or
Level sampled during RESET
UART (high). Level sampled during RESET
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