List of key parts---------------------------------------------------------------------15
IC BLOCK Diagram----------------------------------------------------------------16-29
MAIN PCB-TOP--------------------------------------------------------------------30
MAIN PCB-BOT--------------------------------------------------------------------31
Circuit Diagrams--------------------------------------------------------------------32-40
-2-
LCD 8M79B chassis.
-3-
4.
65
120
For 32LED
For 42LED
Base on different order
5.
-4-
93
93
95
95
400
450
97
97
FOR 32LED
FOR 42LED
For 42LED
For 42LED
9800
8
8
12500
12500(266, 276)
9800(280, 290)
6500(313, 329)
-5-
1015
24
40
40
3
1
4.2
50
2
80
0.5
12000
40
6
-6-
1080
1920
For 42LED
For 42LED
40
NO
YES
8
6
46
46
NO
Standard
Standard
20
uv
uv
English
No
Middle
-7-
Base on different order
"Low" in some status
4
-8-
DTV-PRODUCTOINS SPECIFICATION
Model #
Country( West Eu./East Eu./Russia/AP/US/S.A./Japan/…)Brazil & Argentina
Predecessor (replace)MP date requested (ETD)2011.8
MP date confirmed by supplier (ETD/ETA)Status( Pre./Finish )-
Regional requirement
Homologation (Gostandard/CE/MPTT/CB/…)CB
42"~55"
RoHSYes
Power supply(100-240V AC +/-10%/...)100-240V AC (-20%,+10%)
Power consumption working / AnnualPower consumption standby<1W
Power plug(VDE/UL/BS/…)UCIEE/2pins
Color process (Gama correction/Skin correction /... )Follow main IC
Colour preset (Cool/Normal/Warm/Personal)Neutral, Cool, Warm and Personal in PC mode
>10000:1
Picture control ( Bright/Con./Sharpness/Color/Tint/…)Yes
Picture presets : Standard / Bright / Soft / UserNormal / Soft / Personal / Bright
-9-
Picture freezeYes
Multi picture : PIP ( AV )/POP(AV)
Dynamic Backlight ControlNo
LED BacklightYes
Deinterlacer (No/linerar/motion adaptive/motion
compensative)
Film mode / reverse 3:2/2:2 pull downYes / Yes
Full HD support ( 1080P )Yes
Single scan / Dual scan ( 120HZ )Single scan
Zoom type : 4/3 formatYes
Zoom type : 14/9 ZoomYes
Zoom type : 16/9 Zoom16/9 ZOOM 1
Zoom type : 16/9 Zoom up/down16/9 ZOOM 2
Zoom type : CineramaYes
Zoom type : 16/9 FormatYes
Zoom type : Auto ( by SCART Pin8 and WSS )Yes
Picture Auto adjustment (PC mode)Yes
3D Panel Type(PR / SG)PR
3D ModeLeft/Right, Up/Down, Frame Sequence
3D To 2D (Y/N)Yes
2D To 3D (Y/N)Yes
Left / Right Swap (For PR Panel)Yes
Sound
Sound type ( Mono/AV stereo/Stereo ) stereo
Music Power (Watt)/RMS Power (Watt)2 x 8W
Tone control ( Bass&Treble / Graphic Equalizer )Bass&Treble
Special sound effect ( AVL / WIDE / Pseudo /… )AVL
Suround system ( Dolby / VD / SRS / BBE / … )Built-in Surround
Sound control ( Volume , Balance , Mute )Volume, Balance, Mute
Sound presets (User/Speech/News/Standard)Standard / Music / Film / News / Personal
Headphone volume control ( Separated / linked )Yes(Linked)
Sound quality ( High / Mid / Low )Mid
Reception and Decoding capability
RF range(ATV)54MHz~864MHz
RF range(DTV)
Color System (PAL/SECAM/NTSC/PAL M,N )PAL M,PAL N,NTSC M
Audio Standard ( B/G/H/D/K/K'/I/L/L' )M,N
Stereo audio system ( Nicam,MTS,A2,….)BTSC,SAP
Video standard NTSC 3.58 / 4.43 (AV)/PAL 60NTSC 3.58/4.43 , PAL
DTV SD support (DVB-T/S/C , ATSC , QAM , … )ISDB-T
DTV HD SupportMPEG2,MPEG4,H.264
VHF 177-213 MHZ, UHF 473-803 MHZ
3D motion adaptive
No
MHEG5No
HD capability with YPbPrYes (720p; 1080i; 1080p@24/50/60Hz; 480i/p; 576i/p)
PC capability (up to maximum format)Up to 1280X1024 60Hz
HDMI capability (AV/PC Format)
Compatible video format if DVD/USB:
DviX/VCD/SVCD/JPEG/AVI/MPEG2/WMV- HD/SD
JPEG/MPEG2/MPEG4/H.264/DivX (depending on license)
Up to 1080P 24/50/60HZ
-10-
Compatible audio format if DVD/USB:
)
t
MP3/WMA/AAC/MPEG1/…
Playable Discs (CD/CD-R(RW)/CD-ROM/DVD+R/+RW/R/-RW
Card reader format compatibilityNo
MacrovisionYes
PVR
DTV Program Numbers370
Program edit ( naming , sorting , skip , swap …. ) Skip / Delete
Auto Naming/Auto SortingNo
TV Guide(DTV EPG)EPG(next Seven-day)
Favorite programYes
Number of buttons on cabinet (Power; Vol+/-; Pr+/-, Menu
)
Main switch button (yes/No)Yes
CCD(Closed Caption)/V-CHIP
Text Standard: (Top, FLOF,,,)No
Teletext Level: 2.5 / 1.5Pages for teletextTeletext character sets ****DVB-T teletext-
Real clockFrom DTV
Sleep timer10-240 Min.
TimerTurn On / Off, Program Switch
Parent Control -Source and Channel lock (Input code for
certain channel)
Parent Control - Child lock (set the lock of the keyboard,
only the RCU can control the TV)
Parent Control - Kid pass (preset the ontime, channel for
each day of the week)
Parent Control - Channel lock (For digital transmission
and DVD program, to filter some programms)
Calendar / GamesNo
No program auto switch off15 mins.
Hotel mode (Y/N)T.B.D
DVD player (No/slot/tray)No
Tuner FM (yes/No)No
software download(RS232/CI/USB/OAD)USB
MP3/WMA(depending on license)
No
Yes(FOR USB)
No
Vol+/-; CH+/-, Menu ,Source,Standby(optional)
Yes/No
Yes
No
No
Yes
Factory resetYes
-11-
Screen saverYes
Blue BackNo
LED indicator(Power on/Standby)Blue / Red
Connectors
RF Input (Antenna): Air/ Cable/ 2in1Air+Cable
Scart : CVBS in&out / RGB / S-VIDEONo
CINCH video in / out(AV1)
CINCH audio in / out (No volumpe control on Audio
out/can be jack 3,5mm)
S-video inNo
Component Video Input (YCrCb/YPrPb)No
Component Audio Input (YCrCb/YPrPb)No
VGA in / Audio L/R in / Jack audio in 3.5mmVGA + dia. 3.5mm for audio in
HDMI2
DVINo
Audio input for DVINo
CINCH subwoofer out / Coaxial out (S/PDIF)No
Headphone output connector (mm)No
CINCH subwoofer out / Coaxial out (S/PDIF)
RS232 ( Y/N , VGA or DB9 port …)No
Card ReadersNo
-Rear
No
No
S/PDIF out ( Coaxial )
USB slot (No/1.1/2)
DVB-CI (common interface)No
External power converter inputNo
Connectors
HDMI1
AV-IN1
AV-OUTNo
Component Video Input (YCrCb/YPrPb)1
Component Audio Input (YCrCb/YPrPb)1 (Share with AV audio in)
Headphone output connector (dia.mm)
CINCH subwoofer out / Coaxial out (S/PDIF)No
USB slot (No/1.1/2)
DVB-CI (common interface)No
DLNANo
UI/RC
UI design (font/pixel, 2D/3D graphic engine..)
RC Model
RC system
RC # of keys
Size (W x H x D, with stand) in mmSize (W x H x D, without stand) in mmPackage Size (W x H x D, without stand) in mmNet Weight in kgGross Weight in Kg-
Design / Mechanical
Wallmount VESA compatible (standard reference)Yes
Adaptor for VESA wallmount compatibility (accessory ref)Yes
Desktop Stand (included/optionnal + ref/No)included
Panel Tilt (Fowards/Backwards/Rotation)No
Swivel function desktop stand (yes/No) + motorized?No
Docking station (yes/No)No
Floor Stand (included/optionnal + ref/No)No
Glass shield (yes/No)No
Finish on FrontFinish on sideFinish on backFinish on standnumber of colors on carton box2
Brand logoCustomer Inlet
Other logoNo
External AC/DC Power with DC power cord (yes/No)No
Handle (yes/No)No
Detachable speaker (yes/No)No
Rating Label langagesEnglish
Yes(English)
-13-
SYSTEM
POWER SUPPLY
Uplayer1
HDMI1
PR
PB
Y
R
L
Video
Optional
PIXELWORKS 3D Processor
Motion Engine
PA131DG
DVB-T&ATV
Demo d
MSD309PX-LF-SB
DVB-T & IF Demo. Build in
MPEG1/2/4 /H.264 Decoder
JPEG MP3 Decoder
3D Comb filter Video Decoder
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially
written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pi
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle
is in progress. When CS# is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After
must transition from high to low before a new instruction will be accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,
while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI
signals.
n provides the timing for serial input and output operations. ("See
power-up, CS#
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s B
Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
lock Protect (BP0, BP1and BP2) bits and Status Register
All functions required for ISDB-T demodulation and error correction are built into the TC90517.
The input signals to be supported are a low IF (intermediate frequency) signal and direct IF signal.
Baseband IQ signals can also be input.
The output signal is an MPEG-2 transport stream (TS) in serial format. Note that a TS in parallel format
can be output by setting registers.
This specification indicates pins and their signals in upper case letters and registers and their signals in lower case
letters.
Pin Pin name
1 TSMD0 I - Shut down 0: Normal operation 1: Shut down
2 XSEL1 I - Crystal frequency division ratio 1 Set according to crystal frequency.
3 XSEL0 I - Crystal frequency division ratio 0 Set according to crystal frequency.
4 VSS - - Digital GND Connects to DGND.
5 SLADRS1 I/O - Slave address 1 Set according to slave address.
6 SLADRS0 I/O - Slave address 0 Set according to slave address.
7 AGCI I - External AGC input Connects to DGND when not used.
8 S_INFO I - Pin for pre-shipment test Connects to DGND.
9 AGCCNTI I/O PD IF_AGC control output Connects to tuner IF_AGC control input pin.
10 AGCCNTR I/O PD RF_AGC control output
11 CKI I - Pin for pre-shipment test Connects to DGND.
12 TNSCL I/O OD I2C clock output
13 VDDS - - I/O power supply Connects to digital +3.3 V typ.
14 TNSDA I/O OD I2C data I/O
15 VSS - - Digital GND Connects to DGND.
16 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
17 PLLVSS - - Clock PLL GND Connects to AGND.
18 XO O - Crystal output
19 XI I - Crystal or reference clock input
20 PLLVDD - - Clock PLL power supply Connects to analog +2.5 V typ.
21
22 AD_AVDD - - ADC analog power supply Connects to analog +2.5 V typ.
23 AD_AVSS - - ADC analog GND Connects to AGND.
24 AD_VREFP - - ADC reference voltage output +1.75 V typ. Connects to AGND via PC.
25 AD_VREFN - - ADC reference voltage output +0.75 V typ. Connects to AGND via PC.
26 AD_VREF - - ADC reference voltage output +1.25 V typ. Connects to AGND via PC.
27 ADQ_AIN I -
28 ADQ_AIP I -
29 ADI_AIN I -
FIL O - PLL filter output Connects to AGND via 1500 pF.
(Note4)
30 ADI_AIP I -
I/O
(Note5,7)
PU/PD
Function
Q signal (differential negative side)
input
Q signal (differential positive side)
input
IF signal (differential negative side)
input or Isignal (differential
negative side) input
IF signal (differential positive side)
input or I signal (differential
positive side) input
(Note 3)
-25-
(Note 2 and 6)
skrameR
Connects to tuner RF_AGC control input pin.
Open, fixed to L when not used.
Connects to tuner I2C clock pin.
(Pull-up performed outside IC.)
Connects to tuner I2C data pin.
(Pull-up performed outside IC.)
Connects to crystal.
ixosl="1" and open when an external reference clock
is input.
Connects to crystal.
The amplitude (p-p) is 0.5 V to PLLVDD when an
external reference clock is input.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to AGND via PC.
Single-ended IQ: Connects to AGND via PC.
Differential IQ: Connects to tuner Q (-) output after
the DC component was cut.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to AGND via PC.
Single-ended IQ: Connects to tuner Q output after
the DC component was cut.
Differential IQ: Connects to tuner Q (+) output after
the DC component was cut.
Single-ended IF: Connects to AGND via PC.
Differential IF: Connects to tuner IF (-) output after
the DC component was cut.
Single-ended IQ: Connects to AGND via PC.
Differential IQ: Connects to tuner I (-) output after the
DC component was cut.
Single-ended IF: Connects to tuner IF output after
the DC component was cut.
Differential IF: Connects to tuner IF (+) output after
the DC component was cut.
Single-ended IQ: Connects to tuner I output after the
DC component was cut.
Differential IQ: Connects to tuner I (+) output after the
31 AD_DVSS - - ADC digital GND Connects to DGND.
32 AD_ DVDD - - ADC digital power supply Connects to digital +2.5 V typ.
33 VSS - - Digital GND Connects to DGND.
34 DR1VDD - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
35 VDDS - - I/O power supply Con nects to digital +3.3 V typ.
36 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
37 VSS - - Digital GND Connects to DGND. 38 STSFLG1 O PD Status flag 1 output Open, fixed to L when not used.
39 DTCLK I PD Pin for pre-shipment test Open or connects to DGND.
40 DTMB I PU Pin for pre-shipment test Open or connects to digital +3.3 V typ.
41 TSMD1 I - Pin for pre-shipment test Connects to DGND.
42 SYRSTN I/O OD System reset input Input at specified timing at power ON.
43 DR2VDD - - Digital +2.5 V power supply Connects to digital +2.5 V typ.
44 VSS - - Digital GND Connects to DGND.
45 SCL I/O OD I2C clock input for host CPU
46 SDA I/O OD I2C data I/O for host CPU
47 VSS - - Digital GND Connects to DGND.
48 DR1VDD - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
49 VDDS - - I/O power supply Con nects to digital +3.3 V typ.
50 VSS - - Digital GND Connects to DGND.
51 STSFLG0 I/O PD Status flag 0 output Open, fixed to L when not used.
52 SLOCK O
53 RERR O - RS decoding error flag output Open, fixed to L when not used.
54 RLOCK O - RS decoding error free flag output Open, fixed to L when not used.
55 RSEORF O - TS error flag output Open, fixed to L when not used.
56 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
57 VSS - - Digital GND Connects to DGND.
58 PBVAL O - TS valid flag output Open, fixed to L when not used.
59 SBYTE O - TS synchronization byte flag output Open, fixed to L when not used.
60 SRDT O - Serial TS data output 61 SRCK O - TS serial clock output 62 VSS - - Digital GND Connects to DGND.
63 VDDC - - Digital +1.2 V power supply Connects to digital +1.2 V typ.
64 VDDS - - I/O power supply Con nects to digital +3.3 V typ.
CONFIDENTIAL
Synchronization completion
(sequence 8 or higher) flag
DC component was cut.
Connects to I2C clock bus.
(Pull-up performed outside IC.)
Connects to I2C data bus.
(Pull-up performed outside IC.)
Open, fixed to L when not used.
Note 2 AGND is the abbreviation for analog GND, and DGND is the abbreviation for digital GND.
Note 3 The test dedicated pin is used for the pre-shipment test only. Make sure that processing is performed as
indicated in the "Remarks" column. Any other method will lead to malfunction or failure.
Note 4 I/O indicates the type of the cell used. It may be different from the pin function because a test is conducted
concurrently.
Note 5 PU indicates an I/O with a pull-up resistor (50 k typ.) and PD indicates an I/O with a pull-down resistor (50
k typ.). Pulling down the PU pin or pulling up the PD pin outside the
potential to the midpoint, resulting in instability. Caution is required.
Note 6 The unused output pins must be open and fixed to L by setting the output enable control register of each pin
for noise reduction or set to the output OFF state.
Note 7 OD indicates an open drain I/O. To use the pin for output, pull up the resistance outside the IC.
IC sometimes changes the electric
* The following pins are added with the upgrade from TC90507 to TC90517 (except the changes of power
supply and GND pins):
Pin
Number
21 FIL Added to the PLL loop filter.
27 ADQ_AIN Added for IQ input (differential).
28 ADQ_AIP Added for IQ input.
7 AGCI Added to passthrough the AGC control signal of other ICs.
52 SLOCK Changed from conventional FLOCK.
Pin Name Description
-26-
IC Block Diagram
4. B A L L C O N FIG U R A TIO N
123456789
PRELIMINARY W9751G6JB
V D D
D Q 14
V D D Q
D Q 12
V D D
D Q 6
V D D Q
D Q 4
V D D L
N C
N C
V S S Q
D Q 9
V S S Q
N C
V S S Q
D Q 1
V S S Q
V S S
U D M
V D D Q
D Q 11
V S S
LD M
V D D Q
D Q 3
V S SV R E F
C K E
W E
B A 0B A 1
A
B
C
V S S Q
U D Q S
V D D Q
D
E
F
G
H
J
K
L
V S S QL D Q S
LD Q S
V D D Q
D Q 2
V S S D L
R A S
C A S
U D Q S
V S S Q
D Q 8
V S S QD Q 10
V S S Q
D Q 0
V S S Q
C L K
C L K
C S
V D D Q
D Q 15
V D D Q
D Q 13
V D D Q
D Q 7
V D D Q
D Q 5
V D D
O D T
V S S
A 1 0 /A P
A 3
A 1
A 5
M
N
P
V D DA 1 2N CN CN C
R
-27-
A 1 1A 8A 9A 7
A 2
A 6
A 0
A 4
V D D
V S S
IC Block Diagram
5. BALL DESCRIPTION
PRELIMINARY W9751G6JB
BALL NUMBER SYMBOL
M8,M3,M7,N2,N8,N3
,N7,P2,P8,P3,M2,P7
,R2
L2,L3 BA0−BA1 Bank Select
G8,G2,H7,H3,H1,H9
,F1,F9,C8,C2,D7,D3,
D1,D9,B1,B9
K9 ODT
F7,E8
B7,A8
L8
K7,L7,K3
B3,F3
J8,K8
K2 CKE Clock Enable
J2 VREFReference Voltage VREF is reference voltage for inputs.
A1,E1,J9,M9,R1 VDDPower Supply
A3,E3,J3,N1,P9 VSSGround Ground.
A9,C1,C3,C7,C9,E9,
G1,G3,G7,G9
A7,B2,B8,D2,D8,E7,
F2,F8,H2,H8
A2,E2,L1,R3,R7,R8 NC No Connection No connection.
J7 VSSDLDLL Ground DLL Ground.
J1 VDDLDLL Power Supply
A0−A12 Address
DQ0−DQ15
LDQS,
LDQS
UDQS,
RAS , CAS
UDM
LDM
CLK,
CLK
VDDQDQ Power Supply
VSSQDQ Ground DQ Ground. Isolated on the device for improved noise immunity.
FUNCTION DESCRIPTION
Provide the row address for active commands, and the column
address and Auto-precharge bit for Read/Write commands to select
one location out of the memory array in the respective bank.
Row address: A0−A12.
Column address: A0−A9. (A10 is used for Auto-precharge)
BA0−BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Data Input
/ Output
On Die Termination
Control
LOW Data Strobe
UP Data Strobe
Chip Select
Command Inputs
Input Data Mask
Differential Clock
Inputs
Bi-directional data bus.
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM.
Data Strobe for Lower Byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data.LDQS corresponds to the data on
DQ0−DQ7.
is enabled via the control bit at EMR (1)[A10 EMRS command].
Data Strobe for Upper Byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data.UDQS corresponds to the data on
DQ8−DQ15.
is enabled via the control bit at EMR (1)[A10 EMRS command].
All commands are masked when
HIGH.
multiple ranks.
RAS , CAS andWE (along with CS) define the command being
entered.
DM is an input mask signal for write data. Input data is masked when
DM is sampled high coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
CLK and CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of CLK . Output (read) data is referenced to the
crossings of CLK and CLK (both directions of crossing).
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
Power Supply: 1.8V ± 0.1V.
DQ Power Supply: 1.8V ± 0.1V.
DLL Power Supply: 1.8V ± 0.1V.
provides for external bank selection on systems with
is only used when differential data strobe mode
LDQS
is only used when differential data strobe mode
is registered
is considered part of the command code.
-28-
IC Block Diagram
6. BLOCK DIAGRAM
PRELIMINARY W9751G6JB
CLK
CLK
CKE
RAS
CAS
CS
WE
A10
A11
A12
BA0
BA1
DLL
CLOCK
BUFFER
CONTROL
SIGNAL
COMMAND
DECODER
A0
REFRESH
COUNTER
ADDRESS
BUFFER
A9
GENERATOR
MODE
REGISTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
PREFETCH REGISTER
DATA CONTROL
COLUMN DECODER
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DQ
BUFFER
COLUMN DECODER
ODT
CONTROL
ODT
DQ0
|
DQ15
LDQS
LDQS
UDQS
UDQS
LDM
UDM
CELL ARRAY
BANK #2
SENSE AMPLIFIER
NOTE: The cell array configuration is 8192 * 1024 * 16
PART NO. : 168P-P32EWM-K0
DESCRIPTION :
VERSION NO. : 1.0
PAGE : 13
DESCRIBED : Zhou Cong
CHECKED : Hu xiangfeng
APPROVED : Bao xiaojie
Released Date: 2012-07-21
168P-P32EWM-K0 Service manual
Modification record
Edition
1.0 2012-7-21 First recordZhou Cong Hu Xiangfeng Bao Xiaojie
Modification
date
Record Described Checked Approved
I
168P-P32EWM-K0 Service manual
Contents
NO. Main contents Page
1 General Description
2 General Introduction of Circuit
3 The main chip description
4 PCB TopOverlay or BottomOverlay
5 Maintenance instructions
6 The information of power supply designer
7 Schematic diagram
1
2
4
9
11
14
14
II
168P-P32EWM-K0 Service manual
Warning
This manual is only used for the experienced service person , and does not apply to the general
consumer。The manual does not have warnning or alert for the potential hazards caused of the non-technical
personnel attempting to repair this product . Electrical products should be an experienced professional and
technical personnel for maintenance and repair ,any other person attempts to maintain and repair the
products covered by this manual will likely be seriously hurt or even life-threatening.
1.General Description
1.1 General description of power supply
This power apply to 32-inch universal standard power interface; the total standby power consumption
less than 1W (5V DC the Load 50mA); protection functions; low cost; mature power supply structure; the
voltage range is 90-264V and wide supply voltage input,.For 32” LED panel, supplies 4 channels, each
channel nominal current value is 130mA。
1.2 Main technical specifications
1.2.1 Input Electrical Characteristics
Input voltage range
Rated voltage range 100Vac to 240Vac
Frequency range 50Hz/60Hz±5%
Max input ac current 0.85Amax at 100Vac input & full load condition
Inrush current (cold start) 70Atyp peak
Efficiency(full load) 80%min @ 100Vac,Full Load
Harmonic current Meet GB17625.1-1998/IEC61000-3-2 class D
Leakage Current Less Than 0.75mA, 230Vac input
Standby Power Loss ≦1W, 240Vac input, 50mA Load of 5V
Input Fuse T3.15A L/250Vac
Note: 1) Measurements shall be made with an oscilloscope with 20MHz bandwidth.
2) Outputs shall be bypassed at the connector with a 0.1uF ceramic capacitor and a 10uF
electrolytic capacitor to simulate system loading.
2.Circuit description
2.1 The power circuit diagram
2.2 Each part of the circuit description
2.2.1 the main part of the circuit:NXP TEA1733P
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168P-P32EWM-K0 Service manual
2.2.2 the LEDdriverof the circuit:MICRO ELECTRONICSOZ9967
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3. The main chip description
3.1 The main chip
3.1.1 The main chip general description
The main chip of power supply is the TEA1733P which is produced by NXP corporation.
The operating mode is CCM (continuous conduction mode), and the operating frequency is
65KHz.
3.1.2 The chip pin information
3.1.3 T
he chip block diagram
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3.1.4 The IC pin description
3.2 The DC-DC chip
3.2.1
frequency is 700KHz.
3.2.2
General description
The DC-DC used for standby chip, using SY8172Y, double synchronous rectification,and operating
The chip block diagram
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3.2.3 The chip pin information
3.2.4 The
pin description and the voltage
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168P-P32EWM-K0 Service manual
3.3 The LEDdriver chip
3.3.1 General descriptionThe OZ9967 is an LED controller that drives a number of LEDs connected in serial or parallel
configuration.
3.3.2
The chip block diagram
3.3.3The chip pin information
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3.3.4 The pin description and the voltage
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4. PCB TopOverlay and BottomOverlay
4.1 The power supply TopOverlay
4.2 The power supply BottomOverlay
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5. Maintenance instructions
5.1 Common Fault Analysis and Notes
1.No +5VSB output voltage If there is no +5VSB output voltage , we should focus on checking the DC-DC IC(IC301) and judge
whether the IC is operating . Monitor its VIN pin and check voltage is normal or abnormal . If it is normal ,
firstly , check the DC-DC IC peripheral circuit . Secondly, check DC-DC IC(IC301)and judge it has broken
or not. If the VIN pin voltage is abnormal, you need to check the IC100 power circuits.
2.+5VSB output is normal ,+12V output is abnormal
First, check +12 V voltage of the MOS transistor(Q300) S pole is normal or abnormal , if it is
normal,please check the MOS transistor(Q300) peripheral circuit is normal or not. If the +12 V voltage of
the MOS transistor(Q300) S pole is abnormal, please check the IC100 circuits.
3.+5VSB is abnormal
Check the +5 VSB feedback loop , and the re ference voltage of the IC301 is normal or not.
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5.2 Service process
NO +5VSB
168P-P32EWM-K0 Service manual
Check + 5V output , Whether
the short-circuit
N
Is IC301 damaged?
N
Examine the positive voltage
of C312: 11.8V-12.2V?
Box must have the product name, model, identification,quality inspection department certification,the
date of manufacture and so on.
5.4.2 Transportation
The productor adapted to cars, boats, aircraft transport .Transportation should be covered, prevented
sunshine and loading lightly.
Storage
5.4.3
Products should be stored in a box if it is not used .The storehouse environment temperature is from
-40 ℃ to -55 ℃, relatived humidity is from 10% to -95%. The storehouse must not allow any harmful
gases, flammable ,explosive and corrosive product chemicals, and must not allow strong mechanical
vibration, shock and strong magnetic field. Boxes should be at least 20cm high from the ground .The
distance from the wall, heat source, windows or air enter is at least 50cm. The storage period is about two
years, more than two years should be re-tested under the regulation .