SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH
CAUTION:
Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.
ATTENTION:
Avant d’effectuer l’entretien du châssis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.
42PD6600L
42PD6A10
Data contained within this Service
manual is subject to alteration for
improvement.
Les données fournies dans le présent
manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.
Die in diesem Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
42” Plasma TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a
1024*1024 panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC
(playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including
German and NICAM stereo. Sound system output is supplying 2x10W (10%THD) for stereo 8ȍ
speakers. The chassis is equipped with many inputs and outputs allowing it to be used as a center of a
media system.
It supports following peripherals:
3 SCART sockets
1 AV input (CVBS + Stereo Audio)
1 SVHS input
1 Stereo Headphone input
1 Component input (YPbPr + Stereo Audio)
1 D-Sub 15 PC input
1 HDMI input
1 Stereo audio input for PC
1 Stereo audio output
1 Subwoofer output
2. TUNER
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L’,
I/I’, and D/K. The tuning is available through the digitally controlled I
info on one of the Tuners in use.
2
C bus (PLL). Below you will find
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low
IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient
suppression of triple transient.
Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I
2
C-bus
4. Off-air channels, S-cable channels and Hyperband
5. World standardised mechanical dimensions and world standard pinning
6. Compact size
7. Complies to “CENELEC EN55020” and “EN55013”
Pinning:
1. Gain control voltage (AGC) : 4.0V, Max: 4.5V
2. Tuning voltage
3. I²C-bus address select : Max: 5.5V
4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V
5. I²C-bus serial data : Min:-0.3V, Max: 5.5V
6. Not connected
7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V
8. ADC input
9. Tuner supply voltage : 33V, Min: 30V, Max: 35V
10. Symmetrical IF output 1
11. Symmetrical IF output 2
3. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL.
The following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO
and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF
amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition
1
help, Audio amplifier and mute time constant, I²C-bus transceivers and MAD (module address), Internal
voltage stabilizer.
4. MULTI STANDARD SOUND PROCESSOR
The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of
all analogue TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analogue sound IF signal-in, down to processed analogue AF-out, is
performed on a single chip.
These TV sound processing ICs include versions for processing the multichannel television sound
(MTS) signal conforming to the standard recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is
performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard
(EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for
BTSC and EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
5. VIDEO SWITCH TEA6415
In case of three or more external sources are used, the video switch IC TEA6415 is used. The main
function of this device is to switch 8 video-input sources on the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level
of the signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment
is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used
as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching
possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible
to have the same input connected to several outputs.
6. AUDIO AMPLIFIER STAGE WITH TPA3004D2
The TPA3004D2 is a 12-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied
stereo speakers. The TPA3004D2 can drive stereo speakers as low as 4 . The high efficiency of the
TPA3004D2 eliminates the need for external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a
range of gain from –40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are
also dc voltage controlled with a range of gain from –56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
2
7. POWER SUPPLY (SMPS)
The required DC voltages; at various parts of the chassis; are provided by an SMPS (switch mode
power supply). Block diagram of SMPS as follow
Connector layout as follows
3
SMPS can work between 120V – 240 AC and generate following voltages
Vs 80V 3A (For panel)
Va 60V 0.7A (For panel)
15V audio 15V 2.1 A (Audio)
12V 12V 1A (For 60V regulation circuitry)
Vcc on 5.1V 6.2 A ( For panel and main board)
5V stby 5V 1.5A (For panel and main board)
POWER ON/OFF SEQUENCE
START UP SEQUENCE
- Set CPUGO “High”. VCC becomes ready.
- Set PDPGO “High” This product outputs VCEGO “High” after the confirmation of PDPGO
“High” and VCC “Low”.
- Input Vcc after the confirmation of VCEGO “High”. When Vcc becomes higher than a set
voltage, and Va, Vs are confirmed to lower than set voltages.
- Input Vs and Va after confirmation of VSAGO “High”. This product wait 5 sec for Va, Vs more
than set values. If Va and Vs don’t rise up to more than set voltages within 5 sec., this product
once shuts down and retries the start up sequence from the beginning.
*Vcego mentioned as Stanby and Vsage mentioned as PDP go on main board.
4
SHUT DOWN SEQUENCE
Shut Down sequence for this product as follows.
-Set PDPGO or CPUGO “low”. This product stops to display and outputs VSAGO “low”.
- Cut Vs and Va after the confirmation of VSAGO “low”. This product outputs VCEGO “low” after the
confirmation that Vs and Va are lower than set Values.
- Cut Vcc after the confirmation of VCEGO “low”.
On daughter board 3.3 V (normal) is generating and transferring the voltages to main board. Main
board gets 5V stby, 5V, 3.3V and 15V.
8. MICROCONTROLLER
The Micronas SDA 55xx TV microcontroller is dedicated to 8 bit applications for TV control and provides
dedicated graphic features designed for modern low class to mid range TV sets. The SDA 55xx provides also
an integrated general purposefully 8051-compatible microcontroller with specific hardware features
especially suitable in TV sets. The microcontroller core has been enhanced to provide powerful features such
as memory banking, data pointers and additional interrupts, etc. The internal XRAM consists of up to 16
kBytes. The microcontroller provides an internal ROM of up to 128 kBytes. ROMless versions can access up
to 1 MByte of external RAM and ROM. The 8-bit microcontroller runs at 33.33 MHz internal clock. SDA 55xx
is realized in 0.25 micron technology with 2.5 V supply voltage for the core and 3.3 V for the I/O port pins to
make them TTL compatible. Based on the SDA 55xx microcontroller the MINTS software package was
developed and provides dedicated device drivers for many Micronas video & audio products and includes a
full blown TV control SW for the PEPER application chassis. The SDA 55xx is also supported with powerful
design tools like emulators from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler and TEDIpro OSD
development SW by Tara Systems.
5
9. EEPROM 24LC32
The Microchip Technology Inc. 24AA32A/24LC32A(24XX32A*) is a 32 Kbit Electrically Erasable PROM. The
device is organized as four blocks of 8K x 8-bitmemory with a 2-wire serial interface. Low-voltage design
permits operation down to 1.8V, with standby and active currents of only 1μA and 1mA, respectively. It has
been developed for advanced, low-power applications such as personal communications or data acquisition.
The 24XX32A also has a page write capability for up to 32 bytes of data. Functional address lines allow up to
eight devices on the same bus, for up to 256Kbits address space.
10. CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package.
The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital
audio applications.
11. SAW FILTERS
K9656M:
Standard:
• B/G
• D/K
• I
• L/L’
Features
• TV IF audio filter with two channels
• Channel 1 (L’) with one pass band for sound carriers at 40.40 MHz (L’) and 39.75 MHz (L’- NICAM)
• Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32.35 MHz and 33.40 MHz
The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be
switched on only one of each input. On each input an alignment of the lowest level of the signal is made
(bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input
and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an
external resistor bridge, 5 V
DC on the input. Each input can be used as a normal input or as a MAC or
Chroma input (with external resistor bridge). All the switching possibilities are changed through the
BUS. Driving 75 load needs an external transistor. It is possible to have the same input connected to
several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In
this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16
bits is necessary to determine one configuration.
12.1.2. Features
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor
bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
12.1.3. Pinning
1. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
2. Data : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
3. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
4. Clock : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
5. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
6. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
10. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
11. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
12. Ground
13. Output : 5.5Vpp, Min : 4.5Vpp
14. Output : 5.5Vpp, Min : 4.5Vpp
15. Output : 5.5Vpp, Min : 4.5Vpp
16. Output : 5.5Vpp, Min : 4.5Vpp
17. Output : 5.5Vpp, Min : 4.5Vpp
18. Output : 5.5Vpp, Min : 4.5Vpp
19. Ground
20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA
8
12.2. 24LC02
12.2.1. Description
The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM.
The device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby and active currents of only 1μA and 1mA,
respectively. The 24XX02 also has a page write capability for up to 8 bytes of data.
12.2.2. Features
• Single supply with operation down to 1.8V
• Low-power CMOS technology
-1mA active current typical
-1μA standby current typical (I-temp)
• Organized as 1 block of 256 bytes (1 x 256 x 8)
• 2-wire serial interface bus, I
2
C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes
• 2ms typical write cycle time for page write
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP and MSOP packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available for extended temperature ranges:
-Industrial (I): -40°C to +85°C
-Automotive (E): -40°C to +125°C
12.2.3. Pinning
9
12.3. 24LC32
12.3.1. General Description
The Microchip Technology Inc. 24AA32A/24LC32A(24XX32A*) is a 32 Kbit Electrically Erasable PROM. The
device is organized as four blocks of 8K x 8-bitmemory with a 2-wire serial interface. Low-voltage design
permits operation down to 1.8V, with standby and active currents of only 1μA and 1mA, respectively. It has
been developed for advanced, low-power applications such as personal communications or data acquisition.
The 24XX32A also has a page write capability for up to 32 bytes of data. Functional address lines allow up to
eight devices on the same bus, for up to 256Kbits address space.
12.3.2. Features
• Single supply with operation down to 1.8V
• Low-power CMOS technology
-1mA active current typical
-1μA standby current typical (I-temp)
• Organized as 4 block of 8K bits (32K bit)
• 2-wire serial interface bus, I
2
C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (<2.5V) and 400 kHz (2.5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes
• 2ms typical write cycle time for page write
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP and MSOP packages
• 5-lead SOT-23 package
• Standard and Pb-free finishes available
• Available for extended temperature ranges:
-Industrial (I): -40°C to +85°C
-Automotive (E): -40°C to +125°C
12.3.3. Pinning
10
12.4. 74LVC14A
12.4.1. Description
The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This feature
allows the use of these devices as translators in a mixed 3.3 and 5V environment. The 74LVC14A provides
six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals
into sharply defined, jitter-free output signals.
12.4.2. Features
•
Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no.8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
• Specified from -40 to +85C and -40 to +125C.
12.4.3. Pinning
11
12.5. TEA6420
12.5.1. Features
• 5 Stereo Inputs
• 4 Stereo Outputs
• Gain Control 0/2/4/6dB/Mute for each Output
• Cascadable (2 different addresses)
• Serial Bus Controlled
• Very low Noise
• Very low Distortion
12.5.2. Description
The TEA6420 switches 5 stereo audio inputs on4stereo outputs. All the switching possibilities are
changed through the I
2
C bus.
12.5.3. Pin Connections
12.6. CS4334
12.6.1. Features
•
Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering
• 24-Bit Conversion
• 96 dB Dynamic Range
• -88 dB THD+N
• Low Clock Jitter Sensitivity
• Single +5V Power Supply
• Filtered Line Level Outputs
• On-Chip Digital De-emphasis
• Popgaurd® Technology
• Functionally Compatible with CS4330/31/33
12.6.2. General Description
The CS4334 family members are complete, stereo digital-to-analog output systems including
interpolation, 1-bitD/A conversion and output analog filtering in an 8-pinpackage. The CS4334/5/6/7/8/9
support all major audio data interface formats, and the individual devices differ only in the supported
interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output
controls the reference voltage input to an ultra-linear analog low-pass filter. This architecture allows for
infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock
frequency. The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power
supply, and requires minimal support circuitry. These features are ideal for set-top boxes, DVD players,
SVCD players, and A/V receivers.
12
12.6.3. Pin Descriptions
12.7. DS90C385
12.7.1. General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the
data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock
frequency of 85MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using an 85MHz
clock, the data throughput is 297.5Mbytes/sec. Also available is the DS90C365 that converts 21 bits of
LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both
transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin.
A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver
(DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which
provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal
means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
12.7.2. Features
• 20 to 85MHz shift clock support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx power consumption <130mW (typ) @ 85MHz Grayscale
• Tx Power-down mode <200μW (max)
• Supports VGA, SVGA, XGA and Dual Pixel SXGA.
• Narrow bus reduces cable size and cost
• Up to 2.38Gbps throughput
• Up to 297.5Megabytes/sec bandwidth
• 345mV (typ) swing LVDS devices for low EMI
• PLL requires no external components
• Compatible with TIA/EIA-644 LVDS standard
• Low profile 56-lead or 48-lead TSSOP package
• DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
13
12.7.3. Pin Description
DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter
Pin Name I/O No. Description
TxIN
TxOUT+
TxOUTTxCLKIN
R_FB
TxCLK OUT+
TxCLK OUTPWR DOWN
Vcc
GND
PLL Vcc
PLL GND
LVDS Vcc
LVDS GND
I 28
O 4
O 4
I 1
I 1
O 1
O 1
I 1
I 3
I 4
I 1
I 2
I 1
I 3
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
DS90C385SLC SLC64A Package Pin Description-FPD Link Transmitter
Pin Name I/O No. Description
TxIN
TxOUT+
TxOUTTxCLKIN
R_FB
TxCLK OUT+
TxCLK OUTPWR DOWN
Vcc
GND
PLL Vcc
PLL GND
LVDS Vcc
LVDS GND
NC
I 28
O 4
O 4
I 1
I 1
O 1
O 1
I 1
I 3
I 5
I 1
I 2
I 2
I 4
6
TTL level input.
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Programmable strobe select. HIGH = rising edge, LOW = falling edge.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low
current at power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Pins not connected.
12.8. GAL16LV8
12.8.1. Description
The GAL16LV8D, at 3.5ns maximum propagation delay time, provides the highest speed performance
available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5Vsignal levels. The
GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E
combines CMOS with Electrically Erasable (E
2
) floating gate technology. High speed erase times
2
CMOS process, which
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and
supports all architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during
manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are
specified.
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