SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH
CAUTION:
Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.
No. 0232
26LD6600C
26LD6600D
Data contained within this Service
manual is subject to alteration for
improvement.
ATTENTION:
Avant d’effectuer l’entretien du châssis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.
Les données fournies dans le présent
manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.
Die in diesem Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
a) Menu Subwoofer=> If ON, Subwoofer option is available in TV set, and the item is
visible in sound menu, else Subwoofer is not available. Default “ON”.
b) Subwoofer Level (dB) => This value is gain value of Subwoofer output in dB.
-30...12. Default “0” dB.
c) Subwoofer Corner Freq. (x10Hz) => Last low frequency value that is amplified. 5...40.
Default “22” x 10Hz = 220Hz.
d) Menu Equalizer=> If ON, visible in sound menu, else invisible. Default “ON”.
e) Menu Headphone=> If ON, visible in sound menu, else invisible. Default “ON”.
f)Menu Effect=> If ON, visible in sound menu, else invisible. Default “ON”.
g) Menu Wide Sound=> If ON, visible in sound menu, else invisible. Default “OFF”.
h) Menu Dynamic Bass=> If ON, visible in sound menu, else invisible. Default “ON”.
i)Menu Virtual Dolby=> If ON, visible in sound menu, else invisible. Default “ON”.
j)Carrier Mute=> If ON, in the absence of an FM carrier the output is muted, else not.
Default “ON”.
k) Virtual Dolby Text=> Active if VIRTUAL DOLBY is ON.According to the selection; seen
in sound menu as 3DS or VIRTUAL DOLBY. Default “3DS”.
2.2.SOUND 2
a) AVL=> AVL is controlled from this menu by service user. ON/OFF. Default “ON”.
b) Menu AVL=> If ON, AVL item is visible in sound menu, and AVL can be controlled from
sound menu by normal user, else AVL is invisible to normal user. ON/OFF. Default “ON”.
c) FM PRESCALE AVL ON=> If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127. Default “29”.
d) NICAM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127. Default “62”.
e) SCART PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for scart outputs. 0...127. Default “28”.
f)SCART VOLUME AVL ON=> If AVL ON, set value in this item is used as volume value
for scart1 and scart2. 0...127. Default “116”.
TFT TV Service Manual
1
Page 6
g) FM PRESCALE AVL OFF=> If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127. Default “15”.
h) NICAM PRESCALE AVL OFF=> If AVL OFF, set value in this item is used as
prescale value for the related standard. 0...127. Default “35”.
i)SCART PRESCALE AVL OFF=> If AVL OFF, set value in this item is used as
prescale value for scart outputs. 0...127. Default “14”.
j)SCART VOLOUME AVL OFF=> If AVL OFF, set value in this item is used as volume
value for scart1 and scart2. 0...127. Default “122”.
2.3.Options
a) Burn-In Mode=> If ON, full screen flashes in RED, GREEN, BLUE colors unless
“Menu” button on Remote Control or Keypad is pressed. This property is used to protect the T V
set from burning on the assembly lines in factory. This item becomes automatically OFF, when
First APS item is ON or Factory Reset is pressed. ON/OFF. Default OFF.
b) First APS=> This bit is set “ON” in the factory. When the TV set is opened for
the first time it directs the user to make automatic search in both digital and analog modes.
c) APS Volume=> After First APS function finishes, the volume of the TV is that value.
Default “10”.
d) AGC (dB)=> Tuner AGC value. Default “15”.
e) Power-Up Mode=>Normal, Last State, Stand-by. Default “Last State”
f)PDP Working Hour=>Displays Panel Run time in decimal.
g) Factory Reset=> OK to activate. When OK pressed on this item, factory defaults
loaded.
h) Enter Flash Mode=>OK to activate. When OK pressed on this item, flash mode is entered,
SW starts to wait for uploading the new SW.
2.4.Features
a) Blue Background=> If ON, Blue Background is visible in Features Menu else not.
Default “ON”.
b) Menu Transparency=> If ON, Menu Transparency is visible in Features Menu else not.
Default “ON”.
c) Menu Timeout=> If ON, Menu Timeout is visible in Features Menu else not. Default
“ON”.
d) Backlight=> If ON, Backlight is visible in Features Menu else not.Default “OFF”.
e) Single Tuner=> If OFF, two tuners are available on the chassis. Fixed “ON”.
f)Dynamic WB=> Default
TFT TV Service Manual
2
Page 7
2.5.Teletext
a) TOP TXT=> ON/OFF
b) Fast TXT=> ON/OFF
c) Teletext Language=> Teletext Language may be controlled from this menu by service
user.
d) Txt Start RF
e) Txt Start Ext
f)Txt Start Mix
g) Menu Teletext Language => If ON, Teletext Language item is visible in Features Menu, and
Teletext Language can be controlled from Features Menu by normal user, else Teletext
Language is invisible to normal user.
2.6.Tuner Options
a) Switch Low Band
b) Switch Mid Band
c) Switch High Band
d) Boundry1 Low Byte
e) Boundry1 High Byte
f)Boundry2 Low Byte
g) Boundry2 High Byte
h) Control Byte
These values need to be filled in the factory acording to the tuner used on the chassis.
i)Store=> OK to store; when the values are entered correctly OK needs to be pressed on this
item to store the values.
TFT TV Service Manual
3
Page 8
3.SOFTWARE UPDATE DESCRIPTION
3.1.ANALOG SOFTWARE UPDATE via SCART
STEP.1
Enter service menu by pressing the buttons “MENU”,”4”,”7”,”4”,”5” respectively.
STEP.2
Select “OPTIONS” from the service menu and “ENTER FLASH MODE”
STEP.3
Connect the Software Update Tool (17tr15-3) to parellel port of your PC.
STEP.4
Connect scart-end of the cable to Scart-1 (Ext-1).
STEP.5
Connect other-end of cable to “PL 2” socket on the Update Tool (17tr15-3)
STEP.6
Run IAPWriter.exe.
STEP.7
Click “load file” and load the required software.
TFT TV Service Manual
4
Page 9
3.2.ANALOG SOFTWARE UPDATE via I2C
STEP.1
Enter service menu by pressing the buttons “MENU”,”4”,”7”,”4”,”5” respectively.
STEP.2
Select “OPTIONS” from the service menu and “ENTER FLASH MODE”
STEP.3
Connect the Software Update Tool (17tr15-3) to parellel port of your PC.
STEP.4
Connect one-end of cable to “PL904” socket on the chassis socket MB15
STEP.5
Connect other-end of cable to “PL 2” socket on the Update Tool (17tr15-3)
STEP.6
Run IAPWriter.exe.
STEP.7
Click “load file” and load the required software.
TFT TV Service Manual
5
Page 10
3.3.EEPROM UPDATE via SCART
STEP.1.
Insert the EEROM tool(TR16) to SCART-1
STEP.2.
Enter service menu by pressing the buttons “MENU”,”4”,”7”,”4”,”5” respectively
STEP.3.
Press “YELLOW” colour button on the remote controller.
Then you will have two options
STEP.3.a
Press “RED” colour button to copy data of external EEPROM into internal one
STEP.3.b
Press “GREEN” colour button to copy data of internal EEPROM into external one
TFT TV Service Manual
6
Page 11
4.INTRODUCTION
26”W TFT TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a 1366x768
( LG SLB2) panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC (playback)
colour standards and multiple transmission standards as B/G, D/K, K’, I/I’, and L/L’ including German and
NICAM stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8ȍ speakers. The chassis isinputs
equipped with many and outputs allowing it to be used as a center of a media system.
It supports following peripherals:
2 SCART sockets
1 AV input (CVBS + Stereo Audio)
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, K’, L, L’, I/I’, and
D/K. The tuning is available through the digitally controlled I
Tuners in use.
2
C bus (PLL). Below you will find info on one of the
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF output
impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple
transient.
Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I
2
C-bus
4. Off-air channels, S-cable channels and Hyperband
5. World standardised mechanical dimensions and world standard pinning
6. Compact size
7. Complies to “CENELEC EN55020” and “EN55013”
Pinning:
1.Gain control voltage (AGC):4.0V, Max: 4.5V
2.Tuning voltage
3.I²C-bus address select:Max: 5.5V
4.I²C-bus serial clock:Min:-0.3V, Max: 5.5V
5.I²C-bus serial data:Min:-0.3V, Max: 5.5V
6.Not connected
7.PLL supply voltage:5.0V, Min: 4.75V, Max: 5.5V
8.ADC input
9.Tuner supply voltage:33V, Min: 30V, Max: 35V
10.Symmetrical IF output 1
11.Symmetrical IF output 2
6.IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL. The
following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:
VIF amplifier, Tuner and VIF-AGC, VIF -AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO and
divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF amplifier, SIF-AGC
TFT TV Service Manual
7
Page 12
detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition help, Audio amplifier and
mute time constant,
I²C-bus transceivers and MAD (module address), Internal voltage stabilizer.
7. MULTI STANDARD SOUND PROCESSOR
The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analogue TVStandards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analogue
sound IF signal-in, down to processed analogue AF-out, is performed on a single chip.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal
conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX
noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed
standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BT SC and EIA-J. The
MSP 34x1G has optimum stereo performance without any adjustments.
8. VIDEO SWITCH TEA6415
In case of three or more external sources are used, the video switch IC T EA6415 is used. The main function of this device is
to switch 8 video-input sources on the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level of the
signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain bet ween any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by
forcing, with an external resistor bridge, 5VDC on the input. E ach input can be used as a normal input or as a MAC or
Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm
load needs an exter nal resistor. It is possible to have the same input connected to several outputs.
9.AUDIO AMPLIFIER STAGE WITH TPA3004D2
The TPA3004D2 is a 12-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The
TPA3004D2 can drive stereo speakers as low as 4 7KHKLJKHIILFLHQF\RIWKH73$'HOLPLQDWHVWKHQHHGIRU
external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from –
40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range
ofgainfrom–56dBto20dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
TFT TV Service Manual
8
Page 13
10. POWER SUPPLY (SMPS)
The DC voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC
MC44608, which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer
generates 145V for FBT input, +/-14V for audio amplifier, 5V and 3.3V stand by voltage and 8V, 12V and 5V supplies for
other d ifferent parts of the chassis.
An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation
circuit i n secondary side. This circuit produces a control voltage according to the changes in 145V DC voltage, via an
optocoupler (TCET1102G) to pin3 of the IC.
During the switch on period of the transistor, energy is stored in the transformer. During the switch off period
energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls
each portion of energy transferred to the second side such that the output voltage remains nearly independent
of load variations.
11.MICROCONTROLLER
The Micronas SDA 55xx TV microcontroller is dedicated to 8 bit applications for TV control and provides dedicated
graphic features designed for modern low class to mid range TV sets. The SDA 55xx provides also an integrated
general purposefully 8051-compatible microcontroller with specific hardware features especially suitable in TV sets.
The microcontroller core has been enhanced to provide powerful features such as memory banking, data pointers and
additional interrupts, etc. The internal XRAM consists of up to 16 kBytes. The microcontroller provides an internal
ROM of up to 128 kBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The 8-bit
microcontroller runs at 33.33 MHz internal clock. SDA 55xx is realized in 0.25 micron technology with 2.5 V supply
voltage for the core and 3.3 V for the I/O port pins to make them TTL compatible. Based on the SDA 55xx
microcontroller the MINTS software package was developed and provides dedicated device drivers for many Micronas
video & audio products and includes a full blown TV control SW for the PEPER application chassis. The SDA 55xx is
also supported with powerful design tools like emulators from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler and
TEDIpro OSD development SW by Tara Systems.
12.SERIAL ACCESS CMOS 4Kx8(32KBit)EEPROM 24C32A
The Microchip Technology Inc. 24AA32A/24LC32A(24XX32A*) is a 32 Kbit Electrically Erasable PROM. The device is
organized as four blocks of 8K x 8-bitmemory with a 2-wire serial interface. Low-voltage design permits operation
down to 1.8V, with standby and active currents of only 1μA and 1mA, respectively. It has been developed for
advanced, low-power applications such as personal communications or data acquisition. The 24XX32A also has a
page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for
up to 256Kbits address space.
13.CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The
deviceisfabricatedina1mmCMOSprocessandhasbeenprimarilydevelopedforportabledigitalaudio
applications.
14.SAW FILTERS
K9656M:
Standard:
•B/G
• D/K
•I
• L/L’
Features
• TV IF audio filter with two channels
• Channel 1 (L’) with one pass band for sound carriers at 40.40 MHz (L’) and 39.75 MHz (L’- NICAM)
• Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32.35 MHz and 33.40 MHz
Terminals
• Tinned CuFe alloy
Pin configuration
1Input
2 Switching input
3 Chip carrier - ground
4Output
5Output
TFT TV Service Manual
9
Page 14
K3958M:
Standard:
•B/G
• D/K
•I
• L/L’
Features
• TV IF video filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only
one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for
CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or
Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 V
DC on the input. Each
input can be used as a normal input or as a MAC or Chroma input (with external resistor bridge). All the
switching possibilities are changed through the BUS. Driving 75ORDGQHHGVDQH[WHUQDOWUDQVLVWRU,WLVSRVVLEOH
TFT TV Service Manual
10
Page 15
to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0
to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other
case, 1 word of 16 bits is necessary to determine one configuration.
15.1.2.
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
15.1.3.
1.Input:Max: 2Vpp, Input Current: 1mA, Max: 3mA
2.Data:Low level: -0.3V Max: 1.5V,
3.Input:Max: 2Vpp, Input Current: 1mA,Max: 3mA
4.Clock:Low level: -0.3V Max: 1.5V,
5.Input:Max: 2Vpp, Input Current: 1mA, Max: 3mA
6.Input:Max: 2Vpp, Input Current: 1mA, Max: 3mA
7.Prog
8.Input:Max: 2Vpp, Input Current: 1mA, Max: 3mA
9.Vcc:12V
10.Input:Max: 2Vpp, Input Current: 1mA, Max: 3mA
11.Input:Max: 2Vpp, Input Current: 1mA, Max: 3mA
12.Ground
13.Output:5.5Vpp,Min : 4.5Vpp
14.Output:5.5Vpp,Min : 4.5Vpp
15.Output:5.5Vpp,Min : 4.5Vpp
16.Output:5.5Vpp,Min : 4.5Vpp
17.Output:5.5Vpp,Min : 4.5Vpp
18.Output:5.5Vpp,Min : 4.5Vpp
19.Ground
20.Input:Max : 2Vpp, Input Current: 1mA, Max: 3mA
Features
Pinning
High level: 3.0V Max: Vcc+0.5V
High level: 3.0V Max: Vcc+0.5V
TFT TV Service Manual
11
Page 16
15.2. 24LC02
15.2.1. Description
The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM. The device
is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low -voltage design permits
operation down to 1.8V, with standby and active currents of only 1μA and 1mA, respectively. The 24XX02 also
has a page write capability for up to 8 bytes of data.
15.2.2.
• Single supply with operation down to 1.8V
• Low-power CMOS technology
-1mA active current typical
-1μA standby current typical (I-temp)
• Organized as 1 block of 256 bytes (1 x 256 x 8)
• 2-wire serial interface bus, I
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes
• 2ms typical write cycle time for page write
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP and MSOP packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available for extended temperature ranges:
-Industrial (I): -40°C to +85°C
-Automotive (E): -40°C to +125°C
Features
2
C compatible
15.2.3.
Pinning
TFT TV Service Manual
12
Page 17
15.3. 24C32
15.3.1. General Description
The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. This device has
been developed for advanced, low power applications such as personal communications or data acquisition.
The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also
features a fixed 4K-bit block of ultra-high endurance memory for data that changes frequently. The 24C32 is
capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to 8 24C32 devices on the same bus, for up to 256K bits address space. Advanced CMOS technology makes this
device ideal for low-power non-volatile code and data applications.
15.3.2.
• Voltage operating range: 4.5V to 5.5V
- Peak write current 3 mA at 5.5V
- Maximum read current 150μA at 5.5V
- Standby current 1μA typical
• Industry standard two-wire bus protocol, I
-Including 100 kHz and 400 kHz modes
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
• Endurance:
-10,000,000 Erase/Write cycles guaranteed for High Endurance Block
-10,000,000 E/W cycles guaranteed for Standard Endurance Block
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to 8 chips may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• Temperature ranges:
-Commercial (C): 0°C to +70°C
-Industrial (I): -40°C to +85°C
15.3.3.
Features
Pinning
2
C compatible
TFT TV Service Manual
13
Page 18
15.3.4.
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
The A0...A2 inputs are used by the 24C32 for multiple device operation and conform to the two-wire bus standard. The levels applied to these pins define the address block occupied by the device in the address map. A
particular device is selected by transmitting the corresponding bits (A2, A1, and A0) in the control byte.
SDA Serial Address/Data Input/Outpu
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain
terminal; therefore the SDA bus requires a pull-up resistor to VCC (typical 10KQ for 100 kHz, 1KQ for 400 kHz).
For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
PIN Function Table
t
15.4. 74LVC14A
15.4.1. Description
The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This feature allows the use of
these devices as translators in a mixed 3.3 and 5V environment. The 74LVC14A provides six inverting buffers with
Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output
signals.
15.4.2. Features
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no.8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
• Specified from -40 to +85C and -40 to +125C.
15.4.3. Pinning
TFT TV Service Manual
14
Page 19
15.5. TEA6420
15.5.1. Features
• 5 Stereo Inputs
• 4 Stereo Outputs
• Gain Control 0/2/4/6dB/Mute for each Output
• Cascadable (2 different addresses)
• Serial Bus Controlled
•VerylowNoise
• Very low Distortion
15.5.2.
The TEA6420 switches 5 stereo audio inputs on4stereo outputs. All the switching possibilities are changed
through the I
15.5.3.
Description
2
C bus.
Pin Connections
15.6. CS4334
15.6.1. Features
• Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering
• 24-Bit Conversion
TFT TV Service Manual
15
Page 20
•
96 dB Dynamic Range
• -88 dB THD+N
• Low Clock Jitter Sensitivity
• Single +5V Power Supply
• Filtered Line Level Outputs
• On-Chip Digital De-emphasis
• Popgaurd® Technology
• Functionally Compatible with CS4330/31/33
15.6.2. General Description
The CS4334 family members are complete, stereo digital-to-analog output systems including interpolation, 1 bitD/A conversion and output analog filtering in an 8-pinpackage. The CS4334/5/6/7/8/9 support all major audio
data interface formats, and the individual devices differ only in the supported interface format. The CS4334
family is based on delta-sigma modulation, where the modulator output controls the reference voltage input to
an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2
kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital
de-emphasis, operates from a single +5V power supply, and requires minimal support circuitry. These features
are ideal for set-top boxes, DVD players, SVCD players, and A/V receivers.
15.6.3.
Pin Descriptions
15.7. GAL16LV8
15.7.1. Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available
in the PLD market. The GAL16LV8C can interface with both 3.3V and 5Vsignal levels. The GAL16LV8 is
manufactured using Lattice Semiconductor's advanced 3.3V E
Electrically Erasable (E
2
) floating gate technology. High speed erase times (<100ms) allow the devices to be
2
CMOS process, which combines CMOS with
reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all
architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during
manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all
GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
15.7.2.
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz
TFT TV Service Manual
16
Page 21
- 2.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- 5V Compatible Inputs
- I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
•E2CELLTECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
15.7.3.
Pin connections
15.8. K6R4008V1D
15.8.1. Description
The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by
8 bits. TheK6R4008V1D uses 8 common input and output lines and has an output enable pin which operates
faster than address access time at read cycle. The device is fabricated using SAMSUNG's advanced CMOS
process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-
speed system applications. The K6R4008V1D is packaged in a 400 mil 36-pin plastic SOJ and 44-pin plastic
TSOP type II.
15.8.2.
• Fast Access Time 8, 10ns(Max.)
• Low Power Dissipation
- Standby (TTL) : 20mA(Max.)
- Operating K6R4008V1D-08 : 80mA(Max.)
TFT TV Service Manual
Features
(CMOS) : 5mA(Max.)
17
Page 22
K6R4008V1D-10 : 65mA(Max.)
• Single 3.3 ±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4008V1D-J : 36-SOJ-400
The KA278R33 is a low-dropout voltage regulator suitable for various electronic equipments. It provides
constant voltage power source with TO-220 4 lead full mold package. Dropout voltage of KA278R33 is below
TFT TV Service Manual
Description
18
Page 23
0.5V in full rated current (2A). This regulator has various function such as peak current protection, thermal shut
down, overvoltage protection and output disable function.
15.10.LM1117
15.10.1. General Description
The LM1117 is a series of low dropout voltage regulators with a dropout o f 1.2V at 800mA of load current. It has the same
pin-out as Natio nal Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which
can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed
voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5 V.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT-223, TO-
220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to improve
the transient response and stability.
15.10.2.
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
15.10.3.
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation
Connection Diagrams
Features
Applications
15.11.LM317
15.11.1. General Description
This monolithic integrated circuit is an adjustable 3-terminal positive voltage regulator designed to supply more
than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V. It employs internal current limiting,
thermal shut-down and safe area compensation.
15.11.2.
• Output Current In Excess of 1.5A
• Output Adjustable Between 1.2V and 37V
• Internal Thermal Overload Protection
• Internal Short Circuit Current Limiting
• Output Transistor Safe Operating Area Compensation
• TO-220 Package
TFT TV Service Manual
Features
19
Page 24
15.11.3.
Pin Description
15.12.LM809
15.12.1. General Description
The LM809/810 microprocessor supervisory circuits can be used to monitor the power supplies in microprocessor and
digital systems. They provide a reset to the microprocessor during power-up, power-down and brown-out conditions.
The function of the LM809/810 is to monitor the VCC supply voltage, and assert a reset signal whenever this voltage
declines below the factory-programmed reset threshold. The reset signal remains asserted for 240 ms after VCC rises
above the threshold. The LM809 has an active- low RESET output, while the LM810 has an active-high RESET output.
Seven standard reset voltage options are available, suitable for monitoring 5V, 3.3V, and 3V supply voltages. With a
low supply current of only 15μA, the LM809/810 are ideal for use in portable equipment.
15.12.2. Features
• Precise monitoring of 3V, 3.3V, and 5V supply voltages
• Superior upgrade to MAX809/810
• Fully specified overtemperature
• 140 ms min. Power-On Reset pulse width, 240 ms typical
The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all
analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure
shows a simplified functional block diagram of the MSP 34x1G.
The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature.
Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G includes the
Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby 1) Laboratories for with
the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the “PAN-ORAMA” algorithm.
These TV sound processing ICs include versions for processing the multichannel television sound ( MTS) signal conforming
to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or
alternatively, Micronas Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA- J) and the FM Stereo Radio
standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and
EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated
internally with subsequent switching between mono/stereo/bilingual; no I 2 C interaction is necessary (Automatic
Sound Selection).
Source Select
2
I
S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32
kHz) are transmitted.
2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.
3. I2S_CL: Gives the timing for the transmission of I
2
S serial data (1.024 MHz).
4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.
15.13.2.
Features
• Standard Selection with single I2C transmission
• Automatic Standard Detection of terrestrial TV standards
• Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS
• Two selectable sound IF (SIF) inputs
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
2558476750ANA_IN1+INLVIF input 1
2657466649AVSUPOBLAnalog power supply 5V
---65-AVSUPOBLAnalog power supply 5V
---64-NCLVNot connected
---63-NCLVNot connected
2756456248AVSSOBLAnalog ground
---61-AVSSOBLAnalog ground
2855446047MONO_ININLVMono input
---59-NCLVNot connected
2954435846VREFTOPOBL
3053425745SC1_IN_RINLVSCART 1 input, right
3152415644SC1_IN_LINLVSCART 1 input, left
3251-5543ASG1AHVSSAnalog Shield Ground 1
3350405442SC2_IN_RINLVSCART 2 input, right
3449395341SC2_IN_LINLVSCART 2 input, left
3548-5240ASG2AHVSSAnalog Shield Ground 2
3647385139SC3_IN_RINLVSCART 3 input, right
PSDIP
64-pin
PSDIP
52-pin
PQFP
80-pin
PLQFP
64-pin
Connection
(if not used)
AVSS via
56 pF/LV
AVSS via
56 pF/LV
Short Description
2
S word strobe
Audio clock output
(18.432 MHz)
IF Input 2 (can be left
vacant, only if IF input 1 is
also not in use)
IFcommon(canbeleft
vacant, only if IF input 1 is
also not in use)
Reference voltage IF A/D
converter
TFT TV Service Manual
22
Page 27
3746375038SC3_IN_LINLVSCART 3 input, left
3845-4937ASG4AHVSSAnalog Shield Ground 4
3944-4836SC4_IN_RINLVSCART 4 input, right
4043-4735SC4_IN_LINLVSCART 4 input, left
41--46-NCLV or AHVSSNot connected
4242364534AGNDCOBLAnalog reference voltage
4341354433AHVSSOBLAnalog ground
---43-AHVSSOBLAnalog ground
---42-NCLVNot connected
---41-NCLVNot connected
4440344032CAPL_MOBLVolume capacitor MAIN
4539333931AHVSUPOBLAnalog power supply 8V
4638323830CAPL_AOBLVolume capacitor AUX
4737313729SC1_OUT_LOUTLVSCART output 1, left
4836303628SC1_OUT_ROUTLVSCART output 1, right
4935293527VREF1OBLReference ground 1
5034283426SC2_OUT_LOUTLVSCART output 2, left
5133273325SC2_OUT_ROUTLVSCART output 2, right
52--32-NCLVNot connected
5332-3124NCLVNot connected
5431263023DACM_SUBOUTLVSubwoofer output
5530-2922NCLVNot connected
5629252821DACM_LOUTLVLoudspeaker out, left
5728242720DACM_ROUTLVLoudspeaker out, right
5827232619VREF2OBLReference ground 2
5926222518DACA_LOUTLVHeadphone out, left
6025212417DACA_ROUTLVHeadphone out, right
The M29W040B is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations
can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or EPROM. The M29W040B is fully backward compatible with the
M29W040.The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while
old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from
modifying the memory. Program and Erase commands are writ-ten to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the p rocess of programming or erasing the memory by taki ng care of all of the special
operations that are required to update the memory contents. The end of a program or erase operation can be detected and
any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip
Enable, Output Enable and Write Enable signals control the bus operation o f the memory. They allow simple connection to
most microprocessors, often without additional logic.
15.14.2.
• SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS
• ACCESS TIME: 55ns
• PROGRAMMING TIME
- 10μs per Byte typical8
• UNIFORM 64 Kbytes MEMORY BLOCKS
• PROGRAM/ERASE CONTROLLER
- Embedded Byte Program algorithm
- Embedded Multi-Block/Chip Erase algorithm
- Status Register Polling and Toggle Bits
Features
TFT TV Service Manual
23
Page 28
• ERASE SUSPEND and RESUME MODES
- Read and Program another Block during Erase Suspend
• UNLOCK BYPASS PROGRAM COMMAND
- Faster Production/Batch Programming
• LOW POWER CONSUMPTION
- Standby and Automatic Standby
• 100,000 PROGRAM/ERASE CYCLES per BLOCK
• 20 YEARS DATA RETENTION
- Defectivity below 1 ppm/year
• ELECTRONIC SIGNATURE
- Manufacturer Code: 20h
- Device Code: E3h
15.14.3.
Pin Descriptions
15.15.MC33202
15.15.1. General Description
The MC33201/2/4 family of operational amplifiers provide railítoírail operation on both the input and output.
The inputs can be driven as high as 200mV beyond the supply rails without phase reversal on the outputs, and
the output can swing within 50 mV of each rail. This railítoírail operation enables the user to make full use of
the supply voltage range available. It is designed to work at very low supply voltages (±0.9 V) yet can operate
with a supply of up to +12V and ground. Output current boosting techniques provide a high output current
capability while keeping the drain current of the amplifier to a minimum. Also, the combination of low noise and
distortion with a high slew rate and drive capability make this an ideal amplifier for audio applications.
15.15.2.
• Low Voltage, Single Supply Operation (+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Overídriven Input Signals
• High Output Current (ISC = 80 mA, Typ)
• Low Supply Current (ID = 0.9 mA, Typ)
• 600 Output Drive Capability
• Extended Operating Temperature Ranges (í40° to +105°C and í55° to +125°C)
• Typical Gain Bandwidth Product = 2.2 MHz
•PbíFree Packages are Available
TFT TV Service Manual
Features
24
Page 29
15.15.3.
Pin Connections
15.16.PCF8574
15.16.1. General Description
The P CF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I
interface. T he PCF8574 has a low current consumption and includes latched outputs with high current drive capabilit y for
directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the
microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is
incoming data on its ports without having to communicate via the I
simple slave device.
2
C).The device consists of an 8-bit quasi-bidirectional port and an I2C-bus
2
C-bus. T his means that the PCF8574 can remain a
15.16.2.
Features
• Operating supply voltage 2.5 to 6V
• Low standby current consumption of 10 μA maximum
2
•I
C to parallel port expander
• Open-drain interrupt output
• 8-bit remote I/O port for the I
2
C-bus
• Compatible with most microcontrollers
• Latched outputs with high current drive capability for directly driving LEDs
• Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)
• DIP16, or space-saving SO16 or SSOP20 packages.
15.16.3.
Pinning
TFT TV Service Manual
25
Page 30
15.17.TSOP1836
15.17.1. Description
The TSOP18.– series are miniaturized receivers for infrared remote control systems. PIN diode and preamplifier
are assembled on lead frame, the epoxy package is designed as IR filter. Carrier frequency for TSOP1836 is 36
kHz.
The demodulated output signal can directly be decoded by a microprocessor. The main benefit is the reliable
function even in disturbed ambient and the protection against uncontrolled output pulses.
15.17.2.
• Photo detector and preamplifier in one package
• Internal filter for PCM frequency
• TTL and CMOS compatibility
• Output active low
• Improved shielding against electrical field disturbance
• Suitable burst length .6 cycles/burst
Special Features
• Small size package
• Enhanced immunity against all kinds of disturbance light
• No occurrence of disturbance pulses at the output
• Short settling time after power on (<200_s)
Features
15.18.PI5V330
15.18.1. General Description
The PI5V330 is well suited for video applications when switching composite or RGB analogue. A picture-inpicture application will be described in this brief. The pixel-rate creates video overlays so two or more pictures
can be viewed at the same time. An inexpensive NTSC titler can be implemented by superimposing the output
of a character generator on a standard composite video background.
TFT TV Service Manual
26
Page 31
15.19.SDA55XX (SDA5550)
15.19.1. General description
The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video
Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for
PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and decoding. The
device provides an integrated general-purpose, fully 8051-compatible Microcontroller with television specific
hardware features. Microcontroller has been enhanced to provide powerful features such as memory banking,
data pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can
also be used for customer defined on screen displays. Internal XRAM consists of up to16 Kbytes. Device has an
internal ROM of up to 128 KBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The
SDA 55XX supports a wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS,
PDC, TTX and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5
TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented characters
(DRCS).
The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does most of the
internal TTX acquisition processing, transfers data to/from external memory interface and receives/ transmits
data via I
buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition tasks (hamming and parity-checks,
page search and evaluation of header control bits) once per field. Additionally, the firmware can provide highend Teletext features like Packet-26-handling, FLOF, TOP and list-pages. The interface to user software is
optimized for minimal overhead. SDA 55XX is realized in 0.25 micron technology with 2.5 V supply voltage and
3.3 V I/O (TTL compatible). The software and hardware development environment (TEAM) is available to
simplify and speed up the development of the software and On Screen Display. TEAM stands for TVT Expert
Application Maker. It improves the TV controller software quality in following aspects:
– Shorter time to market
– Re-usability
– Target independent development
– Verification and validation before targeting
– General test concept
– Graphical interface design requiring minimum programming and controller know how.
– Modular and open tool chain, configurable by customer.
2
C-firmware user-interface. The slicer combined with dedicated hardware stores TTX data in a VBI
15.20.SIL 9993
15.20.1. General Description
The SiI 9993 is the first generation of PanelLink receivers that are designed for the HDMI 1.0 (High Definition Multimedia
Interface) specification. DTVs, plasma displa ys, LCD TVs and projectors can now provide the purest level of protected
digital audio/video over a simple, low cost cable. Backwards compatibility with DVI 1.0 allows HDMI systems to connect
to any DVI 1.0 host (DVD players, HD set top boxes, D-VHS players and receivers, PC). The SiI 9993 incorporates a
flexible audio and video interface. The receiver can connect to RGB input and output YCbCr using an integrated color
space converter. This allows full backward compatibility to DVI, and interfaces to all major video processors. A S/PDIF
port can output PCM encoded data as well as Dolby Digital, DTS and all other formats capable of being sent over S/PDIF.
A 2-channel I2S port outputs data converted from S/PDIF. The SiI 9993 comes pre -programmed with HDCP keys, greatly
simplifying the manufacturing process, lowering costs, all the while providing the highest level of HDCP key security.
Silicon Image’s PanelLink receivers use the latest generation of PanelLink TMDS core technology. These PanelLink cores
• Digital video interface supports video processors:
o 24-bit RGB 4:4:4
o 24-bit YCbCr 4:4:4
o 16/20/24-bit YCbCr 4:2:2
o 8/10/12-bit YCbCr 4:2:2 embedded syncs
• Analog RGB and YPbPr output:
o10-bitDAC
o Separate or Composite Syncs (Sync on G)
Features
TFT TV Service Manual
27
Page 32
• S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-48kHz Fs) using IEC 60958
and IEC 61937.
• Programmable I
2
S interface for connection to low-cost audio DACs.
• Integrated HDCP decryption engine for receiving protected audio and video content
• Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing
• Programmable registers via slave I
2
C interface
• 3.3V operation in 100-pin TQFP package
• Flexible power management
15.21.SN74CB3Q3305
15.21.1. General Description
The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (r
allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The
device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data
bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
). The low and flat ON-state resistance
on
15.21.2.
Features
• High-Bandwidth Data Path (Up To 500 MHz)
• 5-V Tolerant I/Os with Device Powered-Up or Powered-Down
• Low and Flat ON-State Resistance (r
) Characteristics Over Operating Range (ron=37\SLFDO
on
• Rail-to-Rail Switching on Data I/O Ports
í 0- to 5-V Switching With 3.3-V VCC
í 0- to 3.3-V Switching With 2.5-V VCC
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (C
• Fast Switching Frequency (f
= 20 MHz Max)
OE
=3.5pFTypical)
io(OFF)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• Low Power Consumption (ICC = 0.25 mA Typical)
• VCC Operating Range From 2.3 V to 3.6 V
• Data I/Os Support 0 to 5-V Signaling Levels (0.8- V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
• Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
•I
Supports Partial-Power-Down Mode Operation
off
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
• ESD Performance Tested Per JESD 22
í 2000-V Human-Body Model (A114-B, Class II)
í 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-
Distortion Signal Gating
15.21.3.
Pin Connections
15.22.ST24LC21
15.22.1. Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This
device can operate in two modes: Transmit Only mode and I
in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The
devicewillswitchtotheI
2
C bidirectional mode upon the falling edge of the signal applied on SCL pin. The
TFT TV Service Manual
2
C bidirectional mode. When powered, the device is
28
Page 33
ST24LC21 can not switch from the I
2
C bidirectional mode to the Transmit Only mode (except when the power
supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line
and Plastic Small Outline packages are available.
15.22.2.
Features
• 1 million Erase/Write cycles
• 40 years data retention
• 2.5V to 5.5V single supply voltage
• 400k Hz compatibility over the full range of supply voltage
• Two wire serial interface I
2
C bus compatible
• Page Write (Up To 8 Bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
• Automatic address incrementing
• Enhanced ESD/Latch up
• Performances
15.22.3.
Pin connections
DIP Pin connectionsCO Pin connections
NC: Not connected
Signal names
SDASerial data Address Input/Output
SCLSerial Clock (I2C mode)
VccSupply voltage
V
ss
VCLKClock transmit only mode
Ground
15.23.LM2576
15.23.1. General Description
The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step–
down switching regulator (buck converter). All circuits of this series are capable of driving a 3.0 A load with excellent line
and load regulation.
These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output
version. These regulators were designed to minimize the number of external components to simplify the power
supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different
inductor manufacturers.
Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in comparison
with popular three–terminal linear regulators, especially with higher input voltages. In many cases, the power
dissipated is so low that no heatsink is required or its size could be reduced dramatically.
A standard series of inductors optimized for use with the LM2576 are available from several different
manufacturers. This feature greatly simplifies the design of switch–mode power supplies.
The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input voltages and
output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is
included, featuring 80 mA (typical) standby current. The output switch includes cycle–by–cycle current limiting,
as well as thermal shutdown for full protection under fault conditions.
• Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line and Load Conditions
• Guaranteed 3.0 A Output Current
• Wide Input Voltage Range
• Requires Only 4 External Components
• 52 kHz Fixed Frequency Internal Oscillator
• TTL Shutdown Capability, Low Power Standby Mode
• High Efficiency
• Uses Readily Available Standard Inductors
• Thermal Shutdown and Current Limit Protection
• Moisture Sensitivity Level (MSL) Equals 1
15.23.3.
Pin description
15.24.MC34063
15.24.1. Description
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to–DC converters.
These devices consist of a n int ernal te mperature co mpensated reference, comparator, controlled duty cycle oscillator with
an active current limit circuit, driver and high current output switch. This series was specifically designed to be
incorporated in Step–Down and Step–Up an d Voltage–Inverting applications with a minimum number of external
components.
15.24.2.
• Operation from 3.0 V to 40 V Input
• Low Standby Current
• Current Limiting
• Output Switch Current to 1.5 A
• Output Voltage Adjustable
• Frequency Operation to 100 kHz
• Precision 2% Reference
Features
15.24.3.
TFT TV Service Manual
Pin connections
30
Page 35
15.25.TDA1308
15.25.1. General Description
The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic
package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable
digital audio applications.
15.25.2.
Features
• Wide temperature range
• No switch ON/OFF clicks
• Excellent power supply ripple rejection
• Low power consumption
• Short-circuit resistant
• High performance
• high signal-to- noise ratio
• High slew rate
• Low distortion
• Large output voltage swing.
15.25.3. Pinning
SYMBOLPINDESCRIPTIONPIN VALUE
OUTA1Output A (Voltage swing)Min : 0.75V, Max : 4.25V
INA(neg)2Inverting input AVo(clip) : Min : 1400mVrms
INA(pos)3Non-inverting input A2.5V
V
SS
INB(pos)5Non-inverting input B2.5V
INB(neg)6Inverting input BVo(clip) : Min : 1400mVrms
OUTB7Output B (Voltage swing)Min : 0.75V, Max : 4.25V
V
DD
4Negative supply0V
8Positive supply5V, Min : 3.0V, Max : 7.0V
15.26.TDA9886
15.26.1. General Description
The TDA9886 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL.
15.26.2.
• 5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good
The TPA3004D2 is a 12-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The
TPA3004D2 can drive stereo speakers as low as 4 7KHKLJKHIILFLHQF\RIWKH73$'HOLPLQDWHVWKHQHHGIRU
external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from –
40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range
ofgainfrom–56dBto20dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.
15.27.2.
• 12-W/Ch Into an 8-/RDG)URP -V Supply
• Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements
• 32-Step DC Volume Control From í40 dB to 36 dB
• Line Outputs For External Headphone Amplifier With Volume Control
• Regulated 5-V Supply Output for Powering TPA6110A2
• Space-Saving, Thermally-Enhanced PowerPAD
• Thermal and Short-Circuit Protection.
Features
TM
Packaging
TFT TV Service Manual
32
Page 37
15.27.3.
Pinning
TFT TV Service Manual
33
Page 38
15.28.
15.29.μPA672T
15.29.1. General Description
The μPA672T is a super-mini-mold device provided with two MOS FET elements. It achieves high-density
mounting and saves mounting costs.
TFT TV Service Manual
34
Page 39
15.29.2.
Features
• Two MOS FET circuits in package the same size as SC-70
• Automatic mounting supported
15.29.3. Pin Connection
15.30.VPC3230D
15.30.1. General Description
The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and
100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x)
and/or it can be used with 3rd-party products.
The main features of the VPC 323xD are
66VRTOUTPUTXReference Voltage Top, Analog
67I2CSELINXI2C Bus Address Select
68ISGNDSUPPLYAXSignal Ground for Analog Input, connect to GND
69V
SUPF
SUPPLYAXSupply Voltage, Analog Front-End
F
70VOUTOUTLVAnalog Video Output
71CININLVChroma/Analog Video 5 Input
72VIN1INVRTVideo 1 Analog Input
73VIN2INVRTVideo 2 Analog Input
74VIN3INVRTVideo 3 Analog Input
75VIN4INVRTVideo 4 Analog Input
TFT TV Service Manual
36
Page 41
76V
77GND
78VREFOUTPUTXReference Voltage Top, Analog Component Inputs
79FB1ININVREFFast Blank Input
80AISGNDSUPPLYAXSignal Ground for Analog Component Inputs, connect
SUPAI
AI
SUPPLYAXSupply Voltage, Analog Component Inputs Front-End
SUPPLYAXGround, Analog Component Inputs Front-End
Front-End
to GND
AI
15.31.MAD4868A
15.31.1. General Description
The Micronas Audio Delay IC MAD 4868A acts as a delay line for TV audio and consumer audio applications.
The IC is designed for synchronizing audio and video signals ensuring "Lip Sync" by delaying the audio signal
with the same amount of time as the video signal is delayed in a TV's video processing.
For TV designs, independent signals for loudspeakers, headphones, and line-out or S/PDIF out must be provided, resulting in the need to delay six independent audio channels.
15.31.2.
Features
x32 k audio samples RAM:
xTotal delay time of 680 ms at 48 kHz or 1020 ms at 32 kHz sampling rate
-32/18-bit word width:
x32-bit High-Resolution mode or 18-bit Standard mode
xSampling rates from 32 kHz to 48 kHz for
serial 8-channel mode are supported
xSampling rates from 4 kHz to 192 kHz for
parallel 2-channel mode are supported
xMemory allocation:
xMAD 4868A's memory can be allocated for 1... 8 audio channels. Delay time can be programmed for
each channel individually.
15.31.3.
Interfaces
x8-channel Micronas I2S input and output:
xIn combination with Micronas ICs (serial mode) (e.g. MSP 44/46xyK, MAS 35xyH), eight audio channels
can be routed through MAD 4868A by using four lines only.
x4x2-channel standard I
2
S inputs and outputs (paral
lel mode) allow routing eight audio channels with
sampling rates of 4... 192 kHz through MAD 4868A
2
xI
C control for delay time programming
xAddress select to set one out of two available I
2
C addresses.
TFT TV Service Manual
37
Page 42
15.31.4.
Pinning
15.32.SVP-EX 59B
General Description
To improve the video quality of the PAL CVBS and HD video input, the all layer changed EX59 improve video sharpness
function in HD channel and enhance the 3D PAL quality compared to EX52 Rev. D chips.
16.SERVICE MENU SETTINGS
To enter the service menu, first enter the MENU by pressing “” button and then press the digits 4, 7, 2 and 5
respectively.
TFT TV Service Manual
38
Page 43
Service Menu Items
16.1. Picture Adjust
xSource=> All possible sources given with the chasis as a list.
xMode=> Three items as a list; NATURAL, DYNAMIC, CINEMA
xColour Temp=> Three items as a list; COOL, NORMAL, WARM
xContrast=> Slider Bar. Changing value between 0 to 63.
xBrightness=> Slider Bar. Changing value between 0 to 63.
xSharpness=> Slider Bar. Changing value between 0 to 16.
xColour=> Slider Bar. Changing value between 0 to 99.
xR=> Slider Bar. Changing value between 0 to 100.
xG=> Slider Bar. Changing value between 0 to 100.
xB=> Slider Bar. Changing value between 0 to 100.
In this menu preset values for each Mode (Contrast, Brightness, Sharpness, Colour values for each ModeNATURAL, DYNAMIC, CINEMA) and for each Colour Temp. (R, G, B values for each Colour Temp- COOL,
NORMAL, WARM) are determined for each source.
16.2. SOUND1
xMenu Subwoofer=> If ON, Subwoofer option is available in TV set, and the item is visible
in sound menu, else Subwoofer is not available.
xSubwoofer Level (dB)=> This value is gain value of Subwoofer output in dB. - 30...12
xSubwoofer Corner Freq. (x10Hz) => Last low frequency value that is amplified. 5...40
xMenu Dolby Prologic=> No functionality now.
xMenu Equalizer=> If ON, visible in sound menu, else invisible.
xMenu Lineout=> No functionality now.
xMenu Headphone=> If ON, visible in sound menu, else invisible.
xMenu Hyper Sound=> If ON, visible in sound menu, else invisible.
xMenu Wide Sound=> If ON, visible in sound menu, else invisible.
xMenu Dynamic Bass=> If ON, visible in sound menu, else invisible.
xMenu Virtual Dolby=> If ON, visible in sound menu, else invisible.
xCarrier Mute=> If ON, in the absence of an FM carrier the output is muted, else not.
xVirtual Dolby Text=> Active if VIRTUAL DOLBY is ON. According to the selection; seen in
sound menu as 3D PANORAMA or VIRTUAL DOLBY.
16.3. SOUND 2
xAVL=> AVL is controlled from this menu by service user. ON/OFF
xMenu AVL=> If ON, AVL item is visible in sound menu, and AVL can be controlled from
sound menu by normal user, else AVL is invisible to normal user.
xFM PRESCALE AVL ON=> If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127
xNICAM PRESCALE AVL ON=> If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127
xSCART PRESCALE AVL ON=> If AVL ON, set value in this item is used as prescale value
for scart outputs. 0...127
xSCART VOLUME AVL ON=> If AVL ON, set value in this item is used as volume value for
scart1 and scart2. 0...127
xFM PRESCALE AVL OFF=> If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127
xNICAM PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127
xSCART PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale value
for scart outputs. 0...127
xSCART VOLOUME AVL OFF=> If AVL OFF, set value in this item is used as volume value for
scart1 and scart2. 0...127
16.4. Options
xScreen Saver=>
xFIRST APS=> If ON, first APS menu is opened when the TV opened with the
factory default settings.
TFT TV Service Manual
39
Page 44
xAPS VOLUME=> After First APS function finishes, the volume of the TV is that value.
xAGC=> Tuner AGC value.
xFactory Reset=> OK to activate. When OK pressed on this item, factory defaults
loaded.
xEnter Flash Mode=>
TV Norm
xBG=> If ON, supported, else not supported
xDK=> If ON, supported, else not supported.
xI=> If ON, supported, else not supported.
xL=> If ON, supported, else not supported.
xLP=> If ON, supported, else not supported.
xM=> If ON, supported, else not supported.
Features
xPIP/PAP=> If ON, PIP/PAP available else not.
xBlue Background=> If ON, Blue Background is visible in Features Menu else not.
xMenu Transparency=> If ON, Menu Transparency is visible in Features Menu else not.
xMenu Timeout=> If ON, Menu Timeout is visible in Features Menu else not.
xBacklight=> If ON, Backlight is visible in Features Menu else not.
xSingle Tuner=>
Teletext
xTeletext Language=> Teletext Language may be controlled from this menu by service
user.
xMenu Teletext Language => If ON, Teletext Language item is visible in Features Menu, and
Teletext Language can be controlled from Features Menu by normal user, else Teletext Language is
invisible to normal user.
This menu is related with the options of the chassis. These items may be ON or OFF. If ON, the source is
available in TV set, and the item is visible in source menu, else the source may be available but invisible to user.