HIT HN58V65AFP-10, HN58V65AP-10, HN58V65AT-10, HN58V66AFP-10, HN58V66AP-10 Datasheet

HN58V65A Series
HN58V66A Series

64 k EEPROM (8-kword × 8-bit)

Ready/Busy function, RES function (HN58V66A)

ADE-203-539B (Z)

Rev. 2.0

Nov. 1997

Description

The Hitachi HN58V65A series and HN58V66A series are a electrically erasable and programmable
EEPROM’s organized as 8192-word × 8-bit. They have realized high speed, low power consumption
and high relisbility by employing advanced MNOS memory technology and CMOS process and
circuitry technology. They also have a 64-byte page programming function to make their write
operations faster.

Features

• Single supply: 2.7 to 5.5 V

• Access time:
 100 ns (max) at 2.7 V ≤ VCC < 4.5 V
 70 ns (max) at 4.5 V ≤ VCC ≤ 5.5 V

• Power dissipation:
 Active: 20 mW/MHz (typ)
 Standby: 110 µW (max)

• On-chip latches: address, data, CE, OE, WE

• Automatic byte write: 10 ms (max)

• Automatic page write (64 bytes): 10 ms (max)

• Ready/Busy

• Data polling and Toggle bit

• Data protection circuit on power on/off

• Conforms to JEDEC byte-wide standard

• Reliable CMOS with MNOS cell technology

HN58V65A Series, HN58V66A Series

Features (cont)

• 105 erase/write cycles (in page mode)

• 10 years data retention

• Software data protection

• Write protection by RES pin (only the HN58V66A series)

• Industrial versions (Temperatur range: –20 to 85˚C and –40 to 85˚C) are also available.

Ordering Information

Access time

Type No. 2.7 V ≤ V

HN58V65AP-10 100 ns 70 ns 600 mil 28-pin plastic DIP (DP-28)
HN58V66AP-10 100 ns 70 ns
HN58V65AFP-10 100 ns 70 ns 400 mil 28-pin plastic SOP (FP-28D)
HN58V66AFP-10 100 ns 70 ns
HN58V65AT-10 100 ns 70 ns 28-pin plastic TSOP(TFP-28DB)
HN58V66AT-10 100 ns 70 ns

< 4.5 V 4.5 V ≤ VCC ≤ 5.5 V Package

CC

Pin Arrangement

HN58V65AP Series

HN58V65AFP Series

RDY/Busy

A12
A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14

(Top view)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

WE

NC
A8
A9
A11

OE

A10

CE

I/O7
I/O6
I/O5
I/O4
I/O3

RDY/Busy

A12
A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

V

SS

HN58V66AP Series

HN58V66AFP Series

1
2
3
4
5
6
7
8
9
10
11
12
13
14

(Top view)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

WE
RES

A8
A9
A11

OE

A10

CE

I/O7
I/O6
I/O5
I/O4
I/O3

Pin Arrangement (cont)

SS

SS

15
16
17
18
19
20
21
22
23
24
25
26
27
28

15
16
17
18
19
20
21
22
23
24
25
26
27
28

A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10

A2
A1
A0
I/O0
I/O1
I/O2
V
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10

HN58V65A Series, HN58V66A Series

HN58V65AT Series

(Top view)

HN58V66AT Series

(Top view)

14
13
12
11
10
9
8
7
6
5
4
3
2
1

14
13
12
11
10
9
8
7
6
5
4
3
2
1

A3
A4
A5
A6
A7
A12
RDY/Busy
V

CC

WE

NC
A8
A9
A11

OE

A3
A4
A5
A6
A7
A12
RDY/Busy
V

CC

WE
RES

A8
A9
A11

OE

HN58V65A Series, HN58V66A Series

Pin Description

Pin name Function

A0 to A12 Address input
I/O0 to I/O7 Data input/output

OE Output enable
CE Chip enable
WE Write enable

V

CC

V

SS

RDY/Busy Ready busy

1

RES*
NC No connection

Notes: 1. This function is supported by only the HN58V66A series.

Block Diagram

Power supply
Ground

Reset

Notes: This function is supported by only the HN58V66A series.

V

CC

V

SS

RES

OE

CE
WE

RES

A0

to

A5

A6

to

A12

1

*

1

*

High voltage generator

Control logic and timing

Address
buffer and
latch

Y decoder

X decoder

to

I/O0 I/O7

I/O buffer
and
input latch

Y gating

Memory array

RDY/Busy

Data latch

Operation Table

HN58V65A Series, HN58V66A Series

VH*

V
V

3

1

H

H

RDY/Busy I/O

High-Z Dout

High-Z to V

Din

OL

High-Z High-Z

× ——

V

H

IL

V

OL

Dout (I/O7)

High-Z High-Z

Operation CE OE WE RES*

Read V
Standby V
Write V
Deselect V

IL

IH

IL

IL

V
×*
V
V

IL

2

IH

IH

Write Inhibit ××V

Data Polling V

× V

IL

IL

V

IL

V

IH

×× High-Z High-Z
V

IL

V

IH

IH

×× ——
V

IH

Program reset ×××V
Notes: 1. Refer to the recommended DC operating conditions.

2. × : Don’t care

3. This function supported by only the HN58V66A series.

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage relative to V
Input voltage relative to V
Operating temperature range *

SS

2

SS

V

CC

Vin –0.5*1 to +7.0*
Topr 0 to +70 ˚C

Storage temperature range Tstg –55 to +125 ˚C
Notes: 1. Vin min : –3.0 V for pulse width ≤ 50 ns.

2. Including electrical characteristics and data retention.

3. Should not exceed V

+ 1 V.

CC

–0.6 to +7.0 V

3

V

HN58V65A Series, HN58V66A Series

Recommended DC Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input voltage V

V

V
VH*

CC

SS

IL

IH

4

Operating temperature Topr 0 — 70 ˚C
Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.

2. V

= 2.2 V for VCC = 3.6 to 5.5 V.

IH

3. V

max: VCC + 1.0 V for pulse width ≤ 50 ns.

IH

4. This function is supported by only the HN58V66A series.

5. V

= 0.8 V for VCC = 3.6 V to 5.5 V

IL

DC Characteristics (Ta = 0 to + 70˚C, VCC = 2.7 to 5.5 V)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current I
Output leakage current I
Standby VCC curren I

Operating VCC current I

Output low voltage V
Output high voltage V

LI

LO

CC1

I

CC2

CC3

OL

OH

Note: 1. ILI on RES : 100 µA max (only the HN58V66A series)

——2*1µA Vin = 0 V to V
——2µA Vout = 0 V to V
— 1 to 2 5 µA CE = VCC – 0.3 V to VCC + 1.0 V
——1mACE = V
— — 6 mA Iout = 0 mA, Duty = 100%,

— — 8 mA Iout = 0 mA, Duty = 100%,

— — 12 mA Iout = 0 mA, Duty = 100%,

— — 25 mA Iout = 0 mA, Duty = 100%,

— — 0.4 V IOL = 2.1 mA
VCC × 0.8 — — V IOH = –400 µA

2.7 — 5.5 V
000V
–0.3*

1.9*

1

— 0.6*

2

—V

5

+ 0.3*3V

CC

V

VCC – 0.5 — VCC + 1.0 V

CC

CC

IH

Cycle = 1 µs at V

Cycle = 1 µs at V

Cycle = 100 ns at V

Cycle = 70 ns at V

= 3.6 V

CC

= 5.5 V

CC

CC

= 5.5 V

CC

= 3.6 V

Capacitance (Ta = 25˚C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance Cin*
Output capacitance Cout*

1

1

Note: 1. This parameter is sampled and not 100% tested.

— — 6 pF Vin = 0 V
— — 12 pF Vout = 0 V

HN58V65A Series, HN58V66A Series

AC Characteristics (Ta = 0 to + 70˚C, VCC = 2.7 to 5.5 V)

Test Conditions

• Input pulse levels : 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V)

0 V to VCC (RES pin*2)

• Input rise and fall time : ≤ 5 ns

• Input timing reference levels : 0.8, 1.8 V

• Output load : 1TTL Gate +100 pF

• Output reference levels : 1.5 V, 1.5 V

Read Cycle 1 (VCC = 2.7 to 4.5 V)

HN58V65A/HN58V66A

-10

Parameter Symbol Min Max Unit Test conditions

Address to output delay t

CE to output delay t
OE to output delay t

Address to output hold t

OE (CE) high to output float*1t
RES low to output float*
RES to output delay*

1, 2

2

ACC

CE

OE

OH

DF

t

DFR

t

RR

— 100 ns CE = OE = VIL, WE = V
— 100 ns OE = VIL, WE = V
10 50 ns CE = VIL, WE = V
0—nsCE = OE = VIL, WE = V
040nsCE = VIL, WE = V
0 350 ns CE = OE = VIL, WE = V
0 450 ns CE = OE= VIL, WE = V

IH

IH

IH

IH

IH

IH

IH

HN58V65A Series, HN58V66A Series

Write Cycle 1 (VCC = 2.7 to 4.5 V)

Parameter Symbol Min*3Typ Max Unit Test conditions

Address setup time t
Address hold time t

CE to write setup time (WE controlled) t
CE hold time (WE controlled) t
WE to write setup time (CE controlled) t
WE hold time (CE controlled) t
OE to write setup time t
OE hold time t

Data setup time t
Data hold time t

WE pulse width (WE controlled) t
CE pulse width (CE controlled) t

Data latch time t
Byte load cycle t
Byte load window t
Write cycle time t
Time to device busy t
Write start time t
Reset protect time*
Reset high time*

Notes: 1. tDF and t

2

2, 6

are defined as the time at which the outputs achieve the open circuit conditions

DFR

and
are no longer driven.

2. This function is supported by only the HN58V66A series.

3. Use this device in longer cycle than this value.

4. t

must be longer than this value unless polling techniques or RDY/Busy are used. This

WC

device automatically completes the internal write operation within this value.

5. Next read or write operation can be initiated after t
used.

6. This parameter is sampled and not 100% tested.

7. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of WE.

8. A6 through A12 are page addresses and these addresses are latched at the first falling edge
of CE.

9. See AC read characteristics.

t
t

AS

AH

CS

CH

WS

WH

OES

OEH

DS

DH

WP

CW

DL

BLC

BL

WC

DB

DW

RP

RES

0 ——ns
50——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
50——ns
0 ——ns
200 — — ns
200 — — ns
100 — — ns

0.3 — 30 µs
100 — — µs
— — 10*

4

ms

120 — — ns

5

0*

——ns
100 — — µs
1——µs

if polling techniques or RDY/Busy are

DW

HN58V65A Series, HN58V66A Series

Read Cycle 2 (VCC = 4.5 to 5.5 V)

HN58V65A/HN58V66A

-10

Parameter Symbol Min Max Unit Test conditions

Address to output delay t

CE to output delay t
OE to output delay t

Address to output hold t

OE (CE) high to output float*1t
RES low to output float*
RES to output delay*

1, 2

2

ACC

CE

OE

OH

DF

t

DFR

t

RR

—70nsCE = OE = VIL, WE = V
—70nsOE = VIL, WE = V
10 40 ns CE = VIL, WE = V
0—nsCE = OE = VIL, WE = V
030nsCE = VIL, WE = V
0 350 ns CE = OE = VIL, WE = V
0 450 ns CE = OE= VIL, WE = V

IH

IH

IH

IH

IH

IH

IH