HIT HN58V65AFP-10, HN58V65AP-10, HN58V65AT-10, HN58V66AFP-10, HN58V66AP-10 Datasheet

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HN58V65A Series

HN58V66A Series

64 k EEPROM (8-kword × 8-bit) Ready/Busy function, RES function (HN58V66A)

ADE-203-539B (Z)

Rev. 2.0

Nov. 1997

Description

The Hitachi HN58V65A series and HN58V66A series are a electrically erasable and programmable EEPROM’s organized as 8192-word × 8-bit. They have realized high speed, low power consumption and high relisbility by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster.

Features

Single supply: 2.7 to 5.5 V

Access time:

100 ns (max) at 2.7 V VCC < 4.5 V

70 ns (max) at 4.5 V VCC 5.5 V

Power dissipation:

Active: 20 mW/MHz (typ)

Standby: 110 µW (max)

On-chip latches: address, data, CE, OE, WE

Automatic byte write: 10 ms (max)

Automatic page write (64 bytes): 10 ms (max)

Ready/Busy

Data polling and Toggle bit

Data protection circuit on power on/off

Conforms to JEDEC byte-wide standard

Reliable CMOS with MNOS cell technology

HN58V65A Series, HN58V66A Series

Features (cont)

105 erase/write cycles (in page mode)

10 years data retention

Software data protection

Write protection by RES pin (only the HN58V66A series)

Industrial versions (Temperatur range: –20 to 85˚C and –40 to 85˚C) are also available.

Ordering Information

 

Access time

 

 

Type No.

2.7 V VCC < 4.5 V

4.5 V VCC 5.5 V

Package

HN58V65AP-10

100 ns

70 ns

600 mil 28-pin plastic DIP (DP-28)

 

 

 

 

HN58V66AP-10

100 ns

70 ns

 

 

 

 

 

HN58V65AFP-10

100 ns

70 ns

400 mil 28-pin plastic SOP (FP-28D)

 

 

 

 

HN58V66AFP-10

100 ns

70 ns

 

 

 

 

 

HN58V65AT-10

100 ns

70 ns

28-pin plastic TSOP(TFP-28DB)

 

 

 

 

HN58V66AT-10

100 ns

70 ns

 

 

 

 

 

Pin Arrangement

 

HN58V65AP Series

 

 

HN58V66AP Series

 

 

HN58V65AFP Series

 

 

HN58V66AFP Series

 

RDY/Busy

1

28

VCC

RDY/Busy

1

28

VCC

A12

2

27

WE

A12

2

27

WE

A7

3

26

NC

A7

3

26

RES

A6

4

25

A8

A6

4

25

A8

A5

5

24

A9

A5

5

24

A9

A4

6

23

A11

A4

6

23

A11

A3

7

22

OE

A3

7

22

OE

A2

8

21

A10

A2

8

21

A10

A1

9

20

CE

A1

9

20

CE

A0

10

19

I/O7

A0

10

19

I/O7

I/O0

11

18

I/O6

I/O0

11

18

I/O6

I/O1

12

17

I/O5

I/O1

12

17

I/O5

I/O2

13

16

I/O4

I/O2

13

16

I/O4

VSS

14

15

I/O3

VSS

14

15

I/O3

(Top view)

(Top view)

HN58V65A Series, HN58V66A Series

Pin Arrangement (cont)

HN58V65AT Series

A2

15

14

 

A3

 

 

A1

16

13

 

A4

 

A0

17

12

 

A5

 

I/O0

18

11

 

A6

 

 

I/O1

19

10

 

A7

 

 

I/O2

20

9

 

A12

 

 

VSS

21

8

 

RDY/Busy

 

 

I/O3

22

7

 

VCC

 

I/O4

23

6

 

WE

 

 

I/O5

24

5

 

NC

 

 

I/O6

 

25

4

 

A8

 

 

 

 

I/O7

 

26

3

 

A9

 

 

 

 

CE

 

27

2

 

A11

 

 

A10

 

28

1

 

OE

 

 

 

 

 

 

 

(Top view)

 

 

 

 

 

HN58V66AT Series

 

 

 

 

 

 

 

A2

15

14

 

A3

 

A1

16

13

 

A4

 

A0

17

12

 

A5

 

I/O0

18

11

 

A6

 

 

I/O1

19

10

 

A7

 

 

I/O2

20

9

 

A12

 

 

VSS

21

8

 

RDY/Busy

 

 

I/O3

22

7

 

VCC

 

I/O4

23

6

 

WE

 

 

I/O5

24

5

 

RES

 

 

I/O6

 

25

4

 

A8

 

 

 

 

I/O7

 

26

3

 

A9

 

 

 

 

CE

 

27

2

 

A11

 

 

A10

 

28

1

 

OE

 

 

 

 

(Top view)

HIT HN58V65AFP-10, HN58V65AP-10, HN58V65AT-10, HN58V66AFP-10, HN58V66AP-10 Datasheet

HN58V65A Series, HN58V66A Series

Pin Description

Pin name

Function

A0 to A12

Address input

 

 

I/O0 to I/O7

Data input/output

 

 

OE

Output enable

 

 

CE

Chip enable

 

 

WE

Write enable

 

 

VCC

Power supply

VSS

Ground

RDY/Busy

Ready busy

 

 

RES*1

Reset

 

 

NC

No connection

Notes: 1. This function is supported by only the HN58V66A series.

Block Diagram

Notes: This function is supported by only the HN58V66A series.

VCC

 

 

I/O0to

I/O7

RDY/Busy

High voltage generator

 

 

 

VSS

 

 

 

 

 

 

 

 

RES *1

 

 

I/O buffer

 

OE

 

 

and

 

 

 

 

 

input latch

 

CE

Control logic and timing

 

 

 

WE

 

 

 

 

 

 

 

 

RES *1

 

 

 

 

 

A0

 

Y decoder

Y gating

 

to

 

 

 

 

 

 

 

A5

 

 

 

 

 

 

Address

 

 

 

 

 

buffer and

 

 

 

 

A6

latch

X decoder

Memory array

 

 

 

 

 

 

to

 

 

 

 

 

A12

 

 

 

 

 

 

 

 

Data latch

 

HN58V65A Series, HN58V66A Series

Operation Table

Operation

CE

OE

WE

RES*3

RDY/Busy

I/O

 

 

 

 

 

 

 

Read

VIL

VIL

VIH

VH*1

High-Z

Dout

Standby

VIH

×*2

×

×

High-Z

High-Z

Write

VIL

VIH

VIL

VH

High-Z to VOL

Din

Deselect

VIL

VIH

VIH

VH

High-Z

High-Z

Write Inhibit

×

×

VIH

×

 

×

VIL

×

×

Data Polling

VIL

VIL

VIH

VH

VOL

Dout (I/O7)

Program reset

×

×

×

VIL

High-Z

High-Z

Notes: 1. Refer to the recommended DC operating conditions.

2.× : Don’t care

3.This function supported by only the HN58V66A series.

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

Power supply voltage relative to VSS

VCC

–0.6 to +7.0

V

Input voltage relative to VSS

Vin

–0.5*1 to +7.0*3

V

 

 

 

 

Operating temperature range *2

Topr

0 to +70

˚C

 

 

 

 

Storage temperature range

Tstg

–55 to +125

˚C

Notes: 1. Vin min : –3.0 V for pulse width ≤ 50 ns.

2.Including electrical characteristics and data retention.

3.Should not exceed VCC + 1 V.

HN58V65A Series, HN58V66A Series

Recommended DC Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Supply voltage

VCC

2.7

5.5

V

 

VSS

0

0

0

V

Input voltage

VIL

–0.3*1

0.6* 5

V

 

VIH

1.9*2

V CC + 0.3*3

V

 

VH*4

VCC – 0.5

V CC + 1.0

V

 

 

 

 

 

 

Operating temperature

Topr

0

70

˚C

Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.

2.VIH = 2.2 V for VCC = 3.6 to 5.5 V.

3.VIH max: VCC + 1.0 V for pulse width ≤ 50 ns.

4.This function is supported by only the HN58V66A series.

5.VIL = 0.8 V for VCC = 3.6 V to 5.5 V

DC Characteristics (Ta = 0 to + 70˚C, VCC = 2.7 to 5.5 V)

Parameter

Symbol

Min

Typ

Max

Unit

 

Test conditions

Input leakage current

ILI

2* 1

µA

 

Vin = 0 V to VCC

Output leakage current

ILO

2

µA

 

Vout = 0 V to VCC

Standby VCC curren

ICC1

1 to 2

5

µA

 

CE = VCC – 0.3 V to VCC + 1.0 V

 

ICC2

1

mA

 

CE = VIH

Operating VCC current

ICC3

6

mA

Iout = 0 mA, Duty = 100%,

 

 

 

 

 

 

 

Cycle = 1 µs at VCC = 3.6 V

 

 

 

 

 

 

 

 

 

8

mA

Iout = 0 mA, Duty = 100%,

 

 

 

 

 

 

 

Cycle = 1 µs at VCC = 5.5 V

 

 

 

 

 

 

 

 

 

12

mA

Iout = 0 mA, Duty = 100%,

 

 

 

 

 

 

 

Cycle = 100 ns at VCC = 3.6 V

 

 

 

 

 

 

 

 

 

25

mA

Iout = 0 mA, Duty = 100%,

 

 

 

 

 

 

 

Cycle = 70 ns at VCC = 5.5 V

 

 

 

 

 

 

 

 

Output low voltage

VOL

0.4

V

I

OL = 2.1 mA

Output high voltage

VOH

VCC × 0.8

V

I

OH = –400 µA

Note: 1. ILI on RES : 100 µA max (only the HN58V66A series)

Capacitance (Ta = 25˚C, f = 1 MHz)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Input capacitance

Cin*1

6

pF

Vin = 0 V

 

 

 

 

 

 

 

Output capacitance

Cout*1

12

pF

Vout = 0 V

Note: 1. This parameter is sampled and not 100% tested.

HN58V65A Series, HN58V66A Series

AC Characteristics (Ta = 0 to + 70˚C, VCC = 2.7 to 5.5 V)

Test Conditions

Input pulse levels : 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V)

0V to VCC (RES pin*2)

Input rise and fall time : 5 ns

Input timing reference levels : 0.8, 1.8 V

Output load : 1TTL Gate +100 pF

Output reference levels : 1.5 V, 1.5 V

Read Cycle 1 (VCC = 2.7 to 4.5 V)

 

 

HN58V65A/HN58V66A

 

 

 

 

 

-10

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

Min

Max

 

Unit

Test conditions

 

 

 

 

 

 

Address to output delay

tACC

100

ns

CE = OE = VIL, WE = VIH

CE to output delay

tCE

100

ns

OE = VIL, WE = VIH

OE to output delay

tOE

10

50

 

ns

CE = VIL, WE = VIH

Address to output hold

tOH

0

ns

CE = OE = VIL, WE = VIH

OE (CE) high to output float*1

tDF

0

40

 

ns

CE = VIL, WE = VIH

RES low to output float*1, 2

tDFR

0

350

 

ns

CE = OE = VIL, WE = VIH

RES to output delay*2

tRR

0

450

 

ns

CE = OE= VIL, WE = VIH

HN58V65A Series, HN58V66A Series

Write Cycle 1 (VCC = 2.7 to 4.5 V)

Parameter

Symbol

Min*3

Typ

Max

Unit Test conditions

 

 

 

 

 

 

Address setup time

tAS

0

ns

Address hold time

tAH

50

ns

CE to write setup time (WE controlled)

tCS

0

ns

CE hold time (WE controlled)

tCH

0

ns

WE to write setup time (CE controlled)

tWS

0

ns

WE hold time (CE controlled)

tWH

0

ns

OE to write setup time

tOES

0

ns

OE hold time

tOEH

0

ns

Data setup time

tDS

50

ns

Data hold time

tDH

0

ns

WE pulse width (WE controlled)

tWP

200

ns

CE pulse width (CE controlled)

tCW

200

ns

Data latch time

tDL

100

ns

Byte load cycle

tBLC

0.3

30

s

Byte load window

tBL

100

s

Write cycle time

tWC

10* 4

ms

Time to device busy

tDB

120

ns

Write start time

tDW

0*5

ns

Reset protect time*2

tRP

100

s

Reset high time*2, 6

tRES

1

s

Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and

are no longer driven.

2.This function is supported by only the HN58V66A series.

3.Use this device in longer cycle than this value.

4.tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value.

5.Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used.

6.This parameter is sampled and not 100% tested.

7.A6 through A12 are page addresses and these addresses are latched at the first falling edge of WE.

8.A6 through A12 are page addresses and these addresses are latched at the first falling edge of CE.

9.See AC read characteristics.

HN58V65A Series, HN58V66A Series

Read Cycle 2 (VCC = 4.5 to 5.5 V)

 

 

HN58V65A/HN58V66A

 

 

 

 

 

-10

 

 

 

 

 

 

 

 

 

 

 

Parameter

Symbol

Min

Max

 

Unit

Test conditions

 

 

 

 

 

 

Address to output delay

tACC

70

ns

CE = OE = VIL, WE = VIH

CE to output delay

tCE

70

ns

OE = VIL, WE = VIH

OE to output delay

tOE

10

40

 

ns

CE = VIL, WE = VIH

Address to output hold

tOH

0

ns

CE = OE = VIL, WE = VIH

OE (CE) high to output float*1

tDF

0

30

 

ns

CE = VIL, WE = VIH

RES low to output float*1, 2

tDFR

0

350

 

ns

CE = OE = VIL, WE = VIH

RES to output delay*2

tRR

0

450

 

ns

CE = OE= VIL, WE = VIH

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