HIT HN58V1001FP-25, HN58V1001P-25, HN58V1001T-25 Datasheet

HN58V1001 Series

1M EEPROM (128-kword × 8-bit)

Ready/Busy and RES function

ADE-203-314G (Z)

Rev. 7.0

Oct. 31, 1997

Description

The Hitachi HN58V1001 is a electrically erasable and programmable ROM organized as 131072-word × 8­bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS
memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming
function to make the write operations faster.

Features

• Single 3 V supply: 2.7 V to 5.5 V

• Access time: 250 ns (max)

• Power dissipation
 Active: 20 mW/MHz, (typ)
 Standby: 110 µW (max)

• On-chip latches: address, data, CE, OE, WE

• Automatic byte write: 15 ms (max)

• Automatic page write (128 bytes): 15 ms (max)

• Data polling and RDY/Busy

• Data protection circuit on power on/off

• Conforms to JEDEC byte-wide standard

• Reliable CMOS with MNOS cell technology

• 104 erase/write cycles (in page mode)

• 10 years data retention

• Software data protection

• Write protection by RES pin

HN58V1001 Series

Ordering Information

Type No. Access time Package

HN58V1001P-25 250 ns 600 mil 32-pin plastic DIP (DP-32)
HN58V1001FP-25 250 ns 525 mil 32-pin plastic SOP (FP-32D)
HN58V1001T-25 250 ns 8 × 14 mm 32-pin plastic TSOP (TFP-32DA)

Pin Arrangement

HN58V1001P/FP Series

RDY/Busy

A16
A14
A12
A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

CC

A15

RES
WE

A13
A8
A9
A11

OE

A10

CE

I/O7
I/O6
I/O5
I/O4
I/O3

(Top view)

Pin Description

Pin name Function

A0 to A16 Address input
I/O0 to I/O7 Data input/output

OE Output enable
CE Chip enable
WE Write enable

V

CC

V

SS

RDY/Busy Ready busy
RES Reset

Power supply
Ground

A3
A2
A1

A0
I/O0
I/O1
I/O2

V

SS

I/O3
I/O4
I/O5
I/O6
I/O7

CE

A10

OE

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

HN58V1001T Series

(Top view)

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

A4
A5
A6
A7
A12
A14
A16
RDY/Busy
V

CC

A15

RES
WE

A13
A8
A9
A11

2

Block Diagram

y

V

CC

V

SS

High voltage generator

HN58V1001 Series

to

I/O0 I/O7

RDY/Bus

RES

OE

CE
WE

RES

A0

to

A6

A7

to

A16

Operation Table

Control logic and timing

Address
buffer and
latch

Y decoder

X decoder

I/O buffer
and
input latch

Y gating

Memory array

Data latch

Operation CE OE WE RES RDY/Busy I/O

Read V
Standby V
Write V
Deselect V

IL

IH

IL

IL

V
×*
V
V

IL

2

IH

IH

V

IH

×× High-Z High-Z
V

IL

V

IH

VH*

V
V

1

H

H

High-Z Dout

High-Z to V

Din

OL

High-Z High-Z

Write Inhibit ××VIH× ——

Data Polling V

×V

IL

IL

V

IL

×× ——
V

IH

V

H

V

OL

Dout (I/O7)

Program reset ×××VILHigh-Z High-Z
Notes: 1. Refer to the recommended DC operating conditions.

2. × : Don’t care

3

HN58V1001 Series

Absolute Maximum Ratings

Parameter Symbol Value Unit

Supply voltage relative to V
Input voltage relative to V

SS

SS

Operating temperature range*

2

V

CC

Vin –0.5*1 to +7.0 V
Topr 0 to +70 °C

Storage temperature range Tstg –55 to +125 °C
Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns

2. Including electrical characteristics and data retention

Recommended DC Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input voltage V

Operating temperature Topr 0 — 70 °C
Notes: 1. VIL (min): –1.0 V for pulse width ≤ 50 ns

2. V

(min): 2.2 V for VCC = 3.6 to 5.5 V

IH

CC

V

SS

IL

V

IH

V

H

–0.6 to +7.0 V

2.7 3.0 5.5 V
000V

1

–0.3*

1.9*

2

— 0.8 V
—V

+ 0.3 V

CC

Vcc – 0.5 — VCC + 1.0 V

DC Characteristics (Ta = 0 to +70 °C, VCC = 2.7 V to 5.5 V)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current I
Output leakage current I
Standby VCC current I

Operating VCC current I

Output low voltage V
Output high voltage V

LI

LO

CC1

I

CC2

CC3

OL

OH

Notes: 1. ILI on RES: 100 µA (max)

4

——2*
——2 µAVCC = 3.6 V, Vout = 3.6/0.4 V
——20µACE = V
——1 mACE = V
— — 6 mA Iout = 0 mA, Duty = 100%,

— — 15 mA Iout = 0 mA, Duty = 100%,

— — 0.4 V IOL = 2.1 mA
VCC × 0.8 — — V IOH = –400 µA

1

µAVCC = 3.6 V, Vin =3.6 V

CC

IH

Cycle = 1 µs at V

Cycle = 250 ns at V

= 3.3 V

CC

CC

= 3.3 V

HN58V1001 Series

Capacitance (Ta = 25°C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance*
Output capacitance*

1

1

Note: 1. This parameter is periodically sampled and not 100% tested.

AC Characteristics (Ta = 0 to +70 °C, VCC = 2.7 V to 5.5 V)

Test Conditions

• Input pulse levels: 0.4 V to 2.4 V

0 V to VCC (RES pin)

• Input rise and fall time: 20 ns

• Output load: 1TTL Gate +100 pF

• Reference levels for measuring timing: 0.8 V, 1.8 V

Read Cycle

Cin — — 6 pF Vin = 0 V
Cout — — 12 pF Vout = 0 V

HN58V1001-25

Parameter Symbol Min Max Unit Test conditions

Address to output delay t

CE to output delay t
OE to output delay t

Address to output hold t

OE (CE) high to output float*1t
RES low to output float

*1

RES to output delay t

ACC

CE

OE

OH

DF

t

DFR

RR

— 250 ns CE = OE = VIL, WE = V
— 250 ns OE = VIL, WE = V
10 120 ns CE = VIL, WE = V
0—nsCE = OE = VIL, WE = V
050nsCE = VIL, WE = V
0 350 ns CE = OE = VIL, WE = V
0 600 ns CE = OE = VIL, WE = V

IH

IH

IH

IH

IH

IH

IH

5

HN58V1001 Series

Write Cycle

Parameter Symbol Min*2Typ Max Unit Test conditions

Address setup time t
Address hold time t

CE to write setup time (WE controlled) t
CE hold time (WE controlled) t
WE to write setup time (CE controlled) t
WE hold time (CE controlled) t
OE to write setup time t
OE hold time t

Data setup time t
Data hold time t

WE pulse width (WE controlled) t
CE pulse width (CE controlled) t

Data latch time t
Byte load cycle t
Byte load window t
Write cycle time t
Time to device busy t
Write start time t
Reset protect time t
Reset high time*

Notes: 1. tDF and t

5

are defined as the time at which the outputs achieve the open circuit conditions and are

DFR

no longer driven.

2. Use this device in longer cycle than this value.

3. t

must be longer than this value unless polling techniques or RDY/Busy are used. This device

WC

automatically completes the internal write operation within this value.

4. Next read or write operation can be initiated after t

5. This parameter is sampled and not 100% tested.

6. A7 to A16 are page addresses and must be same within the page write operation.

7. See AC read characteristics.

t

AS

AH

CS

CH

WS

WH

OES

OEH

DS

DH

WP

CW

DL

BLC

BL

WC

DB

DW

RP

RES

0 ——ns
150 — — ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
100 — — ns
10——ns
250 — — ns
250 — — ns
750 — — ns

1.0 — 30 µs
100 — — µs
— — 15*

3

ms
120 — — ns
250*4——ns
100 — — µs
1——µs

if polling techniques or RDY/Busy are used.

DW

6

Timing Waveforms

Read Timing Waveform

Address

t

ACC

HN58V1001 Series

CE

OE

WE

Data Out

RES

High

t

t

CE

t

OE

OH

t

DF

Data out valid

t

RR

t

DFR

7