HIT HN58S256AT-15, HN58S256AT-20 Datasheet

HN58S256A Series

256 k EEPROM (32-kword × 8-bit)

ADE-203-692B (Z)

Rev. 2.0

Nov. 1997

Description

The Hitachi HN58S256A is a electrically erasable and programmable EEPROM’s organized as 32768­word × 8-bit employing advanced MNOS memory technology and CMOS process and circuitry
technology. It also has a 64-byte page programming function to make the write operations faster.

Features

• Single supply: 2.2 to 3.6 V

• Access time: 150 ns (max)/200 ns (max)

• Power dissipation:
 Active: 10 mW/MHz, (typ)
 Standby: 36 µW (max)

• On-chip latches: address, data, CE, OE, WE

• Automatic byte write: 15 ms (max)

• Automatic page write (64 bytes): 15 ms (max)

• Data polling and Toggle bit

• Data protection circuit on power on/off

• Conforms to JEDEC byte-wide standard

• Reliable CMOS with MNOS cell technology

• 105 erase/write cycles (in page mode)

• 10 years data retention

• Software data protection

• Industrial versions (Temperatur range:–40 to 85˚C) are also available.

HN58S256A Series

Ordering Information

Type No. Access time Package

HN58S256AT-15
HN58S256AT-20

Pin Arrangement

A2
A1

A0
I/O0
I/O1
I/O2

V

SS

I/O3
I/O4
I/O5
I/O6
I/O7

CE

A10

150 ns
200 ns

15
16
17
18
19
20
21
22
23
24
25
26
27
28

28-pin plastic TSOP (TFP-28DB)

HN58S256AT Series

(Top view)

14
13
12
11
10

A3
A4
A5
A6
A7
A12

9

A14

8

V

7

CC

6

WE

5

A13
A8

4
3

A9

2

A11

1

OE

Pin Description

Pin name Function

A0 to A14 Address input
I/O0 to I/O7 Data input/output

OE Output enable
CE Chip enable
WE Write enable

V

CC

V

SS

Power supply
Ground

Block Diagram

V

CC

V

SS

OE

CE
WE

High voltage generator

Control logic and timing

HN58S256A Series

to

I/O0 I/O7

I/O buffer
and
input latch

A0

to

Y decoder

Y gating

A5

Address
buffer and
latch

X decoder

Memory array

A6

to

A14

Data latch

Operation Table

Operation CE OE WE I/O

Read V
Standby V
Write V
Deselect V

IL

IH

IL

IL

V
×*
V
V

IL

2

IH

IH

Write inhibit ××V

Data polling V

× V

IL

IL

V

IL

Notes: 1. Refer to the recommended DC operating condition.

2. × = Don’t care

V

IH

Dout
× High-Z
V

IL

V

IH

IH

Din

High-Z

—
× —
V

IH

Data out (I/O7)

HN58S256A Series

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage relative to V
Input voltage relative to V
Operationg temperature range*

SS

2

SS

V

CC

Vin –0.5*1 to +4.6*
Topr 0 to +70 °C

Storage temperature range Tstg –55 to +125 °C
Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns

2. Including electrical characteristics and data retention

3. Should not exceed V

+ 1.0 V.

CC

Recommended DC Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input voltage V

Operating temperature Topr 0 — 70 °C
Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.

2. V

max: VCC + 1.0 V for pulse width ≤ 50 ns.

IH

CC

V

SS

IL

V

IH

–0.6 to +4.6 V

3

V

2.2 3.0 3.6 V
000V

1

–0.3*

— 0.4 V

Vcc × 0.7 — VCC + 0.3*2V

DC Characteristics (Ta = 0 to +70 °C, VCC = 2.2 to 3.6 V)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current I
Output leakage current I

Standby VCC current I

Operating VCC current I

Output low voltage V
Output high voltage V

LI

LO

CC1

I

CC2

CC3

OL

OH

——2 µAVCC = 3.6 V, Vin = 0 to 3.6 V
——2 µAVCC = 3.6 V, Vout = 3.6/0.4 V,

CE = V
——10µA CE = V
— — 500 µA CE = V

, Vin = 0 to 3.6 V

IH

CC

IH

— — 8 mA Iout = 0 mA, Duty = 100%,

Cycle = 1 µs at V
— — 12 mA Iout = 0 mA, Duty = 100%,

Cycle = 150 ns at V
— — 0.4 V IOL = 1.0 mA
VCC × 0.8 — — V IOH = –100 µA

= 3.6 V

CC

CC

= 3.6 V

HN58S256A Series

Capacitance (Ta = 25°C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance*
Output capacitance*

1

1

Note: 1. This parameter is periodically sampled and not 100% tested.

AC Characteristics (Ta = 0 to +70 °C, VCC = 2.2 to 3.6 V)

Test Conditions

• Input pulse levels: 0.4 V to 1.9 V (VCC ≤ 2.7V), 0.4V to 2.4 V (VCC > 2.7 V)

• Input rise and fall time: ≤ 5 ns

• Input timing reference levels: 0.8, 1.8 V

• Output load: 1TTL Gate +100 pF

• Output reference levels: 1.1 V, 1.1 V (VCC ≤ 2.7V),1.5 V, 1.5 V (VCC > 2.7 V)

Read Cycle

Cin — — 6 pF Vin = 0 V
Cout — — 12 pF Vout = 0 V

HN58S256A

-15 -20

Parameter Symbol Min Max Min Max Unit Test conditions

Address to output delay t

CE to output delay t
OE to output delay t

Address to output hold t
OE (CE) high to output float*1t

ACC

CE

OE

OH

DF

— 150 — 200 ns CE = OE = VIL, WE = V
— 150 — 200 ns OE = VIL, WE = V
10 80 10 100 ns CE = VIL, WE = V
0—0—ns CE = OE = VIL, WE = V
0 100 0 100 ns CE = VIL, WE = V

IH

IH

IH

IH

IH

HN58S256A Series

Write Cycle

Parameter Symbol Min*2Typ Max Unit Test conditions
Address setup time t
Address hold time t

CE to write setup time (WE controlled) t
CE hold time (WE controlled) t
WE to write setup time (CE controlled) t
WE hold time (CE controlled) t
OE to write setup time t
OE hold time t

Data setup time t
Data hold time t

WE pulse width (WE controlled) t
CE pulse width (CE controlled) t

Data latch time t
Byte load cycle t
Byte load window t
Write cycle time t
Write start time t

AS

AH

CS

CH

WS

WH

OES

OEH

DS

DH

WP

CW

DL

BLC

BL

WC

DW

Notes: 1. tDF is defined as the time at which the outputs achieve the open circuit conditions and are no

longer driven.

2. Use this device in longer cycle than this value.

3. t

must be longer than this value unless polling techniques is used. This device automatically

WC

completes the internal write operation within this value.

4. Next read or write operation can be initiated after t

5. A6 through A14 are page addresses and these addresses are latched at the first falling edge
of WE.

6. A6 through A14 are page addresses and these addresses are latched at the first falling edge
of CE.

7. See AC characteristics.

0 ——ns
150 — — ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
150 — — ns
0 ——ns
200 — — ns
200 — — ns
200 — — ns

0.4 — 30 µs
100 — — µs
— — 15*

4

0*

——ns

if polling techniques is used.

DW

3

ms