HIT HN58C256AFP-10, HN58C256AFP-85, HN58C256AP-10, HN58C256AP-85, HN58C256AT-10 Datasheet

HN58C256A Series HN58C257A Series

256k EEPROM (32-kword × 8-bit)

Ready/Busy and RES function (HN58C257A)

ADE-203-410D (Z)

Rev. 4.0

Oct. 24, 1997

Description

The Hitachi HN58C256A and HN58C257A are electrically erasable and programmable ROMs organized as 32768-word × 8-bit. They have realized high speed low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster.

Features

• Single 5 V supply: 5 V ±10%

• Access time: 85 ns/100 ns (max)

• Power dissipation  Active: 20 mW/MHz, (typ)  Standby: 110 µW (max)

• On-chip latches: address, data, CE, OE, WE

• Automatic byte write: 10 ms max

• Automatic page write (64 bytes): 10 ms max

• Ready/Busy (only the HN58C257A series)

• Data polling and Toggle bit

• Data protection circuit on power on/off

• Conforms to JEDEC byte-wide standard

• Reliable CMOS with MNOS cell technology

• 105 erase/write cycles (in page mode)

• 10 years data retention

• Software data protection

• Write protection by RES pin (only the HN58C257A series)

• Industrial versions (Temperatur range: – 20 to 85˚C and – 40 to 85˚C) are also available.

HN58C256A Series, HN58C257A Series

Ordering Information

Type No. Access time Package

HN58C256AP-85 HN58C256AP-10

HN58C256AFP-85 HN58C256AFP-10

HN58C256AT-85 HN58C256AT-10

HN58C257AT-85 HN58C257AT-10

Pin Arrangement

85 ns 100 ns

600 mil 28-pin plastic DIP (DP-28)

400 mil 28-pin plastic SOP (FP-28D)

28-pin plastic TSOP (TFP-28DB)

8 × 14 mm2 32-pin plastic TSOP (TFP-32DA)

HN58C256AP/AFP Series

A14

1

A12

2

A7

3

A6

4

A5

5

A4

6

A3

7

A2

8

A1

9

A0

10

I/O0

11

I/O1

12

I/O2

13

V

14

SS

(Top view)

28 27 26 25 24 23 22 21 20 19 18 17 16 15

V

CC

WE

A13 A8 A9 A11

OE

A10

CE

I/O7 I/O6 I/O5 I/O4 I/O3

A2 A1

A0 I/O0 I/O1 I/O2

V

SS

I/O3 I/O4 I/O5 I/O6 I/O7

CE

A10

A2

A1

A0

NC I/O0 I/O1 I/O2

V

SS

I/O3 I/O4 I/O5 I/O6 I/O7

NC

CE

A10

15 16 17 18 19 20 21 22 23 24 25 26 27 28

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

HN58C256AT Series

(Top view)

HN58C257AT Series

(Top view)

14 13 12 11 10

16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

A3 A4 A5 A6 A7 A12 A14 V

CC

WE

A13 A8 A9 A11

OE

A3 A4 A5 A6 A7 A12 A14 RDY/Busy V

CC

RES WE

A13 A8 A9 A11

OE

2

HN58C256A Series, HN58C257A Series

Pin Description

Pin name Function

A0 to A14 Address input I/O0 to I/O7 Data input/output

OE Output enable CE Chip enable WE Write enable

V

CC

V

SS

RDY/Busy* RES*

1

NC No connection Note: 1. This function is supported by only the HN58C257A series.

Block Diagram

Power supply Ground Ready busy Reset

Note: This function is supported by only the HN58C257A series.

V

CC

V

SS

RES

OE

CE WE

RES

A0

to

A5

A6

to

A14

1

*

1

*

High voltage generator

Control logic and timing

Address buffer and latch

Y decoder

X decoder

to

I/O0 I/O7

I/O buffer and input latch

Y gating

Memory array

RDY/Busy

1

*

Data latch

3

HN58C256A Series, HN58C257A Series

Operation Table

Operation CE OE WE RES* Read V Standby V Write V Deselect V

IL

IH

IL

V ×* V V

IL

2

IH

V

IH

××High-Z High-Z V

IL

V

IH

VH*

V V

1

H

3

RDY/Busy* High-Z Dout

High-Z to V High-Z High-Z

3

I/O

OL

Din

Write inhibit ××VIH× ——

Data polling V

×V

IL

V

IL

××—— V

IH

V

H

V

OL

Dout (I/O7)

Program reset ×××VILHigh-Z High-Z Notes: 1. Refer to the recommended DC operating condition.

2. × : Don’t care

3. This function is supported by only the HN58C257A series.

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage rerative to V Input voltage rerative to V Operationg temperature range*

SS

2

SS

V

CC

Vin –0.5*1 to +7.0* Topr 0 to +70 °C

Storage temperature range Tstg –55 to +125 °C Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns

2. Including electrical characteristics and data retention

3. Should not exceed V

+ 1 V.

CC

–0.6 to +7.0 V

3

V

4

HN58C256A Series, HN58C257A Series

Recommended DC Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input voltage V

V

V VH*

CC

SS

IL

IH

3

Operating temperature Topr 0 — 70 °C Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.

2. V

max: VCC + 1.0 V for pulse width ≤ 50 ns.

IH

3. This function is supported by only the HN58C257A series.

DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V±10%)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current I Output leakage current I Standby VCC current I

Operating VCC current I

Output low voltage V Output high voltage V

LI

LO

CC1

I

CC2

CC3

OL

OH

Note: 1. ILI on RES = 100 µA max (only the HN58C257A series)

——2* ——2 µAVCC = 5.5 V, Vout = 5.5/0.4 V ——20µACE = V ——1 mACE = V — — 12 mA Iout = 0 mA, Duty = 100%,

— — 30 mA Iout = 0 mA, Duty = 100%,

— — 0.4 V IOL = 2.1 mA

2.4 — — V IOH = –400 µA

4.5 5.0 5.5 V 000V

1

–0.3*

— 0.8 V

2.2 — VCC + 0.3*2V VCC – 0.5 — VCC + 1.0 V

1

µAVCC = 5.5 V, Vin = 5.5 V

CC

IH

Cycle = 1 µs at V

Cycle = 85 ns at V

= 5.5 V

CC

= 5.5 V

CC

Capacitance (Ta = +25°C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance* Output capacitance*

1

Note: 1. This parameter is periodically sampled and not 100% tested.

Cin — — 6 pF Vin = 0 V Cout — — 12 pF Vout = 0 V

5

HN58C256A Series, HN58C257A Series

AC Characteristics (Ta = 0 to +70°C, VCC = 5 V±10%)

Test Conditions

• Input pulse levels: 0.4 V to 3.0 V

0 V to VCC (RES pin*2)

• Input rise and fall time: ≤ 5 ns

• Input timing reference levels: 0.8, 2.0 V

• Output load: 1TTL Gate +100 pF

• Output reference levels: 1.5 V, 1.5 V

Read Cycle

HN58C256A/HN58C257A

-85 -10

Parameter Symbol Min Max Min Max Unit Test conditions

Address to output delay t

CE to output delay t OE to output delay t

Address to output hold t

OE (CE) high to output float*1t RES low to output float*

RES to output delay*

1, 2

2

ACC

CE

OE

OH

DF

t

DFR

t

RR

— 85 — 100 ns CE = OE = VIL,

WE = V

IH

— 85 — 100 ns OE = VIL, WE = V 10 40 10 50 ns CE = VIL, WE = V 0—0—nsCE = OE = VIL,

WE = V

IH

0 40 0 40 ns CE = VIL, WE = V 0 350 0 350 ns CE = OE = VIL,

WE = V

IH

0 450 0 450 ns CE = OE = VIL,

WE = V

IH

6

HN58C256A Series, HN58C257A Series

Write Cycle

Parameter Symbol Min*3Typ Max Unit Test conditions

Address setup time t Address hold time t

CE to write setup time (WE controlled) t CE hold time (WE controlled) t WE to write setup time (CE controlled) t WE hold time (CE controlled) t OE to write setup time t OE hold time t

Data setup time t Data hold time t

WE pulse width (WE controlled) t CE pulse width (CE controlled) t

Data latch time t Byte load cycle t Byte load window t Write cycle time t Time to device busy t Write start time t Reset protect time* Reset high time*

Notes: 1. tDF and t

2

2, 6

are defined as the time at which the outputs achieve the open circuit conditions and are

DFR

no longer driven.

2. This function is supported by only the HN58C257A series.

3. Use this device in longer cycle than this value.

4. t

must be longer than this value unless polling techniques or RDY/Busy (only the HN58C257A

WC

series) are used. This device automatically completes the internal write operation within this value.

5. Next read or write operation can be initiated after t HN58C257A series) are used.

6. This parameter is sampled and not 100% tested.

7. A6 through A14 are page address and these addresses are latched at the first falling edge of WE.

8. A6 through A14 are page address and these addresses are latched at the first falling edge of CE.

9. See AC read characteristics.

AS

AH

CS

CH

WS

WH

OES

OEH

DS

DH

WP

CW

DL

BLC

BL

WC

DB

DW

t

RP

t

RES

0 ——ns 50——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 50——ns 0 ——ns 100 — — ns 100 — — ns 50——ns

0.2 — 30 µs 100 — — µs — — 10*

4

ms

120 — — ns

5

0*

——ns 100 — — µs 1——µs

if polling techniques or RDY/Busy (only the

DW

7

HN58C256A Series, HN58C257A Series

Read Timing Waveform

Address

t

ACC

CE

OE

WE

Data Out

2

RES *

High

t

CE

t

OE

OH

t

DF

Data out valid

t

RR

t

DFR

8