HIT HN58C256AFP-10, HN58C256AFP-85, HN58C256AP-10, HN58C256AP-85, HN58C256AT-10 Datasheet

HN58C256A Series
HN58C257A Series

256k EEPROM (32-kword × 8-bit)

Ready/Busy and RES function (HN58C257A)

ADE-203-410D (Z)

Rev. 4.0

Oct. 24, 1997

Description

The Hitachi HN58C256A and HN58C257A are electrically erasable and programmable ROMs organized as
32768-word × 8-bit. They have realized high speed low power consumption and high reliability by
employing advanced MNOS memory technology and CMOS process and circuitry technology. They also
have a 64-byte page programming function to make their write operations faster.

Features

• Single 5 V supply: 5 V ±10%

• Access time: 85 ns/100 ns (max)

• Power dissipation
 Active: 20 mW/MHz, (typ)
 Standby: 110 µW (max)

• On-chip latches: address, data, CE, OE, WE

• Automatic byte write: 10 ms max

• Automatic page write (64 bytes): 10 ms max

• Ready/Busy (only the HN58C257A series)

• Data polling and Toggle bit

• Data protection circuit on power on/off

• Conforms to JEDEC byte-wide standard

• Reliable CMOS with MNOS cell technology

• 105 erase/write cycles (in page mode)

• 10 years data retention

• Software data protection

• Write protection by RES pin (only the HN58C257A series)

• Industrial versions (Temperatur range: – 20 to 85˚C and – 40 to 85˚C) are also available.

HN58C256A Series, HN58C257A Series

Ordering Information

Type No. Access time Package

HN58C256AP-85
HN58C256AP-10

HN58C256AFP-85
HN58C256AFP-10

HN58C256AT-85
HN58C256AT-10

HN58C257AT-85
HN58C257AT-10

Pin Arrangement

85 ns
100 ns

85 ns
100 ns

85 ns
100 ns

85 ns
100 ns

600 mil 28-pin plastic DIP (DP-28)

400 mil 28-pin plastic SOP (FP-28D)

28-pin plastic TSOP (TFP-28DB)

8 × 14 mm2 32-pin plastic TSOP (TFP-32DA)

HN58C256AP/AFP Series

A14

1

A12

2

A7

3

A6

4

A5

5

A4

6

A3

7

A2

8

A1

9

A0

10

I/O0

11

I/O1

12

I/O2

13

V

14

SS

(Top view)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

WE

A13
A8
A9
A11

OE

A10

CE

I/O7
I/O6
I/O5
I/O4
I/O3

A2
A1

A0
I/O0
I/O1
I/O2

V

SS

I/O3
I/O4
I/O5
I/O6
I/O7

CE

A10

A2

A1

A0

NC
I/O0
I/O1
I/O2

V

SS

I/O3
I/O4
I/O5
I/O6
I/O7

NC

CE

A10

15
16
17
18
19
20
21
22
23
24
25
26
27
28

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

HN58C256AT Series

(Top view)

HN58C257AT Series

(Top view)

14
13
12
11
10

16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

9
8
7
6
5
4
3
2
1

A3
A4
A5
A6
A7
A12
A14
V

CC

WE

A13
A8
A9
A11

OE

A3
A4
A5
A6
A7
A12
A14
RDY/Busy
V

CC

RES
WE

A13
A8
A9
A11

OE

2

HN58C256A Series, HN58C257A Series

Pin Description

Pin name Function

A0 to A14 Address input
I/O0 to I/O7 Data input/output

OE Output enable
CE Chip enable
WE Write enable

V

CC

V

SS

RDY/Busy*
RES*

1

1

NC No connection
Note: 1. This function is supported by only the HN58C257A series.

Block Diagram

Power supply
Ground
Ready busy
Reset

Note: This function is supported by only the HN58C257A series.

V

CC

V

SS

RES

OE

CE
WE

RES

A0

to

A5

A6

to

A14

1

*

1

*

High voltage generator

Control logic and timing

Address
buffer and
latch

Y decoder

X decoder

to

I/O0 I/O7

I/O buffer
and
input latch

Y gating

Memory array

RDY/Busy

1

*

Data latch

3

HN58C256A Series, HN58C257A Series

Operation Table

Operation CE OE WE RES*
Read V
Standby V
Write V
Deselect V

IL

IH

IL

IL

V
×*
V
V

IL

2

IH

IH

V

IH

××High-Z High-Z
V

IL

V

IH

VH*

V
V

1

H

H

3

RDY/Busy*
High-Z Dout

High-Z to V
High-Z High-Z

3

I/O

OL

Din

Write inhibit ××VIH× ——

Data polling V

×V

IL

IL

V

IL

××——
V

IH

V

H

V

OL

Dout (I/O7)

Program reset ×××VILHigh-Z High-Z
Notes: 1. Refer to the recommended DC operating condition.

2. × : Don’t care

3. This function is supported by only the HN58C257A series.

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage rerative to V
Input voltage rerative to V
Operationg temperature range*

SS

2

SS

V

CC

Vin –0.5*1 to +7.0*
Topr 0 to +70 °C

Storage temperature range Tstg –55 to +125 °C
Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns

2. Including electrical characteristics and data retention

3. Should not exceed V

+ 1 V.

CC

–0.6 to +7.0 V

3

V

4

HN58C256A Series, HN58C257A Series

Recommended DC Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input voltage V

V

V
VH*

CC

SS

IL

IH

3

Operating temperature Topr 0 — 70 °C
Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.

2. V

max: VCC + 1.0 V for pulse width ≤ 50 ns.

IH

3. This function is supported by only the HN58C257A series.

DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V±10%)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current I
Output leakage current I
Standby VCC current I

Operating VCC current I

Output low voltage V
Output high voltage V

LI

LO

CC1

I

CC2

CC3

OL

OH

Note: 1. ILI on RES = 100 µA max (only the HN58C257A series)

——2*
——2 µAVCC = 5.5 V, Vout = 5.5/0.4 V
——20µACE = V
——1 mACE = V
— — 12 mA Iout = 0 mA, Duty = 100%,

— — 30 mA Iout = 0 mA, Duty = 100%,

— — 0.4 V IOL = 2.1 mA

2.4 — — V IOH = –400 µA

4.5 5.0 5.5 V
000V

1

–0.3*

— 0.8 V

2.2 — VCC + 0.3*2V
VCC – 0.5 — VCC + 1.0 V

1

µAVCC = 5.5 V, Vin = 5.5 V

CC

IH

Cycle = 1 µs at V

Cycle = 85 ns at V

= 5.5 V

CC

= 5.5 V

CC

Capacitance (Ta = +25°C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance*
Output capacitance*

1

1

Note: 1. This parameter is periodically sampled and not 100% tested.

Cin — — 6 pF Vin = 0 V
Cout — — 12 pF Vout = 0 V

5

HN58C256A Series, HN58C257A Series

AC Characteristics (Ta = 0 to +70°C, VCC = 5 V±10%)

Test Conditions

• Input pulse levels: 0.4 V to 3.0 V

0 V to VCC (RES pin*2)

• Input rise and fall time: ≤ 5 ns

• Input timing reference levels: 0.8, 2.0 V

• Output load: 1TTL Gate +100 pF

• Output reference levels: 1.5 V, 1.5 V

Read Cycle

HN58C256A/HN58C257A

-85 -10

Parameter Symbol Min Max Min Max Unit Test conditions

Address to output delay t

CE to output delay t
OE to output delay t

Address to output hold t

OE (CE) high to output float*1t
RES low to output float*

RES to output delay*

1, 2

2

ACC

CE

OE

OH

DF

t

DFR

t

RR

— 85 — 100 ns CE = OE = VIL,

WE = V

IH

— 85 — 100 ns OE = VIL, WE = V
10 40 10 50 ns CE = VIL, WE = V
0—0—nsCE = OE = VIL,

WE = V

IH

0 40 0 40 ns CE = VIL, WE = V
0 350 0 350 ns CE = OE = VIL,

WE = V

IH

0 450 0 450 ns CE = OE = VIL,

WE = V

IH

IH

IH

IH

6

HN58C256A Series, HN58C257A Series

Write Cycle

Parameter Symbol Min*3Typ Max Unit Test conditions

Address setup time t
Address hold time t

CE to write setup time (WE controlled) t
CE hold time (WE controlled) t
WE to write setup time (CE controlled) t
WE hold time (CE controlled) t
OE to write setup time t
OE hold time t

Data setup time t
Data hold time t

WE pulse width (WE controlled) t
CE pulse width (CE controlled) t

Data latch time t
Byte load cycle t
Byte load window t
Write cycle time t
Time to device busy t
Write start time t
Reset protect time*
Reset high time*

Notes: 1. tDF and t

2

2, 6

are defined as the time at which the outputs achieve the open circuit conditions and are

DFR

no longer driven.

2. This function is supported by only the HN58C257A series.

3. Use this device in longer cycle than this value.

4. t

must be longer than this value unless polling techniques or RDY/Busy (only the HN58C257A

WC

series) are used. This device automatically completes the internal write operation within this value.

5. Next read or write operation can be initiated after t
HN58C257A series) are used.

6. This parameter is sampled and not 100% tested.

7. A6 through A14 are page address and these addresses are latched at the first falling edge of WE.

8. A6 through A14 are page address and these addresses are latched at the first falling edge of CE.

9. See AC read characteristics.

AS

AH

CS

CH

WS

WH

OES

OEH

DS

DH

WP

CW

DL

BLC

BL

WC

DB

DW

t

RP

t

RES

0 ——ns
50——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
50——ns
0 ——ns
100 — — ns
100 — — ns
50——ns

0.2 — 30 µs
100 — — µs
— — 10*

4

ms

120 — — ns

5

0*

——ns
100 — — µs
1——µs

if polling techniques or RDY/Busy (only the

DW

7

HN58C256A Series, HN58C257A Series

Read Timing Waveform

Address

t

ACC

CE

OE

WE

Data Out

2

RES *

High

t

t

CE

t

OE

OH

t

DF

Data out valid

t

RR

t

DFR

8

HN58C256A Series, HN58C257A Series

Byte Write Timing Waveform (1) (WE Controlled)

Address

t

CS

CE

t

WC

t

AH

t

CH

WE

OE

Din

RDY/Busy *

2

RES *

V

CC

t

AS

t

OES

2

t

RES

High-Z

t

RP

t

WP

t

DS

t

BL

t

OEH

t

DH

t

DW

t

DB

High-Z

9

HN58C256A Series, HN58C257A Series

Byte Write Timing Waveform (2) (CE Controlled)

Address

t

CE

WE

OE

t

t

AS

t

OES

WS

AH

t

CW

t

t

OEH

t

BL

WH

t

WC

Din

RDY/Busy *

2

RES *

V

CC

t

DS

2

High-Z High-Z

t

RP

t

RES

t

DH

t

DW

t

DB

10

HN58C256A Series, HN58C257A Series

Page Write Timing Waveform (1) (WE Controlled)

Address
A0 to A14

WE

CE

OE

Din

RDY/Busy *

*7

t

t

AH

AS

t

WP

t

DL

t

t

DH

DB

t

CH

t

CS

t

OES

t

DS

2

High-Z High-Z

t

RP

t

BLC

t

OEH

t

BL

t

WC

t

DW

RES *

V

CC

2

t

RES

11

HN58C256A Series, HN58C257A Series

Page Write Timing Waveform (2) (CE Controlled)

Address
A0 to A14

CE

WE

OE

Din

RDY/Busy *

*8

t

AH

t

AS

t

CW

t

DL

t

t

DH

DB

t

WH

t

WS

t

OES

t

DS

2

High-Z High-Z

t

RP

t

BLC

t

OEH

t

BL

t

WC

t

DW

RES *

V

CC

2

t

RES

12

Data Polling Timing Waveform

HN58C256A Series, HN58C257A Series

Address

CE

WE

OE

I/O7

*9

t

CE

An

*9

Dout X

t

Dout X

WC

An An

t

OEH

t

OE

Din X

t

DW

t

OES

13

HN58C256A Series, HN58C257A Series

Toggle bit

This device provide another function to determine the internal programming cycle. If the EEPROM is set to
read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read.
When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible
for next read or program.

Toggle bit Waveform

Notes: 1. I/O6 beginning state is "1".

2. I/O6 ending state will vary.

3. See AC read characteristics.

4. Any address location can be used, but the address must be fixed.

Next mode

*4

Address

*3

t

CE

CE

WE

OE

I/O6

Din

t

OEH

*3

t

OE

*1 *2 *2

Dout

Dout Dout Dout

t

WC

t

DW

t

OES

14

HN58C256A Series, HN58C257A Series

Software Data Protection Timing Waveform (1) (in protection mode)

V

CC

CE

WE

t

BLC

t

WC

Address
Data

5555
AA

2AAA
55

5555
A0

Write address

Write data

Software Data Protection Timing Waveform (2) (in non-protection mode)

V

CC

CE

WE

Address
Data

5555AA2AAA555555805555AA2AAA555555

20

t

WC

Normal active
mode

15

HN58C256A Series, HN58C257A Series

Functional Description

Automatic Page Write

Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When
CE or WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input
data are written into the EEPROM.

Data Polling

Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode
during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is
performing a write operation.

RDY/Busy Signal (only the HN58C257A series)

RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle,
the RDY/Busy signal changes state to high impedance.

RES Signal (only the HN58C257A series)

When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping
RES low when VCC is switched. RES should be high during read and programming because it doesn't provide
a latch function.

V

CC

RES

Read inhibit Read inhibit

Program inhibit

Program inhibit

16

HN58C256A Series, HN58C257A Series

WE, CE Pin Operation

During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising
edge of WE or CE.

Write/Erase Endurance and Data Retention Time

The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming
(1% cumulative failure rate). The data retention time is more than 10 years when a device is page­programmed less than 104 cycles.

Data Protection

1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to

programming mode by mistake.

To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns
or less.

Be careful not to allow noise of a width of more than 20 ns on the control pins.

WE
CE

OE

20 ns max

V

IH

0 V

V

IH

0 V

17

HN58C256A Series, HN58C257A Series

2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a

trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the
EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.

Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET

signal.

V

CC

CPU
RESET

*

Unprogrammable

(1) Protection by CE, OE, WE

To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.

*

Unprogrammable

CE V

CC

OE × V
WE ×× V

××

SS

×

CC

×: Don’t care.
V

: Pull-up to VCC level.

CC

V

: Pull-down to VSS level.

SS

18

HN58C256A Series, HN58C257A Series

(2) Protection by RES (only the HN58C257A series)

The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s
RES pin. RES should be kept VSS level during VCC on/off.

The EEPROM breaks off programming operation when RES becomes low, programming operation doesn’t
finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms
after the last data input.

V

CC

RES

WE

or CE

Program inhibit

1 µs min

100 µs min

10 ms min

Program inhibit

19

HN58C256A Series, HN58C257A Series

3. Software data protection
To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is

enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is
input. To program data in the SDP enable mode, 3 bytes code must be input before write data.

Address

5555

↓

2AAA

↓

5555

↓

Write address Normal data input

Data

AA

↓

55

↓

A0

↓

Write data }

The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP
disable cycle, data can not be written.

Address

5555

↓

2AAA

↓

5555

↓

5555

↓

2AAA

↓

5555

Data

AA

↓

55

↓

80

↓

AA

↓

55

↓

20

The software data protection is not enabled at the shipment.

Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence of

software data protection. If there are any questions , please contact with Hitachi sales offices.

20

Package Dimensions

HN58C256AP Series (DP-28)

28

35.6

36.5 Max

HN58C256A Series, HN58C257A Series

Unit: mm

15

13.4

14.6 Max

1

1.9 Max

2.54 ± 0.25

1.2

0.48 ± 0.10

14

5.70 Max

2.54 Min

0.51 Min

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

0° – 15°

15.24

0.25

DP-28
—
Conforms

4.6 g

+ 0.11
– 0.05

21

HN58C256A Series, HN58C257A Series

Package Dimensions (cont.)

HN58C256AFP Series (FP-28D)

18.3

18.8 Max

Unit: mm

28

1

1.12 Max

1.27

0.40 ± 0.08

0.38 ± 0.06

Dimension including the plating thickness

Base material dimension

0.15

0.20

14

M

15

8.4

0.20 ± 0.10

2.50 Max

Hitachi Code
JEDEC
EIAJ
Weight

11.8 ± 0.3

0.17 ± 0.05

0.15 ± 0.04

1.0 ± 0.2

(reference value)

1.7

0° – 8°

FP-28D
Conforms
—

0.7 g

22

Package Dimensions (cont.)

HN58C256AT Series (TFP-28DB)

8.00

8.20 Max

28

HN58C256A Series, HN58C257A Series

Unit: mm

15

11.80

1

14

0.55

0.22 ± 0.08

0.20 ± 0.06

0.10

M

0.45 Max

0.10

1.20 Max

Dimension including the plating thickness

Base material dimension

0.17 ± 0.05

0.15 ± 0.04

13.40 ± 0.30

+0.07

–0.08

0.13

0° – 5°

Hitachi Code
JEDEC
EIAJ

(reference value)

Weight

0.80

0.50 ± 0.10

TFP-28DB
—
—

0.23 g

23

HN58C256A Series, HN58C257A Series

Package Dimensions (cont.)

HN58C257AT Series (TFP-32DA)

8.00

8.20 Max

32

116

0.22 ± 0.08

0.20 ± 0.06

0.45 Max

0.50

0.08

17

12.40

M

14.00 ± 0.20

Unit: mm

0.80

0.10

1.20 Max

Dimension including the plating thickness

Base material dimension

0.17 ± 0.05

0.125 ± 0.04

0.13 ± 0.05

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

0° – 5°

0.50 ± 0.10

TFP-32DA
Conforms
Conforms

0.26 g

24

HN58C256A Series, HN58C257A Series

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.

3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.

4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.

5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.

6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.

Hitachi, Ltd.

Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo [phone]
Fax: [phone]

For further information write to:

Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: [phone]
Fax: [phone]

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Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: [phone]
Fax: [phone]

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Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
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United Kingdom
Tel: [phone]
Fax: [phone]

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16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: [phone]
Fax: [phone]

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Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: [phone]
Fax: [phone]

25