HIT HM658512ALFP-10, HM658512ALFP-10V, HM658512ALFP-7V, HM658512ALFP-8, HM658512ALFP-8V Datasheet

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HM658512A Series

4 M PSRAM (512-kword × 8-bit)

2 k Refresh

ADE-203-218C(Z)

Rev. 3.0

Nov. 1997

Description

The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology.

It offers low power data retention by self refresh mode. It also offers easy non multiplexed address interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery back-up systems.

The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8 × 20 mm TSOP with thickness of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also available.

Features

Single 5 V (±10%)

High speed

Access time

CE access time: 70/80/100 ns (max)

Cycle time

Random read/write cycle time: 115/130/160 ns (min)

Low power

Active: 250 mW (typ)

Standby: 200 µW (typ)

Directly TTL compatible All inputs and outputs

Simple address configuration Non multiplexed address

Refresh cycle

2048 refresh cycles: 32 ms

HM658512A Series

Easy refresh functions

Address refresh

Automatic refresh

Self refresh

Ordering Information

Type No.

Access time

 

 

 

 

 

 

 

 

 

 

 

Package

HM658512ALP-7

70 ns

 

 

 

 

 

 

 

 

 

 

 

600-mil 32-pin plastic DIP (DP-32)

HM658512ALP-8

80 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALP-10

100 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALP-7V

70 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALP-8V

80 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALP-10V

100 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALFP-7

70 ns

 

 

 

 

 

 

 

 

 

 

 

525-mil 32-pin plastic SOP (FP-32D)

HM658512ALFP-8

80 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALFP-10

100 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALFP-7V

70 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALFP-8V

80 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALFP-10V

100 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALTT-7

70 ns

 

 

 

 

 

 

 

 

 

 

 

400-mil 32-pin plastic TSOP (TTP-32D)

HM658512ALTT-8

80 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALTT-10

100 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALTT-7V

70 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALTT-8V

80 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALTT-10V

100 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALRR-7

70 ns

 

 

 

 

 

 

 

 

 

 

 

400-mil 32-pin plastic TSOP (TTP-32DR)

HM658512ALRR-8

80 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALRR-10

100 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALRR-7V

70 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALRR-8V

80 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

HM658512ALRR-10V

100 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

HM658512A Series

Pin Arrangement

 

 

HM658512ALP/ALFP Series

 

 

 

 

 

 

 

 

 

 

 

 

A18

 

1

32

 

VCC

 

 

 

 

 

 

A16

 

2

31

 

A15

 

 

 

 

 

 

A14

 

3

30

 

A17

 

 

A12

 

4

29

 

WE

 

 

A7

 

5

28

 

A13

 

 

A6

 

6

27

 

A8

 

 

A5

 

7

26

 

A9

 

 

A4

 

8

25

 

A11

 

 

A3

 

9

24

 

OE/RFSH

 

A2

 

10

23

 

A10

 

 

A1

 

11

22

 

CE

 

 

A0

 

12

21

 

I/O7

 

 

I/O0

 

13

20

 

I/O6

 

 

I/O1

 

14

19

 

I/O5

 

 

I/O2

 

15

18

 

I/O4

 

 

VSS

 

16

17

 

I/O3

 

 

 

 

 

(Top view)

 

 

 

 

HM658512ALTT Series

 

 

A18

1

 

 

 

 

 

 

32

VCC

A16

2

 

 

 

 

 

 

31

A15

A14

3

 

 

 

 

 

 

30

A17

A12

4

 

 

 

 

 

 

29

WE

A7

5

 

 

 

 

 

 

28

A13

A6

6

 

 

 

 

 

 

27

A8

A5

7

 

 

 

 

 

 

26

A9

A4

8

 

 

 

 

 

 

25

A11

A3

9

 

 

 

 

 

 

24

OE/RFSH

A2

10

 

 

 

 

 

 

23

A10

A1

11

 

 

 

 

 

 

22

CE

A0

12

 

 

 

 

 

 

21

I/O7

I/O0

13

 

 

 

 

 

 

20

I/O6

I/O1

14

 

 

 

 

 

 

19

I/O5

I/O2

15

 

 

 

 

 

 

18

I/O4

VSS

16

 

 

 

 

 

 

17

I/O3

(Top view)

3

HM658512A Series

Pin Arrangement (cont.)

 

 

 

 

 

HM658512ALRR Series

 

 

 

VCC

32

1

A18

 

 

A15

31

2

A16

 

 

A17

30

3

A14

 

 

WE

29

4

A12

 

 

A13

28

5

A7

 

 

A8

27

6

A6

 

 

A9

26

7

A5

 

 

A11

 

25

8

A4

OE/RFSH

24

9

A3

 

 

A10

23

10

A2

 

 

CE

22

11

A1

 

 

I/O7

21

12

A0

 

 

I/O6

20

13

I/O0

 

 

I/O5

19

14

I/O1

 

 

I/O4

18

15

I/O2

 

 

I/O3

17

16

VSS

(Top view)

Pin Description

Pin name

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

A0 to A18

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O0 to I/O7

Input/Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

Chip enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE/RFSH

Output enable/Refresh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

Write enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

Power supply

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

Ground

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

HIT HM658512ALFP-10, HM658512ALFP-10V, HM658512ALFP-7V, HM658512ALFP-8, HM658512ALFP-8V Datasheet

HM658512A Series

Block Diagram

A0

 

 

 

 

Address

Row

 

 

Latch

 

 

Decoder

Memory Matrix

 

Control

 

 

(2048 × 256) × 8

 

 

 

A10

 

 

 

I/O 0

 

Input

Column I/O

 

Column Decoder

 

Data

 

 

I/O 7

 

Control

 

 

 

Address Latch Control

 

 

 

 

 

A11

A18

 

Refresh

 

 

 

Control

 

 

CE

Timing Pulse Gen.

 

OE/RFSH

Read Write Control

 

WE

 

 

 

 

5

HM658512A Series

Pin Functions

CE: Chip Enable (Input)

CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high.

A0 to A18: Address Inputs (Input)

A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18 are fetched into RAM by the falling edge of CE.

OE/RFSH: Output Enable/Refresh (Input)

This pin has two functions. Basically it works as OE when CE is low, and as RFSH when CE is high (in standby mode). After a read or write cycle finishes, refresh does not start if CE goes high while OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when OE/RFSH goes low.

I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.

WE: Write Enable (Input)

RAM is in write mode when WE is low, and is in read mode when WE is high. I/O data is fetched into RAM by the rising edge of WE or CE (earlier timing) and the data is written into memory cells.

Refresh

There are three refresh modes : address refresh, automatic refresh and self refresh.

(1)Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at least once every 32 ms. In address refresh mode, OE/RFSH can remain high. In this case, the I/O pins remain at high impedance, but the refresh is done within RAM.

(2)Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic

refresh mode if OE/RFSH falls while CE is high and it remains low for at least tFAP. One automatic refresh cycle is executed by one low pulse of OE/RFSH. It is not necessary to input the refresh

address from outside since it is generated internally by an on-chip address counter. 2048 automatic refresh cycles must be done every 32 ms.

(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh starts automatically when OE/RFSH stays low for more than 8 µs. Refresh addresses are automatically specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.

Automatic refresh and self refresh are distinguished from each other by the width of the OE/RFSH low pulse in standby mode. If the OE/RFSH low pulse is wider than 8 µs, RAM becomes into self refresh mode; if the OE/RFSH low pulse is less than 8 µs, it is recognized as an automatic refresh instruction.

6

HM658512A Series

At the end of self refresh, refresh reset time (tRFS) is required to reset the internal self refresh operation of the RAM. During tRFS, CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low transition of OE/RFSH at the beginning of automatic refresh must not occur during tRFS period.

Notes on Using the HM658512A

Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive than conventional SRAM’s.

(1)If a short CE pulse of a width less than tCE min is applied to RAM, an incomplete read occurs and stored data may be destroyed. Make sure that CE low pulses of less than tCE min are inhibited. Note that a 10 ns CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is

generated by the decoding of higher address signals on the board. Avoid these short pulses.

(2)OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an incomplete refresh that will destroy data. Make sure that OE/RFSH low pulse of less than tFAP min are also inhibited.

(3)tOHC and tOCD are the timing specs which distinguish the OE function of OE/RFSH from the RFSH function. The tOHC and tOCD specs must be strictly maintained.

(4)Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100 µs after the power voltage reaches 4.5 V-5.5 V after power-on.

Function Table

CE

OE/RFSH

WE

I/O pin

Mode

 

 

 

 

 

L

L

H

Dout

Read

 

 

 

 

 

L

X

L

High-Z

Write

 

 

 

 

 

L

H

H

High-Z

 

 

 

 

 

H

L

X

High-Z

Refresh

 

 

 

 

 

H

H

X

High-Z

Standby

Note: X means H or L.

7

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