HIT HM62W8512BLRR-5UL, HM62W8512BLRR-7, HM62W8512BLRR-7SL, HM62W8512BLRR-7UL, HM62W8512BLTT-5 Datasheet
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HM62W8512B Series
4 M SRAM (512-kword × 8-bit)
ADE-203-904E (Z)
Rev. 4.0
Oct. 20, 1999
Description
The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The
device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high
density mounting. The HM62W8512B is suitable for battery backup system.
Features
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 55/70 ns (max)
• Power dissipation
Active: 16.5 mW/MHz (typ)
Standby: 3.3 µW (typ)
• Completely static memory. No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state output
• Directly LV-TTL compatible: All inputs and outputs
• Battery backup operation
HM62W8512B Series
Ordering Information
Type No. Access time Package
HM62W8512BLFP-5
HM62W8512BLFP-7
HM62W8512BLFP-5SL
HM62W8512BLFP-7SL
HM62W8512BLFP-5UL
HM62W8512BLFP-7UL
HM62W8512BLTT-5
HM62W8512BLTT-7
HM62W8512BLTT-5SL
HM62W8512BLTT-7SL
HM62W8512BLTT-5UL
HM62W8512BLTT-7UL
HM62W8512BLRR-5
HM62W8512BLRR-7
HM62W8512BLRR-5SL
HM62W8512BLRR-7SL
HM62W8512BLRR-5UL
HM62W8512BLRR-7UL
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
525-mil 32-pin plastic SOP (FP-32D)
400-mil 32-pin plastic TSOP II (TTP-32D)
400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
2
Pin Arrangement
HM62W8512BLFP Series HM62W8512BLTT Series
HM62W8512B Series
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(Top view)
HM62W8512BLRR Series
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
Pin Description
Pin name Function
A0 to A18 Address input
I/O0 to I/O7 Data input/output
CS Chip select
OE Output enable
WE Write enable
V
CC
V
SS
Power supply
Ground
(Top view)
3
HM62W8512B Series
Block Diagram
A18
A16
A1
A0
A2
A12
A14
A3
A7
A6
Row
Decoder
V
CC
V
SS
•
•
•
•
•
Memory Matrix
×
1,024 4,096
I/O0
I/O7
CS
WE
OE
•
•
Input
Data
Control
Timing Pulse Generator
Read/Write Control
Column I/O
Column Decoder
A13A17A15A8 A10A11
•
•
•
•
A5A9 A4
4
HM62W8512B Series
Function Table
WE CS OE Mode VCC current Dout pin Ref. cycle
× H × Not selected I
H L H Output disable I
H L L Read I
L L H Write I
L L L Write I
, I
SB
SB1
CC
CC
CC
CC
Note: ×: H or L
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage V
Voltage on any pin relative to V
SS
Power dissipation P
CC
V
T
T
Operating temperature Topr –20 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –20 to +85 °C
Notes: 1. –3.0 V for pulse half-width ≤ 30 ns
2. Maximum voltage is 4.6 V
–0.5 to +4.6 V
–0.5*1 to VCC + 0.5*
1.0 W
High-Z —
High-Z —
Dout Read cycle
Din Write cycle (1)
Din Write cycle (2)
2
V
Recommended DC Operating Conditions (Ta = –20 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage V
Input high voltage V
Input low voltage V
CC
V
SS
IH
IL
Note: 1. –3.0 V for pulse half-width ≤ 30 ns
3.0 3.3 3.6 V
000V
2.0 — VCC + 0.3 V
1
–0.3*
— 0.8 V
5
HM62W8512B Series
DC Characteristics (Ta = –20 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter Symbol Min Typ*1Max Unit Test conditions
Input leakage current |I
Output leakage current |ILO|— — 1 µACS = VIH or OE = VIH or
Operating power
supply current: DC
Operating
HM62W8512B-5 I
power supply
current
HM62W8512B-7 I
Operating power
supply current
Standby power supply
current: DC
Standby power supply
current (1): DC
Output low voltage V
Output high voltage V
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L version.
3. This characteristics is guaranteed only for L-SL version.
4. This characteristics is guaranteed only for L-UL version.
|——1µA Vin = VSS to V
LI
WE = V
I
CC
— — 10 mA CS = VIL,
others = V
CC1
— — 45 mA Min cycle, duty = 100%
CS = V
I
= 0 mA
I/O
CC1
I
CC2
— — 40 mA
— 5 10 mA Cycle time = 1 µs,
duty = 100%
I
= 0 mA, CS ≤ 0.2 V
I/O
V
≥ VCC – 0.2 V,
IH
V
≤ 0.2 V
IL
I
SB
I
SB1
— 0.1 0.3 mA CS = V
—1*
2
40*
2
µA Vin ≥ 0 V,
CS ≥ V
—1*
—1*
OL
— — 0.4 V IOL = 2.0 mA
3
45*4
20*
3
µA
µA
— — 0.2 V IOL = 100 µA
OH
VCC – 0.2 — — V IOH = –100 µA
2.4 — — V IOH = –2.0 mA
CC
, V
= VSS to V
IL
I/O
, I
IH/VIL
, others = VIH/V
IL
IH
– 0.2 V
CC
= 0 mA
I/O
CC
IL
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter Symbol Typ Max Unit Test conditions
Input capacitance*
1
Input/output capacitance*1C
Note: 1. This parameter is sampled and not 100% tested.
6
Cin — 8 pF Vin = 0 V
I/O
—10pFV
= 0 V
I/O
HM62W8512B Series
AC Characteristics (Ta = –20 to +70°C, VCC = 3.3 V ±0.3 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: 0.4 V to 2.4 V
• Input rise and fall time: 5 ns
• Input timing reference levels: 1.4 V
• Output timing reference level: 0.8 V/2.0 V
• Output load (Including scope & jig)
Ω
Dout
500
50 pF
1.4 V
Read Cycle
HM62W8512B
-5 -7
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time t
Address access time t
Chip select access time t
Output enable to output valid t
Chip selection to output in low-Z t
Output enable to output in low-Z t
Chip deselection to output in high-Z t
Output disable to output in high-Z t
Output hold from address change t
RC
AA
CO
OE
LZ
OLZ
HZ
OHZ
OH
55 — 70 — ns
— 55 — 70 ns
— 55 — 70 ns
— 25 — 35 ns
10 — 10 — ns 2
5—5—ns2
0 20 0 30 ns 1, 2
0 20 0 30 ns 1, 2
10 — 10 — ns
7
HM62W8512B Series
Write Cycle
HM62W8512B
-5 -7
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time t
Chip selection to end of write t
Address setup time t
Address valid to end of write t
Write pulse width t
Write recovery time t
WE to output in high-Z t
Data to write time overlap t
Data hold from write time t
Output active from output in high-Z t
Output disable to output in high-Z t
Notes: 1. tHZ, t
OHZ
and t
are defined as the time at which the outputs achieve the open circuit conditions and
WHZ
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high
or WE going high. t
4. t
is measured from CS going low to the end of write.
CW
5. t
is measured from the address valid to the beginning of write.
AS
6. t
is measured from the earlier of WE or CS going high to the end of write cycle.
WR
is measured from the beginning of write to the end of write.
WP
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10.Dout is the read data of next address.
11.If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12.In the write cycle with OE low fixed, t
data bus contention. t
≥ tDW min + t
WP
WC
CW
AS
AW
WP
WR
WHZ
DW
DH
OW
OHZ
55 — 70 — ns
50 — 60 — ns 4
0—0—ns5
50 — 60 — ns
40 — 50 — ns 3, 12
0—0—ns6
0 20 0 30 ns 1, 2, 7
25 — 30 — ns
0—0—ns
5—5—ns2
0 20 0 30 ns 1, 2, 7
) of a low CS and a low WE. A write begins at the later
WP
must satisfy the following equation to avoid a problem of
WP
max
WHZ
8
Timing Waveforms
Read Timing Waveform (WE = VIH)
Address
CS
OE
HM62W8512B Series
t
RC
t
AA
t
CO
t
LZ
t
OE
t
OLZ
t
HZ
t
OHZ
Dout
Valid Data
t
OH
9
HM62W8512B Series
Write Timing Waveform (1) (OE Clock)
Address
t
WC
OE
CS
WE
Dout
Din
t
AW
t
CW
*8
t
AS
t
OHZ
t
WP
t
DW
t
WR
t
DH
Valid Data
10
Write Timing Waveform (2) (OE Low Fixed)
Address
t
HM62W8512B Series
WC
CS
WE
Dout
Din
t
CW
*8
t
AW
t
WP
t
AS
t
WHZ
t
DW
t
WR
t
OH
t
OW
*9
t
DH
*11
*10
Valid Data
11
HM62W8512B Series
Low VCC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter Symbol Min Typ Max Unit Test conditions*
VCC for data retention V
Data retention current I
DR
CCDR
2——VCS ≥ VCC – 0.2 V, Vin ≥ 0 V
— 0.8*520*1µAVCC = 3.0 V, Vin ≥ 0 V
CS ≥ V
– 0.2 V
CC
— 0.8*510*2µA
3
µA
Chip deselect to data retention time t
Operation recovery time t
CDR
R
— 0.8*52*
0 — — ns See retention waveform
tRC*6——ns
Notes: 1. For L-version and 10 µA (max.) at Ta = –20 to +40°C.
2. For L-SL-version and 3 µA (max.) at Ta = –20 to +40°C.
3. For L-UL-version and 2 µA (max.) at Ta = –20 to +40°C.
4. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
5. Typical values are at V
6. t
= read cycle time.
RC
= 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
CC
Low VCC Data Retention Timing Waveform (CS Controlled)
V
CC
3.0 V
t
CDR
Data retention mode
t
R
4
12
V
DR
2.0 V
CS
0 V
≥
CS V – 0.2 V
CC
Package Dimensions
HM62W8512BLFP Series (FP-32D)
20.45
20.95 Max
32
HM62W8512B Series
Unit: mm
17
11.30
1
1.00 Max
0.15
0.10
M
1.27
*0.40 ± 0.08
0.38 ± 0.06
*Dimension including the plating thickness
Base material dimension
16
+ 0.12
– 0.10
0.15
3.00 Max
0.20 ± 0.04
*0.22 ± 0.05
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
14.14 ± 0.30
1.42
0° – 8°
0.80 ± 0.20
FP-32D
Conforms
—
1.3 g
13
HM62W8512B Series
Package Dimensions (cont.)
HM62W8512BLTT Series (TTP-32D)
20.95
21.35 Max
32
Unit: mm
17
10.16
1
*0.42 ± 0.08
0.40 ± 0.06
1.15 Max
1.20 Max
*Dimension including the plating thickness
Base material dimension
0.21
0.10
1.27
M
16
*0.17 ± 0.05
0.125 ± 0.04
11.76 ± 0.20
0.13 ± 0.05
Hitachi Code
JEDEC
EIAJ
Weight
0° – 5°
(reference value)
0.80
0.50 ± 0.10
TTP-32D
Conforms
—
0.51 g
14
Package Dimensions (cont.)
HM62W8512BLRR Series (TTP-32DR)
20.95
21.35 Max
1
HM62W8512B Series
Unit: mm
16
10.16
32
*0.42 ± 0.08
0.40 ± 0.06
1.15 Max
1.20 Max
*Dimension including the plating thickness
Base material dimension
0.21
0.10
1.27
M
17
*0.17 ± 0.05
0.125 ± 0.04
11.76 ± 0.20
0.13 ± 0.05
Hitachi Code
JEDEC
EIAJ
Weight
0° – 5°
(reference value)
0.80
0.50 ± 0.10
TTP-32DR
Conforms
—
0.51 g
15
HM62W8512B Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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16
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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