HIT HM62W8511HLJP-12, HM62W8511HLJP-15, HM62W8511HJP-12, HM62W8511HJP-15 Datasheet

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HM62W8511H Series

4M High Speed SRAM (512-kword × 8-bit)

ADE-203-750D (Z)

Rev. 1.0

Sep. 15, 1998

Description

The HM62W8511H is a 4-Mbit high speed static RAM organized 512-kword × 8-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W8511H is packaged in 400-mil 36-pin SOJ for high density surface mounting.

Features

• Single supply : 3.3 V ± 0.3 V

• Access time 12/15 ns (max)

• Completely static memory  No clock or timing strobe required

• Equal access and cycle times

• Directly TTL compatible  All inputs and outputs

• Operating current : 150/130 mA (max)

• TTL standby current : 60/50 mA (max)

• CMOS standby current : 5 mA (max)

: 1 mA (max) (L-version)

• Data retension current : 0.6 mA (max) (L-version)

• Data retension voltage : 2 V (min) (L-version)

• Center VCC and VSS type pinout

HM62W8511H Series

Ordering Information

Type No. Access time Package

HM62W8511HJP-12 HM62W8511HJP-15

HM62W8511HLJP-12 HM62W8511HLJP-15

Pin Arrangement

12 ns 15 ns

HM62W8511HJP/HLJP Series

400-mil 36-pin plastic SOJ (CP-36D)

A0 A1 A2 A3

A4 CS I/O1 I/O2 V

I/O3 I/O4 WE

A5 A6 A7 A8 A9

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

(T op Vie w)

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

NC A18 A17 A16 A15

I/O8 I/O7 V

I/O6 I/O5 A14 A13 A12 A11 A10 NC

Pin Description

Pin name Function

A0 to A18 Address input I/O1 to I/O8 Data input/output

CS Chip select OE Output enable WE Write enable

Power supply Ground

NC No connection

Block Diagram

(LSB)

A17

A7 A11 A16

(MSB)

Row

decoder

Memory matrix

256 rows × 8 columns ×

256 blocks × 8 bit

(4,194,304 bits)

HM62W8511H Series

I/O1

. . .

I/O8

WE CS

Input

data

control

Column I/O

Column decoder

A10 A8 A9 A12 A13 A14 A0 A18 A15 A3 A4

(LSB)

(MSB)

HM62W8511H Series

Operation Table

CS OE WE Mode VCC current I/O Ref. cycle

H ××Standby I L H H Output disable I L L H Read I L H L Write I L L L Write I

, I

SB1

Note: ×: H or L

Absolute Maximum Ratings

Parameter Symbol Value Unit

Supply voltage relative to V Voltage on any pin relative to V

Power dissipation P Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C

Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns

2. V

(max) = VCC+2.0 V for pulse width (over shoot)≤ 8 ns

High-Z — High-Z — Dout Read cycle (1) to (3) Din Write cycle (1) Din Write cycle (2)

–0.5 to +4.6 V –0.5*1 to VCC+0.5*

1.0 W

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input voltage V

VSS*

Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns

2. V

(max) = VCC+2.0 V for pulse width (over shoot)≤ 8 ns

3. The supply voltage with all V

4. The supply voltage with all V

3.0 3.3 3.6 V 000V

2.2 — VCC + 0.5*

–0.5*

pins must be on the same level.

— 0.8 V

HM62W8511H Series

DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V)

Parameter Symbol Min Typ*

Input leakage current II

I——2 µA Vin = VSS to V

Max Unit Test conditions

Output leakage current IILOI——2 µA Vin = VSS to V Operation power

supply current

12 ns cycle I

— — 150 mA Min cycle

CS = V

, lout = 0 mA

Other inputs = V

Standby power supply current

15 ns cycle I 12 ns cycle I

— — 130 — — 60 mA Min cycle

CS = V

Other inputs = V

15 ns cycle I

SB1

——50 — 0.05 5 mA f = 0 MHz

≥ CS ≥ VCC - 0.2 V,

(1) 0 V ≤ Vin ≤ 0.2 V or (2) V

≥ Vin ≥ VCC - 0.2 V

Output voltage V

—*

— — 0.4 V IOL = 8 mA

2.4 — — V IOH = –4 mA

0.05*21.0*

Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.

2. This characteristics is guaranteed only for L-version.

IH/VIL

Capacitance (Ta = +25°C, f = 1.0 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance*

Input/output capacitance* Note: 1. This parameter is sampled and not 100% tested.

Cin — — 6 pF Vin = 0 V

I/O

——8 pFV

= 0 V

I/O

HM62W8511H Series

AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)

Test Conditions

• Input pulse levels: 3.0 V/0.0 V

• Input rise and fall time: 3 ns

• Input and output timing reference levels: 1.5 V

• Output load: See figures (Including scope and jig)

3.3 V

Dout

Zo=50 Ω

RL=50 Ω

Dout

353Ω

5 pF

1.5 V

319Ω

Output load (A)

(for t

CLZ

Output load (B)

, t

OLZ

CHZ

, t

OHZ

, and tOW)

WHZ

Read Cycle

HM62W8511H

-12 -15

Parameter Symbol Min Max Min Max Unit Notes

Read cycle time t Address access time t Chip select access time t Output enable to outpput valid t Output hold from address change t Chip select to output in low-Z t Output enable to output in low-Z t Chip deselect to output in high-Z t Output disable to output in high-Z t

ACS

CLZ

OLZ

CHZ

OHZ

12 — 15 — ns — 12 — 15 ns — 12 — 15 ns —6 —7 ns 3—3—ns 3—3—ns1 0—0—ns1 —6 —7 ns1 —6 —7 ns1

HM62W8511H Series

Write Cycle

HM62W8511H

-12 -15

Parameter Symbol Min Max Min Max Unit Notes

Write cycle time t Address valid to end of write t Chip select to end of write t Write pulse width t Address setup time t Write recovery time t Data to write time overlap t Data hold from write time t Write disable to output in low-Z t Output disable to output in high-Z t Write enable to output in high-Z t

OHZ

WHZ

Note: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled

and not 100% tested.

2. Address should be valid prior to or coincident with CS transition low.

3. WE and/or CS must be high during address transition time.

4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them.

5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state.

6. t

is measured from the latest address transition to the later of CS or WE going low.

7. t

is measured from the earlier of CS or WE going high to the first address transition.

8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low. A write ends at the earliest transition among CS going high and WE going high. t

9. t

is measured from the later of CS going low to the the end of write.

is measured from the beginnig of write to the end of write.

12 — 15 — ns 8 — 10 — ns 8—10—ns9 8—10—ns8 0—0—ns6 0—0—ns7 6—7—ns 0—0—ns 3—3—ns1 —6 —7 ns1 —6 —7 ns1

HM62W8511H Series

Timing Waveforms

Read Timing Waveform (1) (WE = VIH)

Address

Valid address

ACS

OLZ

CLZ

Dout

High Impedance

Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)

Address

Valid address

CHZ

OHZ

Valid data

Dout

Valid data

HM62W8511H Series

Read Timing Waveform (3) (WE = VIH, CS = VIL, OE = VIL)*

ACS

Dout

CLZ

High Impedance

Write Timing Waveform (1) (WE Controlled)

Address

Valid address

Valid data

CHZ

High Impedance

CS*

WE*

Dout

Din

OHZ

High impedance*

Valid data

HM62W8511H Series

Write Timing Waveform (2) (CS Controlled)

Address

CS *

WE *

Dout

Din

Valid address

WHZ

High impedance*

Valid data

HM62W8511H Series

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

This characteristics is guaranteed only for L-version.

Parameter Symbol Min Typ*1Max Unit Test conditions

for data retention V

Data retention current I

Chip deselect to data

CCDR

CDR

retention time Operation recovery time t

Note: 1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.

Low VCC Data Retention Timing Waveform

2.0 — — V VCC ≥ CS ≥ VCC – 0.2 V (1) 0 V ≤ Vin ≤ 0.2 V or (2) V

≥ Vin ≥ VCC – 0.2 V

— 40 600 µAVCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V

(1) 0 V ≤ Vin ≤ 0.2 V or (2) V

≥ Vin ≥ VCC – 0.2 V

0 — — ns See retention waveform

5 ——ms

3.0 V

2.2 V

0 V

CDR

Data retention mode

VCC ≥ CS ≥ VCC – 0.2 V

HM62W8511H Series

Package Dimensions

HM62W8511HJP/HLJP Series (CP-36D)

23.25

23.62 Max

0.74

10.16 ± 0.13

Unit: mm

11.18 ± 0.13

1.30 Max

0.43 ± 0.10

0.41 ± 0.08

Dimension including the plating thickness

Base material dimension

0.10

1.27

3.50 ± 0.26

+0.25

–0.17

0.80

Hitachi Code JEDEC EIAJ Weight

9.40 ± 0.25

(reference value)

2.85 ± 0.12

CP-36D Conforms Conforms

1.4 g

HM62W8511H Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Hitachi, Ltd.

Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL NorthAmerica : http:semiconductor.hitachi.com/

For further information write to:

Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA 94005-1897 Tel: <1> (800) 285-1601 Fax: <1> (303) 297-0447

Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm

Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00

Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322

Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533

Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180

Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX

HIT HM62W8511HLJP-12, HM62W8511HLJP-15, HM62W8511HJP-12, HM62W8511HJP-15 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Description

Features

Ordering Information

Pin Arrangement

Pin Description

Block Diagram

Operation Table

Absolute Maximum Ratings

Recommended DC Operating Conditions (Ta = 0 to +70°C)

DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V)

Capacitance (Ta = +25°C, f = 1.0 MHz)

AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)

Timing Waveforms

Read Timing Waveform (1) (WE = VIH)

Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)

Write Timing Waveform (1) (WE Controlled)

Write Timing Waveform (2) (CS Controlled)

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

Low VCC Data Retention Timing Waveform

Package Dimensions

HM62W8511HJP/HLJP Series (CP-36D)