HIT HM62W16255HJPI-15, HM62W16255HTTI-15 Datasheet
HM62W16255HI Series
4M High Speed SRAM (256-kword × 16-bit)
ADE-203-1038B (Z)
Rev. 2.0
Jan. 20, 2000
Description
The HM62W16255HI is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high
speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed
circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged
in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII.
Features
• Single 3.3 V supply: 3.3 V ± 0.3V
• Access time: 15 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current: 160 mA (max)
• TTL standby current: 50 mA (max)
• CMOS standby current: 5 mA (max)
• Center VCC and VSS type pinout
• Temperature range: –40 to 85°C
HM62W16255HI Series
Ordering Information
Type No. Access time Package
HM62W16255HJPI-15 15 ns 400-mil 44-pin plastic SOJ (CP-44D)
HM62W16255HTTI-15 15 ns 400-mil 44-pin plastic TSOPII (TTP-44DE)
Pin Arrangement
HM62W16255HJPI Series
A0
A1
A2
A3
A4
CS
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
(Top View)
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
HM62W16255HTTI Series
1
A0
2
A1
3
A2
4
A3
5
A4
6
CS
7
I/O1
8
I/O2
9
I/O3
10
I/O4
CC
SS
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
11
12
13
14
15
16
17
18
19
20
21
22
V
V
(Top View)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
2
Pin Description
Pin name Function
A0 to A17 Address input
I/O1 to I/O16 Data input/output
CS Chip select
OE Output enable
WE Write enable
UB Upper byte select
LB Lower byte select
V
CC
V
SS
Power supply
Ground
NC No connection
Block Diagram
HM62W16255HI Series
(LSB)
(MSB)
I/O16
A1
A17
A7
A11
A16
A2
A6
A5
I/O1
I/O8
I/O9
WE
CS
LB
UB
OE
V
CC
Row
decoder
Memory matrix
256 rows × 8 columns ×
128 blocks × 16 bit
V
SS
(4,194,304 bits)
CS
.
.
.
Input
data
.
.
.
control
A10 A8 A9 A12 A13 A14 A0 A15 A3 A4
Column I/O
Column decoder
CS
CS
3
HM62W16255HI Series
Operation Table
CS OE WE LB UB Mode VCC current I/O1–I/O8 I/O9–I/O16 Ref. cycle
H ××××Standby I
LHH××Output disable I
L L H L L Read I
L L H L H Lower byte read I
L L H H L Upper byte read I
L LHHH— I
L × L L L Write I
L × L L H Lower byte write I
L × L H L Upper byte write I
L × L HH— I
, I
SB
CC
CC
CC
CC
CC
CC
CC
CC
CC
Note: ×: H or L
Absolute Maximum Ratings
SB1
High-Z High-Z —
High-Z High-Z —
Output Output Read cycle
Output High-Z Read cycle
High-Z Output Read cycle
High-Z High-Z —
Input Input Write cycle
Input High-Z Write cycle
High-Z Input Write cycle
High-Z High-Z —
Parameter Symbol Value Unit
Supply voltage relative to V
Voltage on any pin relative to V
SS
SS
Power dissipation P
V
CC
V
T
T
–0.5 to +4.6 V
–0.5*1 to VCC + 0.5*
2
V
1.0 W
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –40 to +85 °C
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
2. V
(max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns
T
4
HM62W16255HI Series
Recommended DC Operating Conditions (Ta = –40 to +85°C)
Parameter Symbol Min Typ Max Unit
3
Supply voltage V
Input voltage V
CC
VSS*
IH
V
IL
*
4
Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
2. V
(max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns
IH
3. The supply voltage with all V
4. The supply voltage with all V
pins must be on the same level.
CC
pins must be on the same level.
SS
DC Characteristics (Ta = –40 to +85°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
3.0 3.3 3.6 V
000V
2.2 — VCC + 0.5*2V
1
–0.5*
— 0.8 V
Parameter Symbol Min Typ*
Input leakage current |I
Output leakage
current*
Operating power
1
15 ns cycle I
|——2 µA Vin = VSS to V
LI
|ILO|——2 µA Vin = VSS to V
CC
— — 160 mA Min cycle
supply current
Standby power supply
15 ns cycle I
SB
— — 50 mA Min cycle, CS = VIH,
current
I
SB1
— 0.05 5 mA f = 0 MHz
1
Max Unit Test conditions
CS = V
Other inputs = V
Other inputs = V
V
≥ CS ≥ VCC – 0.2 V,
CC
CC
CC
, Iout = 0 mA
IL
IH/VIL
IH/VIL
(1) 0 V ≤ Vin ≤ 0.2 V or
Output voltage V
(2) V
OL
V
OH
— — 0.4 V IOL = 8 mA
2.4 — — V IOH = –4 mA
≥ Vin ≥ VCC – 0.2 V
CC
Note: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*
Input/output capacitance*
1
1
Note: 1. This parameter is sampled and not 100% tested.
Cin — — 6 pF Vin = 0 V
C
I/O
——8 pFV
= 0 V
I/O
5
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