HIT HM6216255HJP-10, HM6216255HJP-12, HM6216255HJP-15, HM6216255HLJP-10, HM6216255HLJP-12 Datasheet

HM6216255H Series

4M high Speed SRAM (256-kword × 16-bit)

ADE-203-763D (Z)

Rev. 1.0

Sep. 15, 1998

Description

The HM6216255H Series is a 4-Mbit high speed static RAM organized 256-k word × 16-bit. It has realized
high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high
speed circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged
in 400-mil 44-pin plastic SOJ and 400-mil 44-pin plastic TSOPII.

Features

• Single 5.0 Vsupply : 5.0 V ± 10 %

• Access time: 10/12/15 ns (max)

• Completely static memory
 No clock or timing strobe required

• Equal access and cycle times

• Directly TTL compatible
 All inputs and outputs

• Operating current: 200/180/160 mA (max)

• TTL standby current: 70/60/50 mA (max)

• CMOS standby current: 5 mA (max)

: 1.2 mA (max) (L-version)

• Data retansion current: 0.8 mA (max) (L-version)

• Data retantion voltage: 2 V (min) (L-version)

• Center VCC and VSS type pinout

HM6216255H Series

Ordering Information

Type No. Access time Package

HM6216255HJP-10
HM6216255HJP-12
HM6216255HJP-15

HM6216255HLJP-10
HM6216255HLJP-12
HM6216255HLJP-15

HM6216255HTT-10
HM6216255HTT-12
HM6216255HTT-15

HM6216255HLTT-10
HM6216255HLTT-12
HM6216255HLTT-15

Pin Arrangement

10 ns
12 ns
15 ns

10 ns
12 ns
15 ns

10 ns
12 ns
15 ns

10 ns
12 ns
15 ns

400-mil 44-pin plastic SOJ (CP-44D)

400-mil 44-pin plastic TSOPII (TTP-44DE)

HM6216255HJP/HLJP Series

A0
A1
A2
A3
A4

CS

I/O1
I/O2
I/O3
I/O4

V

CC

V

SS

I/O5
I/O6
I/O7
I/O8

WE

A5
A6
A7
A8
A9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A17
A16
A15

OE
UB
LB

I/O16
I/O15
I/O14
I/O13
V

SS

V

CC

I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10

(Top View)

HM6216255HTT/HLTT Series

1

I/O1
I/O2
I/O3
I/O4

V

V

I/O5
I/O6
I/O7
I/O8

WE

A0
A1
A2
A3
A4

CS

CC
SS

A5
A6
A7
A8
A9

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

(Top View)

A17
A16
A15

OE
UB
LB

I/O16
I/O15
I/O14
I/O13
V

SS

V

CC

I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10

2

HM6216255H Series

Pin Description

Pin name Function Pin name Function

A0 to A17 Address input UB Upper byte select
I/O1 to I/O16 Data input/output LB Lower byte select

CS Chip select V
OE Output enable V

CC

SS

WE Write enable NC No connection

Block Diagram

(LSB)

A1

A17

(MSB)

A7
A11
A16

A2

A6

A5

Row

decoder

Memory matrix

256 rows × 8 columns ×

128 blocks × 16 bit

(4,194,304 bits)

Power supply
Ground

generater

Internal
voltage

V

CC

V

SS

I/O1

.

.

.

I/O8
I/O9

.

.

.

I/O16

WE
CS

LB

UB

OE

CS

CS

Input

data

control

Column I/O

Column decoder

A10 A8 A9 A12 A13 A14 A0 A15 A3 A4

CS

3

HM6216255H Series

Operation Table

CS OE WE LB UB Mode VCC current I/O1–I/O8 I/O9–I/O16 Ref. cycle

H ××××Standby I
LHH××Output disable I
L L H L L Read I
L L H L H Lower byte read I
L L H H L Upper byte read I
L LHHH— I
L × L L L Write I
L × L L H Lower byte write I
L × L H L Upper byte write I
L × L HH— I

, I

SB

CC

CC

CC

CC

CC

CC

CC

CC

CC

Note: ×: H or L

Absolute Maximum Ratings

SB1

High-Z High-Z —
High-Z High-Z —
Output Output Read cycle
Output High-Z Read cycle
High-Z Output Read cycle
High-Z High-Z —
Input Input Write cycle
Input High-Z Write cycle
High-Z Input Write cycle
High-Z High-Z —

Parameter Symbol Value Unit

Supply voltage relative to V
Voltage on any pin relative to V

SS

SS

Power dissipation P

V

CC

V

T

T

–0.5 to +7.0 V
–0.5*1 to VCC + 0.5*

1.0*3/1.3*

4

2

V

W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C

Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns

2. V

(max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns

T

3. At still air condition

4. At air flow ≥ 1.0 m/s

4

HM6216255H Series

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter Symbol Min Typ Max Unit

2

Supply voltage V

Input voltage V

CC

VSS*

IH

V

IL

*

3

Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns

2. V

(max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns

IH

3. The supply voltage with all V

4. The supply voltage with all V

pins must be on the same level.

CC

pins must be on the same level.

SS

DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, VSS = 0 V)

4.5 5.0 5.5 V
000V

2.2 — VCC + 0.5*2V

1

–0.5*

— 0.8 V

Parameter Symbol Min Typ*

Input leakage current |I
Output leakage

current*
Operating power

1

10 ns cycle I

|——2 µA Vin = VSS to V

LI

|ILO|——2 µA Vin = VSS to V

CC

— — 200 mA CS = VIL, Iout = 0 mA

1

Max Unit Test conditions

supply current

Standby power supply

12 ns cycle I
15 ns cycle I
10 ns cycle I

CC

CC

SB

— — 180
— — 160
——70mACS = VIH,

current

12 ns cycle I
15 ns cycle I

Output voltage V

SB

SB

I

SB1

OL

V

OH

——60
——50
— 0.1 5 mA VCC ≥ CS ≥ VCC – 0.2 V,

—*

2

0.1*

2

1.2 *

2

— — 0.4 V IOL = 8 mA

2.4 — — V IOH = –4 mA

Note: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.

2. This characteristics is guaranteed only for L-version.

CC

CC

Other inputs = V

Other inputs = V

IH/VIL

IH/VIL

(1) 0 V ≤ Vin ≤ 0.2 V or
(2) V

≥ Vin ≥ VCC – 0.2 V

CC

5

HM6216255H Series

Capacitance (Ta = +25°C, f = 1.0 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance*
Input/output capacitance*

1

1

Note: 1. This parameter is sampled and not 100% tested.

Cin — — 6 pF Vin = 0 V
C

I/O

——8 pFV

= 0 V

I/O

6

HM6216255H Series

AC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, unless otherwise noted.)

Test Conditions

• Input pulse levels: 3.0 V/0.0 V

• Input rise and fall time: 3 ns

• Input and output timing reference levels: 1.5 V

• Output load: See figures (Including scope and jig)

5 V

Dout

Zo=50 Ω

RL=50 Ω

Dout

255Ω

5 pF

1.5 V

480Ω

Output load (A)

(for t

Output load (B)

, t

CLZ

OLZ

t

, t

LBHZ

, t

UBHZ

LBLZ

, t

, t

UBLZ

, and tOW)

WHZ

, t

, t

OHZ

,

CHZ

Read Cycle

HM6216255H

-10 -12 -15

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read cycle time t
Address access time t
Chip select access time t
Output enable to output valid t

RC

AA

ACS

OE

Byte select to output valid tLB, t
Output hold from address change t
Chip select to output in low-Z t
Output enable to output in low-Z t
Byte select to output in low-Z t
Chip deselect to output in high-Z t
Output disable to output in high-Z t
Byte deselect to output in high-Z t

OH

CLZ

OLZ

LBLZ

CHZ

OHZ

LBHZ

UB

, t

, t

10 — 12 — 15 — ns
—10—12—15ns
—10—12—15ns
—5 —6 —7 ns
—5 —6 —7 ns
3—3—3—ns
3—3—3—ns1
0—0—0—ns1
0—0—0—ns1

UBLZ

—5 —6 —7 ns1
—5 —6 —7 ns1
—5 —6 —7 ns1

UBHZ

7

HM6216255H Series

Write Cycle

HM6216255H

-10 -12 -15

Parameter Symbol Min Max Min Max Min Max Unit Notes

Write cycle time t
Address valid to end of write t
Chip select to end of write t
Write pulse width t
Byte select to end of write t
Address setup time t
Write recovery time t
Data to write time overlap t
Data hold from write time t
Write disable to output in low-Z t
Output disable to output in high-Z t
Write enable to output in high-Z t

WC

AW

CW

WP

LBW

AS

WR

DW

DH

OW

OHZ

WHZ

, t

Notes: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled

and not 100% tested.

2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the
WE transition, output remains a high impedance state.

3. WE and/or CS must be high during address transition time.

4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.

5. t

is measured from the latest address transition to the latest of CS, WE, LB or UB going low.

AS

6. t

is measured from the earliest of CS, WE, LB or UB going high to the first address transition.

WR

7. A write occurs during the overlap of low CS, low WE and low LB or low UB.

8. t

is measured from the later of CS going low to the end of write.

CW

9. t

is measured from the later of LB going low to the end of write.

LBW

10.t

is measured from the later of UB going low to the end of write.

UBW

10 — 12 — 15 — ns
7—8—10—ns
7—8—10—ns8
7—8—10—ns7
7 — 8 — 10 — ns 9, 10

UBW

0—0—0—ns5
0—0—0—ns6
5—6—7—ns
0—0—0—ns
3—3—3—ns1
—5 —6 —7 ns1
—5 —6 —7 ns1

8

Timing Waveforms

Read Timing Waveform (1) (WE = VIH)

HM6216255H Series

t

RC

Address

CS

OE

LB

UB

Dout

(Lower byte)

t

AA

High Impedance

Valid address

t

ACS

t

OE

t

LB

t

UB

t

LBLZ

4

*

t

UBLZ

t

OLZ

1

*

t

CHZ

1

t

*

OHZ

1

t

*

LBHZ

1

t

1

*

Valid data

1

*

1

*

UBHZ

t

OH

*

4

*

Dout

(Upper byte)

High Impedance

1

t

*

CLZ

4

*

Valid data

4

*

9

HM6216255H Series

Read Timing Waveform (2) (WE = VIH, LB = VIL, UB, = VIL)

t

RC

Address

CS

OE

Dout

(Lower/Upper

byte)

High Impedance

Valid address

t

AA

t

ACS

t

OLZ

t

CLZ

4

*

t

OH

1

t

*

CHZ

t

OE

1

*

1

*

Valid data

t

OHZ

1

*

4

*

10

Write Timing Waveform (1) (LB, UB Controlled)

t

HM6216255H Series

WC

Address

3

WE*

3

CS*

OE

LB

UB

Valid address

t

AW

t

AS

t

WP

t

CW

t

LBW

t

UBW

t

WHZ

t

WR

t

OLZ

Dout

(Lower byte)

Dout

(Upper byte)

Din

(Lower byte)

Din

(Upper byte)

t

OHZ

High impedance

High impedance

t

DW

t

DW

Valid data

Valid data

t

DH

t

OW

t

DH

11

HM6216255H Series

Write Timing Waveform (2) (WE Controlled)

t

WC

Address

3

WE*

3

CS*

OE

LB, UB

Dout

(Lower/Upper

byte)

Valid address

t

AW

t

AS

t

OHZ

t

WHZ

t

LBW

t

CW

t

WP

t

UBW

t

WR

t

t

OW

OLZ

High impedance

2

*

t

DW

t

DH

Din

(Lower/Upper

byte)

12

Valid data

Write Timing Waveform (3) (CS Controlled)

t

HM6216255H Series

WC

Address

3

WE

*

3

CS *

OE

LB, UB

Dout

(Lower/Upper

byte)

Valid address

t

AW

t

AS

t

WHZ

t

OHZ

t

LBW

t

WP

t

t

UBW

CW

High impedance

2

*

t

DW

t

WR

t

OLZ

t

OW

4

*

t

DH

Din

(Lower/Upper

byte)

Valid data

13

HM6216255H Series

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

This characteristics is guaranteed only for L-version.

Parameter Symbol Min Typ*1Max Unit Test conditions

for data retention V

V

CC

Data retention current I

Chip deselect to data retention time t
Operation recovery time t

DR

CCDR

CDR

R

Note: 1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.

Low VCC Data Retention Timing Waveform

2.0 — — V VCC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) V

≥ Vin ≥ VCC – 0.2 V

CC

— 50 800 µAVCC = 3 V

V

≥ CS ≥ VCC – 0.2 V,

CC

(1) 0 V ≤ Vin ≤ 0.2 V or
(2) V

≥ Vin ≥ VCC – 0.2 V

CC

0 — — ns See retention waveform
5 ——ms

V

CC

3.0 V

V

DR

2.2 V

CS

0 V

t

CDR

Data retention mode

VCC ≥ CS ≥ VCC – 0.2 V

t

R

14

Package Dimensions

HM6216255HJP/HLJP Series (CP-44D)

28.33

28.90 Max

44 23

10.16 ± 0.13

HM6216255H Series

Unit: mm

11.18 ± 0.13

122

0.74

1.30 Max

0.43 ± 0.10

0.41 ± 0.08

0.10

Dimension including the plating thickness

Base material dimension

1.27

3.50 ± 0.26

+0.25

–0.17

0.80

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

2.65 ± 0.12

9.40 ± 0.25

CP-44D
Conforms
—

1.8 g

15

HM6216255H Series

HM6216255HTT/HLTT Series (TTP-44DE)

18.41

18.81 Max

44 23

Unit: mm

10.16

122

0.27 ± 0.07

0.25 ± 0.05

0.80

0.13

M

1.005 Max

0.10

1.20 Max

Dimension including the plating thickness

Base material dimension

0.145 ± 0.05

0.125 ± 0.04

11.76 ± 0.20

0.13 ± 0.05

Hitachi Code
JEDEC
EIAJ
Weight

0° – 5°

0.50 ± 0.10

(reference value)

0.80

0.68

TTP-44DE
—
—

0.43 g

16

HM6216255H Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

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Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo [phone] Fax: [phone]

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For further information write to:

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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

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17