HIT HM621400HCJP-10, HM621400HCLJP-10 Datasheet

HM621400HC Series

4M High Speed SRAM (4-Mword × 1-bit)

ADE-203-1199 (Z)

Preliminary

Rev. 0.0

Nov. 30, 2000

Description

The HM621400HC is a 4-Mbit high speed static RAM organized 4-Mword × 1-bit. It has realized high speed
access time by employing CMOS process (6-transistor memory cell)and high speed circuit designing
technology. It is most appropriate for the application which requires high speed and high density memory,
such as cache and buffer memory in system. The HM621400HC is packaged in 400-mil 32-pin SOJ for high
density surface mounting.

Features

• Single 5.0 V supply: 5.0 V ± 10 %

• Access time: 10 ns (max)

• Completely static memory
 No clock or timing strobe required

• Equal access and cycle times

• Directly TTL compatible
 All inputs and outputs

• Operating current: 140 mA (max)

• TTL standby current: 40 mA (max)

• CMOS standby current: 5 mA (max)

: 1.2 mA (max) (L-version)

• Data retension current: 0.8 mA (max) (L-version)

• Data retension voltage: 2 V (min) (L-version)

• Center VCC and VSS type pinout

Preliminary: The specification of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specification.

HM621400HC Series

Ordering Information

Type No. Access time Package

HM621400HCJP-10 10 ns 400-mil 32-pin plastic SOJ (CP-32DB)
HM621400HCLJP-10 10 ns

2

Pin Arrangement

HM621400HC Series

32-pin SOJ

V

V

A10

Pin Description

Pin name Function

A0 to A21 Address input
Din Data input
Dout Data output

CS Chip select
OE Output enable
WE Write enable

V

CC

V

SS

NC No connection

Power supply
Ground

A0
A1
A2
A3
A4
A5

CS

CC

SS

Din

WE

A6
A7
A8
A9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

(Top view)

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

A21
A20
A19
A18
A17
A16

OE

V

SS

V

CC

Dout
A15
A14
A13
A12
A11
NC

3

HM621400HC Series

Block Diagram

(LSB)

A15
A14
A13

A6
A7

A8
A12
A11

A3

A1

(MSB)

Din

CS

Row

decoder

1024-row × 256-column ×

16-block × 1-bit

(4,194,304 bits)

Column I/O

Internal
voltage

generater

Dout

V

CC

V

SS

CS

WE

OE

(LSB)

CS

A9A10A21A19

Column decoder

A17

A20

A16A5

A0

A2A4

CS

A18

(MSB)

4

HM621400HC Series

Operation Table

CS OE WE Mode VCC current Dout Ref. cycle

H ××Standby I
L H H Output disable I
L L H Read I
L H L Write I
L L L Write I

, I

SB

SB1

CC

CC

CC

CC

Note: ×: H or L

Absolute Maximum Ratings

Parameter Symbol Value Unit

Supply voltage relative to V
Voltage on any pin relative to V

SS

SS

Power dissipation P
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C

Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) 6 ns.

2. V

(max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.

T

V

CC

V

T

T

High-Z —
High-Z —
Dout Read cycle (1) to (3)
High-Z Write cycle (1)
High-Z Write cycle (2)

–0.5 to +7.0 V
–0.5*1 to VCC+0.5*

2

V

1.0 W

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter Symbol Min Typ Max Unit

3

Supply voltage V

Input voltage V

CC

VSS*

IH

V

IL

*

4

Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) 6 ns.

2. V

(max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.

IH

3. The supply voltage with all V

4. The supply voltage with all V

4.5 5.0 5.5 V
000V

2.2 — VCC + 0.5*

1

–0.5*

pins must be on the same level.

CC

pins must be on the same level.

SS

— 0.8 V

2

V

5