Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
119and 209-Pin BGA
Commercial Temp
Industrial Temp
2M x 18, 1M x 36, 512K x 72 36Mb Sync NBT SRAMs
250 MHz–133MHz
2.5V or 3.3 V VDD
2.5V or 3.3 V I/O
Features
•NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
•FT pin for user-configurable flow through or pipeline operation
•IEEE 1149.1 JTAG-compatible Boundary Scan
•ZQ mode pin for user-selectable high/low output drive
•2.5 V or 3.3 V +10%/–5% core power supply
•2.5 V or 3.3 V I/O supply
•LBO pin for Linear or Interleaved Burst mode
•Byte Write (BW) and/or Global Write (GW) operation
•Internal self-timed write cycle
•Automatic power-down for portable applications
•JEDEC-standard 119and 209-bump BGA package
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-250 |
-225 -200 -166 -150 -133 |
Unit |
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Pipeline |
tKQ |
2.3 |
2.5 |
3.0 |
3.5 |
3.8 |
4.0 |
ns |
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3-1-1-1 |
tCycle |
4.0 |
4.4 |
5.0 |
6.0 |
6.6 |
7.5 |
ns |
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Curr (x18) |
365 |
335 |
305 |
265 |
245 |
215 |
mA |
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3.3 V |
Curr (x36) |
560 |
510 |
460 |
400 |
370 |
330 |
mA |
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Curr (x72) |
660 |
600 |
540 |
460 |
430 |
380 |
mA |
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Curr (x18) |
360 |
330 |
305 |
260 |
240 |
215 |
mA |
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2.5 V |
Curr (x36) |
550 |
500 |
460 |
390 |
360 |
330 |
mA |
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Curr (x72) |
640 |
590 |
530 |
450 |
420 |
370 |
mA |
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Flow |
tKQ |
6.0 |
6.5 |
7.5 |
8.5 |
10 |
11 |
ns |
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Through |
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tCycle |
7.0 |
7.5 |
8.5 |
10 |
10 |
15 |
ns |
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2-1-1-1 |
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Curr (x18) |
235 |
230 |
210 |
200 |
195 |
150 |
mA |
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3.3 V |
Curr (x36) |
300 |
300 |
270 |
270 |
270 |
200 |
mA |
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Curr (x72) |
350 |
350 |
300 |
300 |
300 |
220 |
mA |
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Curr (x18) |
235 |
230 |
210 |
200 |
195 |
145 |
mA |
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2.5 V |
Curr (x36) |
300 |
300 |
270 |
270 |
270 |
190 |
mA |
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Curr (x72) |
340 |
340 |
300 |
300 |
300 |
220 |
mA |
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with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8324Z18/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
Functional Description
Applications
The GS8324Z18/36/72 is a 37,748,736-bit high performance 2-die synchronous SRAM module with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge- triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated
Rev: 1.00 10/2001 |
1/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z72B Pad Out
209-Bump BGA—Top View
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1 |
2 |
3 |
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4 |
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5 |
6 |
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7 |
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8 |
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9 |
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10 |
11 |
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A |
DQG5 |
DQG1 |
A13 |
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E2 |
A14 |
ADV |
A15 |
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E3 |
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A17 |
DQB1 |
DQB5 |
A |
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B |
DQG6 |
DQG2 |
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BC |
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BG |
NC |
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W |
A16 |
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BB |
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BF |
DQB2 |
DQB6 |
B |
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C |
DQG7 |
DQG3 |
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BH |
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BD |
NC |
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E1 |
NC |
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BE |
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BA |
DQB3 |
DQB7 |
C |
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VSS |
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VSS |
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D |
DQG8 |
DQG4 |
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NC |
NC |
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G |
NC |
NC |
DQB4 |
DQB8 |
D |
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E |
DQPG9 |
DQPC9 |
VDDQ |
VDDQ |
VDD |
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VDD |
VDD |
VDDQ |
VDDQ |
DQPF9 |
DQPB9 |
E |
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F |
DQC4 |
DQC8 |
VSS |
VSS |
VSS |
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ZQ |
VSS |
VSS |
VSS |
DQF8 |
DQF4 |
F |
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G |
DQC3 |
DQC7 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
DQF7 |
DQF3 |
G |
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H |
DQC2 |
DQC6 |
VSS |
VSS |
VSS |
MCL |
VSS |
VSS |
VSS |
DQF6 |
DQF2 |
H |
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J |
DQC1 |
DQC5 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
DQF5 |
DQF1 |
J |
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K |
NC |
NC |
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CK |
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NC |
VSS |
MCL |
VSS |
NC |
NC |
NC |
NC |
K |
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VDDQ |
VDDQ |
VDD |
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VDD |
VDDQ |
VDDQ |
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L |
DQH1 |
DQH5 |
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FT |
DQA5 |
DQA1 |
L |
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M |
DQH2 |
DQH6 |
VSS |
VSS |
VSS |
MCL |
VSS |
VSS |
VSS |
DQA6 |
DQA2 |
M |
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N |
DQH3 |
DQH7 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
DQA7 |
DQA3 |
N |
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P |
DQH4 |
DQH8 |
VSS |
VSS |
VSS |
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ZZ |
VSS |
VSS |
VSS |
DQA8 |
DQA4 |
P |
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R |
DQPD9 |
DQPH9 |
VDDQ |
VDDQ |
VDD |
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VDD |
VDD |
VDDQ |
VDDQ |
DQPA9 |
DQPE9 |
R |
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VSS |
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VSS |
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T |
DQD8 |
DQD4 |
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NC |
NC |
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LBO |
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PE |
NC |
DQE4 |
DQE8 |
T |
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U |
DQD7 |
DQD3 |
NC |
A12 |
NC |
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A11 |
A18 |
A10 |
NC |
DQE3 |
DQE7 |
U |
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V |
DQD6 |
DQD2 |
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A9 |
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A8 |
A7 |
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A1 |
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A6 |
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A5 |
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A4 |
DQE2 |
DQE6 |
V |
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W |
DQD5 |
DQD1 |
TMS |
TDI |
A3 |
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A0 |
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A2 |
TDO |
TCK |
DQE1 |
DQE5 |
W |
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.00 10/2001 |
2/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z36C Pad Out
209-Bump BGA—Top View
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1 |
2 |
3 |
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4 |
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5 |
6 |
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7 |
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8 |
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9 |
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10 |
11 |
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A |
NC |
NC |
A13 |
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E2 |
A14 |
ADV |
A15 |
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E3 |
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A17 |
DQB1 |
DQB5 |
A |
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B |
NC |
NC |
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BC |
NC |
A19 |
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W |
A16 |
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BB |
NC |
DQB2 |
DQB6 |
B |
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C |
NC |
NC |
NC |
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BD |
NC |
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E1 |
NC |
NC |
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BA |
DQB3 |
DQB7 |
C |
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VSS |
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VSS |
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D |
NC |
NC |
NC |
NC |
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G |
NC |
NC |
DQB4 |
DQB8 |
D |
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E |
NC |
DQPC9 |
VDDQ |
VDDQ |
VDD |
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VDD |
VDD |
VDDQ |
VDDQ |
NC |
DQPB9 |
E |
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F |
DQC4 |
DQC8 |
VSS |
VSS |
VSS |
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ZQ |
VSS |
VSS |
VSS |
NC |
NC |
F |
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G |
DQC3 |
DQC7 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
NC |
NC |
G |
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H |
DQC2 |
DQC6 |
VSS |
VSS |
VSS |
MCL |
VSS |
VSS |
VSS |
NC |
NC |
H |
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J |
DQC1 |
DQC5 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
NC |
NC |
J |
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K |
NC |
NC |
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CK |
NC |
VSS |
MCL |
VSS |
NC |
NC |
NC |
NC |
K |
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VDDQ |
VDDQ |
VDD |
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VDD |
VDDQ |
VDDQ |
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L |
NC |
NC |
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FT |
DQA5 |
DQA1 |
L |
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M |
NC |
NC |
VSS |
VSS |
VSS |
MCL |
VSS |
VSS |
VSS |
DQA6 |
DQA2 |
M |
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N |
NC |
NC |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
DQA7 |
DQA3 |
N |
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P |
NC |
NC |
VSS |
VSS |
VSS |
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ZZ |
VSS |
VSS |
VSS |
DQA8 |
DQA4 |
P |
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R |
DQPD9 |
NC |
VDDQ |
VDDQ |
VDD |
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VDD |
VDD |
VDDQ |
VDDQ |
DQPA9 |
NC |
R |
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VSS |
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VSS |
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T |
DQD8 |
DQD4 |
NC |
NC |
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LBO |
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PE |
NC |
NC |
NC |
T |
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U |
DQD7 |
DQD3 |
NC |
A12 |
NC |
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A11 |
A18 |
A10 |
NC |
NC |
NC |
U |
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V |
DQD6 |
DQD2 |
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A9 |
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A8 |
A7 |
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A1 |
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A6 |
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A5 |
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A4 |
NC |
NC |
V |
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W |
DQD5 |
DQD1 |
TMS |
TDI |
A3 |
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A0 |
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A2 |
TDO |
TCK |
NC |
NC |
W |
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.00 10/2001 |
3/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18C Pad Out
209-Bump BGA—Top View
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1 |
2 |
3 |
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4 |
5 |
6 |
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7 |
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8 |
9 |
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10 |
11 |
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A |
NC |
NC |
A13 |
VDD |
A14 |
ADV |
A15 |
VSS |
A17 |
NC |
NC |
A |
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B |
NC |
NC |
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BB |
NC |
A19 |
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W |
A16 |
NC |
NC |
NC |
NC |
B |
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C |
NC |
NC |
NC |
NC |
NC |
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E1 |
A20 |
NC |
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BA |
NC |
NC |
C |
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VSS |
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VSS |
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D |
NC |
NC |
NC |
NC |
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G |
NC |
NC |
NC |
NC |
D |
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E |
NC |
DQPB9 |
VDDQ |
VDDQ |
VDD |
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VDD |
VDD |
VDDQ |
VDDQ |
NC |
NC |
E |
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F |
DQB4 |
DQB8 |
VSS |
VSS |
VSS |
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ZQ |
VSS |
VSS |
VSS |
NC |
NC |
F |
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G |
DQB3 |
DQB7 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
NC |
NC |
G |
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H |
DQB2 |
DQB6 |
VSS |
VSS |
VSS |
MCL |
VSS |
VSS |
VSS |
NC |
NC |
H |
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J |
DQB1 |
DQB5 |
VDDQ |
VDDQ |
VDD |
MCH |
VDD |
VDDQ |
VDDQ |
NC |
NC |
J |
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K |
NC |
NC |
CK |
NC |
VSS |
MCL |
VSS |
NC |
NC |
NC |
NC |
K |
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VDDQ |
VDDQ |
VDD |
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VDD |
VDDQ |
VDDQ |
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L |
NC |
NC |
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FT |
DQA5 |
DQA1 |
L |
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M |
NC |
NC |
VSS |
VSS |
VSS |
MCL |
VSS |
VSS |
VSS |
DQA6 |
DQA2 |
M |
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N |
NC |
NC |
VDDQ |
VDDQ |
VDD |
VDD |
VDD |
VDDQ |
VDDQ |
DQA7 |
DQA3 |
N |
|||||||||||||||
P |
NC |
NC |
VSS |
VSS |
VSS |
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|
ZZ |
VSS |
VSS |
VSS |
DQA8 |
DQA4 |
P |
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R |
NC |
NC |
VDDQ |
VDDQ |
VDD |
|
VDD |
VDD |
VDDQ |
VDDQ |
DQPA9 |
NC |
R |
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VSS |
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VSS |
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T |
NC |
NC |
NC |
NC |
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LBO |
|
PE |
NC |
NC |
NC |
T |
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U |
NC |
NC |
NC |
A12 |
NC |
|
A11 |
A18 |
A10 |
NC |
NC |
NC |
U |
||||||||||||||
V |
NC |
NC |
|
A9 |
A8 |
A7 |
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|
A1 |
|
A6 |
A5 |
|
A4 |
NC |
NC |
V |
||||||||||
W |
NC |
NC |
TMS |
TDI |
A3 |
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|
A0 |
|
A2 |
TDO |
TCK |
NC |
NC |
W |
||||||||||||
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.00 10/2001 |
4/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 209-Bump BGA Pin Description
|
Pin Location |
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Symbol |
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Type |
Description |
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W6, V6 |
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A0, A1 |
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I |
Address field LSBs and Address Counter Preset Inputs. |
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W7, W5, V9, V8, V7, V5, V4, V3, U8, U6, U4, |
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An |
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I |
Address Inputs |
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A3, A5, A7, B7, A9, U7 |
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B5 |
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A19 |
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I |
Address Inputs (x36/x18 Versions) |
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C7 |
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A20 |
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I |
Address Inputs (x18 Version) |
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L11, M11, N11, P11, L10, M10, N10, P10, R10 |
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DQA1–DQA9 |
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A10, B10, C10, D10, A11, B11, C11, D11, E11 |
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DQB1–DQB9 |
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J1, H1, G1, F1, J2, H2, G2, F2, E2 |
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DQC1–DQC9 |
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W2, V2, U2, T2, W1, V1, U1, T1, R1 |
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DQD1–DQD9 |
|
I/O |
Data Input and Output pins (x72 Version) |
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W10, V10, U10, T10, W11, V11, U11, T11, R11 |
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DQE1–DQE9 |
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J11, H11, G11, F11, J10, H10, G10, F10, E10 |
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DQF1–DQF9 |
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A2, B2, C2, D2, A1, B1, C1, D1, E1 |
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DQG1–DQG9 |
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L1, M1, N1, P1, L2, M2, N2, P2, R2 |
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DQH1–DQH9 |
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L11, M11, N11, P11, L10, M10, N10, P10, R10 |
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DQA1–DQA9 |
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A10, B10, C10, D10, A11, B11, C11, D11, E11 |
|
DQB1–DQB9 |
|
I/O |
Data Input and Output pins (x36 Version) |
|||||||||||
|
J1, H1, G1, F1, J2, H2, G2, F2, E2 |
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DQC1–DQC9 |
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|||||||||||||
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W2, V2, U2, T2, W1, V1, U1, T1, R1 |
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DQD1–DQD9 |
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L11, M11, N11, P11, L10, M10, N10, P10, R10 |
|
DQA1–DQA9 |
|
I/O |
Data Input and Output pins (x18 Version) |
|||||||||||
|
J1, H1, G1, F1, J2, H2, G2, F2, E2 |
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DQB1–DQB9 |
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C9, B8 |
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I |
Byte Write Enable for DQA, DQB I/Os; active low |
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BA, BB |
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B3, C4 |
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I |
Byte Write Enable for DQC, DQD I/Os; active low |
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BC,BD |
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(x72/x36 Versions) |
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C8, B9, B4, C3 |
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I |
Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low |
|
|
BE, BF, BG,BH |
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||||||||||||||
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|
(x72 Version) |
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B5 |
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NC |
|
— |
No Connect (x72 Version) |
||||||||
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||||||||
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C7 |
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NC |
|
— |
No Connect (x72/x36 Versions) |
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W10, V10, U10, T10, W11, V11, U11, T11, R11 |
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J11, H11, G11, F11, J10, H10, G10, F10, E10 |
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A2, B2, C2, D2, A1, B1, C1, D1, E1 |
|
|
|
|
NC |
|
— |
No Connect (x36/x18 Versions) |
||||||||
|
L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9, |
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B4, C3 |
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B3, C4 |
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NC |
|
— |
No Connect (x18 Version) |
||||||||
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C5, D4, D5, D7, D8, K1, K2, K4, K8, K9, K10, |
|
|
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NC |
|
— |
No Connect |
||||||||
|
K11, T4, T5, T7, T8, U3, U5, U9 |
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||||||||
|
K3 |
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|
CK |
|
I |
Clock Input Signal; active high |
||||||||
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||||||
|
C6 |
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|
I |
Chip Enable; active low |
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E1 |
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|||||||||||
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||||||
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A8 |
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|
I |
Chip Enable; active low (x72/x36 Versions) |
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|
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E3 |
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|||||||||||
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||||||||
|
A4 |
|
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|
E2 |
|
I |
Chip Enable; active high (x72/x36 Versions) |
||||||||
|
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|||||||
|
D6 |
|
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|
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|
|
|
|
I |
Output Enable; active low |
|
|
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|
G |
|
||||||||||
|
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|
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|||||||||
|
A6 |
|
|
|
ADV |
|
I |
Burst address counter advance enable |
|||||||||
|
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|
|
Rev: 1.00 10/2001 |
5/46 |
|
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 209-Bump BGA Pin Description
Pin Location |
Symbol |
Type |
Description |
||||||
|
|
|
|
|
|
||||
|
|
|
|
|
|
||||
P6 |
|
|
ZZ |
I |
Sleep Mode control; active high |
||||
|
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|
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|
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|
|
L6 |
|
|
|
|
|
|
|
I |
Flow Through or Pipeline mode; active low |
|
|
FT |
|||||||
|
|
|
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|
|
T6 |
|
|
|
|
|
|
|
I |
Linear Burst Order mode; active low |
|
LBO |
||||||||
|
|
|
|
||||||
G6, J6 |
MCH |
I |
Must Connect High |
||||||
|
|
|
|
||||||
N6 |
MCH |
I |
Must Connect High (x72 and x36 versions) |
||||||
|
|
|
|
||||||
H6, J6, K6, M6 |
MCL |
|
Must Connect Low |
||||||
|
|
|
|
||||||
A8, N6 |
MCL |
|
Must Connect Low (x18 version) |
||||||
|
|
|
|
|
|
|
|
||
B6 |
|
|
|
|
|
|
|
I |
Write Enable; active low |
|
|
|
W |
||||||
|
|
|
|
|
|
|
|
|
|
T7 |
|
|
|
|
|
|
|
I |
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 |
|
|
PE |
|||||||
|
|
Mode) |
|||||||
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FLXDrive Output Impedance Control |
F6 |
|
ZQ |
I |
(Low = Low Impedance [High Drive], High = High Impedance [Low |
|||||
|
|
|
|
|
|
|
|
|
Drive]) |
|
|
|
|
||||||
W3 |
TMS |
I |
Scan Test Mode Select |
||||||
|
|
|
|
|
|||||
W4 |
|
TDI |
I |
Scan Test Data In |
|||||
|
|
|
|
||||||
W8 |
TDO |
O |
Scan Test Data Out |
||||||
|
|
|
|
|
|||||
W9 |
|
TCK |
I |
Scan Test Clock |
|||||
|
|
|
|
|
|||||
A4, N6 |
|
VDD |
I |
Core power supply (x18 version) |
|||||
E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5, |
|
VDD |
I |
Core power supply |
|||||
R6, R7 |
|
||||||||
D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7, |
|
VSS |
|
|
|||||
H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3, |
|
I |
I/O and Core Ground |
||||||
P4, P5, P7, P8, P9, T3, T9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9, |
VDDQ |
I |
Output driver power supply |
||||||
L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 |
Rev: 1.00 10/2001 |
6/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z36B Pad Out
119-Bump BGA—Top View
|
|
1 |
2 |
3 |
|
|
4 |
|
|
5 |
|
6 |
|
7 |
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
A |
VDDQ |
A6 |
|
A7 |
A18 |
|
A8 |
|
A9 |
|
VDDQ |
A |
||||||||||||
B |
NC |
E2 |
|
A4 |
ADV |
A15 |
|
E3 |
NC |
B |
||||||||||||||
C |
NC |
A5 |
|
A3 |
VDD |
A14 |
A16 |
NC |
C |
|||||||||||||||
D |
DQC |
DQPC |
VSS |
ZQ |
VSS |
DQPB |
DQB |
D |
||||||||||||||||
E |
DQC |
DQC |
VSS |
|
E1 |
|
VSS |
DQB |
DQB |
E |
||||||||||||||
F |
VDDQ |
DQC |
VSS |
|
|
G |
|
VSS |
DQB |
VDDQ |
F |
|||||||||||||
|
|
|
|
|
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|
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|
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|
|
|
|
|
|
|
|
|
||||
G |
DQC |
DQC |
|
BC |
A17 |
|
BB |
DQB |
DQB |
G |
||||||||||||||
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|||||||
H |
DQC |
DQC |
VSS |
|
|
W |
VSS |
DQB |
DQB |
H |
||||||||||||||
J |
VDDQ |
VDD |
NC |
VDD |
NC |
VDD |
VDDQ |
J |
||||||||||||||||
K |
DQD |
DQD |
VSS |
CK |
VSS |
DQA |
DQA |
K |
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
L |
DQD |
DQD |
|
BD |
NC |
|
BA |
DQA |
DQA |
L |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
M |
VDDQ |
DQD |
VSS |
CKE |
VSS |
DQA |
VDDQ |
M |
||||||||||||||||
N |
DQD |
DQD |
VSS |
|
A1 |
VSS |
DQA |
DQA |
N |
|||||||||||||||
P |
DQD |
DQPD |
VSS |
|
|
A0 |
VSS |
DQPA |
DQA |
P |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
R |
NC |
A2 |
LBO |
VDD |
|
FT |
A13 |
|
PE |
R |
||||||||||||||
T |
NC |
NC |
A10 |
A11 |
A12 |
A19 |
|
ZZ |
T |
|||||||||||||||
U |
|
VDDQ |
TMS |
TDI |
TCK |
TDO |
NC |
VDDQ |
U |
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.00 10/2001 |
7/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18B Pad Out
119-Bump BGA—Top View
|
|
1 |
2 |
3 |
|
|
4 |
|
|
|
5 |
|
6 |
7 |
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||
A |
VDDQ |
A6 |
|
A7 |
|
A18 |
|
A8 |
A9 |
VDDQ |
A |
|||||||||||||
B |
NC |
VDD |
|
A4 |
|
ADV |
A15 |
VSS |
NC |
B |
||||||||||||||
C |
NC |
A5 |
|
A3 |
|
VDD |
A14 |
A16 |
NC |
C |
||||||||||||||
D |
DQB |
NC |
VSS |
|
ZQ |
VSS |
DQPA |
NC |
D |
|||||||||||||||
E |
NC |
DQB |
VSS |
|
|
E1 |
|
VSS |
NC |
DQA |
E |
|||||||||||||
F |
VDDQ |
NC |
VSS |
|
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G |
|
VSS |
DQA |
VDDQ |
F |
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G |
NC |
DQB |
|
BB |
|
A17 |
NC |
NC |
DQA |
G |
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H |
DQB |
NC |
VSS |
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W |
VSS |
DQA |
NC |
H |
|||||||||||||
J |
VDDQ |
VDD |
NC |
|
VDD |
NC |
VDD |
VDDQ |
J |
|||||||||||||||
K |
NC |
DQB |
VSS |
|
CK |
VSS |
NC |
DQA |
K |
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|||||||
L |
DQB |
NC |
NC |
VDD |
|
BA |
DQA |
NC |
L |
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M |
VDDQ |
DQB |
VSS |
|
CKE |
VSS |
NC |
VDDQ |
M |
|||||||||||||||
N |
DQB |
NC |
VSS |
|
|
A1 |
VSS |
DQA |
NC |
N |
||||||||||||||
P |
NC |
DQPB |
VSS |
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A0 |
VSS |
NC |
DQA |
P |
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R |
NC |
A2 |
LBO |
|
VDD |
|
FT |
A13 |
|
PE |
R |
|||||||||||||
T |
NC |
A10 |
A11 |
|
A20 |
A12 |
A19 |
|
ZZ |
T |
||||||||||||||
U |
|
VDDQ |
TMS |
TDI |
|
TCK |
TDO |
NC |
VDDQ |
U |
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.00 10/2001 |
8/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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|
Preliminary |
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|
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C) |
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|
GS8324Z18/36 119-Bump BGA Pin Description |
||||||||||
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|
||||
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Pin Location |
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Symbol |
Type |
|
Description |
|
||||
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P4, N4 |
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A0, A1 |
I |
|
Address field LSBs and Address Counter Preset Inputs |
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||
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R2, C3, B3, C2, A2, A3, A5, A6, T3, |
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An |
I |
|
Address Inputs |
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||
|
T5, R6, C5, B5, C6, G4, A4 |
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T4, T6 |
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An |
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Address Input (x36 Version) |
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T2 |
|
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NC |
— |
|
No Connect (x36 Version) |
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T2, T6, T4 |
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An |
I |
|
Address Input (x18 Version) |
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||||
|
K7, L7, N7, P7, K6, L6, M6, N6 |
|
DQA1–DQA8 |
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|
||||
|
H7, G7, E7, D7, H6, G6, F6, E6 |
|
DQB1–DQB8 |
I/O |
|
Data Input and Output pins. (x36 Version) |
|
||||
|
H1, G1, E1, D1, H2, G2, F2, E2 |
|
DQC1–DQC8 |
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||||||
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||||||
|
K1, L1, N1, P1, K2, L2, M2, N2 |
|
DQD1–DQD8 |
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||||
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||
|
P6, D6, D2, P2 |
|
DQA9, DQB9, |
I/O |
|
Data Input and Output pins. (x36 Version) |
|
||||
|
|
DQC9, DQD9 |
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|||||||
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||
|
L5, G5, G3, L3 |
|
BA, BB, BC, BD |
I |
|
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version) |
|
||||
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|
||||
|
P7, N6, L6, K7, H6, G7, F6, E7, D6 |
|
DQA1–DQA9 |
I/O |
|
Data Input and Output pins (x18 Version) |
|
||||
|
D1, E2, G2, H1, K2, L1, M2, N1, P2 |
|
DQB1–DQB9 |
|
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||||||
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||||||
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L5, G3 |
|
BA, BB |
I |
|
Byte Write Enable for DQA, DQB I/Os; active low (x18 Version) |
|
||
|
|
|
|
|
|
|
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|
|||
|
B1, C1, R1, T1, U6, B7, C7, J3, J5 |
|
|
NC |
— |
|
No Connect |
|
|||
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|
||
|
P6, N7, M6, L7, K6, H7, G6, E6, D7, |
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|
||
|
D2, E1, F2, G1, H2, K1, L2, N2, P1, |
|
|
NC |
— |
|
No Connect (x18 Version) |
|
|||
|
|
|
G5, L3 |
|
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L4 |
|
|
NC |
— |
|
No Connect (x36 Version) |
|
|
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|
|
|
|
|
|
K4 |
|
|
CK |
I |
|
Clock Input Signal; active high |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
M4 |
|
CKE |
I |
|
Clock Enable; active low |
|
||
|
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|
|
|
|
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|
|
|
H4 |
|
|
|
W |
I |
|
Write Enable; active low |
|
|
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|
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|
|
E4 |
|
|
|
E1 |
I |
|
Chip Enable; active low |
|
|
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|
|
|
B6 |
|
|
|
E3 |
I |
|
Chip Enable; active low (x36 version) |
|
|
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|
|
B2 |
|
|
|
E2 |
I |
|
Chip Enable; active high (x36 version) |
|
|
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|
|
F4 |
|
|
|
G |
I |
|
Output Enable; active low |
|
|
|
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|
||
|
|
|
B4 |
|
ADV |
I |
|
Burst address counter advance enable |
|
||
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|
|
T7 |
|
|
|
ZZ |
I |
|
Sleep mode control; active high |
|
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|
|
R5 |
|
|
|
FT |
I |
|
Flow Through or Pipeline mode; active low |
|
|
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|
|
|
R3 |
|
LBO |
I |
|
Linear Burst Order mode; active low |
|
||
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D4 |
|
|
ZQ |
I |
|
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], |
|
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|
|
|
High = High Impedance [Low Drive]) |
|
||||
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R7 |
|
|
PE |
I |
|
Parity Bit Enable; active low |
|
|
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|
||
|
|
|
U2 |
|
TMS |
I |
|
Scan Test Mode Select |
|
||
|
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|
||
|
|
|
U3 |
|
TDI |
I |
|
Scan Test Data In |
|
||
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|
Rev: 1.00 10/2001 |
|
|
|
9/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
|
|
|
|
|
|
|
Preliminary |
|
|
|
|
|
|
|
|
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C) |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
GS8324Z18/36 119-Bump BGA Pin Description |
|
|
|||||
|
|
|
|
|
|
|
||
|
Pin Location |
Symbol |
Type |
|
Description |
|
||
|
|
|
|
|
|
|
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|
U5 |
TDO |
O |
|
Scan Test Data Out |
|
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|
|
U4 |
TCK |
I |
|
Scan Test Clock |
|
|
|
|
|
|
|
|
||
|
J2, C4, J4, R4, J6 |
VDD |
I |
|
Core power supply |
|
||
|
|
|
B2, L4 |
VDD |
I |
|
Core power supply (x18 version) |
|
|
D3, E3, F3, H3, K3, M3, N3, P3, D5, |
VSS |
I |
|
I/O and Core Ground |
|
||
|
E5, F5, H5, K5, M5, N5, P5 |
|
|
|||||
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|
|||
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|
B6 |
VSS |
I |
|
I/O and Core Ground (x18 version) |
|
|
A1, F1, J1, M1, U1, A7, F7, J7, M7, |
VDDQ |
I |
|
Output driver power supply |
|
||
|
|
|
U7 |
|
|
|||
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|
|
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|
|
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|
|
|
Rev: 1.00 10/2001 |
10/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 Block Diagram
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Register |
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||||||||||||||
A0–An |
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D Q |
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A0 |
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|||||||||||||||||||
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A0 |
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D0 |
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Q0 |
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A1 |
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|||||||
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A1 |
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D1 |
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Q1 |
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Counter |
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|||||
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Load |
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LBO |
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ADV |
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|||||
CK |
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ADSC |
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ADSP |
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GW |
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Register |
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BW |
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BA |
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Register |
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BB |
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Register |
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D |
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BC |
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Register |
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BD |
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Register |
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D |
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Register
E1 D Q
Register
D Q
FT
G
Power Down
ZZ
Control
A
Memory
|
Array |
Q |
D |
36 |
36 |
|
4 |
Register Q D |
Register D Q |
|
36 |
|
36 |
36
36
DQx0–DQx9
Note: Only x36 version shown for simplicity.
Rev: 1.00 10/2001 |
11/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
|
|
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|
Preliminary |
|
|
|
|
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C) |
|||
GS8324Z18 Die Layout |
|
|
Inputs |
|
|
|
|
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|
||
TDI |
Die A |
TDO |
TDI |
Die B |
TDO |
|
x18 |
x18 |
|||||
|
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|
|||
|
16Mb |
|
|
16Mb |
|
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|
|
18 I/Os |
|
|
GS8324Z36 Die Layout |
|
|
Inputs |
|
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|
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|
||
TDI |
Die A |
TDO |
TDI |
Die B |
TDO |
|
x18 |
x18 |
|||||
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|||
|
16Mb |
|
|
16Mb |
|
|
|
18 I/Os |
|
|
18 I/Os |
|
GS8324Z72 Die Layout |
|
|
Inputs |
|
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|
||
TDI |
Die A |
TDO |
TDI |
Die B |
TDO |
|
x36 |
x36 |
|||||
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|||
|
32Mb |
|
|
32Mb |
|
|
|
36 I/Os |
|
|
36 I/Os |
|
Rev: 1.00 10/2001 |
12/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device.
|
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Function |
|
W |
|
BA |
|
BB |
|
BC |
|
BD |
|||||
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Read |
|
H |
|
X |
|
X |
|
X |
|
X |
|||||
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|
|
Write Byte “a” |
|
L |
|
L |
|
H |
|
H |
|
H |
|||||
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Write Byte “b” |
|
L |
|
H |
|
L |
|
H |
|
H |
|||||
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|
Write Byte “c” |
|
L |
|
H |
|
H |
|
L |
|
H |
|||||
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Write Byte “d” |
|
L |
|
H |
|
H |
|
H |
|
L |
|||||
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|
Write all Bytes |
|
L |
|
L |
|
L |
|
L |
|
L |
|||||
|
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|
Write Abort/NOP |
|
L |
|
H |
|
H |
|
H |
|
H |
|||||
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Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.
Rev: 1.00 10/2001 |
13/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Byte Write Truth Table
|
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|
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|
|
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|
|
Function |
|
GW |
|
BW |
|
BA |
|
BB |
|
BC |
|
BD |
Notes |
||||||
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Read |
|
H |
|
H |
|
X |
|
X |
|
X |
|
X |
1 |
||||||
|
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Read |
|
H |
|
L |
|
H |
|
H |
|
H |
|
H |
1 |
||||||
|
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|
|
Write byte a |
|
H |
|
L |
|
L |
|
H |
|
H |
|
H |
2, 3 |
||||||
|
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|
|
Write byte b |
|
H |
|
L |
|
H |
|
L |
|
H |
|
H |
2, 3 |
||||||
|
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|
|
Write byte c |
|
H |
|
L |
|
H |
|
H |
|
L |
|
H |
2, 3, 4 |
||||||
|
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|
Write byte d |
|
H |
|
L |
|
H |
|
H |
|
H |
|
L |
2, 3, 4 |
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Write all bytes |
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H |
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L |
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L |
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L |
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L |
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L |
2, 3, 4 |
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Write all bytes |
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L |
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X |
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X |
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X |
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X |
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X |
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Notes:
1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2.Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4.Bytes “C” and “D” are only available on the x36 version.
Rev: 1.00 10/2001 |
14/46 |
© 2001, Giga Semiconductor, Inc. |
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.