Goodmans GDVX-580 Service manual

- GDVX580

GDVX580

Service Manual

CONTENTS :

1.INFORMATIONS……………………………………………………………………………….3 Vibratto-II DVD Processor (ESS 66x8)

2. OPERATING INSTRUCTIONS……………………………………………………………..14

3. PRODUCT SPECIFICATIONS……………………………………………………………...24

4. TROUBLESHOOTING……………………………………………………………………….25

5. MAINTENANCE INSTRUCTIONS……………………………………………………..…..26

6. ELECTRICAL PART LIST…………………………………………………………………..35

7. DISASSEMBLY AND REASSEMBLY……………………………………………………..43

8. CIRCUIT DIAGRAMS………………………………………………………………………..44

9. WIRING DIAGRAM…………………………………………………………………………..49

1. INFORMATIONS Vibratto-II DVD Processor (ESS 66x8)

Vibratto-II DVD Processor

FEATURES:

 Single-chip DVD processoe incorporating all front-end and back-end functions  Unified memory architecture  Proven focusing, sledding, tracking, and CLV/CAV spindke servo control  Proven ESS, EFM,?EFM+ demodulation, and EDC circuit  Built-in ADCs and DACs for servo control signals  Direct interface to ES6603 servo AFE chip  Integrated NTSC/PAL encode with pixel-adaptive de-interlacer and five 10-bit 54MHz video DACs  DVD-video, DVD-VR, VCD1.1 and 2.0, and SVCD  DivX and MPEG-4 Advanced Simple profile at full screen(D1)  Full DVD-audio support including MLP and LPCM decode, CPPM decryption, and watermark

detection

 Media playback with CD-ROM, CD-R/RW, DVD-R/RW, and DVD+R/RW  Up to 7.1 channel audio outputs  Direct interface of 16 bit DRAM up to 128Mb capacity  Direct interface for up to 4 banks of 8-bit EPROM or FLASH EPROM for up to 4MB per bank  Macrovision 7.1 for NTSC/PAL (480p/576p) progressie scan video  Simultaneous composite,S-video and YUV output  CCIR656/601 yuv 4:2:2 output  OSD controller supports 256 colors in 8 degrees of transparency  Subpicture Unit(SPU) decoder supports karaoke iyric,subtitles,and EIA-608 compliant Line 21

Captioning.

 SmartBrght™ for clear and bright movie presentation.  SmartColor™ for vivid flesh-tone image display.  SmartLogo™ for custom JPEG wallpaper.  JPEG digital photo CD support (Kodak Picture CD™ and Fujifilm FujiColor CD™.  ESS Music Slideshor™.  Bass management.  Dolby Digital(AC-3),Dolby ProLogic™,and ProLogicll.  DTS™surround(ES6698D only).  S/PDIF digital audio input and output.  MPEG AAC and Multichannel.  SRS TruSurround  Professional karaoke with full scoring scheme.

Functional Description:

The internal block digram for ESS 6698

Pinout Diagram

ES6698 PIN DEXCRIPTION

Names Pin Numbers I/P Definitions

VD33

1.10.19.35.44.53.6

2.79.96.126.185.

P I/O power supply.

VID_XI 2 I Crystal input. VID_XO 3 O Crystal output. VID_XO 3 O Crystal output. CLK 4 I System clock. DMA[11:0] 5:8 11:17 20 O DRAM address bus.

9.18.34.43.52.61.7

VX33

95.119.127.186.20

8. G Ground for I/O power supply.

8 DCAS# 21 O DRAM column address strobe (active-low). DCS[1:0]# 22.23 O DRAM chip select (active-low). DRAS[2:0]# 24.25.28 O DRAM row address strobe (active-low). VSS 26.70.86.137.197 G Ground for core power supply. VDD 27.71.87.138.198 P Core power supply. DSCK_EN O DRAM clock enable output . DOE#

O DRAM output enable(active-low). DWE# 30 O DRAM write enable(active-low). DB[15:0] 31:33,36:42,45:50 I/O DRAM data bus. DSCK 51 O Output clock to DRAM. DQM 54 O Data input/output mask.

LA[21:0]

55:60,63:69,72:77

80:82

O RISC port address bus .

LCS[3:0]# 83:85 88 O RISC port chip select (active-low). LWRLL# 89 O RISC port low-byte write enable(active-low). LOE# 90 O RISC port output enable (active-low). LD[7:0] 91:94,97:100 I/O RISC port data bus; (5V tolerant input). RSD 101 I Audio receive serial data; (5V tolerant input ). RBCK 102 I Audio receive bit clock; (5V tolerant input ). RWS 103 I Audio receive frame sync; (5V tolerant input ). VD33_PL 104 P Power for PLL blocks. VS33_PL 105 G Ground for PLL blocks. VREF I Internal voltage reference to video DAC. YUV1 COMP I Compensation input . YUV3 RSET I DAC current adjustment resistor input . YUV4 FDAC

106

107

108

109

O YUV pixel 1 output data .

O YUV pixel 3 output data .

O YUV pixel 4 output data.

Video DAC output. Refer to description and matrix for

UDAC pin 115.

YUV7 O YUV pixel 7 output data . VDAC

110

YUV6

Video DAC output . Refer to description and matrix for

UDAC pin 115.

O YUV pixel 6 output data.

Names Pin Numbers I/P Definitions VD33_DA 111 P Power for I/O power supply for VDAC. VS33-DA 112 G Ground for I/O power supply for VDAC. YDAC

113 YUV5 CDAC

114 YUV2

Video DAC output. Refer to description and matrix for

UDAC pin 115.

O YUV pixel 5 output data.

Video DAC output. Refer to description and matrix for

UDAC pin 115.

O YUV pixel 2 output data .

Video DAC output.

Pin 109 110 113 114 115

Valu

UDAC O

7 N/A

9 CVBS

10 CVBS

11 N/A

FDAC VDAC YDAC CDAC UDAC

CVBS/Chrom

CVBS

Y C N/A

Y C

N/A Y C N/A

CVBS

N/A N/A

N/A N/A N/A

Y Pb Pr

N/A Y Pb Pr

SYNC

Chrom

CVBS

SYNC

G B R

Y Pb Pr

G B R

G R B

N/A Y Pr Pb

CVBS

Y Pr Pb

14 Chroma Y G R B F: VCBS/chroma signal for simultaneous mode. Y: Luma component for YUV and Y/C processing.

CVBS2

C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode.

TWS 116 O Audio transmit frame sync output.

Names Pin Numbers I/P Definitions

System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Strapped to VCC or ground via 4.7-KΩ

resistor; read only during reset.

SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock

0 0 0 CLK*4.5

SEL_PLL2 I

0 0 1 CLK*5.0 0 1 0 Bypass 0 1 1 CLK*4.0 1 0 0 CLK*4.25 1 0 1 CLK*4.75 1 1 0 CLK*5.5 1 1 1 CLK*6.0

Type(MHz)

TSD0 O Audio transmit serial data port 0. SEL_PLL0

117

I Refer to the description and matrix for SEL_Pll2 pin 116. TSD1 O Audio transmit serial data port 1. SEL_PLL1

118

Refer to the description and matrix for SEL_PLL2 pin

116. TSD[2:3] 120.121 O Audio transmit serial data ports 2 and 3. MCLK 122 I/O Audio master clock for audio DAC. TBCK 123 O Audio transmit bit clock. SPD_DOBM O S/PDIF output . SEL_PLL3

124

Clock source select. Strapped to VCC or ground via 4.7K

read only during reset .

SEL_PLL3 Clock Source

0 Crystal oscillator 1 CLK input

SPDIF_IN 125 I S/PDIF input; (5V tolerant input). WBLCLK

128 O

DVD-RAM wobble detector circuit clock source to

preamp. WBL 129 O DVD-RAM wobble output. LG 130 O DVD-RAM land/groove flag. IP2 131 I DVD-RAM header position index 2. IP1 132 I DVD-RAM header position index 1. FLAG[3:0] 133:136 O To monitor servo status . TEXI 139 I High-speed tracking error input . TESTAD 140 I Test AD input . SBAD 141 I Sub-beam addition input signal . FEI 142 I Focus input error signal. AVSS_AD 143 G Analog ground for ADC block .

CEI 144 I Center error input signal . TEI 145 I Tracking error input signal . RFRP 146 I RF ripple/envelope input signal. AVDD3_AD 147 P Analog power supply for ADC block. VREF21 148 O 2.1V reference voltage. VREF09 149 O 0.9Vreference voltage. VREF15 150 O 1.5V reference voltage.

Names Pin Numbers I/P Definitions

IREF

151 I

Servo data PLL interface reference current generator

connect a resistor between this pin and ground to set

reference current . AVDD3_DS 152 P Analog power supply for data slicer .block. IPIN 153 I Inverting input of data slicer . RFIN

RFIP

154 I

155 I

Analog RF signal input after passing through

equalizer(minus)

Analog RF signal input after passing through

equalizer(plus). DSSLV 156 O Data slicer level output. AVSS_DS 157 G Analog ground for data slicer block. AVSS_PL 158 G Analog ground for data PLL block. PDOFTR1 159 O Servo data PLL phase detector filter pin number 1. FDO

160 O

Servo data PLL output node of frequency detector

charge pump. FTROPI 161 I Servo data PLL input node of loop filter OP circuit . AVDD3_OL 162 P Analog power supply for data PLL block . PLLFTR1 163 I Servo data PLL loop filter pin number1. PLLFTR2 164 I Servo data PLL loop filter pin number2. VREF0 165 O Servo data PLL reference voltage output. AWRC 166 I/O Auto wide range control VCO signal from/to AWRC DAC. AVSS_DA 167 G Analog ground for DAC part. RFRPCTR 168 I/O Central level of RFRP. TRAY 169 O Output voltage level for tray buffer IC. AVDD3_DA 170 P Analog power supply for DAC part . SPINDLE 171 O Output voltage level for spindle buffer IC. FOCUS 172 O Output voltage level for focus buffer IC. SLEGP 173 O Output voltage level for Sledge buffer IC(plus). SLEGN 174 O Output voltage level for Sledge buffer IC(minus). TRACK 175 O Output voltage level for tracking buffer IC. TESTDA 176 O Test DA output . FGIN 177 I Spindle hall sensor input . PHOI 178 I Sledge photo interrupt signal input. SCSJ 179 O Chip selection signal to RF chip (serial data enable). SDATA 180 I/O Data signal from/to RF chip. SCLK 181 O Serial clock source to RF chip. DFCT 182 I Defect flag input signal.

LDC 183 O Laser diode on/off control output. SPDON 184 O Spindle power driver on/off control output. GPIO[9:4]

187:192 I/O

General-purpose input/output used for servo control;

(5V tolerant input.) EAUX[3:0] 193:196 I/O Extended auxiliary ports;(5V tolerant input). I²CDATA

AUX0 I²C_CLK

AUX1

199

200

I/O I/O Auxiliary port (open collector);(5V tolerant input). I/O I/O Auxiliary port (open collector);(5V tolerant input).

I²C data I/O;(5V tolerant input).

I²C clock I/O;(5V tolerant input).

IOW# O I/O Write strobe(LCS1)(active-low). HSYNC# I/O Horizontal sync (active low);(5V tolerant input). AUX2

201

I/O

Auxiliary port ;(5V tolerant input).

Names Pin Numbers I/P Definitions IOR# O I/O Read strobe (LCS1)(active –low). VSYNC# I/O Vertical sync (active-low);(5V tolerant input ). AUX3 C2PO I Error correction flag from CD;(5V tolerant input). AUX4

202

203

I/O Auxiliary port;(5V tolerant input).

I/O Auxiliary port;(5V tolerant input). AUX[5:6] 204:205 I/O Auxiliary ports ;(5V tolerant input). IR I Infrared remote control input;(5V tolerant input). AUX7

206

I/O Auxiliary port;(5V tolerant input ). RESET# 207 I Reset input (active –low );(5V tolerant input).

101 I Audio receive serial data input[RSD];(5V tolerant input). 102 I Audio receive bit clock input [RBCK]:(5V tolerant input ). 103 I Audio receive frame sync input[RWS];(5V tolerant input). 116 O Audio transmit frame sync output[TWS].

Audio Port Interface

117.118.120.121 O Audio transmit serial data outputs [TSD[3:0]]. 122 I/O Audio DAC master clock[MCLK]. 123 O Audio transmit bit clock output[TBCK]. 124 O Sony/Philips Digital Interface audio output [SPD_DOBM].

125 I

Sony/Philips Digital Interface audio Input [SPDIF_IN];(5V tolerant input).

Auxiliary Port Interface

Clock Inetface and Reset

Interface

193:196 I/O Extended auxiliary ports [EAUX[3:0]];(5V tolerant input).

199.200 I/O Open collectors [AUX[1:0]],(5V tolerant input). 201:206 I/O Primary auxiliary port I/Os [AUX[7:2]];(5V tolerant input).

2 I 27-MHz crystal clock input [VID_XI]. 3 O 27-MHz crystal clock output[VID_XO].

4 I System clock [CLK]. 29 O DRAM clock enable output [DSCK_EN]. 51 O Output clock [DSCK] to video memory (DRAM).

116:118 I Clock frequency select PLL outputs [SEL_PLL[2:0]].

207 I Reset input (active-low)[RESET#];(5V tolerant input).

106:110.113:115 O Pixel data outputs [YUV[7:0]]. Display

201 I/O Horizontal sync[HSYNC#];(%V tolerant input).

202 I/O Vertical sync [VSYNC#];(5V tolerant input ).

EPROM/Flas h ROM and RISC Port Intetface

55:60.63:69.72:77.

80:82

83:85 O

89 O

90 O

91:94.97:100 I/O

RISC port address bus [LA[21:0]]to EPROM or Flash

memory. RISC port chip select outputs [LCS[2:0]#]to EPROM or Flash memory. RISC port low-byte write enable output[LWRLL#]to EPROM or Flash memory. RISC port output enable[LOE#]to EPROM and Flash memory. RISC port data bus [LD[7:0]]to EPROM or Flash memory (5V tolerant input ).

106 I Video DAC reference voltage input[VREF]. Filter and Reference voltang

107 I Compensation input[COMP]. Interface Front Panel Display

206 I Infrared remote control input [IR];(5V tolerant input). Interface

Names Pin Numbers I/P Definitions General-Purp ose I²C Bus

Interface

187:192 I/O

199 I/O 200 I/O

1.10.19.35.44.53.6

2.79.96.126.185

9.18.34.43.52.61.7

8.95.119.127.186.

General –purpose I/O[GPIO[9:4]];(5V tolerant input).

I²C data I/O[12C_DATA];(5V tolerant input). I²C clock I/O[12C_CLK];(5V tolerant input). I/O power supply [VD33].

I/O ground [VS33].

208

26.70.86.137.197 G Ground for core power [VSS].

27.71.87.138.198 P Core power supply [VDD]. 104 P Power supply for PLL block .[VD33_PL].

Power and Ground

105 G Ground for PLL block [VS33_PL].

111 P Power supply for video DAC[VD33_DA]. 112 G Ground for video DAC[VS33_DA]. 143 G Analog ground for ADC[AVSS_AD]. 147 P Analog power supply for ADC[AVDD3_AD]. 152 P Analog power supply for data slicer [AVDD3_DS]. 157 G Analog ground for data slicer[AVSS_DS]. 158 G Analog ground for data PLL [AVSS_PL]. 162 P Analog power supply for data PLL[AVDD3_PL]. 167 G Analog ground for DAC[AVSS_DA]. 170 P Analog power supply for DAC[AVDD3_DA].

Serial Port Interface 203 I

C2PO error correction flag from CD[C2PO];(5V tolerant input).

Servo Data Slicer Interface

153 I

154

Inverting input of data slicer [IPIN].

Analog RF signal input after passing through

equalizer(minus) [RFIN].

Analog RF signal input after passing through

155 I

equalizer(plus) [RFIP].

156 O

Data slicer level output[DSSLV].

2.OPERATING INSTRUCTIONS

1. GENERAL SETUP

Pressing the SETUP button on remote control during STOP or PLAY mode to SETUP MENU.

sing Cursor to select GENERAL SETUP. Press ENTER to enter GENERAL SETUP page.

SETUP MENU - MAIN PAGE

GENERAL SETUP

SPEAKER SETUP AUDIO SETUP PREFERENCE

EXIT SETUP

a.TV DISPLAY

-- GENERAL PAGE --

TV DISPLAY NORMAL P/S

PIC MODE NORMAL L/B ANGLE MARK W IDE OSD LANG CAPTIONS SCR SAVER MA IN P A G E

b. PIC MODE (PICTURE MODE)

( FOR PROGRESSIVE-SCAN MODEL )

-- GENERAL PAGE --

TV DISPLAY

PIC MODE AUTO

ANGLE MARK HI-RES OSD LANG NON-FLICKER CAPTIONS SCR SAVER MA IN P A G E

-- GENERAL PAGE --

TV DISPLAY PIC MODE

NGLE MARK OSD LANG CAPTIONS SCR SAVER MA IN P A G E

Using cursor to move to desired setting and press ENTER to confirm. NORMAL/PS – 4 x 3 Pan Scan Full screen of picture on TV. Normally, left and right edges cannot be shown. NORMAL/LB – 4 x 3 Letter Box Orginal ratio of aspect. WIDE – 16 : 9 Widescreen

-- GENERAL PAGE --

TV DISPLAY

PIC MODE

NGLE MARK FILM OSD LANG CAPTIONS SMART SCR SAVER SUPER SMART MA IN P A G E

UTO

IDE O

c.ANGLE MARK

-- GENERAL PAGE --

TV DISPLY PIC MODE

ANGLE MAR K ON

OSD LANG OFF CAPTIONS SCR SAVER MA IN P A G E

This feature is functioned only for the disc, which has ANGLE function:

When the ANGLE MARK is set ON, the screen displays the mark. When the ANGLE MARK is set OFF, the mark is not displayed.

d. OSD LANG (ON SCREEN DISPLAY LANGUAGE)

-- GENERAL PAGE --

TV DISPLAY PIC MODE ANGLE M ARK

OSD LANG ENGLISH

CA P T ION S IT A L IA N SCR SAVER MA IN P A G E

e. CAPTIONS

-- GENERAL PAGE --

TV DISPLAY PIC MODE ANGLE M ARK OSD LANG

CAPTIONS ON

SCR SAVER OFF MA IN P A G E

f. SCR SAVER

-- GENERAL PAGE --

When the unit is stopped, no operation, no function button is

TV DISPLAY PIC MODE ANGLE M ARK OSD LANG CAPTIONS ON

SCR SAVER OFF

MA IN P A G E

pressed in 1 minute,screen saver appears for the purpose to protect the TV screen if SCR SAVER is set ON.

+ 34 hidden pages