Gigabyte Z490 Aorus Pro AX operation manual

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SiC620, SiC620A

www.vishay.com	Vishay Siliconix

60 A VRPower® Integrated Power Stage

DESCRIPTION

The SiC620 and SiC620A are integrated power stage solutions optimized for synchronous buck applications to offer high current, high efficiency, and high power density performance. Packaged in Vishay’s proprietary 5 mm x 5 mm MLP package, SiC620 and SiC620A enables voltage regulator designs to deliver up to 60 A continuous current per phase.

The internal power MOSFETs utilizes Vishay’s state-of-the-art Gen IV TrenchFET technology that delivers industry benchmark performance to significantly reduce switching and conduction losses.

The SiC620 and SiC620A incorporates an advanced MOSFET gate driver IC that features high current driving capability, adaptive dead-time control, an integrated bootstrap Schottky diode, a thermal warning (THWn) that alerts the system of excessive junction temperature, and zero current detect to improve light load efficiency. The drivers are also compatible with a wide range of PWM controllers and supports tri-state PWM, 3.3 V (SiC620A) / 5 V (SiC620) PWM logic.

FEATURES

• Thermally enhanced PowerPAK® MLP55-31L package

•Vishay’s Gen IV MOSFET technology and a low-side MOSFET with integrated Schottky

diode

•Delivers up to 60 A continuous current

•95 % peak efficiency

•High frequency operation up to 1.5 MHz

•Power MOSFETs optimized for 12 V input stage

•3.3 V (SiC620A) / 5 V (SiC620) PWM logic with tri-state and hold-off

•Zero current detect control for light load efficiency improvement

•Low PWM propagation delay (< 20 ns)

•Thermal monitor flag

•Under voltage lockout for VCIN

•Material categorization: for definitions of compliance please see www.vishay.com/doc?99912

APPLICATIONS

• Multi-phase VRDs for CPU, GPU, and memory

TYPICAL APPLICATION DIAGRAM

5 V

V	HG	IN
DRV	HG	IN
		V

BOOT

VCIN

PHASE

	ZCD_EN#	VSWH
	DSBL#
PWM		Gate

	PWM	driver
controller

THWn

C	LG	P
NDG	LG	NDG

VIN

VOUT

Fig. 1 - SiC620 and SiC620A Typical Application Diagram

S14-2385-Rev. E, 08-Dec-14	1	Document Number: 62922
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PINOUT CONFIGURATION

SiC620, SiC620A

Vishay Siliconix

	BL#DS	THWn	V	P		V	V	V
	BL#DS	THWn	DRV	NDG	LG	WHS	WHS	WHS
	31	30	29	28	27	26	25	24
PWM 1					GL			23 VSWH
ZCD_EN# 2					GL			23 VSWH
ZCD_EN# 2								22 VSWH
VCIN	CGND							22 VSWH
VCIN	3							21 VSWH
CGND	4							20 V	SWH
BOOT 5					PGND			19 VSWH
GH 6								18 VSWH
PHASE 7		VIN						17 VSWH
VIN	8							16 VSWH
	9	10	11		12	13	14	15
	V	V	V		P	P	P	P
	IN	IN	IN		NDG	NDG	NDG	NDG

	33	SWH	SWH	SWH	GL	GND	DRV	THWn	DBL#S
	33	V	V	V	GL	P	V	THWn	DBL#S
	GL	24	25	26	27	28	29	30	31
VSWH 23					GL					1	PWM
					GL					2	ZCD_EN#
VSWH 22								32		2	ZCD_EN#
VSWH 21							CGND			3	VCIN
V	SWH	20								4	CGND
V	SWH	19		35						5	BOOT
	SWH		PGND
VSWH 18			PGND							6	HG
VSWH 18								34		6	HG
VSWH 17								34		7	PHASE
VSWH 17								VIN		7	PHASE
VSWH 16								VIN
VSWH 16										8	VIN
		15	14	13	12		11	10	9
		GND	GND	GND	GND		IN	IN	IN
		GND	GND	GND	GND		V	V	V
		P	P	P	P

	Top view		Bottom view
		Fig. 2 - SiC620 and SiC620A Pin Configuration

PIN CONFIGURATION
PIN NUMBER	NAME		FUNCTION

1	PWM	PWM control input

2	ZCD_EN#	ZCD control. Active low

3	VCIN	Supply voltage for internal logic circuitry
4, 32	CGND	Analog ground for the driver IC
5	BOOT	High-side driver bootstrap voltage

6	GH	High-side gate signal

7	PHASE	Return path of high-side gate driver

8 to 11, 34	VIN	Power stage input voltage. Drain of high-side MOSFET
12 to 15, 28, 35	PGND	Power ground
16 to 26	VSWH	Switch node of the power stage
27, 33	GL	Low-side gate signal

29	VDRV	Supply voltage for internal gate driver
30	THWn	Thermal warning open drain output

31	DSBL#	Disable pin. Active low

ORDERING INFORMATION

PART NUMBER	PACKAGE	MARKING CODE	OPTION

SiC620CD-T1-GE3	PowerPAK MLP55-31L	SiC620	5 V PWM optimized

SiC620ACD-T1-GE3	PowerPAK MLP55-31L	SiC620A	3.3 V PWM optimized

SiC620DB / SiC620ADB		Reference board


S14-2385-Rev. E, 08-Dec-14	2		Document Number: 62922

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC620, SiC620A

www.vishay.com			Vishay Siliconix
			Vishay Siliconix

ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER	CONDITIONS	LIMIT		UNIT

Input Voltage	VIN	-0.3 to +25
Control Logic Supply Voltage	VCIN	-0.3 to +7
Drive Supply Voltage	VDRV	-0.3 to +7
Switch Node (DC voltage)	VSWH	-0.3 to +25

Switch Node (AC voltage) (1)		-7 to +30
Switch Node (AC voltage) (1)		-7 to +30
BOOT Voltage (DC voltage)	VBOOT	32		V

BOOT Voltage (AC voltage) (2)		38
BOOT Voltage (AC voltage) (2)		38
BOOT to PHASE (DC voltage)	VBOOT-PHASE	-0.3 to +7

BOOT to PHASE (AC voltage) (3)		-0.3 to +8
BOOT to PHASE (AC voltage) (3)		-0.3 to +8
All Logic Inputs and Outputs		-0.3 to VCIN +0.3
(PWM, DSBL#, and THWn)		-0.3 to VCIN +0.3
(PWM, DSBL#, and THWn)

Output Current, IOUT(AV) (4)	fS = 300 kHz, VIN = 12 V, VOUT = 1.8 V	60		A
Output Current, IOUT(AV) (4)	fS = 1 MHz, VIN = 12 V, VOUT = 1.8 V	50		A
	fS = 1 MHz, VIN = 12 V, VOUT = 1.8 V	50
Max. Operating Junction Temperature	TJ	150
Ambient Temperature	TA	-40 to +125		°C
Storage Temperature	Tstg	-65 to +150
Electrostatic Discharge Protection	Human body model, JESD22-A114	3000		V

	Charged device model, JESD22-C101	1000
	Charged device model, JESD22-C101	1000

Notes

•Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(1)The specification values indicated “AC” is VSWH to PGND -8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.

(2)The specification value indicates “AC voltage” is VBOOT to PGND, 38 V (< 50 ns) max.

(3)The specification value indicates “AC voltage” is VBOOT to VPHASE, 8 V (< 20 ns) max.

(4)Output current rated with testing evaluation board at TA = 25 °C with natural convection cooling. The rating is limited by the peak evaluation board temperature, TJ

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER	MINIMUM	TYPICAL	MAXIMUM	UNIT

Input Voltage (VIN)	4.5	-	18
Drive Supply Voltage (VDRV)	4.5	5	5.5
Control Logic Supply Voltage (VCIN)	4.5	5	5.5	V
Switch Node (VSWH, DC voltage)	-	-	18
BOOT to PHASE (VBOOT-PHASE, DC voltage)	4	4.5	5.5
Thermal Resistance from Junction to Ambient	-	10.6	-	°C/W

Thermal Resistance from Junction to Case	-	1.6	-
Thermal Resistance from Junction to Case	-	1.6	-

S14-2385-Rev. E, 08-Dec-14	3	Document Number: 62922
	For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC620, SiC620A

www.vishay.com				Vishay Siliconix
				Vishay Siliconix

ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
PARAMETER	SYMBOL	TEST CONDITION		LIMITS		UNIT

			MIN.	TYP.	MAX.
			MIN.	TYP.	MAX.

POWER SUPPLY
		VDSBL# = 0 V, no switching	-	12	-
Control Logic Supply Current	IVCIN	VDSBL# = 5 V, no switching, VPWM = FLOAT	-	300	-	μA
		VDSBL# = 5 V, fS = 300 kHz, D = 0.1	-	380	-
		fS = 300 kHz, D = 0.1	-	15	25	mA
Drive Supply Current	IVDRV	fS = 1 MHz, D = 0.1	-	50	-	mA
		fS = 1 MHz, D = 0.1	-	50	-
		VDSBL# = 0 V, no switching	-	25	-	μA
		VDSBL# = 0 V, no switching	-	25	-
		VDSBL# = 5 V, no switching	-	60	-
		VDSBL# = 5 V, no switching	-	60	-
BOOTSTRAP SUPPLY
Bootstrap Diode Forward Voltage	VF	IF = 2 mA			0.4	V
PWM CONTROL INPUT (SiC620)
Rising Threshold	VTH_PWM_R		3.4	3.8	4.2
Falling Threshold	VTH_PWM_F		0.72	0.9	1.1
Tri-state Voltage	VTRI	VPWM = FLOAT	-	2.3	-	V
Tri-state Rising Threshold	VTRI_TH_R		0.9	1.15	1.38
Tri-state Falling Threshold	VTRI_TH_F		3	3.3	3.6
Tri-state Rising Threshold	VHYS_TRI_R		-	225	-
Hysteresis	VHYS_TRI_R		-	225	-
Hysteresis						mV

Tri-state Falling Threshold	VHYS_TRI_F		-	325	-
Tri-state Falling Threshold
Hysteresis
Hysteresis

PWM Input Current	IPWM	VPWM = 5 V	-	-	350	μA
PWM Input Current	IPWM	VPWM = 0 V	-	-	-350	μA
		VPWM = 0 V	-	-	-350
PWM CONTROL INPUT (SiC620A)
Rising Threshold	VTH_PWM_R		2.2	2.45	2.7
Falling Threshold	VTH_PWM_F		0.72	0.9	1.1
Tri-state Voltage	VTRI	VPWM = FLOAT	-	1.8	-	V
Tri-state Rising Threshold	VTRI_TH_R		0.9	1.15	1.38
Tri-state Falling Threshold	VTRI_TH_F		1.95	2.2	2.45
Tri-state Rising Threshold	VHYS_TRI_R		-	250	-
Hysteresis	VHYS_TRI_R		-	250	-
Hysteresis						mV

Tri-state Falling Threshold	VHYS_TRI_F		-	300	-
Tri-state Falling Threshold
Hysteresis
Hysteresis

PWM Input Current	IPWM	VPWM = 3.3 V	-	-	225	μA
PWM Input Current	IPWM	VPWM = 0 V	-	-	-225	μA
		VPWM = 0 V	-	-	-225
TIMING SPECIFICATIONS
Tri-State to GH/GL Rising	tPD_TRI_R		-	30	-
Propagation Delay	tPD_TRI_R		-	30	-
Propagation Delay

Tri-state Hold-Off Time	tTSHO		-	130	-
GH - Turn Off Propagation Delay	tPD_OFF_GH		-	15	-
GH - Turn On Propagation Delay	tPD_ON_GH	No load, see fig. 4	-	10	-
(Dead time rising)	tPD_ON_GH		-	10	-
(Dead time rising)						ns

GL - Turn Off Propagation Delay	tPD_OFF_GL		-	12	-
GL - Turn Off Propagation Delay	tPD_OFF_GL		-	12	-
GL - Turn On Propagation Delay	tPD_ON_GL		-	10	-
(Dead time falling)	tPD_ON_GL		-	10	-
(Dead time falling)

DSBL# Lo to GH/GL Falling	tPD_DSBL#_F	Fig. 5	-	15	-
Propagation Delay	tPD_DSBL#_F	Fig. 5	-	15	-
Propagation Delay

PWM Minimum On-Time	tPWM_ON_MIN		30	-	-

S14-2385-Rev. E, 08-Dec-14	4	Document Number: 62922
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PWM_TH_F

SiC620, SiC620A

www.vishay.com				Vishay Siliconix
				Vishay Siliconix

ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
PARAMETER	SYMBOL	TEST CONDITION		LIMITS		UNIT

			MIN.	TYP.	MAX.
			MIN.	TYP.	MAX.

DSBL# ZCD_EN# INPUT
DSBL# Logic Input Voltage	VIH_DSBL#	Input logic high	2	-	-
DSBL# Logic Input Voltage	VIL_DSBL#	Input logic low	-	-	0.8	V
	VIL_DSBL#	Input logic low	-	-	0.8
ZCD_EN# Logic Input Voltage	VIH_ZCD_EN#	Input logic high	2	-	-
	VIH_ZCD_EN#	Input logic high	2	-	-
	VIL_ZCD_EN#	Input logic low	-	-	0.8
	VIL_ZCD_EN#	Input logic low	-	-	0.8
PROTECTION
Under Voltage Lockout	VUVLO	VCIN rising, on threshold	-	3.7	4.1	V
Under Voltage Lockout	VUVLO	VCIN falling, off threshold	2.7	3.1	-	V
		VCIN falling, off threshold	2.7	3.1	-
Under Voltage Lockout Hysteresis	VUVLO_HYST		-	575	-	mV
THWn Flag Set (2)	TTHWn_SET		-	160	-
THWn Flag Clear (2)	TTHWn_CLEAR		-	135	-	°C
THWn Flag Hysteresis (2)	TTHWn_HYST		-	25	-
THWn Output Low	VOL_THWn	ITHWn = 2 mA	-	0.02	-	V

Notes

(1)Typical limits are established by characterization and are not production tested.

(2)Guaranteed by design.

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tri-state Function

The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate tri-state logic (H, L and tri-state) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above

VPWM_TH_R the low-side is turned on and the high-side is turned on. When PWM input is driven below V the

high-side is turned OFF and the low-side is turned ON. For tri-state logic, the PWM input operates as previously stated for driving the MOSFETs. However, there is an third state that is entered as the PWM output of tri-state compatible controller enters its high impedance state during shut-down. The high impedance state of the controller’s PWM output allows the SiC620 and SiC620A to pull the PWM input into the tri-state region (see PWM Timing Diagram). If the PWM input stays in this region for the tri-state hold-off period,

tTSHO, both high-side and low-side MOSFETs are turned OFF. This function allows the VR phase to be disabled

without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and tri-state regions are separated by hysteresis to prevent false triggering. The SiC620A incorporates PWM voltage thresholds that are compatible with 3.3 V logic and the SiC620 thresholds are compatible with 5 V logic.

Disable (DSBL#)

In the low state, the DSBL# pin shuts down the driver IC and disables both high-side and low-side MOSFETs. In this state, standby current is minimized. If DSBL# is left unconnected, an internal pull-down resistor will pull the pin to CGND and shut down the IC.

Diode Emulation Mode (ZCD_EN#)

When ZCD_EN# pin is logic Low and PWM signal switches Low, GL is forced on (after normal BBM time). During this time, it is under control of the ZCD (zero crossing detect) comparator. If, after the internal blanking delay, the inductor current becomes zero, the low-side is turned off. This improves light load efficiency by avoiding discharge of output capacitors. If PWM enters tri-state, then device will go into normal tri-state mode after tri-state delay. The GL output will be turned off regardless of Inductor current, this is an alternative method of improving light load efficiency by reducing switching losses.

Thermal Shutdown Warning (THWn)

The THWn pin is an open drain signal that flags the presence of excessive junction temperature. Connect with a maximum of 20 kΩ, to VCIN. An internal temperature sensor detects the junction temperature. The temperature threshold is 160 °C. When this junction temperature is exceeded the THWn flag is set. When the junction temperature drops below 135 °C the device will clear the THWn signal. The SiC620 and SiC620A do not stop operation when the flag is set. The decision to shutdown must be made by an external thermal control function.

Voltage Input (VIN)

This is the power input to the drain of the high-side power MOSFET. This pin is connected to the high power intermediate BUS rail.

S14-2385-Rev. E, 08-Dec-14	5	Document Number: 62922
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SiC620, SiC620A

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Switch Node (VSWH and PHASE)

The switch node, VSWH, is the circuit power stage output. This is the output applied to the power inductor and output filter to deliver the output for the buck converter. The PHASE pin is internally connected to the switch node VSWH. This pin is to be used exclusively as the return pin for the BOOT capacitor. A 20 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET in the event that VCIN goes to zero while VIN is still applied.

Ground Connections (CGND and PGND)

PGND (power ground) should be externally connected to CGND (control signal ground). The layout of the printed circuit board should be such that the inductance separating

CGND and PGND is minimized. Transient differences due to inductance effects between these two pins should not

exceed 0.5 V

Control and Drive Supply Voltage Input (VDRV, VCIN)

VCIN is the bias supply for the gate drive control IC. VDRV is the bias supply for the gate drivers. It is recommended to

separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC.

Bootstrap Circuit (BOOT)

The internal bootstrap diode and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

The SiC620 and SiC620A have an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high-side and low-side MOSFETs are not turned ON at the same time. The adaptive dead time control operates as follows. The HS and LS gate voltages are monitored to prevent the one turning ON from tuning ON until the other's gate voltage is sufficiently low (< 1 V). Built in delays also ensure that one power MOS is completely OFF, before the other can be turned ON. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature. Change with respect to output current and temperature.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET gates low until the supply voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC620, SiC620A also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET.

FUNCTIONAL BLOCK DIAGRAM

THWn

BOOT

VIN

VDRV

Thermal monitor

& warning

VCIN

UVLO

DISB#

VCIN

20K

PHASE

PWM logic

Anti-cross

Vref = 1 V

control &

conduction

PWM

state

control

VSWH

machine

logic

Vref = 1 V

CGND

VSWH

VDRV

PGND

ZCD_EN#

PGND

Fig. 3 - SiC620 and SiC620A Functional Block Diagram

S14-2385-Rev. E, 08-Dec-14

Document Number: 62922

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Gigabyte Z490 Aorus Pro AX operation manual

						SiC620, SiC620A
						SiC620, SiC620A
		www.vishay.com					Vishay Siliconix
							Vishay Siliconix

DEVICE TRUTH TABLE
	DSBL#		ZCD_EN#	PWM	GH		GL

	Open		X	X	L		L

	L		X	X	L		L

	H		L	L	L		H, IL > 0 A
	H		L	L	L		L, IL < 0 A
							L, IL < 0 A
	H		L	H	H		L

	H		L	Tri-state	L		L

	H		H	L	L		H

	H		H	H	H		L

	H		H	Tri-state	L		L

PWM TIMING DIAGRAM

VTH_PWM_R

VTH_TRI_F

VTH_TRI_R

VTH_PWM_F

PWM

tPD_OFF_GL

t TSHO

t PD_ON_GL

tPD_TRI_R

tTSHO

tPD_ON_GH	t PD_OFF_GH

t PD_TRI_R

Fig. 4 - Definition of PWM Logic and Tri-state

DSBL# PROPAGATION DELAY

PWM

DSBL#

Disable

DSBL#

DSBL#Low to GH Falling Propagation Delay

DSBL# Low to GL Falling Propagation Delay

Fig. 5 - DSBL# Falling Propagation Delay

S14-2385-Rev. E, 08-Dec-14	7	Document Number: 62922
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