Gigabyte Z490 Aorus Pro AX operation manual

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PWM

controller

Gate

driver

5V V

IN

V

OUT

V

CIN

ZCD_EN#

DSBL#

PWM

THWn

V

DRV

G

H

V

IN

BOOT

V

SWH

P

GND

GL

C

GND

PHASE

60 A VRPower® Integrated Power Stage

SiC620, SiC620A

Vishay Siliconix

DESCRIPTION

The SiC620 and SiC620A are integrated power stage
solutions optimized for synchronous buck applications to
offer high current, high efficiency, and high power density
performance. Packaged in Vishay’s proprietary

5 mm x 5 mm
MLP package, SiC620 and SiC620A enables voltage
regulator designs to deliver up to 60 A continuous current
per phase.

The internal power MOSFETs utilizes Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.

The SiC620 and SiC620A incorporates an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, a thermal warning (THWn) that
alerts the system of excessive junction temperature, and
zero current detect to improve light load efficiency. The
drivers are also compatible with a wide range of PWM
controllers and supports tri-state PWM, 3.3 V (SiC620A) /
5 V (SiC620) PWM logic.

TYPICAL APPLICATION DIAGRAM

FEATURES

• Thermally enhanced PowerPAK® MLP55-31L
package

• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode

• Delivers up to 60 A continuous current

• 95 % peak efficiency

• High frequency operation up to 1.5 MHz

• Power MOSFETs optimized for 12 V input stage

• 3.3 V (SiC620A) / 5 V (SiC620) PWM logic with tri-state and
hold-off

• Zero current detect control for light load efficiency
improvement

• Low PWM propagation delay (< 20 ns)

• Thermal monitor flag

• Under voltage lockout for V

CIN

• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

APPLICATIONS

• Multi-phase VRDs for CPU, GPU, and memory

S14-2385-Rev. E, 08-Dec-14

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Fig. 1 - SiC620 and SiC620A Typical Application Diagram

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1

Document Number: 62922

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PINOUT CONFIGURATION

DSBL#

THWn

V

DRV

1

PWM

ZCD_EN#

V

CIN

C

GND

BOOT

GH

PHASE

V

2

3

CGND

4

5

6

7

8

IN

VIN

SiC620, SiC620A

Vishay Siliconix

V

V

V

P

GND

GL

GL

PGND

SWH

SWH

SWH

2425262728293031

23 V

22 V

21 V

20 V

19 V

18 V

17 V

16 V

SWH

SWH

SWH

SWH

SWH

SWH

SWH

SWH

33
GL

V

23

SWH

22

V

SWH

21

V

SWH

V

20

SWH

V

19

SWH

V

18

SWH

17

V

SWH

V

16

SWH

SWHVSWHVSWH

V

24 25 26 27 28 29 30 31

35

PGND

GND

DRV

P

GL

V

THWn

DSBL#

PWM

GL

32

CGND

34

VIN

1

ZCD_EN#

2

V

3

CIN

C

4

GND

BOOT

5

6

HG

7

PHASE

8

V

IN

1514131211109

P

VINVINV

IN

P

GND

GNDPGNDPGND

15 14 13 12 11 10 9

GNDPGNDPGNDPGND

P

Top view Bottom view

Fig. 2 - SiC620 and SiC620A Pin Configuration

PIN CONFIGURATION

PIN NUMBER NAME FUNCTION

1PWMPWM control input

2 ZCD_EN# ZCD control. Active low

3V

4, 32 C

CIN

GND

5 BOOT High-side driver bootstrap voltage

6 GH High-side gate signal

7 PHASE Return path of high-side gate driver

8 to 11, 34 V

12 to 15, 28, 35 P

16 to 26 V

IN

GND

SWH

27, 33 GL Low-side gate signal

29 V

DRV

30 THWn Thermal warning open drain output

31 DSBL# Disable pin. Active low

Supply voltage for internal logic circuitry

Analog ground for the driver IC

Power stage input voltage. Drain of high-side MOSFET

Power ground

Switch node of the power stage

Supply voltage for internal gate driver

VINVINV

IN

ORDERING INFORMATION

PART NUMBER PACKAGE MARKING CODE OPTION

SiC620CD-T1-GE3 PowerPAK MLP55-31L SiC620 5 V PWM optimized

SiC620ACD-T1-GE3 PowerPAK MLP55-31L SiC620A 3.3 V PWM optimized

SiC620DB / SiC620ADB Reference board

S14-2385-Rev. E, 08-Dec-14

2

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Document Number: 62922

SiC620, SiC620A

www.vishay.com

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT

Input Voltage V

Control Logic Supply Voltage V

Drive Supply Voltage V

Switch Node (DC voltage)

Switch Node (AC voltage)

(1)

BOOT Voltage (DC voltage)

BOOT Voltage (AC voltage)

(2)

BOOT to PHASE (DC voltage)

BOOT to PHASE (AC voltage)

(3)

IN

CIN

DRV

V

SWH

V

BOOT

V

BOOT-PHASE

A ll Lo g ic I np ut s an d Ou tp u ts
(PWM, DSBL#, and THWn)

Output Current, I

OUT(AV)

(4)

fS = 300 kHz, VIN = 12 V, V

= 1 MHz, VIN = 12 V, V

f

S

Max. Operating Junction Temperature T

Storage Temperature T

Electrostatic Discharge Protection

Human body model, JESD22-A114 3000

Charged device model, JESD22-C101 1000

J

A

stg

= 1.8 V 60

OUT

= 1.8 V 50

OUT

Notes

• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

(1)

The specification values indicated “AC” is V

(2)

The specification value indicates “AC voltage” is V

(3)

The specification value indicates “AC voltage” is V

(4)

Output current rated with testing evaluation board at TA = 25 °C with natural convection cooling. The rating is limited by the peak evaluation
board temperature, T

J

SWH

to P

-8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.

GND

to P

BOOT

BOOT

, 38 V (< 50 ns) max.

GND

to V

PHASE

, 8 V (< 20 ns) max.

-0.3 to +25

-0.3 to +7

-0.3 to +7

-0.3 to +25

-7 to +30

-0.3 to +7

-0.3 to +8

-0.3 to V

150

-40 to +125

-65 to +150

Vishay Siliconix

32

38

+0.3

CIN

V

A

°CAmbient Temperature T

V

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT

Input Voltage (V

Drive Supply Voltage (V

Control Logic Supply Voltage (V

Switch Node (V

BOOT to PHASE (V

Thermal Resistance from Junction to Ambient - 10.6 -

Thermal Resistance from Junction to Case - 1.6 -

S14-2385-Rev. E, 08-Dec-14

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

)4.5-18

IN

) 4.555.5

DRV

) 4.555.5

CIN

, DC voltage) - - 18

SWH

BOOT-PHASE

, DC voltage) 4 4.5 5.5

3

Document Number: 62922

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V

°C/W

SiC620, SiC620A

www.vishay.com

ELECTRICAL SPECIFICATIONS

(DSBL# = ZCD_EN# = 5 V, V

PARAMETER SYMBOL TEST CONDITION

POWER SUPPLY

Control Logic Supply Current I

Drive Supply Current I

BOOTSTRAP SUPPLY

Bootstrap Diode Forward Voltage V

PWM CONTROL INPUT (SiC620)

Rising Threshold V

Falling Threshold V

Tri-state Voltage V

Tri-state Rising Threshold V

Tri-state Falling Threshold V

Tri-state Rising Threshold
Hysteresis

Tri-state Falling Threshold
Hysteresis

PWM Input Current I

PWM CONTROL INPUT (SiC620A)

Rising Threshold V

Falling Threshold V

Tri-state Voltage V

Tri-state Rising Threshold V

Tri-state Falling Threshold V

Tri-state Rising Threshold
Hysteresis

Tri-state Falling Threshold
Hysteresis

PWM Input Current I

TIMING SPECIFICATIONS

Tri-State to GH/GL Rising
Propagation Delay

Tri-state Hold-Off Time t

GH - Turn Off Propagation Delay t

GH - Turn On Propagation Delay
(Dead time rising)

GL - Turn Off Propagation Delay t

GL - Turn On Propagation Delay
(Dead time falling)

DSBL# Lo to GH/GL Falling
Propagation Delay

PWM Minimum On-Time t

= 12 V, V

IN

VCIN

VDRV

TH_PWM_R

TH_PWM_F

TRI_TH_R

TRI_TH_F

V

HYS_TRI_R

V

HYS_TRI_F

PWM

TH_PWM_R

TH_PWM_F

TRI_TH_R

TRI_TH_F

V

HYS_TRI_R

V

HYS_TRI_F

PWM

t

PD_TRI_R

TSHO

PD_OFF_GH

t

PD_ON_GH

PD_OFF_GL

t

PD_ON_GL

t

PD_DSBL#_F

PWM_ON_MIN

TRI

TRI

DRV

and V

= 5 V, TA = 25 °C)

CIN

MIN. TYP. MAX.

V

= 0 V, no switching - 12 -

DSBL#

= 5 V, no switching, V

DSBL#

V

= 5 V, fS = 300 kHz, D = 0.1 - 380 -

DSBL#

= FLOAT - 300 -

PWM

fS = 300 kHz, D = 0.1 - 15 25

= 1 MHz, D = 0.1 - 50 -

f

S

V

= 0 V, no switching - 25 -

DSBL#

= 5 V, no switching - 60 -

V

DSBL#

F

IF = 2 mA 0.4 V

3.4 3.8 4.2

0.72 0.9 1.1

V

= FLOAT - 2.3 -

PWM

0.9 1.15 1.38

33.33.6

- 225 -

- 325 -

V

= 5 V - - 350

PWM

= 0 V - - -350

V

PWM

2.2 2.45 2.7

0.72 0.9 1.1

V

= FLOAT - 1.8 -

PWM

0.9 1.15 1.38

1.95 2.2 2.45

- 250 -

- 300 -

V

= 3.3 V - - 225

PWM

= 0 V - - -225

V

PWM

-30-

- 130 -

-15-

No load, see fig. 4

-10-

-12-

-10-

Fig. 5 - 15 -

30 - -

Vishay Siliconix

LIMITS

UNIT

μAV

mA

μA

V

mV

μA

V

mV

μA

ns

S14-2385-Rev. E, 08-Dec-14

4

Document Number: 62922

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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www.vishay.com

ELECTRICAL SPECIFICATIONS

(DSBL# = ZCD_EN# = 5 V, V

PARAMETER SYMBOL TEST CONDITION

DSBL# ZCD_EN# INPUT

DSBL# Logic Input Voltage

ZCD_EN# Logic Input Voltage

PROTECTION

Under Voltage Lockout V

Under Voltage Lockout Hysteresis V

THWn Flag Set

THWn Flag Hysteresis

THWn Output Low V

Notes

(1)

Typical limits are established by characterization and are not production tested.

(2)

Guaranteed by design.

(2)

(2)

(2)

= 12 V, V

IN

V

IH_DSBL#

V

IL_DSBL#

V

IH_ZCD_EN#

V

IL_ZCD_EN#

UVLO

UVLO_HYST

T

THWn_SET

T

THWn_CLEAR

T

THWn_HYST

OL_THWn

DRV

and V

= 5 V, TA = 25 °C)

CIN

MIN. TYP. MAX.

Input logic high 2 - -

Input logic low - - 0.8

Input logic high 2 - -

Input logic low - - 0.8

V

rising, on threshold - 3.7 4.1

CIN

falling, off threshold 2.7 3.1 -

V

CIN

I

= 2 mA - 0.02 - V

THWn

SiC620, SiC620A

Vishay Siliconix

LIMITS

- 575 - mV

- 160 -

- 135 -

-25-

UNIT

V

V

°CTHWn Flag Clear

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tri-state Function

The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V

PWM_TH_R

turned on. When PWM input is driven below V

the low-side is turned on and the high-side is

PWM_TH_F

the
high-side is turned OFF and the low-side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs. However, there is an third state
that is entered as the PWM output of tri-state compatible
controller enters its high impedance state during shut-down.
The high impedance state of the controller’s PWM output
allows the SiC620 and SiC620A to pull the PWM input into
the tri-state region (see PWM Timing Diagram). If the PWM
input stays in this region for the tri-state hold-off period,

, both high-side and low-side MOSFETs are turned

t

TSHO

OFF. This function allows the VR phase to be disabled
without negative output voltage swing caused by inductor
ringing and saves a Schottky diode clamp. The PWM and
tri-state regions are separated by hysteresis to prevent false
triggering. The SiC620A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC620 thresholds are compatible with 5 V logic.

Disable (DSBL#)

In the low state, the DSBL# pin shuts down the driver IC and
disables both high-side and low-side MOSFETs. In this
state, standby current is minimized. If DSBL# is left
unconnected, an internal pull-down resistor will pull the pin
to C

S14-2385-Rev. E, 08-Dec-14

and shut down the IC.

GND

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Diode Emulation Mode (ZCD_EN#)

When ZCD_EN# pin is logic Low and PWM signal switches
Low, GL is forced on (after normal BBM time). During this
time, it is under control of the ZCD (zero crossing detect)
comparator. If, after the internal blanking delay, the inductor
current becomes zero, the low-side is turned off. This
improves light load efficiency by avoiding discharge of
output capacitors. If PWM enters tri-state, then device will
go into normal tri-state mode after tri-state delay. The GL
output will be turned off regardless of Inductor current, this
is an alternative method of improving light load efficiency by
reducing switching losses.

Thermal Shutdown Warning (THWn)

The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect with a
maximum of 20 kΩ, to V

. An internal temperature sensor

CIN

detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC620 and SiC620A do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.

Voltage Input (V

)

IN

This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.

5

Document Number: 62922

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DISB#

20K

V

SWH

V

SWH

GL

+

-

GL

+

-

ZCD_EN#

Thermal monitor

& warning

UVLO

V

CIN

PWM logic

control &

state

machine

Anti-cross

conduction

control

logic

BOOT

THWn

V

IN

GH

PWM

C

GND

V

CIN

V

ref

= 1 V

V

ref

= 1 V

P

GND

PHASE

V

DRV

V

DRV

P

GND

SiC620, SiC620A

Vishay Siliconix

Switch Node (V

The switch node, V

and PHASE)

SWH

, is the circuit power stage output.

SWH

This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node V

SWH

. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 kΩ resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that V

Ground Connections (C

P

(power ground) should be externally connected

GND

to C

(control signal ground). The layout of the printed

GND

goes to zero while VIN is still applied.

CIN

GND

and P

GND

)

circuit board should be such that the inductance separating
C

GND

and P

is minimized. Transient differences due to

GND

inductance effects between these two pins should not
exceed 0.5 V

Control and Drive Supply Voltage Input (V

V

is the bias supply for the gate drive control IC. V

CIN

DRV

, V

CIN

)

DRV

is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.

FUNCTIONAL BLOCK DIAGRAM

Bootstrap Circuit (BOOT)

The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

The SiC620 and SiC620A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high-side and low-side
MOSFETs are not turned ON at the same time. The adaptive
dead time control operates as follows. The HS and LS gate
voltages are monitored to prevent the one turning ON from
tuning ON until the other's gate voltage is sufficiently low
(< 1 V). Built in delays also ensure that one power MOS is
completely OFF, before the other can be turned ON. This
feature helps to adjust dead time as gate transitions change
with respect to output current and temperature. Change
with respect to output current and temperature.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate
drive holding high-side and low-side MOSFET gates low
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC620,
SiC620A also incorporates logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 kΩ
resistor is connected between GH and PHASE to provide a
discharge path for the HS MOSFET.

Fig. 3 - SiC620 and SiC620A Functional Block Diagram

S14-2385-Rev. E, 08-Dec-14

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Document Number: 62922

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PWM

DSBL#

GH

GL

DSBL#Low to GH Falling Propagation Delay

t

DSBL# Low to GL Falling Propagation Delay

PWM

DSBL#

GH

GL

t

Disable

DEVICE TRUTH TABLE

DSBL# ZCD_EN# PWM GH GL

Open X X L L

LXXLL

HLLL

HLHHL

HLTri-stateLL

HHL LH

HHHHL

HHTri-stateL L

PWM TIMING DIAGRAM

SiC620, SiC620A

Vishay Siliconix

H, I

> 0 A

L

L, I

< 0 A

L

VTH_PWM_R

VTH_PWM_F

PWM

GL

GH

DSBL# PROPAGATION DELAY

t

PD_OFF _GL

t

PD_ON_GH

VTH_TRI_F

VTH_TRI_R

t

TSHO

t

PD_ON_GL

t

PD_OFF _GH

t

PD_TRI_R

Fig. 4 - Definition of PWM Logic and Tri-state

t

PD_TRI_R

t

TSHO

S14-2385-Rev. E, 08-Dec-14

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Fig. 5 - DSBL# Falling Propagation Delay

7

Document Number: 62922