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Z490 Aorus Pro AX
operation manual
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Gigabyte Z490 Aorus Pro AX operation manual

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PWM
controller
Gate
driver
5V V
IN
V
OUT
V
CIN
ZCD_EN#
DSBL#
PWM
THWn
V
DRV
G
H
V
IN
BOOT
V
SWH
P
GND
GL
C
GND
PHASE
60 A VRPower® Integrated Power Stage
SiC620, SiC620A
Vishay Siliconix
DESCRIPTION
The SiC620 and SiC620A are integrated power stage solutions optimized for synchronous buck applications to offer high current, high efficiency, and high power density performance. Packaged in Vishay’s proprietary
5 mm x 5 mm MLP package, SiC620 and SiC620A enables voltage regulator designs to deliver up to 60 A continuous current per phase.
The internal power MOSFETs utilizes Vishay’s state-of-the-art Gen IV TrenchFET technology that delivers industry benchmark performance to significantly reduce switching and conduction losses.
The SiC620 and SiC620A incorporates an advanced MOSFET gate driver IC that features high current driving capability, adaptive dead-time control, an integrated bootstrap Schottky diode, a thermal warning (THWn) that alerts the system of excessive junction temperature, and zero current detect to improve light load efficiency. The drivers are also compatible with a wide range of PWM controllers and supports tri-state PWM, 3.3 V (SiC620A) / 5 V (SiC620) PWM logic.
TYPICAL APPLICATION DIAGRAM
FEATURES
• Thermally enhanced PowerPAK® MLP55-31L package
• Vishay’s Gen IV MOSFET technology and a low-side MOSFET with integrated Schottky diode
• Delivers up to 60 A continuous current
• 95 % peak efficiency
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 12 V input stage
• 3.3 V (SiC620A) / 5 V (SiC620) PWM logic with tri-state and hold-off
• Zero current detect control for light load efficiency improvement
• Low PWM propagation delay (< 20 ns)
• Thermal monitor flag
• Under voltage lockout for V
CIN
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for CPU, GPU, and memory
S14-2385-Rev. E, 08-Dec-14
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 1 - SiC620 and SiC620A Typical Application Diagram
For technical questions, contact: powerictechsupport@vishay.com
1
Document Number: 62922
Page 2
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PINOUT CONFIGURATION
DSBL#
THWn
V
DRV
1
PWM
ZCD_EN#
V
CIN
C
GND
BOOT
GH
PHASE
V
2
3
CGND
4
5
6
7
8
IN
VIN
SiC620, SiC620A
Vishay Siliconix
V
V
V
P
GND
GL
GL
PGND
SWH
SWH
SWH
2425262728293031
23 V
22 V
21 V
20 V
19 V
18 V
17 V
16 V
SWH
SWH
SWH
SWH
SWH
SWH
SWH
SWH
33 GL
V
23
SWH
22
V
SWH
21
V
SWH
V
20
SWH
V
19
SWH
V
18
SWH
17
V
SWH
V
16
SWH
SWHVSWHVSWH
V
24 25 26 27 28 29 30 31
35
PGND
GND
DRV
P
GL
V
THWn
DSBL#
PWM
GL
32
CGND
34
VIN
1
ZCD_EN#
2
V
3
CIN
C
4
GND
BOOT
5
6
HG
7
PHASE
8
V
IN
1514131211109
P
VINVINV
IN
P
GND
GNDPGNDPGND
15 14 13 12 11 10 9
GNDPGNDPGNDPGND
P
Top view Bottom view
Fig. 2 - SiC620 and SiC620A Pin Configuration
PIN CONFIGURATION
PIN NUMBER NAME FUNCTION
1PWMPWM control input
2 ZCD_EN# ZCD control. Active low
3V
4, 32 C
CIN
GND
5 BOOT High-side driver bootstrap voltage
6 GH High-side gate signal
7 PHASE Return path of high-side gate driver
8 to 11, 34 V
12 to 15, 28, 35 P
16 to 26 V
IN
GND
SWH
27, 33 GL Low-side gate signal
29 V
DRV
30 THWn Thermal warning open drain output
31 DSBL# Disable pin. Active low
Supply voltage for internal logic circuitry
Analog ground for the driver IC
Power stage input voltage. Drain of high-side MOSFET
Power ground
Switch node of the power stage
Supply voltage for internal gate driver
VINVINV
IN
ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE OPTION
SiC620CD-T1-GE3 PowerPAK MLP55-31L SiC620 5 V PWM optimized
SiC620ACD-T1-GE3 PowerPAK MLP55-31L SiC620A 3.3 V PWM optimized
SiC620DB / SiC620ADB Reference board
S14-2385-Rev. E, 08-Dec-14
2
For technical questions, contact: powerictechsupport@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Document Number: 62922
Page 3
SiC620, SiC620A
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT
Input Voltage V
Control Logic Supply Voltage V
Drive Supply Voltage V
Switch Node (DC voltage)
Switch Node (AC voltage)
(1)
BOOT Voltage (DC voltage)
BOOT Voltage (AC voltage)
(2)
BOOT to PHASE (DC voltage)
BOOT to PHASE (AC voltage)
(3)
IN
CIN
DRV
V
SWH
V
BOOT
V
BOOT-PHASE
A ll Lo g ic I np ut s an d Ou tp u ts (PWM, DSBL#, and THWn)
Output Current, I
OUT(AV)
(4)
fS = 300 kHz, VIN = 12 V, V
= 1 MHz, VIN = 12 V, V
f
S
Max. Operating Junction Temperature T
Storage Temperature T
Electrostatic Discharge Protection
Human body model, JESD22-A114 3000
Charged device model, JESD22-C101 1000
J
A
stg
= 1.8 V 60
OUT
= 1.8 V 50
OUT
Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(1)
The specification values indicated “AC” is V
(2)
The specification value indicates “AC voltage” is V
(3)
The specification value indicates “AC voltage” is V
(4)
Output current rated with testing evaluation board at TA = 25 °C with natural convection cooling. The rating is limited by the peak evaluation board temperature, T
J
SWH
to P
-8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.
GND
to P
BOOT
BOOT
, 38 V (< 50 ns) max.
GND
to V
PHASE
, 8 V (< 20 ns) max.
-0.3 to +25
-0.3 to +7
-0.3 to +7
-0.3 to +25
-7 to +30
-0.3 to +7
-0.3 to +8
-0.3 to V
150
-40 to +125
-65 to +150
Vishay Siliconix
32
38
+0.3
CIN
V
A
°CAmbient Temperature T
V
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT
Input Voltage (V
Drive Supply Voltage (V
Control Logic Supply Voltage (V
Switch Node (V
BOOT to PHASE (V
Thermal Resistance from Junction to Ambient - 10.6 -
Thermal Resistance from Junction to Case - 1.6 -
S14-2385-Rev. E, 08-Dec-14
)4.5-18
IN
) 4.555.5
DRV
) 4.555.5
CIN
, DC voltage) - - 18
SWH
BOOT-PHASE
, DC voltage) 4 4.5 5.5
3
Document Number: 62922
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
V
°C/W
Page 4
SiC620, SiC620A
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ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, V
PARAMETER SYMBOL TEST CONDITION
POWER SUPPLY
Control Logic Supply Current I
Drive Supply Current I
BOOTSTRAP SUPPLY
Bootstrap Diode Forward Voltage V
PWM CONTROL INPUT (SiC620)
Rising Threshold V
Falling Threshold V
Tri-state Voltage V
Tri-state Rising Threshold V
Tri-state Falling Threshold V
Tri-state Rising Threshold Hysteresis
Tri-state Falling Threshold Hysteresis
PWM Input Current I
PWM CONTROL INPUT (SiC620A)
Rising Threshold V
Falling Threshold V
Tri-state Voltage V
Tri-state Rising Threshold V
Tri-state Falling Threshold V
Tri-state Rising Threshold Hysteresis
Tri-state Falling Threshold Hysteresis
PWM Input Current I
TIMING SPECIFICATIONS
Tri-State to GH/GL Rising Propagation Delay
Tri-state Hold-Off Time t
GH - Turn Off Propagation Delay t
GH - Turn On Propagation Delay (Dead time rising)
GL - Turn Off Propagation Delay t
GL - Turn On Propagation Delay (Dead time falling)
DSBL# Lo to GH/GL Falling Propagation Delay
PWM Minimum On-Time t
= 12 V, V
IN
VCIN
VDRV
TH_PWM_R
TH_PWM_F
TRI_TH_R
TRI_TH_F
V
HYS_TRI_R
V
HYS_TRI_F
PWM
TH_PWM_R
TH_PWM_F
TRI_TH_R
TRI_TH_F
V
HYS_TRI_R
V
HYS_TRI_F
PWM
t
PD_TRI_R
TSHO
PD_OFF_GH
t
PD_ON_GH
PD_OFF_GL
t
PD_ON_GL
t
PD_DSBL#_F
PWM_ON_MIN
TRI
TRI
DRV
and V
= 5 V, TA = 25 °C)
CIN
MIN. TYP. MAX.
V
= 0 V, no switching - 12 -
DSBL#
= 5 V, no switching, V
DSBL#
V
= 5 V, fS = 300 kHz, D = 0.1 - 380 -
DSBL#
= FLOAT - 300 -
PWM
fS = 300 kHz, D = 0.1 - 15 25
= 1 MHz, D = 0.1 - 50 -
f
S
V
= 0 V, no switching - 25 -
DSBL#
= 5 V, no switching - 60 -
V
DSBL#
F
IF = 2 mA 0.4 V
3.4 3.8 4.2
0.72 0.9 1.1
V
= FLOAT - 2.3 -
PWM
0.9 1.15 1.38
33.33.6
- 225 -
- 325 -
V
= 5 V - - 350
PWM
= 0 V - - -350
V
PWM
2.2 2.45 2.7
0.72 0.9 1.1
V
= FLOAT - 1.8 -
PWM
0.9 1.15 1.38
1.95 2.2 2.45
- 250 -
- 300 -
V
= 3.3 V - - 225
PWM
= 0 V - - -225
V
PWM
-30-
- 130 -
-15-
No load, see fig. 4
-10-
-12-
-10-
Fig. 5 - 15 -
30 - -
Vishay Siliconix
LIMITS
UNIT
μAV
mA
μA
V
mV
μA
V
mV
μA
ns
S14-2385-Rev. E, 08-Dec-14
4
Document Number: 62922
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Page 5
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ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, V
PARAMETER SYMBOL TEST CONDITION
DSBL# ZCD_EN# INPUT
DSBL# Logic Input Voltage
ZCD_EN# Logic Input Voltage
PROTECTION
Under Voltage Lockout V
Under Voltage Lockout Hysteresis V
THWn Flag Set
THWn Flag Hysteresis
THWn Output Low V
Notes
(1)
Typical limits are established by characterization and are not production tested.
(2)
Guaranteed by design.
(2)
(2)
(2)
= 12 V, V
IN
V
IH_DSBL#
V
IL_DSBL#
V
IH_ZCD_EN#
V
IL_ZCD_EN#
UVLO
UVLO_HYST
T
THWn_SET
T
THWn_CLEAR
T
THWn_HYST
OL_THWn
DRV
and V
= 5 V, TA = 25 °C)
CIN
MIN. TYP. MAX.
Input logic high 2 - -
Input logic low - - 0.8
Input logic high 2 - -
Input logic low - - 0.8
V
rising, on threshold - 3.7 4.1
CIN
falling, off threshold 2.7 3.1 -
V
CIN
I
= 2 mA - 0.02 - V
THWn
SiC620, SiC620A
Vishay Siliconix
LIMITS
- 575 - mV
- 160 -
- 135 -
-25-
UNIT
V
V
°CTHWn Flag Clear
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR controller IC. The PWM input is designed to be compatible with standard controllers using two state logic (H and L) and advanced controllers that incorporate tri-state logic (H, L and tri-state) on the PWM output. For two state logic, the PWM input operates as follows. When PWM is driven above V
PWM_TH_R
turned on. When PWM input is driven below V
the low-side is turned on and the high-side is
PWM_TH_F
the high-side is turned OFF and the low-side is turned ON. For tri-state logic, the PWM input operates as previously stated for driving the MOSFETs. However, there is an third state that is entered as the PWM output of tri-state compatible controller enters its high impedance state during shut-down. The high impedance state of the controller’s PWM output allows the SiC620 and SiC620A to pull the PWM input into the tri-state region (see PWM Timing Diagram). If the PWM input stays in this region for the tri-state hold-off period,
, both high-side and low-side MOSFETs are turned
t
TSHO
OFF. This function allows the VR phase to be disabled without negative output voltage swing caused by inductor ringing and saves a Schottky diode clamp. The PWM and tri-state regions are separated by hysteresis to prevent false triggering. The SiC620A incorporates PWM voltage thresholds that are compatible with 3.3 V logic and the SiC620 thresholds are compatible with 5 V logic.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and disables both high-side and low-side MOSFETs. In this state, standby current is minimized. If DSBL# is left unconnected, an internal pull-down resistor will pull the pin to C
S14-2385-Rev. E, 08-Dec-14
and shut down the IC.
GND
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Diode Emulation Mode (ZCD_EN#)
When ZCD_EN# pin is logic Low and PWM signal switches Low, GL is forced on (after normal BBM time). During this time, it is under control of the ZCD (zero crossing detect) comparator. If, after the internal blanking delay, the inductor current becomes zero, the low-side is turned off. This improves light load efficiency by avoiding discharge of output capacitors. If PWM enters tri-state, then device will go into normal tri-state mode after tri-state delay. The GL output will be turned off regardless of Inductor current, this is an alternative method of improving light load efficiency by reducing switching losses.
Thermal Shutdown Warning (THWn)
The THWn pin is an open drain signal that flags the presence of excessive junction temperature. Connect with a maximum of 20 kΩ, to V
. An internal temperature sensor
CIN
detects the junction temperature. The temperature threshold is 160 °C. When this junction temperature is exceeded the THWn flag is set. When the junction temperature drops below 135 °C the device will clear the THWn signal. The SiC620 and SiC620A do not stop operation when the flag is set. The decision to shutdown must be made by an external thermal control function.
Voltage Input (V
)
IN
This is the power input to the drain of the high-side power MOSFET. This pin is connected to the high power intermediate BUS rail.
5
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DISB#
20K
V
SWH
V
SWH
GL
+
-
GL
+
-
ZCD_EN#
Thermal monitor
& warning
UVLO
V
CIN
PWM logic
control &
state
machine
Anti-cross
conduction
control
logic
BOOT
THWn
V
IN
GH
PWM
C
GND
V
CIN
V
ref
= 1 V
V
ref
= 1 V
P
GND
PHASE
V
DRV
V
DRV
P
GND
SiC620, SiC620A
Vishay Siliconix
Switch Node (V
The switch node, V
and PHASE)
SWH
, is the circuit power stage output.
SWH
This is the output applied to the power inductor and output filter to deliver the output for the buck converter. The PHASE pin is internally connected to the switch node V
SWH
. This pin is to be used exclusively as the return pin for the BOOT capacitor. A 20 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET in the event that V
Ground Connections (C
P
(power ground) should be externally connected
GND
to C
(control signal ground). The layout of the printed
GND
goes to zero while VIN is still applied.
CIN
GND
and P
GND
)
circuit board should be such that the inductance separating C
GND
and P
is minimized. Transient differences due to
GND
inductance effects between these two pins should not exceed 0.5 V
Control and Drive Supply Voltage Input (V
V
is the bias supply for the gate drive control IC. V
CIN
DRV
, V
CIN
)
DRV
is the bias supply for the gate drivers. It is recommended to separate these pins through a resistor. This creates a low pass filtering effect to avoid coupling of high frequency gate drive noise into the IC.
FUNCTIONAL BLOCK DIAGRAM
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap capacitor form a charge pump that supplies voltage to the BOOT pin. An integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. Connect a boot strap capacitor with one leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC620 and SiC620A have an internal adaptive logic to avoid shoot through and optimize dead time. The shoot through protection ensures that both high-side and low-side MOSFETs are not turned ON at the same time. The adaptive dead time control operates as follows. The HS and LS gate voltages are monitored to prevent the one turning ON from tuning ON until the other's gate voltage is sufficiently low (< 1 V). Built in delays also ensure that one power MOS is completely OFF, before the other can be turned ON. This feature helps to adjust dead time as gate transitions change with respect to output current and temperature. Change with respect to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate drive holding high-side and low-side MOSFET gates low until the supply voltage rail has reached a point at which the logic circuitry can be safely activated. The SiC620, SiC620A also incorporates logic to clamp the gate drive signals to zero when the UVLO falling edge triggers the shutdown of the device. As an added precaution, a 20 kΩ resistor is connected between GH and PHASE to provide a discharge path for the HS MOSFET.
Fig. 3 - SiC620 and SiC620A Functional Block Diagram
S14-2385-Rev. E, 08-Dec-14
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6
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Page 7
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PWM
DSBL#
GH
GL
DSBL#Low to GH Falling Propagation Delay
t
DSBL# Low to GL Falling Propagation Delay
PWM
DSBL#
GH
GL
t
Disable
DEVICE TRUTH TABLE
DSBL# ZCD_EN# PWM GH GL
Open X X L L
LXXLL
HLLL
HLHHL
HLTri-stateLL
HHL LH
HHHHL
HHTri-stateL L
PWM TIMING DIAGRAM
SiC620, SiC620A
Vishay Siliconix
H, I
> 0 A
L
L, I
< 0 A
L
VTH_PWM_R
VTH_PWM_F
PWM
GL
GH
DSBL# PROPAGATION DELAY
t
PD_OFF _GL
t
PD_ON_GH
VTH_TRI_F
VTH_TRI_R
t
TSHO
t
PD_ON_GL
t
PD_OFF _GH
t
PD_TRI_R
Fig. 4 - Definition of PWM Logic and Tri-state
t
PD_TRI_R
t
TSHO
S14-2385-Rev. E, 08-Dec-14
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Fig. 5 - DSBL# Falling Propagation Delay
7
Document Number: 62922
Page 8
SiC620, SiC620A
80
82
84
86
88
90
92
94
96
0 5 10 15 20 25 30 35 40 45 50 55
Efciency (%)
Output Current, I
OUT
(A)
Complete converter efciency
P
IN
= [(VIN x IIN) + 5 V x (I
VDRV
+ I
VCIN
)]
P
OUT
= V
OUT
x I
OUT
, measured at output capacitor
500 kHz
300 kHz
1 MHz
800 kHz
I
OUT
= 30 A
0.9
0.95
1
1.05
1.1
1.15
1.2
4 6 8 1012141618
Normalized Power Loss
Input Voltage, V
IN
(V)
0.8
0.9
1
1.1
1.2
1.3
1.4
200 300 400 500 600 700 800 900 1000 1100
Normalized Power Loss
Switching Frequency, fs (kHz)
I
OUT
= 30 A
0.9
0.95
1
1.05
1.1
1.15
1.2
4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
Normalized Power Loss
Drive Supply Voltage, V
DRV
(V)
I
OUT
= 30 A
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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 12 V, V cooling (All power loss and normalized power loss curves show SiC620 and SiC620A losses only unless otherwise stated)
Fig. 6 - Efficiency vs. Output Current
DRV
= V
= 5 V, ZCD_EN# = 5 V, V
CIN
= 1.8 V, L
OUT
= 250 nH (DCR = 0.32 mΩ), TA = 25 °C, natural convection
OUT
65
60
55
50
45
40
35
30
25
20
Power Output Purrent, IOUT (A)
15
10
5
0
0 25 50 75 100 125 150
PCB Temperature, T
Fig. 9 - Safe Operating Area
Vishay Siliconix
1 MHz
(°C)
PCB
300 kHz
8
7
6
5
(W)
L
4
3
Power Loss, P
2
1
0
0 5 10 15 20 25 30 35 40 45 50 55
Output Current, I
Fig. 7 - Power Loss vs. Output Current
S14-2385-Rev. E, 08-Dec-14
Fig. 8 - Power Loss vs. Input Voltage
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800 kHz
500 kHz
300 kHz
(A)
OUT
1 MHz
Fig. 10 - Power Loss vs. Switching Frequency
Fig. 11 - Power Loss vs. Drive Supply Voltage
8
Document Number: 62922
Page 9
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0.8
0.9
1
1.1
1.2
1.3
0.5 1 1.5 2 2.5 3 3.5
Normalized Power Loss
Output Voltage, V
OUT
(V)
I
OUT
= 30 A
5
10
15
20
25
30
35
40
45
4.00 4.25 4.50 4.75 5.00 5.25 5.50
Driver Supply Current, I
VDRV
& I
VCIN
(mA)
Driver Supply Voltage, V
DRV &VCIN
(V)
I
OUT
= 0 A
1 MHz
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
0 5 10 15 20 25 30 35 40 45 50 55
Normalized Driver Supply Current, I
VCIN
and I
VDRV
Output Current, I
OUT
(A)
300 kHz
I
OUT
= 30 A
0.97
0.98
0.99
1
1.01
200 250 300 350 400 450 500
Normalized Power Loss
Output Inductor, L
OUT
(nH)
SiC620, SiC620A
Vishay Siliconix
Fig. 12 - Power Loss vs. Output Voltage
Fig. 13 - Driver Supply Current vs. Driver Supply Voltage
Fig. 15 - Power Loss vs. Output Inductor
50
(mA)
CVIN
and I
VDRV
45
40
35
30
25
I
= 0 A
OUT
20
15
10
Driver Supply Current, I
5
0
300 400 500 600 700 800 900 1000
Switching frequency, fs (kHz)
Fig. 16 - Driver Supply Current vs. Switching Frequency
4.2
4.0
(V)
3.8
CIN
3.6
V
UVLO_RISING
Fig. 14 - Driver Supply Current vs. Output Current
S14-2385-Rev. E, 08-Dec-14
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3.4
3.2
3.0
2.8
Control Logic Supply Voltage, V
2.6
-60 -40 -20 0 20 40 60 80 100 120 140
Fig. 17 - UVLO Threshold vs. Temperature
9
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V
UVLO_FALLING
Temperature (°C)
Document Number: 62922
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0.40
0.75
1.10
1.45
1.80
2.15
2.50
2.85
3.20
-60 -40 -20 0 20 40 60 80 100 120 140
Control Logic Supply Voltage, V
PWM
(V)
Temperature (°C)
V
TRI_TH_R
V
TRI_TH_F
V
TRI
V
TH_PWM_R
V
TH_PWM_F
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-60 -40 -20 0 20 40 60 80 100 120 140
Control Logic Supply Voltage, V
PWM
(V)
Temperature (°C)
V
TRI_TH_R
V
TRI_TH_F
V
TRI
V
TH_PWM_R
V
TH_PWM_F
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
-60 -40 -20 0 20 40 60 80 100 120 140
DSBL# Threshold Voltage, V
DSBL#
(V)
Temperature (°C)
V
IL_DSBL#
V
IH_DSBL#
0.40
0.75
1.10
1.45
1.80
2.15
2.50
2.85
3.20
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
PWM Threshold Voltage, V
PWM
(V)
Driver Supply Voltage, V
CIN
(V)
V
TH_PWM_F
V
TH_PWM_R
V
TRI_TH_F
V
TRI_TH_R
V
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
ZCD_EN# Threshold Voltage, V
ZCD_EN#
(V)
Driver Supply Voltage, V
CIN
(V)
V
IH_ZCD_EN#_R
V
IL_ZCD_EN#_F
SiC620, SiC620A
Vishay Siliconix
TRI
Fig. 18 - PWM Threshold vs. Temperature (SiC620A)
Fig. 19 - PWM Threshold vs. Temperature (SiC620)
Fig. 21 - PWM Threshold vs. Driver Supply Voltage (SiC620A)
5.00
4.50
(V)
4.00
PWM
3.50
3.00
V
2.50
TRI
V
TH_PWM_R
V
TRI_TH_F
2.00
1.50
1.00
PWM Threshold Voltage, V
0.50
V
TRI_TH_R
V
TH_PWM_F
0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 Driver Supply Voltage, V
(V)
CIN
Fig. 22 - PWM Threshold vs. Driver Supply Voltage (SiC620)
S14-2385-Rev. E, 08-Dec-14
Fig. 20 - DSBL# Threshold vs. Temperature
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 23 - ZCD_EN# Threshold vs. Driver Supply Voltage
10
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0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
DSBL# Threshold Voltage, V
DSBL#
(V)
Driver Supply Voltage, V
CIN
(V)
V
IH_DSBL#
V
IL_DSBL#
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
-60 -40 -20 0 20 40 60 80 100 120 140
DSBL# Pull-Down Current, I
DSBL#
(uA)
Temperature (°C)
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-60 -40 -20 0 20 40 60 80 100 120 140
BOOT Diode Forward Voltage, V
F
(V)
Temperature (°C)
IF= 2 mA
SiC620, SiC620A
Vishay Siliconix
80
Fig. 24 - DSBL# vs. Driver Input Voltage
70
V
(V)
& I
60
VCIN
50
VDVR
40
DSBL#
30
20
10
Driver Supply Current, I
0
-60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)
Fig. 27 - Driver Shutdown Current vs. Temperature
390
380
(V)
370
VCIN
& I
360
VDVR
350
340
V
PWM
= FLOAT
= 0 V
330
320
Driver Supply Current, I
310
-60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C)
Fig. 25 - DSBL# Pull-Down Current vs. Temperature
Fig. 26 - Boot Diode Forward Voltage vs. Temperature
Fig. 28 - Driver Supply Current vs. Temperature
S14-2385-Rev. E, 08-Dec-14
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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PGND Plane
VSWH
Snubber
V
SWH
P
GND
plane
C
GND
C
VCIN
C
VDRV
P
G
N D
PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling
V
SWH
P
GND
V
IN
V
plane
IN
P
GND
plane
Step 3: V
CIN/VDRV
SiC620, SiC620A
Vishay Siliconix
Input Filter
1. Layout VIN and P
planes as shown above
GND
2. Ceramic capacitors should be placed right between V and P
, and very close to the device for best
GND
decoupling effect
3. Difference values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210, 0805, 0603 and 0402
4. Smaller capacitance value, closer to device V
pin(s)
IN
- better high frequency noise absorbing
Step 2: V
SWH
Plane
1. The V
IN
2. C
3. C
CIN/VDRV
very close to IC. It is recommended to connect two caps separately.
cap should be placed between pin 3 and pin 4
VCIN
(C
of driver IC) to achieve best noise filtering.
GND
cap should be placed between pin 28 (P
VDRV
input filter ceramic cap should be placed
of
GND
driver IC) and pin 29 to provide maximum instantaneous driver current for low-side MOSFET during switching cycle
4. For connecting C
analog ground, it is recommended
VCIN
to use large plane to reduce parasitic inductance.
Step 4: BOOT Resistor and Capacitor Placement
Cboot
Rboot
1. Connect output inductor to DrMOS with large plane to lower the resistance
2. If any snubber network is required, place the components as shown above and the network can be placed at bottom
S14-2385-Rev. E, 08-Dec-14
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1. These components need to be placed very close to IC, right between PHASE (pin 7) and BOOT (pin 5).
2. To reduce parasitic inductance, chip size 0402 can be used.
12
Document Number: 62922
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VIN plane
P
GND
plane
V
SWH
P
GND
V
IN
C
GND
V
SWH
P
GND
C
GND
Step 5: Signal Routing
C
GND
C
GND
P
GND
1. Route the PWM / ZCD_EN# / DSBL# / THWn signal traces out of the top left corner next DrMOS pin 1.
2. PWM signal is very important signal, both signal and return traces need to pay special attention of not letting this trace cross any power nodes on any layer.
3. It is best to “shield” traces form power switching nodes, e.g. V
4. GL (pin 27) has been connected with GL pad internally and does not need to connect externally.
Step 6: Adding Thermal Relief Vias
, to improve signal integrity.
SWH
SiC620, SiC620A
Vishay Siliconix
1. Thermal relief vias can be added on the V pads to utilize inner layers for high-current and thermal dissipation.
2. To achieve better thermal performance, additional vias can be put on VIN plane and P
3. V
pad is a noise source and not recommended to put
SWH
GND
plane.
vias on this plane.
4. 8 mil drill for pads and 10 mils drill for plane can be the optional via size. Vias on pad may drain solder during assembly and cause assembly issue. Please consult with the assembly house for guideline.
Step 7: Ground Connection
1. It is recommended to make single connection between C
GND
and P
and this connection can be done on top
GND
layer.
2. It is recommended to make the whole inner 1 layer (next to top layer) ground plane and separate them into C and P
GND
plane.
3. These ground planes provide shielding between noise source on top layer and signal trace on bottom layer.
and P
IN
GND
GND
S14-2385-Rev. E, 08-Dec-14
13
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Document Number: 62922
Page 14
SiC620, SiC620A
V
OUT
P
GND
V
IN
www.vishay.com
Multi-Phases VRPower PCB Layout
Following is an example for 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with decoupling caps next to them. The inductors are placed as close as possible to the SiC620 and SiC620A to minimize the PCB copper loss. Vias are applied on all PADs (VIN, P performance are excellent. Large copper planes are used for all the high current loops, such as VIN, V copper planes are duplicated in other layers to minimize the inductance and resistance. All the control signals are routed from the SiC620 and SiC620A to a controller placed to the north of the power stage through inner layers to avoid the overlap of high current loops. This achieves a compact design with the output from the inductors feeding a load located to the south of the design as shown in the figure.
GND
, C
) of the SiC620 and SiC620A to ensure that both electrical and thermal
GND
Vishay Siliconix
, V
OUT
and P
GND
SWH
. These
V
P
IN
GND
Fig. 29 - Multi - Phase VRPower Layout Top View
V
OUT
Fig. 30 - Multi - Phase VRPower Layout Bottom View
S14-2385-Rev. E, 08-Dec-14
14
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Document Number: 62922
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Land pattern for MLP55-31LPackage outline top view, transparent
All dimensions in millimeters
1.75
0.1
0.4
0.75
24
1
0.3
0.3
0.5
1.15
1.13
31
1.35
5
0.57
2.02
23
16
0.75
15
0.5
0.18
0.35
0.35
0.65
0.5
9
0.35
0.3
1
5
0.35
0.15
1.42
0.33
0.07
0.42.08
0.55
1.2
2.15
3.05
0.3
0.33
0.75
1.6
3.5
0.3
0.65
0.58 0.5
8
(D2-4)
3.4
(D2-1)
1.03
(D2-5)
1.05 24
31
(K2) 0.22
(K1) 0.67
(D3) 0.3
(D2-2)
1.03
(D2-3)
1.92
9
15
16
23
8
1
24
31
9
15
16
23
8
1
(L)
0.4
(L)
0.4
(E2-2)
1.32
0.5 (e)
(E2-3)
1.98
(E3)
0.45
(E2-1)
4.2
(b)
0.25
33
33
32
35
RECOMMENDED LAND PATTERN POWERPAK MLP55-31L
SiC620, SiC620A
Vishay Siliconix
S14-2385-Rev. E, 08-Dec-14
15
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Document Number: 62922
Page 16
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by marking
E
Pin 1 dot
Top view
D
MLP55-31L
(5 mm x 5 mm)
E2- 1
(Nd-1) x e
ref.
Bottom viewSide view
e
D2-3 D2-2
E2- 2
A
0.1
C
A
2x
0.1 C B
2x
0.08 C
C
A
A2
A1
B
(Nd-1) x e
ref.
K7
56
D2- 1
E2- 3
4
0.1
M
CAB
D2-4
E2-4
1
9
8
1
16
23
31
24
15
9
8
K8
b
L
K3
K10
K1
K2
K4
K5
K6
K9
D2-5
K11
K12
PACKAGE OUTLINE DRAWING MLP55-31L
SiC620, SiC620A
Vishay Siliconix
DIM.
(8)
A
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
(4)
b
D 5.00 BSC 0.196 BSC
e 0.50 BSC 0.019 BSC
E 5.00 BSC 0.196 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
(3)
N
(3)
Nd
(3)
Ne
D2-1 0.98 1.03 1.08 0.039 0.041 0.043
D2-2 0.98 1.03 1.08 0.039 0.041 0.043
D2-3 1.87 1.92 1.97 0.074 0.076 0.078
D2-4 0.30 BSC 0.012 BSC
D2-5 1.00 1.05 1.10 0.039 0.041 0.043
E2-1 1.27 1.32 1.37 0.050 0.052 0.054
E2-2 1.93 1.98 2.03 0.076 0.078 0.080
E2-3 3.75 3.80 3.82 0.148 0.150 0.152
E2-4 0.45 BSC 0.018 BSC
K1 0.67 BSC 0.026 BSC
K2 0.22 BSC 0.008 BSC
K3 1.25 BSC 0.049 BSC
S14-2385-Rev. E, 08-Dec-14
MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
0.70 0.75 0.80 0.027 0.029 0.031
0.20 0.25 0.30 0.008 0.010 0.012
32 32
88
88
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16
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Document Number: 62922
Page 17
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SiC620, SiC620A
Vishay Siliconix
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
MILLIMETERS INCHES
K4 0.05 BSC 0.002 BSC
K5 0.38 BSC 0.015 BSC
K6 0.12 BSC 0.005 BSC
K7 0.40 BSC 0.016 BSC
K8 0.40 BSC 0.016 BSC
K9 0.40 BSC 0.016 BSC
K10 0.85 BSC 0.033 BSC
K11 0.40 BSC 0.016 BSC
K12 0.40 BSC 0.016 BSC
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62922
S14-2385-Rev. E, 08-Dec-14
.
17
Document Number: 62922
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Page 18
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by marking
E
Pin 1 dot
Top view
D
MLP55-31L
(5 mm x 5 mm)
E2- 1
(Nd-1) x e
ref.
Bottom view
Side view
e
D2- 3 D2- 2
E2- 2
A
0.10 C A
2 x
0.10 C B
2 x
0.08 C
C
A
A2
A1
B
(Nd-1) xe
ref.
K7
56
D2- 1
E2- 3
4
0.10 m C A B
D2- 4
E2-4
K8
b
L
K3
K10
K1
K2
K4
K5
K6
K9
D2-5
K11
K12
F1
F2
1
9
8
1
16
23
31
24
15
9
8
PowerPAK® MLP55-31L Case Outline
Package Information
Vishay Siliconix
DIM.
Nd
Ne
D2-1 0.98 1.03 1.08 0.039 0.041 0.043
D2-2 0.98 1.03 1.08 0.039 0.041 0.043
D2-3 1.87 1.92 1.97 0.074 0.076 0.078
D2-4 0.30 BSC 0.012 BSC
D2-5 1.00 1.05 1.10 0.039 0.041 0.043
E2-1 1.27 1.32 1.37 0.050 0.052 0.054
E2-2 1.93 1.98 2.03 0.076 0.078 0.080
E2-3 3.75 3.80 3.82 0.148 0.150 0.152
E2-4 0.45 BSC 0.018 BSC
Revision: 24-Oct-16
MILLIMETERS INCHES
MIN. NOM. MAX. MIN. NOM. MAX.
(8)
A
0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
(4)
b
0.20 0.25 0.30 0.008 0.010 0.012
D 4.90 5.00 5.10 0.193 0.196 0.200
e 0.50 BSC 0.019 BSC
E 4.90 5.00 5.10 0.193 0.196 0.200
L 0.35 0.40 0.45 0.013 0.015 0.017
(3)
N
(3)
(3)
F1 0.20 BSC 0.008 BSC
F2 0.20 BSC 0.008 BSC
32 32
88
88
K1 0.67 BSC 0.026 BSC
K2 0.22 BSC 0.008 BSC
K3 1.25 BSC 0.049 BSC
K4 0.05 BSC 0.002 BSC
K5 0.38 BSC 0.015 BSC
K6 0.12 BSC 0.005 BSC
1
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Document Number: 64909
Page 19
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Package Information
Vishay Siliconix
DIM.
K7 0.40 BSC 0.016 BSC
K8 0.40 BSC 0.016 BSC
K9 0.40 BSC 0.016 BSC
K10 0.85 BSC 0.033 BSC
K11 0.40 BSC 0.016 BSC
K12 0.40 BSC 0.016 BSC
ECN: T16-0644-Rev. E, 24-Oct-16 DWG: 6025
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals,
Nd is the number of terminals in X-direction, and
Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
MIN. NOM. MAX. MIN. NOM. MAX.
MILLIMETERS INCHES
Revision: 24-Oct-16
For technical questions, contact: powerictechsupport@vishay.com
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
2
Document Number: 64909
Page 20
1.32
(E2-2)
1.98
(E2-3)
(L)
0.4
www.vishay.com
PowerPAK
Top side transparent view
(not bottom view)
(D2-4)
1.03
1.03
(E3)
3.4
0.45
1
0.5 (e)
8
31
9
(D2-1)
(D2-2)
Recommended Land Pattern
®
MLP55-31L for SiC620, SiC620A
(D2-5)
1.05 24
(D3) 0.3
(K2) 0.22
(K1) 0.67
(D2-3)
1.92
23
4.2
(E2-1)
(b)
0.25
16
15
(L)
0.4
5
0.3
1
0.35
0.58 0.5
0.15
8
0.35
Land pattern for MLP55-31L
5
2.15
1.6
0.85
2.02
3.05
1.35
1.15
1.75
0.18
0.5
0.75
31
1.42
0.42.08
9
0.5
0.5
1.13
0.3
0.33
0.07
0.35
0.35
0.65
PAD Pattern
Vishay Siliconix
0.57
0.3
23
16
0.3
0.33
0.3
0.75
3.5
0.65
1
24
15
0.75
All dimensions in millimeters
31
1
32
33
8
9
33
24
23
35
16
15
Component for MLP55-31L
Land pattern for MLP55-31L
Revision: 24-Jul-17
1
Document Number: 66944
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Page 21
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
1
Document Number: 91000
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