Circuit or PCB layout change for
next version history
PCB Rev
1.009/03Initial Version1.0B10/09 Change Memory &
DateChange ItemReason
BB
AA
GIGABYTE
Title
BOM & PCB Modify History
Size Document NumberRev
C
5
4
3
2
Date:Sheet
GV-N52128D
1
11Monday, February 02, 2004
1.0
of
5
4
3
2
1
FGH
PAGE
DATE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
DETAIL
ID
NAME
DE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
8 DAC A,B, DAC B MUX, PLL, Video OUT
9 DAC A,B RGB filter
10 Power Supply A3V3, FBVDD/FBVDDQ, Mechanicals.
11 BIOS and Strapping
12 DVO,GPIOs and Xtal.
13 TMDS LinkA and its power supplies, Backdrive.
14 NVVDD SW.
15 Current Supplement and Fan control.
16 Net Rules.
P162-A00 History:
1-Added P162 specific features:
- SW PS,TMDS LinkA, Backdrive, new slim VGA, Fan Cntl.
- Added Current sharing, TMDS IO and PLL linear regulators.
2-Added TH parts in PS section as ALT.
3-Added SST serial support.
4-Changed AGP_PLL_VDD, FB_PLLVDD, DAC_A/B_VDD and PLL_VDD to A3V3.
5-Added 10 caps as part of P160 sync up.
6-Added PU resitors on Jtag TMS and TDI
7-Incorporated recommendations from PS Vendor.
8-Added extra X elements near connectors to bridge CGND and GND cut.
9-Added an option to use a single dual FET for low end bd.
10-Fixed error on 6529 power good and current supplement.
11-Changed C302 to 0603 (too big pkg for .1uf in 0805)
12-Deleted C296 and C293 (shared them with C313, C324)
13-Changed C329 and C324 to 0603 pkg.
14-Removed alternate Semtech SW (could not route).
Changes after the design review:
1-Remove C301 and R137-left over from Semtech PS circuit.
2-Remove sync buffer bypass resistors.
3-Remove R122 and R123 from Intersil power rails.
4-Add snubber circuit for NVVDD PS.
5-Add PD res on TP_XTALOUTBUF to terminate the signal.
6-Fan controler PU to 3V3 from A3V3.
7-Cleaned up Unnamed nets.
============================
8-Split CGND into 2 nets (added CGND1 to J6.25 and J2. 16).
9-Added PD resistor on FAN_ON.
10-Added 8 caps for DQS/DQM routings that break plane reference.
P162-A01 History:
Merged net IFPBIOVDD with IFPAIOVDD.
P160 HISTORY:
INITIAL VERSIONX00
X01
X02
X03
X04
X05
X06
X07
X08
Cleaned up schematics - changes from initial design review meeting
Imported board file #65 and synchronized with latest version of schematics.
Nov 18/02 - Replaced LB502 with an 805 bead, changed PLLVDD rail to 3V3
instead of A3V3, and removed AGPVDDQ deoupling caps C130, C257, and C570.
Nov 21/02 - C75 is changed to decouple 3V3 to GND.
Nov 22/02 - VIP interface rail changed to 3V3 instead of A3V3 due to
short between VIPVDDQ and VDD33.
Nov 25/02 - FRWR_VAUXP rail changed to 3V3.
Nov 26/02 - Changed DACB_LOAD_TEST GPIO assignment for NV34.
Dec 02/02 - AGP_PLL_VDD and FB_DLLVDD are supplied from A3V3 rail.
P162-C00 History:
Added PUs on TMDS diff pairs by the GPU and series Rs by the conn.
Merged Q4 and Q5 into one package.
Implemented TV signal return scheme thru zero Ohm resistors.
P162-A02 History:
The main changes for this revision is to improve routing for DAC B and
add 100ps inter-pair skew to pass EMC as modeled on A01 board. See 149- document for detail.
P162-A03 History:
Merged CGND and GND to become GND net to pass EMI at 16x12. This modificaiton was tested on P162-A02
P162-B00 History:
Removed TMDS backdrive prevention circuit.
Changed memory FBVDD(Q) to be regulated from AGP3.3V (was from AGP5V)
Added power sequencing (BUGID 74855)
Isolated 5VCLAMP and I2C PU from AGP5V.
P162-B01 History:
Modified Current Supplement circuit to prevent bacdrive into AGP3V3 from AGP5V. GPIO5 state is
unknown before valid PCICLK.
Isolated IFPA/BIOGND from the main digital GND to improve 16x12 TMDS emission.
Moved Sync buffer VDD and Fuse to 5VCLAMP (was 5V)--BugID:78364.
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
DETAIL
ID
NAME
DE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
DETAIL
ID
NAME
DE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
NOT USED
NOT USED
NOT USED
NOT USED50 OHM 1% TO FBVDDQ50 OHM 1% TO FBVDDQFBCAL_PD_VDDQ
GND
R12
0
5%
0402
COMMON
NOT USED ON NV18B
FBVDDQ
R34
49.9
1%
0402
COMMON
R35
49.9
1%
0402
COMMON
GND
TARGET RESISTANCE IS 550 OHM
1.2V / 550 ohm = 2.2 mA
1.2V / 550 ohm = 2.2 mA
NV31
TIE TO GND
550 OHM 1% TO GND
50 OHM 1% TO GND
GND
DRAWING DETAIL
CONTINUED...
p162
mlao
NV34
NOT USED
NOT USED
50 OHM 1% TO GND
3 OF 19
SEP 03 2001
IN
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
Vref
NCNCNC
RAS
CAS
WE
A<3>
A<1>
A<0>
A<4>
A<6>
A<5>
A<2>
CS
A<7>
BA<0>
A<12>
A<11>
AP/A<10>
A<8>
BA<1>
A<9>
CKE
CLK
NCNCNC
CLK
INININININININ
IN
DQ<4>
DQ<3>
DQ<2>
DQ<0>
DQ<1>
DQ<5>
DQS
DQM
DQ<6>
DQ<7>
IN
DQ<4>
DQ<3>
DQ<2>
DQ<0>
DQ<1>
DQ<5>
DQS
DQM
DQ<6>
DQ<7>
OUT
DQ<4>
DQ<3>
DQ<2>
DQ<0>
DQ<1>
DQ<5>
DQS
DQM
DQ<6>
DQ<7>
IN
DQ<4>
DQ<3>
DQ<2>
DQ<0>
DQ<1>
DQ<5>
DQS
DQM
DQ<6>
DQ<7>
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
Vref
NCNCNC
RAS
CAS
WE
A<3>
A<1>
A<0>
A<4>
A<6>
A<5>
A<2>
CS
A<7>
BA<0>
A<12>
A<11>
AP/A<10>
A<8>
BA<1>
A<9>
CKE
CLK
NCNCNC
CLK
INININININININININBIIN
IN
5
4
3
2
1
FGH
PAGE
DATE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
DETAIL
ID
NAME
DE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
BC
2
A
1
3
4
5
EGDFHCBA
MEMORY 1st bank 0..31
PLACE ALL DISCRETE COMPONENTS AS NEAR AS POSSIBLE TO MEMORY
NV31 FB i/f can be configured in two ways:
2x64 bits or 2x32 bits
THIS REQUIRES THAT BOTH PARTITIONS
TO BE CONNECTED TO BE FUNCTIONAL
Place the differential termination resistor at the end of the transmission line.
FBACLK0
23
22
21
24
29
30
31
32
35
36
37
38
39
40
28
41
42
26
27
44
45
46
U13
16MX16DDR-5
16M66
16M66
COMMONCHG
14
17
NTP_MEM1_NC8
NTP_MEM1_NC9
4.2E<
3.5B>
4.2B<
5.1H>
50
431925
NTP_MEM1_NC11
NTP_MEM1_NC12
NTP_MEM1_NC13
NTP_MEM1_NC10
1
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
49
53
NTP_MEM1_NC14
C181
220PF
25V
5%
NPO
FBVDDQFBVDD
0402
COMMON
GND
FBVDDQ
C204
16V
10%
X7R
0402
GND
COMMON
GND
GND
VREF_A
C218
.047UF
16V
10%
X7R
0402
COMMON
5.1H> 4.3D>
FBVDD
C172
.022UF
25V
X7R
0402
COMMON
GND
FBVDDQ
C208
220PF
25V
5%
NPO
0402
COMMON
GND
FBVDDQ
C186
.047UF
16V
10%
X7R
0402
COMMON
GND
Place plane decoupling caps near DQS-DQM pairs.
C257
.01UF
16V
10%
X7R
0402
COMMON
FBVDDQ
GND
FBVDDQ
GND
C26
.01UF
16V
10%
X7R
0402
COMMON
FBVDDQ
GND
C270
.01UF
16V
10%
X7R
0402
COMMON
C197
220PF
25V
5%
NPO
0402
COMMON
C213
4700PF.047UF
16V
20%
X7R
0402
COMMON
C176
4700PF
16V
X7R
0402
COMMON
C192
220PF
25V
5%
NPO
0402
COMMON
C212
4700PF
16V
20%
X7R
0402
COMMON
FBVDDQ
GND
C217
220PF
25V
5%
NPO
0402
COMMON
C205
16V
20%
X7R
0402
COMMON
C228
.022UF
25V
X7R
0402
COMMON
C216
220PF
25V
5%
NPO
0402
COMMON
C203
4700PF
16V
20%
X7R
0402
COMMON
FBVDDQ
C293
.01UF
16V
10%
X7R
0402
COMMON
GND
C193
220PF
25V
5%
NPO
0402
COMMON
C189
4700PF4700PF
16V
20%
X7R
0402
COMMON
C221
4700PF
16V
X7R
0402
COMMON
C196
220PF
25V
5%
NPO
0402
COMMON
C187
4700PF
16V
20%
X7R
0402
COMMON
FBVDDQ
C296
.01UF
16V
10%
X7R
0402
COMMON
C302
.01UF
16V
10%
X7R
0402
COMMON
GND
MEMORY 64MB 4/8MX16 Bits 0..31
p162
mlao
C237
.022UF
25V
X7R
0402
COMMON
FBVDDQ
GND
C209
220PF
25V
5%
NPO
0402
COMMON
C188
.047UF
16V
10%
X7R
0402
COMMON
C180
220PF
25V
5%
NPO
0402
COMMON
C202
.047UF
16V
10%
X7R
0402
COMMON
C304
.01UF
16V
10%
X7R
0402
COMMON
FBVDDQ
GND
C169
4.7UF
6.3V
10%
X5R
0805
COMMON
C241
4700PF
16V
X7R
0402
COMMON
C168
4.7UF
6.3V
10%
X5R
0805
COMMON
C307
.01UF
16V
10%
X7R
0402
COMMON
C233
4.7UF
6.3V
10%20%10%20%10%20%10%
X5R
0805
COMMON
4 OF 19
SEP 03 2001
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
Vref
NCNCNC
RAS
CAS
WE
A<3>
A<1>
A<0>
A<4>
A<6>
A<5>
A<2>
CS
A<7>
BA<0>
A<12>
A<11>
AP/A<10>
A<8>
BA<1>
A<9>
CKE
CLK
NCNCNC
CLK
INININININININ
IN
DQ<4>
DQ<3>
DQ<2>
DQ<0>
DQ<1>
DQ<5>
DQS
DQM
DQ<6>
DQ<7>
DQ<4>
DQ<3>
DQ<2>
DQ<0>
DQ<1>
DQ<5>
DQS
DQM
DQ<6>
DQ<7>
IN
DQ<4>
DQ<3>
DQ<2>
DQ<0>
DQ<1>
DQ<5>
DQS
DQM
DQ<6>
DQ<7>
IN
DQ<4>
DQ<3>
DQ<2>
DQ<0>
DQ<1>
DQ<5>
DQS
DQM
DQ<6>
DQ<7>
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
Vref
NCNCNC
RAS
CAS
WE
A<3>
A<1>
A<0>
A<4>
A<6>
A<5>
A<2>
CS
A<7>
BA<0>
A<12>
A<11>
AP/A<10>
A<8>
BA<1>
A<9>
CKE
CLK
NCNCNC
CLK
INININININININININBIIN
IN
5
4
3
2
1
FGH
PAGE
DATE
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY
SANTA CLARA, CA 95050, USA
DETAIL
ID
NAME
DE
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
BC
2
A
1
3
4
5
EGDFHCBA
MEMORY 1st bank 32..63
PLACE ALL DISCRETE COMPONENTS AS NEAR AS POSSIBLE TO MEMORY